hw/lm32_uart.c

   1 /*
   2  *  QEMU model of the LatticeMico32 UART block.
   3  *
   4  *  Copyright (c) 2010 Michael Walle <michael@walle.cc>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  *
  19  *
  20  * Specification available at:
  21  *   http://www.latticesemi.com/documents/mico32uart.pdf
  22  */
  23
  24
  25 #include "hw.h"
  26 #include "sysbus.h"
  27 #include "trace.h"
  28 #include "qemu-char.h"
  29 #include "qemu-error.h"
  30
  31 enum {
  32     R_RXTX = 0,
  33     R_IER,
  34     R_IIR,
  35     R_LCR,
  36     R_MCR,
  37     R_LSR,
  38     R_MSR,
  39     R_DIV,
  40     R_MAX
  41 };
  42
  43 enum {
  44     IER_RBRI = (1<<0),
  45     IER_THRI = (1<<1),
  46     IER_RLSI = (1<<2),
  47     IER_MSI  = (1<<3),
  48 };
  49
  50 enum {
  51     IIR_STAT = (1<<0),
  52     IIR_ID0  = (1<<1),
  53     IIR_ID1  = (1<<2),
  54 };
  55
  56 enum {
  57     LCR_WLS0 = (1<<0),
  58     LCR_WLS1 = (1<<1),
  59     LCR_STB  = (1<<2),
  60     LCR_PEN  = (1<<3),
  61     LCR_EPS  = (1<<4),
  62     LCR_SP   = (1<<5),
  63     LCR_SB   = (1<<6),
  64 };
  65
  66 enum {
  67     MCR_DTR  = (1<<0),
  68     MCR_RTS  = (1<<1),
  69 };
  70
  71 enum {
  72     LSR_DR   = (1<<0),
  73     LSR_OE   = (1<<1),
  74     LSR_PE   = (1<<2),
  75     LSR_FE   = (1<<3),
  76     LSR_BI   = (1<<4),
  77     LSR_THRE = (1<<5),
  78     LSR_TEMT = (1<<6),
  79 };
  80
  81 enum {
  82     MSR_DCTS = (1<<0),
  83     MSR_DDSR = (1<<1),
  84     MSR_TERI = (1<<2),
  85     MSR_DDCD = (1<<3),
  86     MSR_CTS  = (1<<4),
  87     MSR_DSR  = (1<<5),
  88     MSR_RI   = (1<<6),
  89     MSR_DCD  = (1<<7),
  90 };
  91
  92 struct LM32UartState {
  93     SysBusDevice busdev;
  94     CharDriverState *chr;
  95     qemu_irq irq;
  96
  97     uint32_t regs[R_MAX];
  98 };
  99 typedef struct LM32UartState LM32UartState;
 100
 101 static void uart_update_irq(LM32UartState *s)
 102 {
 103     unsigned int irq;
 104
 105     if ((s->regs[R_LSR] & (LSR_OE | LSR_PE | LSR_FE | LSR_BI))
 106             && (s->regs[R_IER] & IER_RLSI)) {
 107         irq = 1;
 108         s->regs[R_IIR] = IIR_ID1 | IIR_ID0;
 109     } else if ((s->regs[R_LSR] & LSR_DR) && (s->regs[R_IER] & IER_RBRI)) {
 110         irq = 1;
 111         s->regs[R_IIR] = IIR_ID1;
 112     } else if ((s->regs[R_LSR] & LSR_THRE) && (s->regs[R_IER] & IER_THRI)) {
 113         irq = 1;
 114         s->regs[R_IIR] = IIR_ID0;
 115     } else if ((s->regs[R_MSR] & 0x0f) && (s->regs[R_IER] & IER_MSI)) {
 116         irq = 1;
 117         s->regs[R_IIR] = 0;
 118     } else {
 119         irq = 0;
 120         s->regs[R_IIR] = IIR_STAT;
 121     }
 122
 123     trace_lm32_uart_irq_state(irq);
 124     qemu_set_irq(s->irq, irq);
 125 }
 126
 127 static uint32_t uart_read(void *opaque, target_phys_addr_t addr)
 128 {
 129     LM32UartState *s = opaque;
 130     uint32_t r = 0;
 131
 132     addr >>= 2;
 133     switch (addr) {
 134     case R_RXTX:
 135         r = s->regs[R_RXTX];
 136         s->regs[R_LSR] &= ~LSR_DR;
 137         uart_update_irq(s);
 138         break;
 139     case R_IIR:
 140     case R_LSR:
 141     case R_MSR:
 142         r = s->regs[addr];
 143         break;
 144     case R_IER:
 145     case R_LCR:
 146     case R_MCR:
 147     case R_DIV:
 148         error_report("lm32_uart: read access to write only register 0x"
 149                 TARGET_FMT_plx, addr << 2);
 150         break;
 151     default:
 152         error_report("lm32_uart: read access to unknown register 0x"
 153                 TARGET_FMT_plx, addr << 2);
 154         break;
 155     }
 156
 157     trace_lm32_uart_memory_read(addr << 2, r);
 158     return r;
 159 }
 160
 161 static void uart_write(void *opaque, target_phys_addr_t addr, uint32_t value)
 162 {
 163     LM32UartState *s = opaque;
 164     unsigned char ch = value;
 165
 166     trace_lm32_uart_memory_write(addr, value);
 167
 168     addr >>= 2;
 169     switch (addr) {
 170     case R_RXTX:
 171         if (s->chr) {
 172             qemu_chr_write(s->chr, &ch, 1);
 173         }
 174         break;
 175     case R_IER:
 176     case R_LCR:
 177     case R_MCR:
 178     case R_DIV:
 179         s->regs[addr] = value;
 180         break;
 181     case R_IIR:
 182     case R_LSR:
 183     case R_MSR:
 184         error_report("lm32_uart: write access to read only register 0x"
 185                 TARGET_FMT_plx, addr << 2);
 186         break;
 187     default:
 188         error_report("lm32_uart: write access to unknown register 0x"
 189                 TARGET_FMT_plx, addr << 2);
 190         break;
 191     }
 192     uart_update_irq(s);
 193 }
 194
 195 static CPUReadMemoryFunc * const uart_read_fn[] = {
 196     NULL,
 197     NULL,
 198     &uart_read,
 199 };
 200
 201 static CPUWriteMemoryFunc * const uart_write_fn[] = {
 202     NULL,
 203     NULL,
 204     &uart_write,
 205 };
 206
 207 static void uart_rx(void *opaque, const uint8_t *buf, int size)
 208 {
 209     LM32UartState *s = opaque;
 210
 211     if (s->regs[R_LSR] & LSR_DR) {
 212         s->regs[R_LSR] |= LSR_OE;
 213     }
 214
 215     s->regs[R_LSR] |= LSR_DR;
 216     s->regs[R_RXTX] = *buf;
 217
 218     uart_update_irq(s);
 219 }
 220
 221 static int uart_can_rx(void *opaque)
 222 {
 223     LM32UartState *s = opaque;
 224
 225     return !(s->regs[R_LSR] & LSR_DR);
 226 }
 227
 228 static void uart_event(void *opaque, int event)
 229 {
 230 }
 231
 232 static void uart_reset(DeviceState *d)
 233 {
 234     LM32UartState *s = container_of(d, LM32UartState, busdev.qdev);
 235     int i;
 236
 237     for (i = 0; i < R_MAX; i++) {
 238         s->regs[i] = 0;
 239     }
 240
 241     /* defaults */
 242     s->regs[R_LSR] = LSR_THRE | LSR_TEMT;
 243 }
 244
 245 static int lm32_uart_init(SysBusDevice *dev)
 246 {
 247     LM32UartState *s = FROM_SYSBUS(typeof(*s), dev);
 248     int uart_regs;
 249
 250     sysbus_init_irq(dev, &s->irq);
 251
 252     uart_regs = cpu_register_io_memory(uart_read_fn, uart_write_fn, s,
 253             DEVICE_NATIVE_ENDIAN);
 254     sysbus_init_mmio(dev, R_MAX * 4, uart_regs);
 255
 256     s->chr = qdev_init_chardev(&dev->qdev);
 257     if (s->chr) {
 258         qemu_chr_add_handlers(s->chr, uart_can_rx, uart_rx, uart_event, s);
 259     }
 260
 261     return 0;
 262 }
 263
 264 static const VMStateDescription vmstate_lm32_uart = {
 265     .name = "lm32-uart",
 266     .version_id = 1,
 267     .minimum_version_id = 1,
 268     .minimum_version_id_old = 1,
 269     .fields      = (VMStateField[]) {
 270         VMSTATE_UINT32_ARRAY(regs, LM32UartState, R_MAX),
 271         VMSTATE_END_OF_LIST()
 272     }
 273 };
 274
 275 static SysBusDeviceInfo lm32_uart_info = {
 276     .init = lm32_uart_init,
 277     .qdev.name  = "lm32-uart",
 278     .qdev.size  = sizeof(LM32UartState),
 279     .qdev.vmsd  = &vmstate_lm32_uart,
 280     .qdev.reset = uart_reset,
 281 };
 282
 283 static void lm32_uart_register(void)
 284 {
 285     sysbus_register_withprop(&lm32_uart_info);
 286 }
 287
 288 device_init(lm32_uart_register)