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Merge remote-tracking branch 'afaerber/qom-cpu-x86-prop.v3' into staging
[qemu.git] / hw / ppc405_uc.c
blob89e5013b577871701299c72273f9c7c2b9832dad
1 /*
2 * QEMU PowerPC 405 embedded processors emulation
3 *
4 * Copyright (c) 2007 Jocelyn Mayer
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "ppc.h"
26 #include "ppc405.h"
27 #include "pc.h"
28 #include "qemu-timer.h"
29 #include "sysemu.h"
30 #include "qemu-log.h"
31 #include "exec-memory.h"
32
33 #define DEBUG_OPBA
34 #define DEBUG_SDRAM
35 #define DEBUG_GPIO
36 #define DEBUG_SERIAL
37 #define DEBUG_OCM
38 //#define DEBUG_I2C
39 #define DEBUG_GPT
40 #define DEBUG_MAL
41 #define DEBUG_CLOCKS
42 //#define DEBUG_CLOCKS_LL
43
44 ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd,
45 uint32_t flags)
46 {
47 ram_addr_t bdloc;
48 int i, n;
49
50 /* We put the bd structure at the top of memory */
51 if (bd->bi_memsize >= 0x01000000UL)
52 bdloc = 0x01000000UL - sizeof(struct ppc4xx_bd_info_t);
53 else
54 bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info_t);
55 stl_be_phys(bdloc + 0x00, bd->bi_memstart);
56 stl_be_phys(bdloc + 0x04, bd->bi_memsize);
57 stl_be_phys(bdloc + 0x08, bd->bi_flashstart);
58 stl_be_phys(bdloc + 0x0C, bd->bi_flashsize);
59 stl_be_phys(bdloc + 0x10, bd->bi_flashoffset);
60 stl_be_phys(bdloc + 0x14, bd->bi_sramstart);
61 stl_be_phys(bdloc + 0x18, bd->bi_sramsize);
62 stl_be_phys(bdloc + 0x1C, bd->bi_bootflags);
63 stl_be_phys(bdloc + 0x20, bd->bi_ipaddr);
64 for (i = 0; i < 6; i++) {
65 stb_phys(bdloc + 0x24 + i, bd->bi_enetaddr[i]);
66 }
67 stw_be_phys(bdloc + 0x2A, bd->bi_ethspeed);
68 stl_be_phys(bdloc + 0x2C, bd->bi_intfreq);
69 stl_be_phys(bdloc + 0x30, bd->bi_busfreq);
70 stl_be_phys(bdloc + 0x34, bd->bi_baudrate);
71 for (i = 0; i < 4; i++) {
72 stb_phys(bdloc + 0x38 + i, bd->bi_s_version[i]);
73 }
74 for (i = 0; i < 32; i++) {
75 stb_phys(bdloc + 0x3C + i, bd->bi_r_version[i]);
76 }
77 stl_be_phys(bdloc + 0x5C, bd->bi_plb_busfreq);
78 stl_be_phys(bdloc + 0x60, bd->bi_pci_busfreq);
79 for (i = 0; i < 6; i++) {
80 stb_phys(bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]);
81 }
82 n = 0x6A;
83 if (flags & 0x00000001) {
84 for (i = 0; i < 6; i++)
85 stb_phys(bdloc + n++, bd->bi_pci_enetaddr2[i]);
86 }
87 stl_be_phys(bdloc + n, bd->bi_opbfreq);
88 n += 4;
89 for (i = 0; i < 2; i++) {
90 stl_be_phys(bdloc + n, bd->bi_iic_fast[i]);
91 n += 4;
92 }
93
94 return bdloc;
95 }
96
97 /*****************************************************************************/
98 /* Shared peripherals */
99
100 /*****************************************************************************/
101 /* Peripheral local bus arbitrer */
102 enum {
103 PLB0_BESR = 0x084,
104 PLB0_BEAR = 0x086,
105 PLB0_ACR = 0x087,
106 };
107
108 typedef struct ppc4xx_plb_t ppc4xx_plb_t;
109 struct ppc4xx_plb_t {
110 uint32_t acr;
111 uint32_t bear;
112 uint32_t besr;
113 };
114
115 static uint32_t dcr_read_plb (void *opaque, int dcrn)
116 {
117 ppc4xx_plb_t *plb;
118 uint32_t ret;
119
120 plb = opaque;
121 switch (dcrn) {
122 case PLB0_ACR:
123 ret = plb->acr;
124 break;
125 case PLB0_BEAR:
126 ret = plb->bear;
127 break;
128 case PLB0_BESR:
129 ret = plb->besr;
130 break;
131 default:
132 /* Avoid gcc warning */
133 ret = 0;
134 break;
135 }
136
137 return ret;
138 }
139
140 static void dcr_write_plb (void *opaque, int dcrn, uint32_t val)
141 {
142 ppc4xx_plb_t *plb;
143
144 plb = opaque;
145 switch (dcrn) {
146 case PLB0_ACR:
147 /* We don't care about the actual parameters written as
148 * we don't manage any priorities on the bus
149 */
150 plb->acr = val & 0xF8000000;
151 break;
152 case PLB0_BEAR:
153 /* Read only */
154 break;
155 case PLB0_BESR:
156 /* Write-clear */
157 plb->besr &= ~val;
158 break;
159 }
160 }
161
162 static void ppc4xx_plb_reset (void *opaque)
163 {
164 ppc4xx_plb_t *plb;
165
166 plb = opaque;
167 plb->acr = 0x00000000;
168 plb->bear = 0x00000000;
169 plb->besr = 0x00000000;
170 }
171
172 static void ppc4xx_plb_init(CPUPPCState *env)
173 {
174 ppc4xx_plb_t *plb;
175
176 plb = g_malloc0(sizeof(ppc4xx_plb_t));
177 ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
178 ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb);
179 ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb);
180 qemu_register_reset(ppc4xx_plb_reset, plb);
181 }
182
183 /*****************************************************************************/
184 /* PLB to OPB bridge */
185 enum {
186 POB0_BESR0 = 0x0A0,
187 POB0_BESR1 = 0x0A2,
188 POB0_BEAR = 0x0A4,
189 };
190
191 typedef struct ppc4xx_pob_t ppc4xx_pob_t;
192 struct ppc4xx_pob_t {
193 uint32_t bear;
194 uint32_t besr[2];
195 };
196
197 static uint32_t dcr_read_pob (void *opaque, int dcrn)
198 {
199 ppc4xx_pob_t *pob;
200 uint32_t ret;
201
202 pob = opaque;
203 switch (dcrn) {
204 case POB0_BEAR:
205 ret = pob->bear;
206 break;
207 case POB0_BESR0:
208 case POB0_BESR1:
209 ret = pob->besr[dcrn - POB0_BESR0];
210 break;
211 default:
212 /* Avoid gcc warning */
213 ret = 0;
214 break;
215 }
216
217 return ret;
218 }
219
220 static void dcr_write_pob (void *opaque, int dcrn, uint32_t val)
221 {
222 ppc4xx_pob_t *pob;
223
224 pob = opaque;
225 switch (dcrn) {
226 case POB0_BEAR:
227 /* Read only */
228 break;
229 case POB0_BESR0:
230 case POB0_BESR1:
231 /* Write-clear */
232 pob->besr[dcrn - POB0_BESR0] &= ~val;
233 break;
234 }
235 }
236
237 static void ppc4xx_pob_reset (void *opaque)
238 {
239 ppc4xx_pob_t *pob;
240
241 pob = opaque;
242 /* No error */
243 pob->bear = 0x00000000;
244 pob->besr[0] = 0x0000000;
245 pob->besr[1] = 0x0000000;
246 }
247
248 static void ppc4xx_pob_init(CPUPPCState *env)
249 {
250 ppc4xx_pob_t *pob;
251
252 pob = g_malloc0(sizeof(ppc4xx_pob_t));
253 ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob);
254 ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob);
255 ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob);
256 qemu_register_reset(ppc4xx_pob_reset, pob);
257 }
258
259 /*****************************************************************************/
260 /* OPB arbitrer */
261 typedef struct ppc4xx_opba_t ppc4xx_opba_t;
262 struct ppc4xx_opba_t {
263 MemoryRegion io;
264 uint8_t cr;
265 uint8_t pr;
266 };
267
268 static uint32_t opba_readb (void *opaque, target_phys_addr_t addr)
269 {
270 ppc4xx_opba_t *opba;
271 uint32_t ret;
272
273 #ifdef DEBUG_OPBA
274 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
275 #endif
276 opba = opaque;
277 switch (addr) {
278 case 0x00:
279 ret = opba->cr;
280 break;
281 case 0x01:
282 ret = opba->pr;
283 break;
284 default:
285 ret = 0x00;
286 break;
287 }
288
289 return ret;
290 }
291
292 static void opba_writeb (void *opaque,
293 target_phys_addr_t addr, uint32_t value)
294 {
295 ppc4xx_opba_t *opba;
296
297 #ifdef DEBUG_OPBA
298 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
299 value);
300 #endif
301 opba = opaque;
302 switch (addr) {
303 case 0x00:
304 opba->cr = value & 0xF8;
305 break;
306 case 0x01:
307 opba->pr = value & 0xFF;
308 break;
309 default:
310 break;
311 }
312 }
313
314 static uint32_t opba_readw (void *opaque, target_phys_addr_t addr)
315 {
316 uint32_t ret;
317
318 #ifdef DEBUG_OPBA
319 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
320 #endif
321 ret = opba_readb(opaque, addr) << 8;
322 ret |= opba_readb(opaque, addr + 1);
323
324 return ret;
325 }
326
327 static void opba_writew (void *opaque,
328 target_phys_addr_t addr, uint32_t value)
329 {
330 #ifdef DEBUG_OPBA
331 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
332 value);
333 #endif
334 opba_writeb(opaque, addr, value >> 8);
335 opba_writeb(opaque, addr + 1, value);
336 }
337
338 static uint32_t opba_readl (void *opaque, target_phys_addr_t addr)
339 {
340 uint32_t ret;
341
342 #ifdef DEBUG_OPBA
343 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
344 #endif
345 ret = opba_readb(opaque, addr) << 24;
346 ret |= opba_readb(opaque, addr + 1) << 16;
347
348 return ret;
349 }
350
351 static void opba_writel (void *opaque,
352 target_phys_addr_t addr, uint32_t value)
353 {
354 #ifdef DEBUG_OPBA
355 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
356 value);
357 #endif
358 opba_writeb(opaque, addr, value >> 24);
359 opba_writeb(opaque, addr + 1, value >> 16);
360 }
361
362 static const MemoryRegionOps opba_ops = {
363 .old_mmio = {
364 .read = { opba_readb, opba_readw, opba_readl, },
365 .write = { opba_writeb, opba_writew, opba_writel, },
366 },
367 .endianness = DEVICE_NATIVE_ENDIAN,
368 };
369
370 static void ppc4xx_opba_reset (void *opaque)
371 {
372 ppc4xx_opba_t *opba;
373
374 opba = opaque;
375 opba->cr = 0x00; /* No dynamic priorities - park disabled */
376 opba->pr = 0x11;
377 }
378
379 static void ppc4xx_opba_init(target_phys_addr_t base)
380 {
381 ppc4xx_opba_t *opba;
382
383 opba = g_malloc0(sizeof(ppc4xx_opba_t));
384 #ifdef DEBUG_OPBA
385 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
386 #endif
387 memory_region_init_io(&opba->io, &opba_ops, opba, "opba", 0x002);
388 memory_region_add_subregion(get_system_memory(), base, &opba->io);
389 qemu_register_reset(ppc4xx_opba_reset, opba);
390 }
391
392 /*****************************************************************************/
393 /* Code decompression controller */
394 /* XXX: TODO */
395
396 /*****************************************************************************/
397 /* Peripheral controller */
398 typedef struct ppc4xx_ebc_t ppc4xx_ebc_t;
399 struct ppc4xx_ebc_t {
400 uint32_t addr;
401 uint32_t bcr[8];
402 uint32_t bap[8];
403 uint32_t bear;
404 uint32_t besr0;
405 uint32_t besr1;
406 uint32_t cfg;
407 };
408
409 enum {
410 EBC0_CFGADDR = 0x012,
411 EBC0_CFGDATA = 0x013,
412 };
413
414 static uint32_t dcr_read_ebc (void *opaque, int dcrn)
415 {
416 ppc4xx_ebc_t *ebc;
417 uint32_t ret;
418
419 ebc = opaque;
420 switch (dcrn) {
421 case EBC0_CFGADDR:
422 ret = ebc->addr;
423 break;
424 case EBC0_CFGDATA:
425 switch (ebc->addr) {
426 case 0x00: /* B0CR */
427 ret = ebc->bcr[0];
428 break;
429 case 0x01: /* B1CR */
430 ret = ebc->bcr[1];
431 break;
432 case 0x02: /* B2CR */
433 ret = ebc->bcr[2];
434 break;
435 case 0x03: /* B3CR */
436 ret = ebc->bcr[3];
437 break;
438 case 0x04: /* B4CR */
439 ret = ebc->bcr[4];
440 break;
441 case 0x05: /* B5CR */
442 ret = ebc->bcr[5];
443 break;
444 case 0x06: /* B6CR */
445 ret = ebc->bcr[6];
446 break;
447 case 0x07: /* B7CR */
448 ret = ebc->bcr[7];
449 break;
450 case 0x10: /* B0AP */
451 ret = ebc->bap[0];
452 break;
453 case 0x11: /* B1AP */
454 ret = ebc->bap[1];
455 break;
456 case 0x12: /* B2AP */
457 ret = ebc->bap[2];
458 break;
459 case 0x13: /* B3AP */
460 ret = ebc->bap[3];
461 break;
462 case 0x14: /* B4AP */
463 ret = ebc->bap[4];
464 break;
465 case 0x15: /* B5AP */
466 ret = ebc->bap[5];
467 break;
468 case 0x16: /* B6AP */
469 ret = ebc->bap[6];
470 break;
471 case 0x17: /* B7AP */
472 ret = ebc->bap[7];
473 break;
474 case 0x20: /* BEAR */
475 ret = ebc->bear;
476 break;
477 case 0x21: /* BESR0 */
478 ret = ebc->besr0;
479 break;
480 case 0x22: /* BESR1 */
481 ret = ebc->besr1;
482 break;
483 case 0x23: /* CFG */
484 ret = ebc->cfg;
485 break;
486 default:
487 ret = 0x00000000;
488 break;
489 }
490 break;
491 default:
492 ret = 0x00000000;
493 break;
494 }
495
496 return ret;
497 }
498
499 static void dcr_write_ebc (void *opaque, int dcrn, uint32_t val)
500 {
501 ppc4xx_ebc_t *ebc;
502
503 ebc = opaque;
504 switch (dcrn) {
505 case EBC0_CFGADDR:
506 ebc->addr = val;
507 break;
508 case EBC0_CFGDATA:
509 switch (ebc->addr) {
510 case 0x00: /* B0CR */
511 break;
512 case 0x01: /* B1CR */
513 break;
514 case 0x02: /* B2CR */
515 break;
516 case 0x03: /* B3CR */
517 break;
518 case 0x04: /* B4CR */
519 break;
520 case 0x05: /* B5CR */
521 break;
522 case 0x06: /* B6CR */
523 break;
524 case 0x07: /* B7CR */
525 break;
526 case 0x10: /* B0AP */
527 break;
528 case 0x11: /* B1AP */
529 break;
530 case 0x12: /* B2AP */
531 break;
532 case 0x13: /* B3AP */
533 break;
534 case 0x14: /* B4AP */
535 break;
536 case 0x15: /* B5AP */
537 break;
538 case 0x16: /* B6AP */
539 break;
540 case 0x17: /* B7AP */
541 break;
542 case 0x20: /* BEAR */
543 break;
544 case 0x21: /* BESR0 */
545 break;
546 case 0x22: /* BESR1 */
547 break;
548 case 0x23: /* CFG */
549 break;
550 default:
551 break;
552 }
553 break;
554 default:
555 break;
556 }
557 }
558
559 static void ebc_reset (void *opaque)
560 {
561 ppc4xx_ebc_t *ebc;
562 int i;
563
564 ebc = opaque;
565 ebc->addr = 0x00000000;
566 ebc->bap[0] = 0x7F8FFE80;
567 ebc->bcr[0] = 0xFFE28000;
568 for (i = 0; i < 8; i++) {
569 ebc->bap[i] = 0x00000000;
570 ebc->bcr[i] = 0x00000000;
571 }
572 ebc->besr0 = 0x00000000;
573 ebc->besr1 = 0x00000000;
574 ebc->cfg = 0x80400000;
575 }
576
577 static void ppc405_ebc_init(CPUPPCState *env)
578 {
579 ppc4xx_ebc_t *ebc;
580
581 ebc = g_malloc0(sizeof(ppc4xx_ebc_t));
582 qemu_register_reset(&ebc_reset, ebc);
583 ppc_dcr_register(env, EBC0_CFGADDR,
584 ebc, &dcr_read_ebc, &dcr_write_ebc);
585 ppc_dcr_register(env, EBC0_CFGDATA,
586 ebc, &dcr_read_ebc, &dcr_write_ebc);
587 }
588
589 /*****************************************************************************/
590 /* DMA controller */
591 enum {
592 DMA0_CR0 = 0x100,
593 DMA0_CT0 = 0x101,
594 DMA0_DA0 = 0x102,
595 DMA0_SA0 = 0x103,
596 DMA0_SG0 = 0x104,
597 DMA0_CR1 = 0x108,
598 DMA0_CT1 = 0x109,
599 DMA0_DA1 = 0x10A,
600 DMA0_SA1 = 0x10B,
601 DMA0_SG1 = 0x10C,
602 DMA0_CR2 = 0x110,
603 DMA0_CT2 = 0x111,
604 DMA0_DA2 = 0x112,
605 DMA0_SA2 = 0x113,
606 DMA0_SG2 = 0x114,
607 DMA0_CR3 = 0x118,
608 DMA0_CT3 = 0x119,
609 DMA0_DA3 = 0x11A,
610 DMA0_SA3 = 0x11B,
611 DMA0_SG3 = 0x11C,
612 DMA0_SR = 0x120,
613 DMA0_SGC = 0x123,
614 DMA0_SLP = 0x125,
615 DMA0_POL = 0x126,
616 };
617
618 typedef struct ppc405_dma_t ppc405_dma_t;
619 struct ppc405_dma_t {
620 qemu_irq irqs[4];
621 uint32_t cr[4];
622 uint32_t ct[4];
623 uint32_t da[4];
624 uint32_t sa[4];
625 uint32_t sg[4];
626 uint32_t sr;
627 uint32_t sgc;
628 uint32_t slp;
629 uint32_t pol;
630 };
631
632 static uint32_t dcr_read_dma (void *opaque, int dcrn)
633 {
634 return 0;
635 }
636
637 static void dcr_write_dma (void *opaque, int dcrn, uint32_t val)
638 {
639 }
640
641 static void ppc405_dma_reset (void *opaque)
642 {
643 ppc405_dma_t *dma;
644 int i;
645
646 dma = opaque;
647 for (i = 0; i < 4; i++) {
648 dma->cr[i] = 0x00000000;
649 dma->ct[i] = 0x00000000;
650 dma->da[i] = 0x00000000;
651 dma->sa[i] = 0x00000000;
652 dma->sg[i] = 0x00000000;
653 }
654 dma->sr = 0x00000000;
655 dma->sgc = 0x00000000;
656 dma->slp = 0x7C000000;
657 dma->pol = 0x00000000;
658 }
659
660 static void ppc405_dma_init(CPUPPCState *env, qemu_irq irqs[4])
661 {
662 ppc405_dma_t *dma;
663
664 dma = g_malloc0(sizeof(ppc405_dma_t));
665 memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq));
666 qemu_register_reset(&ppc405_dma_reset, dma);
667 ppc_dcr_register(env, DMA0_CR0,
668 dma, &dcr_read_dma, &dcr_write_dma);
669 ppc_dcr_register(env, DMA0_CT0,
670 dma, &dcr_read_dma, &dcr_write_dma);
671 ppc_dcr_register(env, DMA0_DA0,
672 dma, &dcr_read_dma, &dcr_write_dma);
673 ppc_dcr_register(env, DMA0_SA0,
674 dma, &dcr_read_dma, &dcr_write_dma);
675 ppc_dcr_register(env, DMA0_SG0,
676 dma, &dcr_read_dma, &dcr_write_dma);
677 ppc_dcr_register(env, DMA0_CR1,
678 dma, &dcr_read_dma, &dcr_write_dma);
679 ppc_dcr_register(env, DMA0_CT1,
680 dma, &dcr_read_dma, &dcr_write_dma);
681 ppc_dcr_register(env, DMA0_DA1,
682 dma, &dcr_read_dma, &dcr_write_dma);
683 ppc_dcr_register(env, DMA0_SA1,
684 dma, &dcr_read_dma, &dcr_write_dma);
685 ppc_dcr_register(env, DMA0_SG1,
686 dma, &dcr_read_dma, &dcr_write_dma);
687 ppc_dcr_register(env, DMA0_CR2,
688 dma, &dcr_read_dma, &dcr_write_dma);
689 ppc_dcr_register(env, DMA0_CT2,
690 dma, &dcr_read_dma, &dcr_write_dma);
691 ppc_dcr_register(env, DMA0_DA2,
692 dma, &dcr_read_dma, &dcr_write_dma);
693 ppc_dcr_register(env, DMA0_SA2,
694 dma, &dcr_read_dma, &dcr_write_dma);
695 ppc_dcr_register(env, DMA0_SG2,
696 dma, &dcr_read_dma, &dcr_write_dma);
697 ppc_dcr_register(env, DMA0_CR3,
698 dma, &dcr_read_dma, &dcr_write_dma);
699 ppc_dcr_register(env, DMA0_CT3,
700 dma, &dcr_read_dma, &dcr_write_dma);
701 ppc_dcr_register(env, DMA0_DA3,
702 dma, &dcr_read_dma, &dcr_write_dma);
703 ppc_dcr_register(env, DMA0_SA3,
704 dma, &dcr_read_dma, &dcr_write_dma);
705 ppc_dcr_register(env, DMA0_SG3,
706 dma, &dcr_read_dma, &dcr_write_dma);
707 ppc_dcr_register(env, DMA0_SR,
708 dma, &dcr_read_dma, &dcr_write_dma);
709 ppc_dcr_register(env, DMA0_SGC,
710 dma, &dcr_read_dma, &dcr_write_dma);
711 ppc_dcr_register(env, DMA0_SLP,
712 dma, &dcr_read_dma, &dcr_write_dma);
713 ppc_dcr_register(env, DMA0_POL,
714 dma, &dcr_read_dma, &dcr_write_dma);
715 }
716
717 /*****************************************************************************/
718 /* GPIO */
719 typedef struct ppc405_gpio_t ppc405_gpio_t;
720 struct ppc405_gpio_t {
721 MemoryRegion io;
722 uint32_t or;
723 uint32_t tcr;
724 uint32_t osrh;
725 uint32_t osrl;
726 uint32_t tsrh;
727 uint32_t tsrl;
728 uint32_t odr;
729 uint32_t ir;
730 uint32_t rr1;
731 uint32_t isr1h;
732 uint32_t isr1l;
733 };
734
735 static uint32_t ppc405_gpio_readb (void *opaque, target_phys_addr_t addr)
736 {
737 #ifdef DEBUG_GPIO
738 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
739 #endif
740
741 return 0;
742 }
743
744 static void ppc405_gpio_writeb (void *opaque,
745 target_phys_addr_t addr, uint32_t value)
746 {
747 #ifdef DEBUG_GPIO
748 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
749 value);
750 #endif
751 }
752
753 static uint32_t ppc405_gpio_readw (void *opaque, target_phys_addr_t addr)
754 {
755 #ifdef DEBUG_GPIO
756 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
757 #endif
758
759 return 0;
760 }
761
762 static void ppc405_gpio_writew (void *opaque,
763 target_phys_addr_t addr, uint32_t value)
764 {
765 #ifdef DEBUG_GPIO
766 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
767 value);
768 #endif
769 }
770
771 static uint32_t ppc405_gpio_readl (void *opaque, target_phys_addr_t addr)
772 {
773 #ifdef DEBUG_GPIO
774 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
775 #endif
776
777 return 0;
778 }
779
780 static void ppc405_gpio_writel (void *opaque,
781 target_phys_addr_t addr, uint32_t value)
782 {
783 #ifdef DEBUG_GPIO
784 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
785 value);
786 #endif
787 }
788
789 static const MemoryRegionOps ppc405_gpio_ops = {
790 .old_mmio = {
791 .read = { ppc405_gpio_readb, ppc405_gpio_readw, ppc405_gpio_readl, },
792 .write = { ppc405_gpio_writeb, ppc405_gpio_writew, ppc405_gpio_writel, },
793 },
794 .endianness = DEVICE_NATIVE_ENDIAN,
795 };
796
797 static void ppc405_gpio_reset (void *opaque)
798 {
799 }
800
801 static void ppc405_gpio_init(target_phys_addr_t base)
802 {
803 ppc405_gpio_t *gpio;
804
805 gpio = g_malloc0(sizeof(ppc405_gpio_t));
806 #ifdef DEBUG_GPIO
807 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
808 #endif
809 memory_region_init_io(&gpio->io, &ppc405_gpio_ops, gpio, "pgio", 0x038);
810 memory_region_add_subregion(get_system_memory(), base, &gpio->io);
811 qemu_register_reset(&ppc405_gpio_reset, gpio);
812 }
813
814 /*****************************************************************************/
815 /* On Chip Memory */
816 enum {
817 OCM0_ISARC = 0x018,
818 OCM0_ISACNTL = 0x019,
819 OCM0_DSARC = 0x01A,
820 OCM0_DSACNTL = 0x01B,
821 };
822
823 typedef struct ppc405_ocm_t ppc405_ocm_t;
824 struct ppc405_ocm_t {
825 MemoryRegion ram;
826 MemoryRegion isarc_ram;
827 MemoryRegion dsarc_ram;
828 uint32_t isarc;
829 uint32_t isacntl;
830 uint32_t dsarc;
831 uint32_t dsacntl;
832 };
833
834 static void ocm_update_mappings (ppc405_ocm_t *ocm,
835 uint32_t isarc, uint32_t isacntl,
836 uint32_t dsarc, uint32_t dsacntl)
837 {
838 #ifdef DEBUG_OCM
839 printf("OCM update ISA %08" PRIx32 " %08" PRIx32 " (%08" PRIx32
840 " %08" PRIx32 ") DSA %08" PRIx32 " %08" PRIx32
841 " (%08" PRIx32 " %08" PRIx32 ")\n",
842 isarc, isacntl, dsarc, dsacntl,
843 ocm->isarc, ocm->isacntl, ocm->dsarc, ocm->dsacntl);
844 #endif
845 if (ocm->isarc != isarc ||
846 (ocm->isacntl & 0x80000000) != (isacntl & 0x80000000)) {
847 if (ocm->isacntl & 0x80000000) {
848 /* Unmap previously assigned memory region */
849 printf("OCM unmap ISA %08" PRIx32 "\n", ocm->isarc);
850 memory_region_del_subregion(get_system_memory(), &ocm->isarc_ram);
851 }
852 if (isacntl & 0x80000000) {
853 /* Map new instruction memory region */
854 #ifdef DEBUG_OCM
855 printf("OCM map ISA %08" PRIx32 "\n", isarc);
856 #endif
857 memory_region_add_subregion(get_system_memory(), isarc,
858 &ocm->isarc_ram);
859 }
860 }
861 if (ocm->dsarc != dsarc ||
862 (ocm->dsacntl & 0x80000000) != (dsacntl & 0x80000000)) {
863 if (ocm->dsacntl & 0x80000000) {
864 /* Beware not to unmap the region we just mapped */
865 if (!(isacntl & 0x80000000) || ocm->dsarc != isarc) {
866 /* Unmap previously assigned memory region */
867 #ifdef DEBUG_OCM
868 printf("OCM unmap DSA %08" PRIx32 "\n", ocm->dsarc);
869 #endif
870 memory_region_del_subregion(get_system_memory(),
871 &ocm->dsarc_ram);
872 }
873 }
874 if (dsacntl & 0x80000000) {
875 /* Beware not to remap the region we just mapped */
876 if (!(isacntl & 0x80000000) || dsarc != isarc) {
877 /* Map new data memory region */
878 #ifdef DEBUG_OCM
879 printf("OCM map DSA %08" PRIx32 "\n", dsarc);
880 #endif
881 memory_region_add_subregion(get_system_memory(), dsarc,
882 &ocm->dsarc_ram);
883 }
884 }
885 }
886 }
887
888 static uint32_t dcr_read_ocm (void *opaque, int dcrn)
889 {
890 ppc405_ocm_t *ocm;
891 uint32_t ret;
892
893 ocm = opaque;
894 switch (dcrn) {
895 case OCM0_ISARC:
896 ret = ocm->isarc;
897 break;
898 case OCM0_ISACNTL:
899 ret = ocm->isacntl;
900 break;
901 case OCM0_DSARC:
902 ret = ocm->dsarc;
903 break;
904 case OCM0_DSACNTL:
905 ret = ocm->dsacntl;
906 break;
907 default:
908 ret = 0;
909 break;
910 }
911
912 return ret;
913 }
914
915 static void dcr_write_ocm (void *opaque, int dcrn, uint32_t val)
916 {
917 ppc405_ocm_t *ocm;
918 uint32_t isarc, dsarc, isacntl, dsacntl;
919
920 ocm = opaque;
921 isarc = ocm->isarc;
922 dsarc = ocm->dsarc;
923 isacntl = ocm->isacntl;
924 dsacntl = ocm->dsacntl;
925 switch (dcrn) {
926 case OCM0_ISARC:
927 isarc = val & 0xFC000000;
928 break;
929 case OCM0_ISACNTL:
930 isacntl = val & 0xC0000000;
931 break;
932 case OCM0_DSARC:
933 isarc = val & 0xFC000000;
934 break;
935 case OCM0_DSACNTL:
936 isacntl = val & 0xC0000000;
937 break;
938 }
939 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl);
940 ocm->isarc = isarc;
941 ocm->dsarc = dsarc;
942 ocm->isacntl = isacntl;
943 ocm->dsacntl = dsacntl;
944 }
945
946 static void ocm_reset (void *opaque)
947 {
948 ppc405_ocm_t *ocm;
949 uint32_t isarc, dsarc, isacntl, dsacntl;
950
951 ocm = opaque;
952 isarc = 0x00000000;
953 isacntl = 0x00000000;
954 dsarc = 0x00000000;
955 dsacntl = 0x00000000;
956 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl);
957 ocm->isarc = isarc;
958 ocm->dsarc = dsarc;
959 ocm->isacntl = isacntl;
960 ocm->dsacntl = dsacntl;
961 }
962
963 static void ppc405_ocm_init(CPUPPCState *env)
964 {
965 ppc405_ocm_t *ocm;
966
967 ocm = g_malloc0(sizeof(ppc405_ocm_t));
968 /* XXX: Size is 4096 or 0x04000000 */
969 memory_region_init_ram(&ocm->isarc_ram, "ppc405.ocm", 4096);
970 vmstate_register_ram_global(&ocm->isarc_ram);
971 memory_region_init_alias(&ocm->dsarc_ram, "ppc405.dsarc", &ocm->isarc_ram,
972 0, 4096);
973 qemu_register_reset(&ocm_reset, ocm);
974 ppc_dcr_register(env, OCM0_ISARC,
975 ocm, &dcr_read_ocm, &dcr_write_ocm);
976 ppc_dcr_register(env, OCM0_ISACNTL,
977 ocm, &dcr_read_ocm, &dcr_write_ocm);
978 ppc_dcr_register(env, OCM0_DSARC,
979 ocm, &dcr_read_ocm, &dcr_write_ocm);
980 ppc_dcr_register(env, OCM0_DSACNTL,
981 ocm, &dcr_read_ocm, &dcr_write_ocm);
982 }
983
984 /*****************************************************************************/
985 /* I2C controller */
986 typedef struct ppc4xx_i2c_t ppc4xx_i2c_t;
987 struct ppc4xx_i2c_t {
988 qemu_irq irq;
989 MemoryRegion iomem;
990 uint8_t mdata;
991 uint8_t lmadr;
992 uint8_t hmadr;
993 uint8_t cntl;
994 uint8_t mdcntl;
995 uint8_t sts;
996 uint8_t extsts;
997 uint8_t sdata;
998 uint8_t lsadr;
999 uint8_t hsadr;
1000 uint8_t clkdiv;
1001 uint8_t intrmsk;
1002 uint8_t xfrcnt;
1003 uint8_t xtcntlss;
1004 uint8_t directcntl;
1005 };
1006
1007 static uint32_t ppc4xx_i2c_readb (void *opaque, target_phys_addr_t addr)
1008 {
1009 ppc4xx_i2c_t *i2c;
1010 uint32_t ret;
1011
1012 #ifdef DEBUG_I2C
1013 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1014 #endif
1015 i2c = opaque;
1016 switch (addr) {
1017 case 0x00:
1018 // i2c_readbyte(&i2c->mdata);
1019 ret = i2c->mdata;
1020 break;
1021 case 0x02:
1022 ret = i2c->sdata;
1023 break;
1024 case 0x04:
1025 ret = i2c->lmadr;
1026 break;
1027 case 0x05:
1028 ret = i2c->hmadr;
1029 break;
1030 case 0x06:
1031 ret = i2c->cntl;
1032 break;
1033 case 0x07:
1034 ret = i2c->mdcntl;
1035 break;
1036 case 0x08:
1037 ret = i2c->sts;
1038 break;
1039 case 0x09:
1040 ret = i2c->extsts;
1041 break;
1042 case 0x0A:
1043 ret = i2c->lsadr;
1044 break;
1045 case 0x0B:
1046 ret = i2c->hsadr;
1047 break;
1048 case 0x0C:
1049 ret = i2c->clkdiv;
1050 break;
1051 case 0x0D:
1052 ret = i2c->intrmsk;
1053 break;
1054 case 0x0E:
1055 ret = i2c->xfrcnt;
1056 break;
1057 case 0x0F:
1058 ret = i2c->xtcntlss;
1059 break;
1060 case 0x10:
1061 ret = i2c->directcntl;
1062 break;
1063 default:
1064 ret = 0x00;
1065 break;
1066 }
1067 #ifdef DEBUG_I2C
1068 printf("%s: addr " TARGET_FMT_plx " %02" PRIx32 "\n", __func__, addr, ret);
1069 #endif
1070
1071 return ret;
1072 }
1073
1074 static void ppc4xx_i2c_writeb (void *opaque,
1075 target_phys_addr_t addr, uint32_t value)
1076 {
1077 ppc4xx_i2c_t *i2c;
1078
1079 #ifdef DEBUG_I2C
1080 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1081 value);
1082 #endif
1083 i2c = opaque;
1084 switch (addr) {
1085 case 0x00:
1086 i2c->mdata = value;
1087 // i2c_sendbyte(&i2c->mdata);
1088 break;
1089 case 0x02:
1090 i2c->sdata = value;
1091 break;
1092 case 0x04:
1093 i2c->lmadr = value;
1094 break;
1095 case 0x05:
1096 i2c->hmadr = value;
1097 break;
1098 case 0x06:
1099 i2c->cntl = value;
1100 break;
1101 case 0x07:
1102 i2c->mdcntl = value & 0xDF;
1103 break;
1104 case 0x08:
1105 i2c->sts &= ~(value & 0x0A);
1106 break;
1107 case 0x09:
1108 i2c->extsts &= ~(value & 0x8F);
1109 break;
1110 case 0x0A:
1111 i2c->lsadr = value;
1112 break;
1113 case 0x0B:
1114 i2c->hsadr = value;
1115 break;
1116 case 0x0C:
1117 i2c->clkdiv = value;
1118 break;
1119 case 0x0D:
1120 i2c->intrmsk = value;
1121 break;
1122 case 0x0E:
1123 i2c->xfrcnt = value & 0x77;
1124 break;
1125 case 0x0F:
1126 i2c->xtcntlss = value;
1127 break;
1128 case 0x10:
1129 i2c->directcntl = value & 0x7;
1130 break;
1131 }
1132 }
1133
1134 static uint32_t ppc4xx_i2c_readw (void *opaque, target_phys_addr_t addr)
1135 {
1136 uint32_t ret;
1137
1138 #ifdef DEBUG_I2C
1139 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1140 #endif
1141 ret = ppc4xx_i2c_readb(opaque, addr) << 8;
1142 ret |= ppc4xx_i2c_readb(opaque, addr + 1);
1143
1144 return ret;
1145 }
1146
1147 static void ppc4xx_i2c_writew (void *opaque,
1148 target_phys_addr_t addr, uint32_t value)
1149 {
1150 #ifdef DEBUG_I2C
1151 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1152 value);
1153 #endif
1154 ppc4xx_i2c_writeb(opaque, addr, value >> 8);
1155 ppc4xx_i2c_writeb(opaque, addr + 1, value);
1156 }
1157
1158 static uint32_t ppc4xx_i2c_readl (void *opaque, target_phys_addr_t addr)
1159 {
1160 uint32_t ret;
1161
1162 #ifdef DEBUG_I2C
1163 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1164 #endif
1165 ret = ppc4xx_i2c_readb(opaque, addr) << 24;
1166 ret |= ppc4xx_i2c_readb(opaque, addr + 1) << 16;
1167 ret |= ppc4xx_i2c_readb(opaque, addr + 2) << 8;
1168 ret |= ppc4xx_i2c_readb(opaque, addr + 3);
1169
1170 return ret;
1171 }
1172
1173 static void ppc4xx_i2c_writel (void *opaque,
1174 target_phys_addr_t addr, uint32_t value)
1175 {
1176 #ifdef DEBUG_I2C
1177 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1178 value);
1179 #endif
1180 ppc4xx_i2c_writeb(opaque, addr, value >> 24);
1181 ppc4xx_i2c_writeb(opaque, addr + 1, value >> 16);
1182 ppc4xx_i2c_writeb(opaque, addr + 2, value >> 8);
1183 ppc4xx_i2c_writeb(opaque, addr + 3, value);
1184 }
1185
1186 static const MemoryRegionOps i2c_ops = {
1187 .old_mmio = {
1188 .read = { ppc4xx_i2c_readb, ppc4xx_i2c_readw, ppc4xx_i2c_readl, },
1189 .write = { ppc4xx_i2c_writeb, ppc4xx_i2c_writew, ppc4xx_i2c_writel, },
1190 },
1191 .endianness = DEVICE_NATIVE_ENDIAN,
1192 };
1193
1194 static void ppc4xx_i2c_reset (void *opaque)
1195 {
1196 ppc4xx_i2c_t *i2c;
1197
1198 i2c = opaque;
1199 i2c->mdata = 0x00;
1200 i2c->sdata = 0x00;
1201 i2c->cntl = 0x00;
1202 i2c->mdcntl = 0x00;
1203 i2c->sts = 0x00;
1204 i2c->extsts = 0x00;
1205 i2c->clkdiv = 0x00;
1206 i2c->xfrcnt = 0x00;
1207 i2c->directcntl = 0x0F;
1208 }
1209
1210 static void ppc405_i2c_init(target_phys_addr_t base, qemu_irq irq)
1211 {
1212 ppc4xx_i2c_t *i2c;
1213
1214 i2c = g_malloc0(sizeof(ppc4xx_i2c_t));
1215 i2c->irq = irq;
1216 #ifdef DEBUG_I2C
1217 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
1218 #endif
1219 memory_region_init_io(&i2c->iomem, &i2c_ops, i2c, "i2c", 0x011);
1220 memory_region_add_subregion(get_system_memory(), base, &i2c->iomem);
1221 qemu_register_reset(ppc4xx_i2c_reset, i2c);
1222 }
1223
1224 /*****************************************************************************/
1225 /* General purpose timers */
1226 typedef struct ppc4xx_gpt_t ppc4xx_gpt_t;
1227 struct ppc4xx_gpt_t {
1228 MemoryRegion iomem;
1229 int64_t tb_offset;
1230 uint32_t tb_freq;
1231 struct QEMUTimer *timer;
1232 qemu_irq irqs[5];
1233 uint32_t oe;
1234 uint32_t ol;
1235 uint32_t im;
1236 uint32_t is;
1237 uint32_t ie;
1238 uint32_t comp[5];
1239 uint32_t mask[5];
1240 };
1241
1242 static uint32_t ppc4xx_gpt_readb (void *opaque, target_phys_addr_t addr)
1243 {
1244 #ifdef DEBUG_GPT
1245 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1246 #endif
1247 /* XXX: generate a bus fault */
1248 return -1;
1249 }
1250
1251 static void ppc4xx_gpt_writeb (void *opaque,
1252 target_phys_addr_t addr, uint32_t value)
1253 {
1254 #ifdef DEBUG_I2C
1255 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1256 value);
1257 #endif
1258 /* XXX: generate a bus fault */
1259 }
1260
1261 static uint32_t ppc4xx_gpt_readw (void *opaque, target_phys_addr_t addr)
1262 {
1263 #ifdef DEBUG_GPT
1264 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1265 #endif
1266 /* XXX: generate a bus fault */
1267 return -1;
1268 }
1269
1270 static void ppc4xx_gpt_writew (void *opaque,
1271 target_phys_addr_t addr, uint32_t value)
1272 {
1273 #ifdef DEBUG_I2C
1274 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1275 value);
1276 #endif
1277 /* XXX: generate a bus fault */
1278 }
1279
1280 static int ppc4xx_gpt_compare (ppc4xx_gpt_t *gpt, int n)
1281 {
1282 /* XXX: TODO */
1283 return 0;
1284 }
1285
1286 static void ppc4xx_gpt_set_output (ppc4xx_gpt_t *gpt, int n, int level)
1287 {
1288 /* XXX: TODO */
1289 }
1290
1291 static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt)
1292 {
1293 uint32_t mask;
1294 int i;
1295
1296 mask = 0x80000000;
1297 for (i = 0; i < 5; i++) {
1298 if (gpt->oe & mask) {
1299 /* Output is enabled */
1300 if (ppc4xx_gpt_compare(gpt, i)) {
1301 /* Comparison is OK */
1302 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask);
1303 } else {
1304 /* Comparison is KO */
1305 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask ? 0 : 1);
1306 }
1307 }
1308 mask = mask >> 1;
1309 }
1310 }
1311
1312 static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt)
1313 {
1314 uint32_t mask;
1315 int i;
1316
1317 mask = 0x00008000;
1318 for (i = 0; i < 5; i++) {
1319 if (gpt->is & gpt->im & mask)
1320 qemu_irq_raise(gpt->irqs[i]);
1321 else
1322 qemu_irq_lower(gpt->irqs[i]);
1323 mask = mask >> 1;
1324 }
1325 }
1326
1327 static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt)
1328 {
1329 /* XXX: TODO */
1330 }
1331
1332 static uint32_t ppc4xx_gpt_readl (void *opaque, target_phys_addr_t addr)
1333 {
1334 ppc4xx_gpt_t *gpt;
1335 uint32_t ret;
1336 int idx;
1337
1338 #ifdef DEBUG_GPT
1339 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1340 #endif
1341 gpt = opaque;
1342 switch (addr) {
1343 case 0x00:
1344 /* Time base counter */
1345 ret = muldiv64(qemu_get_clock_ns(vm_clock) + gpt->tb_offset,
1346 gpt->tb_freq, get_ticks_per_sec());
1347 break;
1348 case 0x10:
1349 /* Output enable */
1350 ret = gpt->oe;
1351 break;
1352 case 0x14:
1353 /* Output level */
1354 ret = gpt->ol;
1355 break;
1356 case 0x18:
1357 /* Interrupt mask */
1358 ret = gpt->im;
1359 break;
1360 case 0x1C:
1361 case 0x20:
1362 /* Interrupt status */
1363 ret = gpt->is;
1364 break;
1365 case 0x24:
1366 /* Interrupt enable */
1367 ret = gpt->ie;
1368 break;
1369 case 0x80 ... 0x90:
1370 /* Compare timer */
1371 idx = (addr - 0x80) >> 2;
1372 ret = gpt->comp[idx];
1373 break;
1374 case 0xC0 ... 0xD0:
1375 /* Compare mask */
1376 idx = (addr - 0xC0) >> 2;
1377 ret = gpt->mask[idx];
1378 break;
1379 default:
1380 ret = -1;
1381 break;
1382 }
1383
1384 return ret;
1385 }
1386
1387 static void ppc4xx_gpt_writel (void *opaque,
1388 target_phys_addr_t addr, uint32_t value)
1389 {
1390 ppc4xx_gpt_t *gpt;
1391 int idx;
1392
1393 #ifdef DEBUG_I2C
1394 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1395 value);
1396 #endif
1397 gpt = opaque;
1398 switch (addr) {
1399 case 0x00:
1400 /* Time base counter */
1401 gpt->tb_offset = muldiv64(value, get_ticks_per_sec(), gpt->tb_freq)
1402 - qemu_get_clock_ns(vm_clock);
1403 ppc4xx_gpt_compute_timer(gpt);
1404 break;
1405 case 0x10:
1406 /* Output enable */
1407 gpt->oe = value & 0xF8000000;
1408 ppc4xx_gpt_set_outputs(gpt);
1409 break;
1410 case 0x14:
1411 /* Output level */
1412 gpt->ol = value & 0xF8000000;
1413 ppc4xx_gpt_set_outputs(gpt);
1414 break;
1415 case 0x18:
1416 /* Interrupt mask */
1417 gpt->im = value & 0x0000F800;
1418 break;
1419 case 0x1C:
1420 /* Interrupt status set */
1421 gpt->is |= value & 0x0000F800;
1422 ppc4xx_gpt_set_irqs(gpt);
1423 break;
1424 case 0x20:
1425 /* Interrupt status clear */
1426 gpt->is &= ~(value & 0x0000F800);
1427 ppc4xx_gpt_set_irqs(gpt);
1428 break;
1429 case 0x24:
1430 /* Interrupt enable */
1431 gpt->ie = value & 0x0000F800;
1432 ppc4xx_gpt_set_irqs(gpt);
1433 break;
1434 case 0x80 ... 0x90:
1435 /* Compare timer */
1436 idx = (addr - 0x80) >> 2;
1437 gpt->comp[idx] = value & 0xF8000000;
1438 ppc4xx_gpt_compute_timer(gpt);
1439 break;
1440 case 0xC0 ... 0xD0:
1441 /* Compare mask */
1442 idx = (addr - 0xC0) >> 2;
1443 gpt->mask[idx] = value & 0xF8000000;
1444 ppc4xx_gpt_compute_timer(gpt);
1445 break;
1446 }
1447 }
1448
1449 static const MemoryRegionOps gpt_ops = {
1450 .old_mmio = {
1451 .read = { ppc4xx_gpt_readb, ppc4xx_gpt_readw, ppc4xx_gpt_readl, },
1452 .write = { ppc4xx_gpt_writeb, ppc4xx_gpt_writew, ppc4xx_gpt_writel, },
1453 },
1454 .endianness = DEVICE_NATIVE_ENDIAN,
1455 };
1456
1457 static void ppc4xx_gpt_cb (void *opaque)
1458 {
1459 ppc4xx_gpt_t *gpt;
1460
1461 gpt = opaque;
1462 ppc4xx_gpt_set_irqs(gpt);
1463 ppc4xx_gpt_set_outputs(gpt);
1464 ppc4xx_gpt_compute_timer(gpt);
1465 }
1466
1467 static void ppc4xx_gpt_reset (void *opaque)
1468 {
1469 ppc4xx_gpt_t *gpt;
1470 int i;
1471
1472 gpt = opaque;
1473 qemu_del_timer(gpt->timer);
1474 gpt->oe = 0x00000000;
1475 gpt->ol = 0x00000000;
1476 gpt->im = 0x00000000;
1477 gpt->is = 0x00000000;
1478 gpt->ie = 0x00000000;
1479 for (i = 0; i < 5; i++) {
1480 gpt->comp[i] = 0x00000000;
1481 gpt->mask[i] = 0x00000000;
1482 }
1483 }
1484
1485 static void ppc4xx_gpt_init(target_phys_addr_t base, qemu_irq irqs[5])
1486 {
1487 ppc4xx_gpt_t *gpt;
1488 int i;
1489
1490 gpt = g_malloc0(sizeof(ppc4xx_gpt_t));
1491 for (i = 0; i < 5; i++) {
1492 gpt->irqs[i] = irqs[i];
1493 }
1494 gpt->timer = qemu_new_timer_ns(vm_clock, &ppc4xx_gpt_cb, gpt);
1495 #ifdef DEBUG_GPT
1496 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
1497 #endif
1498 memory_region_init_io(&gpt->iomem, &gpt_ops, gpt, "gpt", 0x0d4);
1499 memory_region_add_subregion(get_system_memory(), base, &gpt->iomem);
1500 qemu_register_reset(ppc4xx_gpt_reset, gpt);
1501 }
1502
1503 /*****************************************************************************/
1504 /* MAL */
1505 enum {
1506 MAL0_CFG = 0x180,
1507 MAL0_ESR = 0x181,
1508 MAL0_IER = 0x182,
1509 MAL0_TXCASR = 0x184,
1510 MAL0_TXCARR = 0x185,
1511 MAL0_TXEOBISR = 0x186,
1512 MAL0_TXDEIR = 0x187,
1513 MAL0_RXCASR = 0x190,
1514 MAL0_RXCARR = 0x191,
1515 MAL0_RXEOBISR = 0x192,
1516 MAL0_RXDEIR = 0x193,
1517 MAL0_TXCTP0R = 0x1A0,
1518 MAL0_TXCTP1R = 0x1A1,
1519 MAL0_TXCTP2R = 0x1A2,
1520 MAL0_TXCTP3R = 0x1A3,
1521 MAL0_RXCTP0R = 0x1C0,
1522 MAL0_RXCTP1R = 0x1C1,
1523 MAL0_RCBS0 = 0x1E0,
1524 MAL0_RCBS1 = 0x1E1,
1525 };
1526
1527 typedef struct ppc40x_mal_t ppc40x_mal_t;
1528 struct ppc40x_mal_t {
1529 qemu_irq irqs[4];
1530 uint32_t cfg;
1531 uint32_t esr;
1532 uint32_t ier;
1533 uint32_t txcasr;
1534 uint32_t txcarr;
1535 uint32_t txeobisr;
1536 uint32_t txdeir;
1537 uint32_t rxcasr;
1538 uint32_t rxcarr;
1539 uint32_t rxeobisr;
1540 uint32_t rxdeir;
1541 uint32_t txctpr[4];
1542 uint32_t rxctpr[2];
1543 uint32_t rcbs[2];
1544 };
1545
1546 static void ppc40x_mal_reset (void *opaque);
1547
1548 static uint32_t dcr_read_mal (void *opaque, int dcrn)
1549 {
1550 ppc40x_mal_t *mal;
1551 uint32_t ret;
1552
1553 mal = opaque;
1554 switch (dcrn) {
1555 case MAL0_CFG:
1556 ret = mal->cfg;
1557 break;
1558 case MAL0_ESR:
1559 ret = mal->esr;
1560 break;
1561 case MAL0_IER:
1562 ret = mal->ier;
1563 break;
1564 case MAL0_TXCASR:
1565 ret = mal->txcasr;
1566 break;
1567 case MAL0_TXCARR:
1568 ret = mal->txcarr;
1569 break;
1570 case MAL0_TXEOBISR:
1571 ret = mal->txeobisr;
1572 break;
1573 case MAL0_TXDEIR:
1574 ret = mal->txdeir;
1575 break;
1576 case MAL0_RXCASR:
1577 ret = mal->rxcasr;
1578 break;
1579 case MAL0_RXCARR:
1580 ret = mal->rxcarr;
1581 break;
1582 case MAL0_RXEOBISR:
1583 ret = mal->rxeobisr;
1584 break;
1585 case MAL0_RXDEIR:
1586 ret = mal->rxdeir;
1587 break;
1588 case MAL0_TXCTP0R:
1589 ret = mal->txctpr[0];
1590 break;
1591 case MAL0_TXCTP1R:
1592 ret = mal->txctpr[1];
1593 break;
1594 case MAL0_TXCTP2R:
1595 ret = mal->txctpr[2];
1596 break;
1597 case MAL0_TXCTP3R:
1598 ret = mal->txctpr[3];
1599 break;
1600 case MAL0_RXCTP0R:
1601 ret = mal->rxctpr[0];
1602 break;
1603 case MAL0_RXCTP1R:
1604 ret = mal->rxctpr[1];
1605 break;
1606 case MAL0_RCBS0:
1607 ret = mal->rcbs[0];
1608 break;
1609 case MAL0_RCBS1:
1610 ret = mal->rcbs[1];
1611 break;
1612 default:
1613 ret = 0;
1614 break;
1615 }
1616
1617 return ret;
1618 }
1619
1620 static void dcr_write_mal (void *opaque, int dcrn, uint32_t val)
1621 {
1622 ppc40x_mal_t *mal;
1623 int idx;
1624
1625 mal = opaque;
1626 switch (dcrn) {
1627 case MAL0_CFG:
1628 if (val & 0x80000000)
1629 ppc40x_mal_reset(mal);
1630 mal->cfg = val & 0x00FFC087;
1631 break;
1632 case MAL0_ESR:
1633 /* Read/clear */
1634 mal->esr &= ~val;
1635 break;
1636 case MAL0_IER:
1637 mal->ier = val & 0x0000001F;
1638 break;
1639 case MAL0_TXCASR:
1640 mal->txcasr = val & 0xF0000000;
1641 break;
1642 case MAL0_TXCARR:
1643 mal->txcarr = val & 0xF0000000;
1644 break;
1645 case MAL0_TXEOBISR:
1646 /* Read/clear */
1647 mal->txeobisr &= ~val;
1648 break;
1649 case MAL0_TXDEIR:
1650 /* Read/clear */
1651 mal->txdeir &= ~val;
1652 break;
1653 case MAL0_RXCASR:
1654 mal->rxcasr = val & 0xC0000000;
1655 break;
1656 case MAL0_RXCARR:
1657 mal->rxcarr = val & 0xC0000000;
1658 break;
1659 case MAL0_RXEOBISR:
1660 /* Read/clear */
1661 mal->rxeobisr &= ~val;
1662 break;
1663 case MAL0_RXDEIR:
1664 /* Read/clear */
1665 mal->rxdeir &= ~val;
1666 break;
1667 case MAL0_TXCTP0R:
1668 idx = 0;
1669 goto update_tx_ptr;
1670 case MAL0_TXCTP1R:
1671 idx = 1;
1672 goto update_tx_ptr;
1673 case MAL0_TXCTP2R:
1674 idx = 2;
1675 goto update_tx_ptr;
1676 case MAL0_TXCTP3R:
1677 idx = 3;
1678 update_tx_ptr:
1679 mal->txctpr[idx] = val;
1680 break;
1681 case MAL0_RXCTP0R:
1682 idx = 0;
1683 goto update_rx_ptr;
1684 case MAL0_RXCTP1R:
1685 idx = 1;
1686 update_rx_ptr:
1687 mal->rxctpr[idx] = val;
1688 break;
1689 case MAL0_RCBS0:
1690 idx = 0;
1691 goto update_rx_size;
1692 case MAL0_RCBS1:
1693 idx = 1;
1694 update_rx_size:
1695 mal->rcbs[idx] = val & 0x000000FF;
1696 break;
1697 }
1698 }
1699
1700 static void ppc40x_mal_reset (void *opaque)
1701 {
1702 ppc40x_mal_t *mal;
1703
1704 mal = opaque;
1705 mal->cfg = 0x0007C000;
1706 mal->esr = 0x00000000;
1707 mal->ier = 0x00000000;
1708 mal->rxcasr = 0x00000000;
1709 mal->rxdeir = 0x00000000;
1710 mal->rxeobisr = 0x00000000;
1711 mal->txcasr = 0x00000000;
1712 mal->txdeir = 0x00000000;
1713 mal->txeobisr = 0x00000000;
1714 }
1715
1716 static void ppc405_mal_init(CPUPPCState *env, qemu_irq irqs[4])
1717 {
1718 ppc40x_mal_t *mal;
1719 int i;
1720
1721 mal = g_malloc0(sizeof(ppc40x_mal_t));
1722 for (i = 0; i < 4; i++)
1723 mal->irqs[i] = irqs[i];
1724 qemu_register_reset(&ppc40x_mal_reset, mal);
1725 ppc_dcr_register(env, MAL0_CFG,
1726 mal, &dcr_read_mal, &dcr_write_mal);
1727 ppc_dcr_register(env, MAL0_ESR,
1728 mal, &dcr_read_mal, &dcr_write_mal);
1729 ppc_dcr_register(env, MAL0_IER,
1730 mal, &dcr_read_mal, &dcr_write_mal);
1731 ppc_dcr_register(env, MAL0_TXCASR,
1732 mal, &dcr_read_mal, &dcr_write_mal);
1733 ppc_dcr_register(env, MAL0_TXCARR,
1734 mal, &dcr_read_mal, &dcr_write_mal);
1735 ppc_dcr_register(env, MAL0_TXEOBISR,
1736 mal, &dcr_read_mal, &dcr_write_mal);
1737 ppc_dcr_register(env, MAL0_TXDEIR,
1738 mal, &dcr_read_mal, &dcr_write_mal);
1739 ppc_dcr_register(env, MAL0_RXCASR,
1740 mal, &dcr_read_mal, &dcr_write_mal);
1741 ppc_dcr_register(env, MAL0_RXCARR,
1742 mal, &dcr_read_mal, &dcr_write_mal);
1743 ppc_dcr_register(env, MAL0_RXEOBISR,
1744 mal, &dcr_read_mal, &dcr_write_mal);
1745 ppc_dcr_register(env, MAL0_RXDEIR,
1746 mal, &dcr_read_mal, &dcr_write_mal);
1747 ppc_dcr_register(env, MAL0_TXCTP0R,
1748 mal, &dcr_read_mal, &dcr_write_mal);
1749 ppc_dcr_register(env, MAL0_TXCTP1R,
1750 mal, &dcr_read_mal, &dcr_write_mal);
1751 ppc_dcr_register(env, MAL0_TXCTP2R,
1752 mal, &dcr_read_mal, &dcr_write_mal);
1753 ppc_dcr_register(env, MAL0_TXCTP3R,
1754 mal, &dcr_read_mal, &dcr_write_mal);
1755 ppc_dcr_register(env, MAL0_RXCTP0R,
1756 mal, &dcr_read_mal, &dcr_write_mal);
1757 ppc_dcr_register(env, MAL0_RXCTP1R,
1758 mal, &dcr_read_mal, &dcr_write_mal);
1759 ppc_dcr_register(env, MAL0_RCBS0,
1760 mal, &dcr_read_mal, &dcr_write_mal);
1761 ppc_dcr_register(env, MAL0_RCBS1,
1762 mal, &dcr_read_mal, &dcr_write_mal);
1763 }
1764
1765 /*****************************************************************************/
1766 /* SPR */
1767 void ppc40x_core_reset (CPUPPCState *env)
1768 {
1769 target_ulong dbsr;
1770
1771 printf("Reset PowerPC core\n");
1772 cpu_interrupt(env, CPU_INTERRUPT_RESET);
1773 dbsr = env->spr[SPR_40x_DBSR];
1774 dbsr &= ~0x00000300;
1775 dbsr |= 0x00000100;
1776 env->spr[SPR_40x_DBSR] = dbsr;
1777 }
1778
1779 void ppc40x_chip_reset (CPUPPCState *env)
1780 {
1781 target_ulong dbsr;
1782
1783 printf("Reset PowerPC chip\n");
1784 cpu_interrupt(env, CPU_INTERRUPT_RESET);
1785 /* XXX: TODO reset all internal peripherals */
1786 dbsr = env->spr[SPR_40x_DBSR];
1787 dbsr &= ~0x00000300;
1788 dbsr |= 0x00000200;
1789 env->spr[SPR_40x_DBSR] = dbsr;
1790 }
1791
1792 void ppc40x_system_reset (CPUPPCState *env)
1793 {
1794 printf("Reset PowerPC system\n");
1795 qemu_system_reset_request();
1796 }
1797
1798 void store_40x_dbcr0 (CPUPPCState *env, uint32_t val)
1799 {
1800 switch ((val >> 28) & 0x3) {
1801 case 0x0:
1802 /* No action */
1803 break;
1804 case 0x1:
1805 /* Core reset */
1806 ppc40x_core_reset(env);
1807 break;
1808 case 0x2:
1809 /* Chip reset */
1810 ppc40x_chip_reset(env);
1811 break;
1812 case 0x3:
1813 /* System reset */
1814 ppc40x_system_reset(env);
1815 break;
1816 }
1817 }
1818
1819 /*****************************************************************************/
1820 /* PowerPC 405CR */
1821 enum {
1822 PPC405CR_CPC0_PLLMR = 0x0B0,
1823 PPC405CR_CPC0_CR0 = 0x0B1,
1824 PPC405CR_CPC0_CR1 = 0x0B2,
1825 PPC405CR_CPC0_PSR = 0x0B4,
1826 PPC405CR_CPC0_JTAGID = 0x0B5,
1827 PPC405CR_CPC0_ER = 0x0B9,
1828 PPC405CR_CPC0_FR = 0x0BA,
1829 PPC405CR_CPC0_SR = 0x0BB,
1830 };
1831
1832 enum {
1833 PPC405CR_CPU_CLK = 0,
1834 PPC405CR_TMR_CLK = 1,
1835 PPC405CR_PLB_CLK = 2,
1836 PPC405CR_SDRAM_CLK = 3,
1837 PPC405CR_OPB_CLK = 4,
1838 PPC405CR_EXT_CLK = 5,
1839 PPC405CR_UART_CLK = 6,
1840 PPC405CR_CLK_NB = 7,
1841 };
1842
1843 typedef struct ppc405cr_cpc_t ppc405cr_cpc_t;
1844 struct ppc405cr_cpc_t {
1845 clk_setup_t clk_setup[PPC405CR_CLK_NB];
1846 uint32_t sysclk;
1847 uint32_t psr;
1848 uint32_t cr0;
1849 uint32_t cr1;
1850 uint32_t jtagid;
1851 uint32_t pllmr;
1852 uint32_t er;
1853 uint32_t fr;
1854 };
1855
1856 static void ppc405cr_clk_setup (ppc405cr_cpc_t *cpc)
1857 {
1858 uint64_t VCO_out, PLL_out;
1859 uint32_t CPU_clk, TMR_clk, SDRAM_clk, PLB_clk, OPB_clk, EXT_clk, UART_clk;
1860 int M, D0, D1, D2;
1861
1862 D0 = ((cpc->pllmr >> 26) & 0x3) + 1; /* CBDV */
1863 if (cpc->pllmr & 0x80000000) {
1864 D1 = (((cpc->pllmr >> 20) - 1) & 0xF) + 1; /* FBDV */
1865 D2 = 8 - ((cpc->pllmr >> 16) & 0x7); /* FWDVA */
1866 M = D0 * D1 * D2;
1867 VCO_out = cpc->sysclk * M;
1868 if (VCO_out < 400000000 || VCO_out > 800000000) {
1869 /* PLL cannot lock */
1870 cpc->pllmr &= ~0x80000000;
1871 goto bypass_pll;
1872 }
1873 PLL_out = VCO_out / D2;
1874 } else {
1875 /* Bypass PLL */
1876 bypass_pll:
1877 M = D0;
1878 PLL_out = cpc->sysclk * M;
1879 }
1880 CPU_clk = PLL_out;
1881 if (cpc->cr1 & 0x00800000)
1882 TMR_clk = cpc->sysclk; /* Should have a separate clock */
1883 else
1884 TMR_clk = CPU_clk;
1885 PLB_clk = CPU_clk / D0;
1886 SDRAM_clk = PLB_clk;
1887 D0 = ((cpc->pllmr >> 10) & 0x3) + 1;
1888 OPB_clk = PLB_clk / D0;
1889 D0 = ((cpc->pllmr >> 24) & 0x3) + 2;
1890 EXT_clk = PLB_clk / D0;
1891 D0 = ((cpc->cr0 >> 1) & 0x1F) + 1;
1892 UART_clk = CPU_clk / D0;
1893 /* Setup CPU clocks */
1894 clk_setup(&cpc->clk_setup[PPC405CR_CPU_CLK], CPU_clk);
1895 /* Setup time-base clock */
1896 clk_setup(&cpc->clk_setup[PPC405CR_TMR_CLK], TMR_clk);
1897 /* Setup PLB clock */
1898 clk_setup(&cpc->clk_setup[PPC405CR_PLB_CLK], PLB_clk);
1899 /* Setup SDRAM clock */
1900 clk_setup(&cpc->clk_setup[PPC405CR_SDRAM_CLK], SDRAM_clk);
1901 /* Setup OPB clock */
1902 clk_setup(&cpc->clk_setup[PPC405CR_OPB_CLK], OPB_clk);
1903 /* Setup external clock */
1904 clk_setup(&cpc->clk_setup[PPC405CR_EXT_CLK], EXT_clk);
1905 /* Setup UART clock */
1906 clk_setup(&cpc->clk_setup[PPC405CR_UART_CLK], UART_clk);
1907 }
1908
1909 static uint32_t dcr_read_crcpc (void *opaque, int dcrn)
1910 {
1911 ppc405cr_cpc_t *cpc;
1912 uint32_t ret;
1913
1914 cpc = opaque;
1915 switch (dcrn) {
1916 case PPC405CR_CPC0_PLLMR:
1917 ret = cpc->pllmr;
1918 break;
1919 case PPC405CR_CPC0_CR0:
1920 ret = cpc->cr0;
1921 break;
1922 case PPC405CR_CPC0_CR1:
1923 ret = cpc->cr1;
1924 break;
1925 case PPC405CR_CPC0_PSR:
1926 ret = cpc->psr;
1927 break;
1928 case PPC405CR_CPC0_JTAGID:
1929 ret = cpc->jtagid;
1930 break;
1931 case PPC405CR_CPC0_ER:
1932 ret = cpc->er;
1933 break;
1934 case PPC405CR_CPC0_FR:
1935 ret = cpc->fr;
1936 break;
1937 case PPC405CR_CPC0_SR:
1938 ret = ~(cpc->er | cpc->fr) & 0xFFFF0000;
1939 break;
1940 default:
1941 /* Avoid gcc warning */
1942 ret = 0;
1943 break;
1944 }
1945
1946 return ret;
1947 }
1948
1949 static void dcr_write_crcpc (void *opaque, int dcrn, uint32_t val)
1950 {
1951 ppc405cr_cpc_t *cpc;
1952
1953 cpc = opaque;
1954 switch (dcrn) {
1955 case PPC405CR_CPC0_PLLMR:
1956 cpc->pllmr = val & 0xFFF77C3F;
1957 break;
1958 case PPC405CR_CPC0_CR0:
1959 cpc->cr0 = val & 0x0FFFFFFE;
1960 break;
1961 case PPC405CR_CPC0_CR1:
1962 cpc->cr1 = val & 0x00800000;
1963 break;
1964 case PPC405CR_CPC0_PSR:
1965 /* Read-only */
1966 break;
1967 case PPC405CR_CPC0_JTAGID:
1968 /* Read-only */
1969 break;
1970 case PPC405CR_CPC0_ER:
1971 cpc->er = val & 0xBFFC0000;
1972 break;
1973 case PPC405CR_CPC0_FR:
1974 cpc->fr = val & 0xBFFC0000;
1975 break;
1976 case PPC405CR_CPC0_SR:
1977 /* Read-only */
1978 break;
1979 }
1980 }
1981
1982 static void ppc405cr_cpc_reset (void *opaque)
1983 {
1984 ppc405cr_cpc_t *cpc;
1985 int D;
1986
1987 cpc = opaque;
1988 /* Compute PLLMR value from PSR settings */
1989 cpc->pllmr = 0x80000000;
1990 /* PFWD */
1991 switch ((cpc->psr >> 30) & 3) {
1992 case 0:
1993 /* Bypass */
1994 cpc->pllmr &= ~0x80000000;
1995 break;
1996 case 1:
1997 /* Divide by 3 */
1998 cpc->pllmr |= 5 << 16;
1999 break;
2000 case 2:
2001 /* Divide by 4 */
2002 cpc->pllmr |= 4 << 16;
2003 break;
2004 case 3:
2005 /* Divide by 6 */
2006 cpc->pllmr |= 2 << 16;
2007 break;
2008 }
2009 /* PFBD */
2010 D = (cpc->psr >> 28) & 3;
2011 cpc->pllmr |= (D + 1) << 20;
2012 /* PT */
2013 D = (cpc->psr >> 25) & 7;
2014 switch (D) {
2015 case 0x2:
2016 cpc->pllmr |= 0x13;
2017 break;
2018 case 0x4:
2019 cpc->pllmr |= 0x15;
2020 break;
2021 case 0x5:
2022 cpc->pllmr |= 0x16;
2023 break;
2024 default:
2025 break;
2026 }
2027 /* PDC */
2028 D = (cpc->psr >> 23) & 3;
2029 cpc->pllmr |= D << 26;
2030 /* ODP */
2031 D = (cpc->psr >> 21) & 3;
2032 cpc->pllmr |= D << 10;
2033 /* EBPD */
2034 D = (cpc->psr >> 17) & 3;
2035 cpc->pllmr |= D << 24;
2036 cpc->cr0 = 0x0000003C;
2037 cpc->cr1 = 0x2B0D8800;
2038 cpc->er = 0x00000000;
2039 cpc->fr = 0x00000000;
2040 ppc405cr_clk_setup(cpc);
2041 }
2042
2043 static void ppc405cr_clk_init (ppc405cr_cpc_t *cpc)
2044 {
2045 int D;
2046
2047 /* XXX: this should be read from IO pins */
2048 cpc->psr = 0x00000000; /* 8 bits ROM */
2049 /* PFWD */
2050 D = 0x2; /* Divide by 4 */
2051 cpc->psr |= D << 30;
2052 /* PFBD */
2053 D = 0x1; /* Divide by 2 */
2054 cpc->psr |= D << 28;
2055 /* PDC */
2056 D = 0x1; /* Divide by 2 */
2057 cpc->psr |= D << 23;
2058 /* PT */
2059 D = 0x5; /* M = 16 */
2060 cpc->psr |= D << 25;
2061 /* ODP */
2062 D = 0x1; /* Divide by 2 */
2063 cpc->psr |= D << 21;
2064 /* EBDP */
2065 D = 0x2; /* Divide by 4 */
2066 cpc->psr |= D << 17;
2067 }
2068
2069 static void ppc405cr_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[7],
2070 uint32_t sysclk)
2071 {
2072 ppc405cr_cpc_t *cpc;
2073
2074 cpc = g_malloc0(sizeof(ppc405cr_cpc_t));
2075 memcpy(cpc->clk_setup, clk_setup,
2076 PPC405CR_CLK_NB * sizeof(clk_setup_t));
2077 cpc->sysclk = sysclk;
2078 cpc->jtagid = 0x42051049;
2079 ppc_dcr_register(env, PPC405CR_CPC0_PSR, cpc,
2080 &dcr_read_crcpc, &dcr_write_crcpc);
2081 ppc_dcr_register(env, PPC405CR_CPC0_CR0, cpc,
2082 &dcr_read_crcpc, &dcr_write_crcpc);
2083 ppc_dcr_register(env, PPC405CR_CPC0_CR1, cpc,
2084 &dcr_read_crcpc, &dcr_write_crcpc);
2085 ppc_dcr_register(env, PPC405CR_CPC0_JTAGID, cpc,
2086 &dcr_read_crcpc, &dcr_write_crcpc);
2087 ppc_dcr_register(env, PPC405CR_CPC0_PLLMR, cpc,
2088 &dcr_read_crcpc, &dcr_write_crcpc);
2089 ppc_dcr_register(env, PPC405CR_CPC0_ER, cpc,
2090 &dcr_read_crcpc, &dcr_write_crcpc);
2091 ppc_dcr_register(env, PPC405CR_CPC0_FR, cpc,
2092 &dcr_read_crcpc, &dcr_write_crcpc);
2093 ppc_dcr_register(env, PPC405CR_CPC0_SR, cpc,
2094 &dcr_read_crcpc, &dcr_write_crcpc);
2095 ppc405cr_clk_init(cpc);
2096 qemu_register_reset(ppc405cr_cpc_reset, cpc);
2097 }
2098
2099 CPUPPCState *ppc405cr_init(MemoryRegion *address_space_mem,
2100 MemoryRegion ram_memories[4],
2101 target_phys_addr_t ram_bases[4],
2102 target_phys_addr_t ram_sizes[4],
2103 uint32_t sysclk, qemu_irq **picp,
2104 int do_init)
2105 {
2106 clk_setup_t clk_setup[PPC405CR_CLK_NB];
2107 qemu_irq dma_irqs[4];
2108 CPUPPCState *env;
2109 qemu_irq *pic, *irqs;
2110
2111 memset(clk_setup, 0, sizeof(clk_setup));
2112 env = ppc4xx_init("405cr", &clk_setup[PPC405CR_CPU_CLK],
2113 &clk_setup[PPC405CR_TMR_CLK], sysclk);
2114 /* Memory mapped devices registers */
2115 /* PLB arbitrer */
2116 ppc4xx_plb_init(env);
2117 /* PLB to OPB bridge */
2118 ppc4xx_pob_init(env);
2119 /* OBP arbitrer */
2120 ppc4xx_opba_init(0xef600600);
2121 /* Universal interrupt controller */
2122 irqs = g_malloc0(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
2123 irqs[PPCUIC_OUTPUT_INT] =
2124 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
2125 irqs[PPCUIC_OUTPUT_CINT] =
2126 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
2127 pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
2128 *picp = pic;
2129 /* SDRAM controller */
2130 ppc4xx_sdram_init(env, pic[14], 1, ram_memories,
2131 ram_bases, ram_sizes, do_init);
2132 /* External bus controller */
2133 ppc405_ebc_init(env);
2134 /* DMA controller */
2135 dma_irqs[0] = pic[26];
2136 dma_irqs[1] = pic[25];
2137 dma_irqs[2] = pic[24];
2138 dma_irqs[3] = pic[23];
2139 ppc405_dma_init(env, dma_irqs);
2140 /* Serial ports */
2141 if (serial_hds[0] != NULL) {
2142 serial_mm_init(address_space_mem, 0xef600300, 0, pic[0],
2143 PPC_SERIAL_MM_BAUDBASE, serial_hds[0],
2144 DEVICE_BIG_ENDIAN);
2145 }
2146 if (serial_hds[1] != NULL) {
2147 serial_mm_init(address_space_mem, 0xef600400, 0, pic[1],
2148 PPC_SERIAL_MM_BAUDBASE, serial_hds[1],
2149 DEVICE_BIG_ENDIAN);
2150 }
2151 /* IIC controller */
2152 ppc405_i2c_init(0xef600500, pic[2]);
2153 /* GPIO */
2154 ppc405_gpio_init(0xef600700);
2155 /* CPU control */
2156 ppc405cr_cpc_init(env, clk_setup, sysclk);
2157
2158 return env;
2159 }
2160
2161 /*****************************************************************************/
2162 /* PowerPC 405EP */
2163 /* CPU control */
2164 enum {
2165 PPC405EP_CPC0_PLLMR0 = 0x0F0,
2166 PPC405EP_CPC0_BOOT = 0x0F1,
2167 PPC405EP_CPC0_EPCTL = 0x0F3,
2168 PPC405EP_CPC0_PLLMR1 = 0x0F4,
2169 PPC405EP_CPC0_UCR = 0x0F5,
2170 PPC405EP_CPC0_SRR = 0x0F6,
2171 PPC405EP_CPC0_JTAGID = 0x0F7,
2172 PPC405EP_CPC0_PCI = 0x0F9,
2173 #if 0
2174 PPC405EP_CPC0_ER = xxx,
2175 PPC405EP_CPC0_FR = xxx,
2176 PPC405EP_CPC0_SR = xxx,
2177 #endif
2178 };
2179
2180 enum {
2181 PPC405EP_CPU_CLK = 0,
2182 PPC405EP_PLB_CLK = 1,
2183 PPC405EP_OPB_CLK = 2,
2184 PPC405EP_EBC_CLK = 3,
2185 PPC405EP_MAL_CLK = 4,
2186 PPC405EP_PCI_CLK = 5,
2187 PPC405EP_UART0_CLK = 6,
2188 PPC405EP_UART1_CLK = 7,
2189 PPC405EP_CLK_NB = 8,
2190 };
2191
2192 typedef struct ppc405ep_cpc_t ppc405ep_cpc_t;
2193 struct ppc405ep_cpc_t {
2194 uint32_t sysclk;
2195 clk_setup_t clk_setup[PPC405EP_CLK_NB];
2196 uint32_t boot;
2197 uint32_t epctl;
2198 uint32_t pllmr[2];
2199 uint32_t ucr;
2200 uint32_t srr;
2201 uint32_t jtagid;
2202 uint32_t pci;
2203 /* Clock and power management */
2204 uint32_t er;
2205 uint32_t fr;
2206 uint32_t sr;
2207 };
2208
2209 static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc)
2210 {
2211 uint32_t CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk;
2212 uint32_t UART0_clk, UART1_clk;
2213 uint64_t VCO_out, PLL_out;
2214 int M, D;
2215
2216 VCO_out = 0;
2217 if ((cpc->pllmr[1] & 0x80000000) && !(cpc->pllmr[1] & 0x40000000)) {
2218 M = (((cpc->pllmr[1] >> 20) - 1) & 0xF) + 1; /* FBMUL */
2219 #ifdef DEBUG_CLOCKS_LL
2220 printf("FBMUL %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 20) & 0xF, M);
2221 #endif
2222 D = 8 - ((cpc->pllmr[1] >> 16) & 0x7); /* FWDA */
2223 #ifdef DEBUG_CLOCKS_LL
2224 printf("FWDA %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 16) & 0x7, D);
2225 #endif
2226 VCO_out = cpc->sysclk * M * D;
2227 if (VCO_out < 500000000UL || VCO_out > 1000000000UL) {
2228 /* Error - unlock the PLL */
2229 printf("VCO out of range %" PRIu64 "\n", VCO_out);
2230 #if 0
2231 cpc->pllmr[1] &= ~0x80000000;
2232 goto pll_bypass;
2233 #endif
2234 }
2235 PLL_out = VCO_out / D;
2236 /* Pretend the PLL is locked */
2237 cpc->boot |= 0x00000001;
2238 } else {
2239 #if 0
2240 pll_bypass:
2241 #endif
2242 PLL_out = cpc->sysclk;
2243 if (cpc->pllmr[1] & 0x40000000) {
2244 /* Pretend the PLL is not locked */
2245 cpc->boot &= ~0x00000001;
2246 }
2247 }
2248 /* Now, compute all other clocks */
2249 D = ((cpc->pllmr[0] >> 20) & 0x3) + 1; /* CCDV */
2250 #ifdef DEBUG_CLOCKS_LL
2251 printf("CCDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 20) & 0x3, D);
2252 #endif
2253 CPU_clk = PLL_out / D;
2254 D = ((cpc->pllmr[0] >> 16) & 0x3) + 1; /* CBDV */
2255 #ifdef DEBUG_CLOCKS_LL
2256 printf("CBDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 16) & 0x3, D);
2257 #endif
2258 PLB_clk = CPU_clk / D;
2259 D = ((cpc->pllmr[0] >> 12) & 0x3) + 1; /* OPDV */
2260 #ifdef DEBUG_CLOCKS_LL
2261 printf("OPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 12) & 0x3, D);
2262 #endif
2263 OPB_clk = PLB_clk / D;
2264 D = ((cpc->pllmr[0] >> 8) & 0x3) + 2; /* EPDV */
2265 #ifdef DEBUG_CLOCKS_LL
2266 printf("EPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 8) & 0x3, D);
2267 #endif
2268 EBC_clk = PLB_clk / D;
2269 D = ((cpc->pllmr[0] >> 4) & 0x3) + 1; /* MPDV */
2270 #ifdef DEBUG_CLOCKS_LL
2271 printf("MPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 4) & 0x3, D);
2272 #endif
2273 MAL_clk = PLB_clk / D;
2274 D = (cpc->pllmr[0] & 0x3) + 1; /* PPDV */
2275 #ifdef DEBUG_CLOCKS_LL
2276 printf("PPDV %01" PRIx32 " %d\n", cpc->pllmr[0] & 0x3, D);
2277 #endif
2278 PCI_clk = PLB_clk / D;
2279 D = ((cpc->ucr - 1) & 0x7F) + 1; /* U0DIV */
2280 #ifdef DEBUG_CLOCKS_LL
2281 printf("U0DIV %01" PRIx32 " %d\n", cpc->ucr & 0x7F, D);
2282 #endif
2283 UART0_clk = PLL_out / D;
2284 D = (((cpc->ucr >> 8) - 1) & 0x7F) + 1; /* U1DIV */
2285 #ifdef DEBUG_CLOCKS_LL
2286 printf("U1DIV %01" PRIx32 " %d\n", (cpc->ucr >> 8) & 0x7F, D);
2287 #endif
2288 UART1_clk = PLL_out / D;
2289 #ifdef DEBUG_CLOCKS
2290 printf("Setup PPC405EP clocks - sysclk %" PRIu32 " VCO %" PRIu64
2291 " PLL out %" PRIu64 " Hz\n", cpc->sysclk, VCO_out, PLL_out);
2292 printf("CPU %" PRIu32 " PLB %" PRIu32 " OPB %" PRIu32 " EBC %" PRIu32
2293 " MAL %" PRIu32 " PCI %" PRIu32 " UART0 %" PRIu32
2294 " UART1 %" PRIu32 "\n",
2295 CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk,
2296 UART0_clk, UART1_clk);
2297 #endif
2298 /* Setup CPU clocks */
2299 clk_setup(&cpc->clk_setup[PPC405EP_CPU_CLK], CPU_clk);
2300 /* Setup PLB clock */
2301 clk_setup(&cpc->clk_setup[PPC405EP_PLB_CLK], PLB_clk);
2302 /* Setup OPB clock */
2303 clk_setup(&cpc->clk_setup[PPC405EP_OPB_CLK], OPB_clk);
2304 /* Setup external clock */
2305 clk_setup(&cpc->clk_setup[PPC405EP_EBC_CLK], EBC_clk);
2306 /* Setup MAL clock */
2307 clk_setup(&cpc->clk_setup[PPC405EP_MAL_CLK], MAL_clk);
2308 /* Setup PCI clock */
2309 clk_setup(&cpc->clk_setup[PPC405EP_PCI_CLK], PCI_clk);
2310 /* Setup UART0 clock */
2311 clk_setup(&cpc->clk_setup[PPC405EP_UART0_CLK], UART0_clk);
2312 /* Setup UART1 clock */
2313 clk_setup(&cpc->clk_setup[PPC405EP_UART1_CLK], UART1_clk);
2314 }
2315
2316 static uint32_t dcr_read_epcpc (void *opaque, int dcrn)
2317 {
2318 ppc405ep_cpc_t *cpc;
2319 uint32_t ret;
2320
2321 cpc = opaque;
2322 switch (dcrn) {
2323 case PPC405EP_CPC0_BOOT:
2324 ret = cpc->boot;
2325 break;
2326 case PPC405EP_CPC0_EPCTL:
2327 ret = cpc->epctl;
2328 break;
2329 case PPC405EP_CPC0_PLLMR0:
2330 ret = cpc->pllmr[0];
2331 break;
2332 case PPC405EP_CPC0_PLLMR1:
2333 ret = cpc->pllmr[1];
2334 break;
2335 case PPC405EP_CPC0_UCR:
2336 ret = cpc->ucr;
2337 break;
2338 case PPC405EP_CPC0_SRR:
2339 ret = cpc->srr;
2340 break;
2341 case PPC405EP_CPC0_JTAGID:
2342 ret = cpc->jtagid;
2343 break;
2344 case PPC405EP_CPC0_PCI:
2345 ret = cpc->pci;
2346 break;
2347 default:
2348 /* Avoid gcc warning */
2349 ret = 0;
2350 break;
2351 }
2352
2353 return ret;
2354 }
2355
2356 static void dcr_write_epcpc (void *opaque, int dcrn, uint32_t val)
2357 {
2358 ppc405ep_cpc_t *cpc;
2359
2360 cpc = opaque;
2361 switch (dcrn) {
2362 case PPC405EP_CPC0_BOOT:
2363 /* Read-only register */
2364 break;
2365 case PPC405EP_CPC0_EPCTL:
2366 /* Don't care for now */
2367 cpc->epctl = val & 0xC00000F3;
2368 break;
2369 case PPC405EP_CPC0_PLLMR0:
2370 cpc->pllmr[0] = val & 0x00633333;
2371 ppc405ep_compute_clocks(cpc);
2372 break;
2373 case PPC405EP_CPC0_PLLMR1:
2374 cpc->pllmr[1] = val & 0xC0F73FFF;
2375 ppc405ep_compute_clocks(cpc);
2376 break;
2377 case PPC405EP_CPC0_UCR:
2378 /* UART control - don't care for now */
2379 cpc->ucr = val & 0x003F7F7F;
2380 break;
2381 case PPC405EP_CPC0_SRR:
2382 cpc->srr = val;
2383 break;
2384 case PPC405EP_CPC0_JTAGID:
2385 /* Read-only */
2386 break;
2387 case PPC405EP_CPC0_PCI:
2388 cpc->pci = val;
2389 break;
2390 }
2391 }
2392
2393 static void ppc405ep_cpc_reset (void *opaque)
2394 {
2395 ppc405ep_cpc_t *cpc = opaque;
2396
2397 cpc->boot = 0x00000010; /* Boot from PCI - IIC EEPROM disabled */
2398 cpc->epctl = 0x00000000;
2399 cpc->pllmr[0] = 0x00011010;
2400 cpc->pllmr[1] = 0x40000000;
2401 cpc->ucr = 0x00000000;
2402 cpc->srr = 0x00040000;
2403 cpc->pci = 0x00000000;
2404 cpc->er = 0x00000000;
2405 cpc->fr = 0x00000000;
2406 cpc->sr = 0x00000000;
2407 ppc405ep_compute_clocks(cpc);
2408 }
2409
2410 /* XXX: sysclk should be between 25 and 100 MHz */
2411 static void ppc405ep_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[8],
2412 uint32_t sysclk)
2413 {
2414 ppc405ep_cpc_t *cpc;
2415
2416 cpc = g_malloc0(sizeof(ppc405ep_cpc_t));
2417 memcpy(cpc->clk_setup, clk_setup,
2418 PPC405EP_CLK_NB * sizeof(clk_setup_t));
2419 cpc->jtagid = 0x20267049;
2420 cpc->sysclk = sysclk;
2421 qemu_register_reset(&ppc405ep_cpc_reset, cpc);
2422 ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc,
2423 &dcr_read_epcpc, &dcr_write_epcpc);
2424 ppc_dcr_register(env, PPC405EP_CPC0_EPCTL, cpc,
2425 &dcr_read_epcpc, &dcr_write_epcpc);
2426 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR0, cpc,
2427 &dcr_read_epcpc, &dcr_write_epcpc);
2428 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR1, cpc,
2429 &dcr_read_epcpc, &dcr_write_epcpc);
2430 ppc_dcr_register(env, PPC405EP_CPC0_UCR, cpc,
2431 &dcr_read_epcpc, &dcr_write_epcpc);
2432 ppc_dcr_register(env, PPC405EP_CPC0_SRR, cpc,
2433 &dcr_read_epcpc, &dcr_write_epcpc);
2434 ppc_dcr_register(env, PPC405EP_CPC0_JTAGID, cpc,
2435 &dcr_read_epcpc, &dcr_write_epcpc);
2436 ppc_dcr_register(env, PPC405EP_CPC0_PCI, cpc,
2437 &dcr_read_epcpc, &dcr_write_epcpc);
2438 #if 0
2439 ppc_dcr_register(env, PPC405EP_CPC0_ER, cpc,
2440 &dcr_read_epcpc, &dcr_write_epcpc);
2441 ppc_dcr_register(env, PPC405EP_CPC0_FR, cpc,
2442 &dcr_read_epcpc, &dcr_write_epcpc);
2443 ppc_dcr_register(env, PPC405EP_CPC0_SR, cpc,
2444 &dcr_read_epcpc, &dcr_write_epcpc);
2445 #endif
2446 }
2447
2448 CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem,
2449 MemoryRegion ram_memories[2],
2450 target_phys_addr_t ram_bases[2],
2451 target_phys_addr_t ram_sizes[2],
2452 uint32_t sysclk, qemu_irq **picp,
2453 int do_init)
2454 {
2455 clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup;
2456 qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];
2457 CPUPPCState *env;
2458 qemu_irq *pic, *irqs;
2459
2460 memset(clk_setup, 0, sizeof(clk_setup));
2461 /* init CPUs */
2462 env = ppc4xx_init("405ep", &clk_setup[PPC405EP_CPU_CLK],
2463 &tlb_clk_setup, sysclk);
2464 clk_setup[PPC405EP_CPU_CLK].cb = tlb_clk_setup.cb;
2465 clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque;
2466 /* Internal devices init */
2467 /* Memory mapped devices registers */
2468 /* PLB arbitrer */
2469 ppc4xx_plb_init(env);
2470 /* PLB to OPB bridge */
2471 ppc4xx_pob_init(env);
2472 /* OBP arbitrer */
2473 ppc4xx_opba_init(0xef600600);
2474 /* Initialize timers */
2475 ppc_booke_timers_init(env, sysclk, 0);
2476 /* Universal interrupt controller */
2477 irqs = g_malloc0(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
2478 irqs[PPCUIC_OUTPUT_INT] =
2479 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
2480 irqs[PPCUIC_OUTPUT_CINT] =
2481 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
2482 pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
2483 *picp = pic;
2484 /* SDRAM controller */
2485 /* XXX 405EP has no ECC interrupt */
2486 ppc4xx_sdram_init(env, pic[17], 2, ram_memories,
2487 ram_bases, ram_sizes, do_init);
2488 /* External bus controller */
2489 ppc405_ebc_init(env);
2490 /* DMA controller */
2491 dma_irqs[0] = pic[5];
2492 dma_irqs[1] = pic[6];
2493 dma_irqs[2] = pic[7];
2494 dma_irqs[3] = pic[8];
2495 ppc405_dma_init(env, dma_irqs);
2496 /* IIC controller */
2497 ppc405_i2c_init(0xef600500, pic[2]);
2498 /* GPIO */
2499 ppc405_gpio_init(0xef600700);
2500 /* Serial ports */
2501 if (serial_hds[0] != NULL) {
2502 serial_mm_init(address_space_mem, 0xef600300, 0, pic[0],
2503 PPC_SERIAL_MM_BAUDBASE, serial_hds[0],
2504 DEVICE_BIG_ENDIAN);
2505 }
2506 if (serial_hds[1] != NULL) {
2507 serial_mm_init(address_space_mem, 0xef600400, 0, pic[1],
2508 PPC_SERIAL_MM_BAUDBASE, serial_hds[1],
2509 DEVICE_BIG_ENDIAN);
2510 }
2511 /* OCM */
2512 ppc405_ocm_init(env);
2513 /* GPT */
2514 gpt_irqs[0] = pic[19];
2515 gpt_irqs[1] = pic[20];
2516 gpt_irqs[2] = pic[21];
2517 gpt_irqs[3] = pic[22];
2518 gpt_irqs[4] = pic[23];
2519 ppc4xx_gpt_init(0xef600000, gpt_irqs);
2520 /* PCI */
2521 /* Uses pic[3], pic[16], pic[18] */
2522 /* MAL */
2523 mal_irqs[0] = pic[11];
2524 mal_irqs[1] = pic[12];
2525 mal_irqs[2] = pic[13];
2526 mal_irqs[3] = pic[14];
2527 ppc405_mal_init(env, mal_irqs);
2528 /* Ethernet */
2529 /* Uses pic[9], pic[15], pic[17] */
2530 /* CPU control */
2531 ppc405ep_cpc_init(env, clk_setup, sysclk);
2532
2533 return env;
2534 }
QEmu