hw/msi.c

   1 /*
   2  * msi.c
   3  *
   4  * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
   5  *                    VA Linux Systems Japan K.K.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16
  17  * You should have received a copy of the GNU General Public License along
  18  * with this program; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "msi.h"
  22 #include "range.h"
  23
  24 /* Eventually those constants should go to Linux pci_regs.h */
  25 #define PCI_MSI_PENDING_32      0x10
  26 #define PCI_MSI_PENDING_64      0x14
  27
  28 /* PCI_MSI_ADDRESS_LO */
  29 #define PCI_MSI_ADDRESS_LO_MASK         (~0x3)
  30
  31 /* If we get rid of cap allocator, we won't need those. */
  32 #define PCI_MSI_32_SIZEOF       0x0a
  33 #define PCI_MSI_64_SIZEOF       0x0e
  34 #define PCI_MSI_32M_SIZEOF      0x14
  35 #define PCI_MSI_64M_SIZEOF      0x18
  36
  37 #define PCI_MSI_VECTORS_MAX     32
  38
  39 /* Flag for interrupt controller to declare MSI/MSI-X support */
  40 bool msi_supported;
  41
  42 /* If we get rid of cap allocator, we won't need this. */
  43 static inline uint8_t msi_cap_sizeof(uint16_t flags)
  44 {
  45     switch (flags & (PCI_MSI_FLAGS_MASKBIT | PCI_MSI_FLAGS_64BIT)) {
  46     case PCI_MSI_FLAGS_MASKBIT | PCI_MSI_FLAGS_64BIT:
  47         return PCI_MSI_64M_SIZEOF;
  48     case PCI_MSI_FLAGS_64BIT:
  49         return PCI_MSI_64_SIZEOF;
  50     case PCI_MSI_FLAGS_MASKBIT:
  51         return PCI_MSI_32M_SIZEOF;
  52     case 0:
  53         return PCI_MSI_32_SIZEOF;
  54     default:
  55         abort();
  56         break;
  57     }
  58     return 0;
  59 }
  60
  61 //#define MSI_DEBUG
  62
  63 #ifdef MSI_DEBUG
  64 # define MSI_DPRINTF(fmt, ...)                                          \
  65     fprintf(stderr, "%s:%d " fmt, __func__, __LINE__, ## __VA_ARGS__)
  66 #else
  67 # define MSI_DPRINTF(fmt, ...)  do { } while (0)
  68 #endif
  69 #define MSI_DEV_PRINTF(dev, fmt, ...)                                   \
  70     MSI_DPRINTF("%s:%x " fmt, (dev)->name, (dev)->devfn, ## __VA_ARGS__)
  71
  72 static inline unsigned int msi_nr_vectors(uint16_t flags)
  73 {
  74     return 1U <<
  75         ((flags & PCI_MSI_FLAGS_QSIZE) >> (ffs(PCI_MSI_FLAGS_QSIZE) - 1));
  76 }
  77
  78 static inline uint8_t msi_flags_off(const PCIDevice* dev)
  79 {
  80     return dev->msi_cap + PCI_MSI_FLAGS;
  81 }
  82
  83 static inline uint8_t msi_address_lo_off(const PCIDevice* dev)
  84 {
  85     return dev->msi_cap + PCI_MSI_ADDRESS_LO;
  86 }
  87
  88 static inline uint8_t msi_address_hi_off(const PCIDevice* dev)
  89 {
  90     return dev->msi_cap + PCI_MSI_ADDRESS_HI;
  91 }
  92
  93 static inline uint8_t msi_data_off(const PCIDevice* dev, bool msi64bit)
  94 {
  95     return dev->msi_cap + (msi64bit ? PCI_MSI_DATA_64 : PCI_MSI_DATA_32);
  96 }
  97
  98 static inline uint8_t msi_mask_off(const PCIDevice* dev, bool msi64bit)
  99 {
 100     return dev->msi_cap + (msi64bit ? PCI_MSI_MASK_64 : PCI_MSI_MASK_32);
 101 }
 102
 103 static inline uint8_t msi_pending_off(const PCIDevice* dev, bool msi64bit)
 104 {
 105     return dev->msi_cap + (msi64bit ? PCI_MSI_PENDING_64 : PCI_MSI_PENDING_32);
 106 }
 107
 108 bool msi_enabled(const PCIDevice *dev)
 109 {
 110     return msi_present(dev) &&
 111         (pci_get_word(dev->config + msi_flags_off(dev)) &
 112          PCI_MSI_FLAGS_ENABLE);
 113 }
 114
 115 int msi_init(struct PCIDevice *dev, uint8_t offset,
 116              unsigned int nr_vectors, bool msi64bit, bool msi_per_vector_mask)
 117 {
 118     unsigned int vectors_order;
 119     uint16_t flags;
 120     uint8_t cap_size;
 121     int config_offset;
 122
 123     if (!msi_supported) {
 124         return -ENOTSUP;
 125     }
 126
 127     MSI_DEV_PRINTF(dev,
 128                    "init offset: 0x%"PRIx8" vector: %"PRId8
 129                    " 64bit %d mask %d\n",
 130                    offset, nr_vectors, msi64bit, msi_per_vector_mask);
 131
 132     assert(!(nr_vectors & (nr_vectors - 1)));   /* power of 2 */
 133     assert(nr_vectors > 0);
 134     assert(nr_vectors <= PCI_MSI_VECTORS_MAX);
 135     /* the nr of MSI vectors is up to 32 */
 136     vectors_order = ffs(nr_vectors) - 1;
 137
 138     flags = vectors_order << (ffs(PCI_MSI_FLAGS_QMASK) - 1);
 139     if (msi64bit) {
 140         flags |= PCI_MSI_FLAGS_64BIT;
 141     }
 142     if (msi_per_vector_mask) {
 143         flags |= PCI_MSI_FLAGS_MASKBIT;
 144     }
 145
 146     cap_size = msi_cap_sizeof(flags);
 147     config_offset = pci_add_capability(dev, PCI_CAP_ID_MSI, offset, cap_size);
 148     if (config_offset < 0) {
 149         return config_offset;
 150     }
 151
 152     dev->msi_cap = config_offset;
 153     dev->cap_present |= QEMU_PCI_CAP_MSI;
 154
 155     pci_set_word(dev->config + msi_flags_off(dev), flags);
 156     pci_set_word(dev->wmask + msi_flags_off(dev),
 157                  PCI_MSI_FLAGS_QSIZE | PCI_MSI_FLAGS_ENABLE);
 158     pci_set_long(dev->wmask + msi_address_lo_off(dev),
 159                  PCI_MSI_ADDRESS_LO_MASK);
 160     if (msi64bit) {
 161         pci_set_long(dev->wmask + msi_address_hi_off(dev), 0xffffffff);
 162     }
 163     pci_set_word(dev->wmask + msi_data_off(dev, msi64bit), 0xffff);
 164
 165     if (msi_per_vector_mask) {
 166         /* Make mask bits 0 to nr_vectors - 1 writable. */
 167         pci_set_long(dev->wmask + msi_mask_off(dev, msi64bit),
 168                      0xffffffff >> (PCI_MSI_VECTORS_MAX - nr_vectors));
 169     }
 170     return config_offset;
 171 }
 172
 173 void msi_uninit(struct PCIDevice *dev)
 174 {
 175     uint16_t flags;
 176     uint8_t cap_size;
 177
 178     if (!(dev->cap_present & QEMU_PCI_CAP_MSI)) {
 179         return;
 180     }
 181     flags = pci_get_word(dev->config + msi_flags_off(dev));
 182     cap_size = msi_cap_sizeof(flags);
 183     pci_del_capability(dev, PCI_CAP_ID_MSI, cap_size);
 184     dev->cap_present &= ~QEMU_PCI_CAP_MSI;
 185
 186     MSI_DEV_PRINTF(dev, "uninit\n");
 187 }
 188
 189 void msi_reset(PCIDevice *dev)
 190 {
 191     uint16_t flags;
 192     bool msi64bit;
 193
 194     flags = pci_get_word(dev->config + msi_flags_off(dev));
 195     flags &= ~(PCI_MSI_FLAGS_QSIZE | PCI_MSI_FLAGS_ENABLE);
 196     msi64bit = flags & PCI_MSI_FLAGS_64BIT;
 197
 198     pci_set_word(dev->config + msi_flags_off(dev), flags);
 199     pci_set_long(dev->config + msi_address_lo_off(dev), 0);
 200     if (msi64bit) {
 201         pci_set_long(dev->config + msi_address_hi_off(dev), 0);
 202     }
 203     pci_set_word(dev->config + msi_data_off(dev, msi64bit), 0);
 204     if (flags & PCI_MSI_FLAGS_MASKBIT) {
 205         pci_set_long(dev->config + msi_mask_off(dev, msi64bit), 0);
 206         pci_set_long(dev->config + msi_pending_off(dev, msi64bit), 0);
 207     }
 208     MSI_DEV_PRINTF(dev, "reset\n");
 209 }
 210
 211 static bool msi_is_masked(const PCIDevice *dev, unsigned int vector)
 212 {
 213     uint16_t flags = pci_get_word(dev->config + msi_flags_off(dev));
 214     uint32_t mask;
 215     assert(vector < PCI_MSI_VECTORS_MAX);
 216
 217     if (!(flags & PCI_MSI_FLAGS_MASKBIT)) {
 218         return false;
 219     }
 220
 221     mask = pci_get_long(dev->config +
 222                         msi_mask_off(dev, flags & PCI_MSI_FLAGS_64BIT));
 223     return mask & (1U << vector);
 224 }
 225
 226 void msi_notify(PCIDevice *dev, unsigned int vector)
 227 {
 228     uint16_t flags = pci_get_word(dev->config + msi_flags_off(dev));
 229     bool msi64bit = flags & PCI_MSI_FLAGS_64BIT;
 230     unsigned int nr_vectors = msi_nr_vectors(flags);
 231     uint64_t address;
 232     uint32_t data;
 233
 234     assert(vector < nr_vectors);
 235     if (msi_is_masked(dev, vector)) {
 236         assert(flags & PCI_MSI_FLAGS_MASKBIT);
 237         pci_long_test_and_set_mask(
 238             dev->config + msi_pending_off(dev, msi64bit), 1U << vector);
 239         MSI_DEV_PRINTF(dev, "pending vector 0x%x\n", vector);
 240         return;
 241     }
 242
 243     if (msi64bit) {
 244         address = pci_get_quad(dev->config + msi_address_lo_off(dev));
 245     } else {
 246         address = pci_get_long(dev->config + msi_address_lo_off(dev));
 247     }
 248
 249     /* upper bit 31:16 is zero */
 250     data = pci_get_word(dev->config + msi_data_off(dev, msi64bit));
 251     if (nr_vectors > 1) {
 252         data &= ~(nr_vectors - 1);
 253         data |= vector;
 254     }
 255
 256     MSI_DEV_PRINTF(dev,
 257                    "notify vector 0x%x"
 258                    " address: 0x%"PRIx64" data: 0x%"PRIx32"\n",
 259                    vector, address, data);
 260     stl_le_phys(address, data);
 261 }
 262
 263 /* call this function after updating configs by pci_default_write_config(). */
 264 void msi_write_config(PCIDevice *dev, uint32_t addr, uint32_t val, int len)
 265 {
 266     uint16_t flags = pci_get_word(dev->config + msi_flags_off(dev));
 267     bool msi64bit = flags & PCI_MSI_FLAGS_64BIT;
 268     bool msi_per_vector_mask = flags & PCI_MSI_FLAGS_MASKBIT;
 269     unsigned int nr_vectors;
 270     uint8_t log_num_vecs;
 271     uint8_t log_max_vecs;
 272     unsigned int vector;
 273     uint32_t pending;
 274
 275     if (!ranges_overlap(addr, len, dev->msi_cap, msi_cap_sizeof(flags))) {
 276         return;
 277     }
 278
 279 #ifdef MSI_DEBUG
 280     MSI_DEV_PRINTF(dev, "addr 0x%"PRIx32" val 0x%"PRIx32" len %d\n",
 281                    addr, val, len);
 282     MSI_DEV_PRINTF(dev, "ctrl: 0x%"PRIx16" address: 0x%"PRIx32,
 283                    flags,
 284                    pci_get_long(dev->config + msi_address_lo_off(dev)));
 285     if (msi64bit) {
 286         fprintf(stderr, " address-hi: 0x%"PRIx32,
 287                 pci_get_long(dev->config + msi_address_hi_off(dev)));
 288     }
 289     fprintf(stderr, " data: 0x%"PRIx16,
 290             pci_get_word(dev->config + msi_data_off(dev, msi64bit)));
 291     if (flags & PCI_MSI_FLAGS_MASKBIT) {
 292         fprintf(stderr, " mask 0x%"PRIx32" pending 0x%"PRIx32,
 293                 pci_get_long(dev->config + msi_mask_off(dev, msi64bit)),
 294                 pci_get_long(dev->config + msi_pending_off(dev, msi64bit)));
 295     }
 296     fprintf(stderr, "\n");
 297 #endif
 298
 299     if (!(flags & PCI_MSI_FLAGS_ENABLE)) {
 300         return;
 301     }
 302
 303     /*
 304      * Now MSI is enabled, clear INTx# interrupts.
 305      * the driver is prohibited from writing enable bit to mask
 306      * a service request. But the guest OS could do this.
 307      * So we just discard the interrupts as moderate fallback.
 308      *
 309      * 6.8.3.3. Enabling Operation
 310      *   While enabled for MSI or MSI-X operation, a function is prohibited
 311      *   from using its INTx# pin (if implemented) to request
 312      *   service (MSI, MSI-X, and INTx# are mutually exclusive).
 313      */
 314     pci_device_deassert_intx(dev);
 315
 316     /*
 317      * nr_vectors might be set bigger than capable. So clamp it.
 318      * This is not legal by spec, so we can do anything we like,
 319      * just don't crash the host
 320      */
 321     log_num_vecs =
 322         (flags & PCI_MSI_FLAGS_QSIZE) >> (ffs(PCI_MSI_FLAGS_QSIZE) - 1);
 323     log_max_vecs =
 324         (flags & PCI_MSI_FLAGS_QMASK) >> (ffs(PCI_MSI_FLAGS_QMASK) - 1);
 325     if (log_num_vecs > log_max_vecs) {
 326         flags &= ~PCI_MSI_FLAGS_QSIZE;
 327         flags |= log_max_vecs << (ffs(PCI_MSI_FLAGS_QSIZE) - 1);
 328         pci_set_word(dev->config + msi_flags_off(dev), flags);
 329     }
 330
 331     if (!msi_per_vector_mask) {
 332         /* if per vector masking isn't supported,
 333            there is no pending interrupt. */
 334         return;
 335     }
 336
 337     nr_vectors = msi_nr_vectors(flags);
 338
 339     /* This will discard pending interrupts, if any. */
 340     pending = pci_get_long(dev->config + msi_pending_off(dev, msi64bit));
 341     pending &= 0xffffffff >> (PCI_MSI_VECTORS_MAX - nr_vectors);
 342     pci_set_long(dev->config + msi_pending_off(dev, msi64bit), pending);
 343
 344     /* deliver pending interrupts which are unmasked */
 345     for (vector = 0; vector < nr_vectors; ++vector) {
 346         if (msi_is_masked(dev, vector) || !(pending & (1U << vector))) {
 347             continue;
 348         }
 349
 350         pci_long_test_and_clear_mask(
 351             dev->config + msi_pending_off(dev, msi64bit), 1U << vector);
 352         msi_notify(dev, vector);
 353     }
 354 }
 355
 356 unsigned int msi_nr_vectors_allocated(const PCIDevice *dev)
 357 {
 358     uint16_t flags = pci_get_word(dev->config + msi_flags_off(dev));
 359     return msi_nr_vectors(flags);
 360 }