target-i386/cpu.h

   1 /*
   2  * i386 virtual CPU header
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #ifndef CPU_I386_H
  20 #define CPU_I386_H
  21
  22 #include "config.h"
  23 #include "qemu-common.h"
  24
  25 #ifdef TARGET_X86_64
  26 #define TARGET_LONG_BITS 64
  27 #else
  28 #define TARGET_LONG_BITS 32
  29 #endif
  30
  31 /* target supports implicit self modifying code */
  32 #define TARGET_HAS_SMC
  33 /* support for self modifying code even if the modified instruction is
  34    close to the modifying instruction */
  35 #define TARGET_HAS_PRECISE_SMC
  36
  37 #define TARGET_HAS_ICE 1
  38
  39 #ifdef TARGET_X86_64
  40 #define ELF_MACHINE     EM_X86_64
  41 #else
  42 #define ELF_MACHINE     EM_386
  43 #endif
  44
  45 #define CPUState struct CPUX86State
  46
  47 #include "cpu-defs.h"
  48
  49 #include "softfloat.h"
  50
  51 #define R_EAX 0
  52 #define R_ECX 1
  53 #define R_EDX 2
  54 #define R_EBX 3
  55 #define R_ESP 4
  56 #define R_EBP 5
  57 #define R_ESI 6
  58 #define R_EDI 7
  59
  60 #define R_AL 0
  61 #define R_CL 1
  62 #define R_DL 2
  63 #define R_BL 3
  64 #define R_AH 4
  65 #define R_CH 5
  66 #define R_DH 6
  67 #define R_BH 7
  68
  69 #define R_ES 0
  70 #define R_CS 1
  71 #define R_SS 2
  72 #define R_DS 3
  73 #define R_FS 4
  74 #define R_GS 5
  75
  76 /* segment descriptor fields */
  77 #define DESC_G_MASK     (1 << 23)
  78 #define DESC_B_SHIFT    22
  79 #define DESC_B_MASK     (1 << DESC_B_SHIFT)
  80 #define DESC_L_SHIFT    21 /* x86_64 only : 64 bit code segment */
  81 #define DESC_L_MASK     (1 << DESC_L_SHIFT)
  82 #define DESC_AVL_MASK   (1 << 20)
  83 #define DESC_P_MASK     (1 << 15)
  84 #define DESC_DPL_SHIFT  13
  85 #define DESC_DPL_MASK   (3 << DESC_DPL_SHIFT)
  86 #define DESC_S_MASK     (1 << 12)
  87 #define DESC_TYPE_SHIFT 8
  88 #define DESC_TYPE_MASK  (15 << DESC_TYPE_SHIFT)
  89 #define DESC_A_MASK     (1 << 8)
  90
  91 #define DESC_CS_MASK    (1 << 11) /* 1=code segment 0=data segment */
  92 #define DESC_C_MASK     (1 << 10) /* code: conforming */
  93 #define DESC_R_MASK     (1 << 9)  /* code: readable */
  94
  95 #define DESC_E_MASK     (1 << 10) /* data: expansion direction */
  96 #define DESC_W_MASK     (1 << 9)  /* data: writable */
  97
  98 #define DESC_TSS_BUSY_MASK (1 << 9)
  99
 100 /* eflags masks */
 101 #define CC_C    0x0001
 102 #define CC_P    0x0004
 103 #define CC_A    0x0010
 104 #define CC_Z    0x0040
 105 #define CC_S    0x0080
 106 #define CC_O    0x0800
 107
 108 #define TF_SHIFT   8
 109 #define IOPL_SHIFT 12
 110 #define VM_SHIFT   17
 111
 112 #define TF_MASK                 0x00000100
 113 #define IF_MASK                 0x00000200
 114 #define DF_MASK                 0x00000400
 115 #define IOPL_MASK               0x00003000
 116 #define NT_MASK                 0x00004000
 117 #define RF_MASK                 0x00010000
 118 #define VM_MASK                 0x00020000
 119 #define AC_MASK                 0x00040000
 120 #define VIF_MASK                0x00080000
 121 #define VIP_MASK                0x00100000
 122 #define ID_MASK                 0x00200000
 123
 124 /* hidden flags - used internally by qemu to represent additional cpu
 125    states. Only the CPL, INHIBIT_IRQ, SMM and SVMI are not
 126    redundant. We avoid using the IOPL_MASK, TF_MASK and VM_MASK bit
 127    position to ease oring with eflags. */
 128 /* current cpl */
 129 #define HF_CPL_SHIFT         0
 130 /* true if soft mmu is being used */
 131 #define HF_SOFTMMU_SHIFT     2
 132 /* true if hardware interrupts must be disabled for next instruction */
 133 #define HF_INHIBIT_IRQ_SHIFT 3
 134 /* 16 or 32 segments */
 135 #define HF_CS32_SHIFT        4
 136 #define HF_SS32_SHIFT        5
 137 /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */
 138 #define HF_ADDSEG_SHIFT      6
 139 /* copy of CR0.PE (protected mode) */
 140 #define HF_PE_SHIFT          7
 141 #define HF_TF_SHIFT          8 /* must be same as eflags */
 142 #define HF_MP_SHIFT          9 /* the order must be MP, EM, TS */
 143 #define HF_EM_SHIFT         10
 144 #define HF_TS_SHIFT         11
 145 #define HF_IOPL_SHIFT       12 /* must be same as eflags */
 146 #define HF_LMA_SHIFT        14 /* only used on x86_64: long mode active */
 147 #define HF_CS64_SHIFT       15 /* only used on x86_64: 64 bit code segment  */
 148 #define HF_RF_SHIFT         16 /* must be same as eflags */
 149 #define HF_VM_SHIFT         17 /* must be same as eflags */
 150 #define HF_SMM_SHIFT        19 /* CPU in SMM mode */
 151 #define HF_SVME_SHIFT       20 /* SVME enabled (copy of EFER.SVME) */
 152 #define HF_SVMI_SHIFT       21 /* SVM intercepts are active */
 153 #define HF_OSFXSR_SHIFT     22 /* CR4.OSFXSR */
 154
 155 #define HF_CPL_MASK          (3 << HF_CPL_SHIFT)
 156 #define HF_SOFTMMU_MASK      (1 << HF_SOFTMMU_SHIFT)
 157 #define HF_INHIBIT_IRQ_MASK  (1 << HF_INHIBIT_IRQ_SHIFT)
 158 #define HF_CS32_MASK         (1 << HF_CS32_SHIFT)
 159 #define HF_SS32_MASK         (1 << HF_SS32_SHIFT)
 160 #define HF_ADDSEG_MASK       (1 << HF_ADDSEG_SHIFT)
 161 #define HF_PE_MASK           (1 << HF_PE_SHIFT)
 162 #define HF_TF_MASK           (1 << HF_TF_SHIFT)
 163 #define HF_MP_MASK           (1 << HF_MP_SHIFT)
 164 #define HF_EM_MASK           (1 << HF_EM_SHIFT)
 165 #define HF_TS_MASK           (1 << HF_TS_SHIFT)
 166 #define HF_IOPL_MASK         (3 << HF_IOPL_SHIFT)
 167 #define HF_LMA_MASK          (1 << HF_LMA_SHIFT)
 168 #define HF_CS64_MASK         (1 << HF_CS64_SHIFT)
 169 #define HF_RF_MASK           (1 << HF_RF_SHIFT)
 170 #define HF_VM_MASK           (1 << HF_VM_SHIFT)
 171 #define HF_SMM_MASK          (1 << HF_SMM_SHIFT)
 172 #define HF_SVME_MASK         (1 << HF_SVME_SHIFT)
 173 #define HF_SVMI_MASK         (1 << HF_SVMI_SHIFT)
 174 #define HF_OSFXSR_MASK       (1 << HF_OSFXSR_SHIFT)
 175
 176 /* hflags2 */
 177
 178 #define HF2_GIF_SHIFT        0 /* if set CPU takes interrupts */
 179 #define HF2_HIF_SHIFT        1 /* value of IF_MASK when entering SVM */
 180 #define HF2_NMI_SHIFT        2 /* CPU serving NMI */
 181 #define HF2_VINTR_SHIFT      3 /* value of V_INTR_MASKING bit */
 182
 183 #define HF2_GIF_MASK          (1 << HF2_GIF_SHIFT)
 184 #define HF2_HIF_MASK          (1 << HF2_HIF_SHIFT)
 185 #define HF2_NMI_MASK          (1 << HF2_NMI_SHIFT)
 186 #define HF2_VINTR_MASK        (1 << HF2_VINTR_SHIFT)
 187
 188 #define CR0_PE_SHIFT 0
 189 #define CR0_MP_SHIFT 1
 190
 191 #define CR0_PE_MASK  (1 << 0)
 192 #define CR0_MP_MASK  (1 << 1)
 193 #define CR0_EM_MASK  (1 << 2)
 194 #define CR0_TS_MASK  (1 << 3)
 195 #define CR0_ET_MASK  (1 << 4)
 196 #define CR0_NE_MASK  (1 << 5)
 197 #define CR0_WP_MASK  (1 << 16)
 198 #define CR0_AM_MASK  (1 << 18)
 199 #define CR0_PG_MASK  (1 << 31)
 200
 201 #define CR4_VME_MASK  (1 << 0)
 202 #define CR4_PVI_MASK  (1 << 1)
 203 #define CR4_TSD_MASK  (1 << 2)
 204 #define CR4_DE_MASK   (1 << 3)
 205 #define CR4_PSE_MASK  (1 << 4)
 206 #define CR4_PAE_MASK  (1 << 5)
 207 #define CR4_MCE_MASK  (1 << 6)
 208 #define CR4_PGE_MASK  (1 << 7)
 209 #define CR4_PCE_MASK  (1 << 8)
 210 #define CR4_OSFXSR_SHIFT 9
 211 #define CR4_OSFXSR_MASK (1 << CR4_OSFXSR_SHIFT)
 212 #define CR4_OSXMMEXCPT_MASK  (1 << 10)
 213
 214 #define DR6_BD          (1 << 13)
 215 #define DR6_BS          (1 << 14)
 216 #define DR6_BT          (1 << 15)
 217 #define DR6_FIXED_1     0xffff0ff0
 218
 219 #define DR7_GD          (1 << 13)
 220 #define DR7_TYPE_SHIFT  16
 221 #define DR7_LEN_SHIFT   18
 222 #define DR7_FIXED_1     0x00000400
 223
 224 #define PG_PRESENT_BIT  0
 225 #define PG_RW_BIT       1
 226 #define PG_USER_BIT     2
 227 #define PG_PWT_BIT      3
 228 #define PG_PCD_BIT      4
 229 #define PG_ACCESSED_BIT 5
 230 #define PG_DIRTY_BIT    6
 231 #define PG_PSE_BIT      7
 232 #define PG_GLOBAL_BIT   8
 233 #define PG_NX_BIT       63
 234
 235 #define PG_PRESENT_MASK  (1 << PG_PRESENT_BIT)
 236 #define PG_RW_MASK       (1 << PG_RW_BIT)
 237 #define PG_USER_MASK     (1 << PG_USER_BIT)
 238 #define PG_PWT_MASK      (1 << PG_PWT_BIT)
 239 #define PG_PCD_MASK      (1 << PG_PCD_BIT)
 240 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
 241 #define PG_DIRTY_MASK    (1 << PG_DIRTY_BIT)
 242 #define PG_PSE_MASK      (1 << PG_PSE_BIT)
 243 #define PG_GLOBAL_MASK   (1 << PG_GLOBAL_BIT)
 244 #define PG_NX_MASK       (1LL << PG_NX_BIT)
 245
 246 #define PG_ERROR_W_BIT     1
 247
 248 #define PG_ERROR_P_MASK    0x01
 249 #define PG_ERROR_W_MASK    (1 << PG_ERROR_W_BIT)
 250 #define PG_ERROR_U_MASK    0x04
 251 #define PG_ERROR_RSVD_MASK 0x08
 252 #define PG_ERROR_I_D_MASK  0x10
 253
 254 #define MCG_CTL_P       (1ULL<<8)   /* MCG_CAP register available */
 255 #define MCG_SER_P       (1ULL<<24) /* MCA recovery/new status bits */
 256
 257 #define MCE_CAP_DEF     (MCG_CTL_P|MCG_SER_P)
 258 #define MCE_BANKS_DEF   10
 259
 260 #define MCG_STATUS_RIPV (1ULL<<0)   /* restart ip valid */
 261 #define MCG_STATUS_EIPV (1ULL<<1)   /* ip points to correct instruction */
 262 #define MCG_STATUS_MCIP (1ULL<<2)   /* machine check in progress */
 263
 264 #define MCI_STATUS_VAL  (1ULL<<63)  /* valid error */
 265 #define MCI_STATUS_OVER (1ULL<<62)  /* previous errors lost */
 266 #define MCI_STATUS_UC   (1ULL<<61)  /* uncorrected error */
 267 #define MCI_STATUS_EN   (1ULL<<60)  /* error enabled */
 268 #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */
 269 #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */
 270 #define MCI_STATUS_PCC  (1ULL<<57)  /* processor context corrupt */
 271 #define MCI_STATUS_S    (1ULL<<56)  /* Signaled machine check */
 272 #define MCI_STATUS_AR   (1ULL<<55)  /* Action required */
 273
 274 /* MISC register defines */
 275 #define MCM_ADDR_SEGOFF 0       /* segment offset */
 276 #define MCM_ADDR_LINEAR 1       /* linear address */
 277 #define MCM_ADDR_PHYS   2       /* physical address */
 278 #define MCM_ADDR_MEM    3       /* memory address */
 279 #define MCM_ADDR_GENERIC 7      /* generic */
 280
 281 #define MSR_IA32_TSC                    0x10
 282 #define MSR_IA32_APICBASE               0x1b
 283 #define MSR_IA32_APICBASE_BSP           (1<<8)
 284 #define MSR_IA32_APICBASE_ENABLE        (1<<11)
 285 #define MSR_IA32_APICBASE_BASE          (0xfffff<<12)
 286 #define MSR_IA32_TSCDEADLINE            0x6e0
 287
 288 #define MSR_MTRRcap                     0xfe
 289 #define MSR_MTRRcap_VCNT                8
 290 #define MSR_MTRRcap_FIXRANGE_SUPPORT    (1 << 8)
 291 #define MSR_MTRRcap_WC_SUPPORTED        (1 << 10)
 292
 293 #define MSR_IA32_SYSENTER_CS            0x174
 294 #define MSR_IA32_SYSENTER_ESP           0x175
 295 #define MSR_IA32_SYSENTER_EIP           0x176
 296
 297 #define MSR_MCG_CAP                     0x179
 298 #define MSR_MCG_STATUS                  0x17a
 299 #define MSR_MCG_CTL                     0x17b
 300
 301 #define MSR_IA32_PERF_STATUS            0x198
 302
 303 #define MSR_MTRRphysBase(reg)           (0x200 + 2 * (reg))
 304 #define MSR_MTRRphysMask(reg)           (0x200 + 2 * (reg) + 1)
 305
 306 #define MSR_MTRRfix64K_00000            0x250
 307 #define MSR_MTRRfix16K_80000            0x258
 308 #define MSR_MTRRfix16K_A0000            0x259
 309 #define MSR_MTRRfix4K_C0000             0x268
 310 #define MSR_MTRRfix4K_C8000             0x269
 311 #define MSR_MTRRfix4K_D0000             0x26a
 312 #define MSR_MTRRfix4K_D8000             0x26b
 313 #define MSR_MTRRfix4K_E0000             0x26c
 314 #define MSR_MTRRfix4K_E8000             0x26d
 315 #define MSR_MTRRfix4K_F0000             0x26e
 316 #define MSR_MTRRfix4K_F8000             0x26f
 317
 318 #define MSR_PAT                         0x277
 319
 320 #define MSR_MTRRdefType                 0x2ff
 321
 322 #define MSR_MC0_CTL                     0x400
 323 #define MSR_MC0_STATUS                  0x401
 324 #define MSR_MC0_ADDR                    0x402
 325 #define MSR_MC0_MISC                    0x403
 326
 327 #define MSR_EFER                        0xc0000080
 328
 329 #define MSR_EFER_SCE   (1 << 0)
 330 #define MSR_EFER_LME   (1 << 8)
 331 #define MSR_EFER_LMA   (1 << 10)
 332 #define MSR_EFER_NXE   (1 << 11)
 333 #define MSR_EFER_SVME  (1 << 12)
 334 #define MSR_EFER_FFXSR (1 << 14)
 335
 336 #define MSR_STAR                        0xc0000081
 337 #define MSR_LSTAR                       0xc0000082
 338 #define MSR_CSTAR                       0xc0000083
 339 #define MSR_FMASK                       0xc0000084
 340 #define MSR_FSBASE                      0xc0000100
 341 #define MSR_GSBASE                      0xc0000101
 342 #define MSR_KERNELGSBASE                0xc0000102
 343 #define MSR_TSC_AUX                     0xc0000103
 344
 345 #define MSR_VM_HSAVE_PA                 0xc0010117
 346
 347 /* cpuid_features bits */
 348 #define CPUID_FP87 (1 << 0)
 349 #define CPUID_VME  (1 << 1)
 350 #define CPUID_DE   (1 << 2)
 351 #define CPUID_PSE  (1 << 3)
 352 #define CPUID_TSC  (1 << 4)
 353 #define CPUID_MSR  (1 << 5)
 354 #define CPUID_PAE  (1 << 6)
 355 #define CPUID_MCE  (1 << 7)
 356 #define CPUID_CX8  (1 << 8)
 357 #define CPUID_APIC (1 << 9)
 358 #define CPUID_SEP  (1 << 11) /* sysenter/sysexit */
 359 #define CPUID_MTRR (1 << 12)
 360 #define CPUID_PGE  (1 << 13)
 361 #define CPUID_MCA  (1 << 14)
 362 #define CPUID_CMOV (1 << 15)
 363 #define CPUID_PAT  (1 << 16)
 364 #define CPUID_PSE36   (1 << 17)
 365 #define CPUID_PN   (1 << 18)
 366 #define CPUID_CLFLUSH (1 << 19)
 367 #define CPUID_DTS (1 << 21)
 368 #define CPUID_ACPI (1 << 22)
 369 #define CPUID_MMX  (1 << 23)
 370 #define CPUID_FXSR (1 << 24)
 371 #define CPUID_SSE  (1 << 25)
 372 #define CPUID_SSE2 (1 << 26)
 373 #define CPUID_SS (1 << 27)
 374 #define CPUID_HT (1 << 28)
 375 #define CPUID_TM (1 << 29)
 376 #define CPUID_IA64 (1 << 30)
 377 #define CPUID_PBE (1 << 31)
 378
 379 #define CPUID_EXT_SSE3     (1 << 0)
 380 #define CPUID_EXT_DTES64   (1 << 2)
 381 #define CPUID_EXT_MONITOR  (1 << 3)
 382 #define CPUID_EXT_DSCPL    (1 << 4)
 383 #define CPUID_EXT_VMX      (1 << 5)
 384 #define CPUID_EXT_SMX      (1 << 6)
 385 #define CPUID_EXT_EST      (1 << 7)
 386 #define CPUID_EXT_TM2      (1 << 8)
 387 #define CPUID_EXT_SSSE3    (1 << 9)
 388 #define CPUID_EXT_CID      (1 << 10)
 389 #define CPUID_EXT_CX16     (1 << 13)
 390 #define CPUID_EXT_XTPR     (1 << 14)
 391 #define CPUID_EXT_PDCM     (1 << 15)
 392 #define CPUID_EXT_DCA      (1 << 18)
 393 #define CPUID_EXT_SSE41    (1 << 19)
 394 #define CPUID_EXT_SSE42    (1 << 20)
 395 #define CPUID_EXT_X2APIC   (1 << 21)
 396 #define CPUID_EXT_MOVBE    (1 << 22)
 397 #define CPUID_EXT_POPCNT   (1 << 23)
 398 #define CPUID_EXT_XSAVE    (1 << 26)
 399 #define CPUID_EXT_OSXSAVE  (1 << 27)
 400 #define CPUID_EXT_HYPERVISOR  (1 << 31)
 401
 402 #define CPUID_EXT2_SYSCALL (1 << 11)
 403 #define CPUID_EXT2_MP      (1 << 19)
 404 #define CPUID_EXT2_NX      (1 << 20)
 405 #define CPUID_EXT2_MMXEXT  (1 << 22)
 406 #define CPUID_EXT2_FFXSR   (1 << 25)
 407 #define CPUID_EXT2_PDPE1GB (1 << 26)
 408 #define CPUID_EXT2_RDTSCP  (1 << 27)
 409 #define CPUID_EXT2_LM      (1 << 29)
 410 #define CPUID_EXT2_3DNOWEXT (1 << 30)
 411 #define CPUID_EXT2_3DNOW   (1 << 31)
 412
 413 #define CPUID_EXT3_LAHF_LM (1 << 0)
 414 #define CPUID_EXT3_CMP_LEG (1 << 1)
 415 #define CPUID_EXT3_SVM     (1 << 2)
 416 #define CPUID_EXT3_EXTAPIC (1 << 3)
 417 #define CPUID_EXT3_CR8LEG  (1 << 4)
 418 #define CPUID_EXT3_ABM     (1 << 5)
 419 #define CPUID_EXT3_SSE4A   (1 << 6)
 420 #define CPUID_EXT3_MISALIGNSSE (1 << 7)
 421 #define CPUID_EXT3_3DNOWPREFETCH (1 << 8)
 422 #define CPUID_EXT3_OSVW    (1 << 9)
 423 #define CPUID_EXT3_IBS     (1 << 10)
 424 #define CPUID_EXT3_SKINIT  (1 << 12)
 425
 426 #define CPUID_SVM_NPT          (1 << 0)
 427 #define CPUID_SVM_LBRV         (1 << 1)
 428 #define CPUID_SVM_SVMLOCK      (1 << 2)
 429 #define CPUID_SVM_NRIPSAVE     (1 << 3)
 430 #define CPUID_SVM_TSCSCALE     (1 << 4)
 431 #define CPUID_SVM_VMCBCLEAN    (1 << 5)
 432 #define CPUID_SVM_FLUSHASID    (1 << 6)
 433 #define CPUID_SVM_DECODEASSIST (1 << 7)
 434 #define CPUID_SVM_PAUSEFILTER  (1 << 10)
 435 #define CPUID_SVM_PFTHRESHOLD  (1 << 12)
 436
 437 #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */
 438 #define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */
 439 #define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */
 440
 441 #define CPUID_VENDOR_AMD_1   0x68747541 /* "Auth" */
 442 #define CPUID_VENDOR_AMD_2   0x69746e65 /* "enti" */
 443 #define CPUID_VENDOR_AMD_3   0x444d4163 /* "cAMD" */
 444
 445 #define CPUID_VENDOR_VIA_1   0x746e6543 /* "Cent" */
 446 #define CPUID_VENDOR_VIA_2   0x48727561 /* "aurH" */
 447 #define CPUID_VENDOR_VIA_3   0x736c7561 /* "auls" */
 448
 449 #define CPUID_MWAIT_IBE     (1 << 1) /* Interrupts can exit capability */
 450 #define CPUID_MWAIT_EMX     (1 << 0) /* enumeration supported */
 451
 452 #define EXCP00_DIVZ     0
 453 #define EXCP01_DB       1
 454 #define EXCP02_NMI      2
 455 #define EXCP03_INT3     3
 456 #define EXCP04_INTO     4
 457 #define EXCP05_BOUND    5
 458 #define EXCP06_ILLOP    6
 459 #define EXCP07_PREX     7
 460 #define EXCP08_DBLE     8
 461 #define EXCP09_XERR     9
 462 #define EXCP0A_TSS      10
 463 #define EXCP0B_NOSEG    11
 464 #define EXCP0C_STACK    12
 465 #define EXCP0D_GPF      13
 466 #define EXCP0E_PAGE     14
 467 #define EXCP10_COPR     16
 468 #define EXCP11_ALGN     17
 469 #define EXCP12_MCHK     18
 470
 471 #define EXCP_SYSCALL    0x100 /* only happens in user only emulation
 472                                  for syscall instruction */
 473
 474 /* i386-specific interrupt pending bits.  */
 475 #define CPU_INTERRUPT_SMI       CPU_INTERRUPT_TGT_EXT_2
 476 #define CPU_INTERRUPT_NMI       CPU_INTERRUPT_TGT_EXT_3
 477 #define CPU_INTERRUPT_MCE       CPU_INTERRUPT_TGT_EXT_4
 478 #define CPU_INTERRUPT_VIRQ      CPU_INTERRUPT_TGT_INT_0
 479 #define CPU_INTERRUPT_INIT      CPU_INTERRUPT_TGT_INT_1
 480 #define CPU_INTERRUPT_SIPI      CPU_INTERRUPT_TGT_INT_2
 481
 482
 483 enum {
 484     CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
 485     CC_OP_EFLAGS,  /* all cc are explicitly computed, CC_SRC = flags */
 486
 487     CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */
 488     CC_OP_MULW,
 489     CC_OP_MULL,
 490     CC_OP_MULQ,
 491
 492     CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
 493     CC_OP_ADDW,
 494     CC_OP_ADDL,
 495     CC_OP_ADDQ,
 496
 497     CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
 498     CC_OP_ADCW,
 499     CC_OP_ADCL,
 500     CC_OP_ADCQ,
 501
 502     CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
 503     CC_OP_SUBW,
 504     CC_OP_SUBL,
 505     CC_OP_SUBQ,
 506
 507     CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
 508     CC_OP_SBBW,
 509     CC_OP_SBBL,
 510     CC_OP_SBBQ,
 511
 512     CC_OP_LOGICB, /* modify all flags, CC_DST = res */
 513     CC_OP_LOGICW,
 514     CC_OP_LOGICL,
 515     CC_OP_LOGICQ,
 516
 517     CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
 518     CC_OP_INCW,
 519     CC_OP_INCL,
 520     CC_OP_INCQ,
 521
 522     CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C  */
 523     CC_OP_DECW,
 524     CC_OP_DECL,
 525     CC_OP_DECQ,
 526
 527     CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */
 528     CC_OP_SHLW,
 529     CC_OP_SHLL,
 530     CC_OP_SHLQ,
 531
 532     CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
 533     CC_OP_SARW,
 534     CC_OP_SARL,
 535     CC_OP_SARQ,
 536
 537     CC_OP_NB,
 538 };
 539
 540 typedef struct SegmentCache {
 541     uint32_t selector;
 542     target_ulong base;
 543     uint32_t limit;
 544     uint32_t flags;
 545 } SegmentCache;
 546
 547 typedef union {
 548     uint8_t _b[16];
 549     uint16_t _w[8];
 550     uint32_t _l[4];
 551     uint64_t _q[2];
 552     float32 _s[4];
 553     float64 _d[2];
 554 } XMMReg;
 555
 556 typedef union {
 557     uint8_t _b[8];
 558     uint16_t _w[4];
 559     uint32_t _l[2];
 560     float32 _s[2];
 561     uint64_t q;
 562 } MMXReg;
 563
 564 #ifdef HOST_WORDS_BIGENDIAN
 565 #define XMM_B(n) _b[15 - (n)]
 566 #define XMM_W(n) _w[7 - (n)]
 567 #define XMM_L(n) _l[3 - (n)]
 568 #define XMM_S(n) _s[3 - (n)]
 569 #define XMM_Q(n) _q[1 - (n)]
 570 #define XMM_D(n) _d[1 - (n)]
 571
 572 #define MMX_B(n) _b[7 - (n)]
 573 #define MMX_W(n) _w[3 - (n)]
 574 #define MMX_L(n) _l[1 - (n)]
 575 #define MMX_S(n) _s[1 - (n)]
 576 #else
 577 #define XMM_B(n) _b[n]
 578 #define XMM_W(n) _w[n]
 579 #define XMM_L(n) _l[n]
 580 #define XMM_S(n) _s[n]
 581 #define XMM_Q(n) _q[n]
 582 #define XMM_D(n) _d[n]
 583
 584 #define MMX_B(n) _b[n]
 585 #define MMX_W(n) _w[n]
 586 #define MMX_L(n) _l[n]
 587 #define MMX_S(n) _s[n]
 588 #endif
 589 #define MMX_Q(n) q
 590
 591 typedef union {
 592     floatx80 d __attribute__((aligned(16)));
 593     MMXReg mmx;
 594 } FPReg;
 595
 596 typedef struct {
 597     uint64_t base;
 598     uint64_t mask;
 599 } MTRRVar;
 600
 601 #define CPU_NB_REGS64 16
 602 #define CPU_NB_REGS32 8
 603
 604 #ifdef TARGET_X86_64
 605 #define CPU_NB_REGS CPU_NB_REGS64
 606 #else
 607 #define CPU_NB_REGS CPU_NB_REGS32
 608 #endif
 609
 610 #define NB_MMU_MODES 2
 611
 612 typedef struct CPUX86State {
 613     /* standard registers */
 614     target_ulong regs[CPU_NB_REGS];
 615     target_ulong eip;
 616     target_ulong eflags; /* eflags register. During CPU emulation, CC
 617                         flags and DF are set to zero because they are
 618                         stored elsewhere */
 619
 620     /* emulator internal eflags handling */
 621     target_ulong cc_src;
 622     target_ulong cc_dst;
 623     uint32_t cc_op;
 624     int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
 625     uint32_t hflags; /* TB flags, see HF_xxx constants. These flags
 626                         are known at translation time. */
 627     uint32_t hflags2; /* various other flags, see HF2_xxx constants. */
 628
 629     /* segments */
 630     SegmentCache segs[6]; /* selector values */
 631     SegmentCache ldt;
 632     SegmentCache tr;
 633     SegmentCache gdt; /* only base and limit are used */
 634     SegmentCache idt; /* only base and limit are used */
 635
 636     target_ulong cr[5]; /* NOTE: cr1 is unused */
 637     int32_t a20_mask;
 638
 639     /* FPU state */
 640     unsigned int fpstt; /* top of stack index */
 641     uint16_t fpus;
 642     uint16_t fpuc;
 643     uint8_t fptags[8];   /* 0 = valid, 1 = empty */
 644     FPReg fpregs[8];
 645     /* KVM-only so far */
 646     uint16_t fpop;
 647     uint64_t fpip;
 648     uint64_t fpdp;
 649
 650     /* emulator internal variables */
 651     float_status fp_status;
 652     floatx80 ft0;
 653
 654     float_status mmx_status; /* for 3DNow! float ops */
 655     float_status sse_status;
 656     uint32_t mxcsr;
 657     XMMReg xmm_regs[CPU_NB_REGS];
 658     XMMReg xmm_t0;
 659     MMXReg mmx_t0;
 660     target_ulong cc_tmp; /* temporary for rcr/rcl */
 661
 662     /* sysenter registers */
 663     uint32_t sysenter_cs;
 664     target_ulong sysenter_esp;
 665     target_ulong sysenter_eip;
 666     uint64_t efer;
 667     uint64_t star;
 668
 669     uint64_t vm_hsave;
 670     uint64_t vm_vmcb;
 671     uint64_t tsc_offset;
 672     uint64_t intercept;
 673     uint16_t intercept_cr_read;
 674     uint16_t intercept_cr_write;
 675     uint16_t intercept_dr_read;
 676     uint16_t intercept_dr_write;
 677     uint32_t intercept_exceptions;
 678     uint8_t v_tpr;
 679
 680 #ifdef TARGET_X86_64
 681     target_ulong lstar;
 682     target_ulong cstar;
 683     target_ulong fmask;
 684     target_ulong kernelgsbase;
 685 #endif
 686     uint64_t system_time_msr;
 687     uint64_t wall_clock_msr;
 688     uint64_t async_pf_en_msr;
 689
 690     uint64_t tsc;
 691     uint64_t tsc_deadline;
 692
 693     uint64_t mcg_status;
 694
 695     /* exception/interrupt handling */
 696     int error_code;
 697     int exception_is_int;
 698     target_ulong exception_next_eip;
 699     target_ulong dr[8]; /* debug registers */
 700     union {
 701         CPUBreakpoint *cpu_breakpoint[4];
 702         CPUWatchpoint *cpu_watchpoint[4];
 703     }; /* break/watchpoints for dr[0..3] */
 704     uint32_t smbase;
 705     int old_exception;  /* exception in flight */
 706
 707     /* KVM states, automatically cleared on reset */
 708     uint8_t nmi_injected;
 709     uint8_t nmi_pending;
 710
 711     CPU_COMMON
 712
 713     uint64_t pat;
 714
 715     /* processor features (e.g. for CPUID insn) */
 716     uint32_t cpuid_level;
 717     uint32_t cpuid_vendor1;
 718     uint32_t cpuid_vendor2;
 719     uint32_t cpuid_vendor3;
 720     uint32_t cpuid_version;
 721     uint32_t cpuid_features;
 722     uint32_t cpuid_ext_features;
 723     uint32_t cpuid_xlevel;
 724     uint32_t cpuid_model[12];
 725     uint32_t cpuid_ext2_features;
 726     uint32_t cpuid_ext3_features;
 727     uint32_t cpuid_apic_id;
 728     int cpuid_vendor_override;
 729     /* Store the results of Centaur's CPUID instructions */
 730     uint32_t cpuid_xlevel2;
 731     uint32_t cpuid_ext4_features;
 732
 733     /* MTRRs */
 734     uint64_t mtrr_fixed[11];
 735     uint64_t mtrr_deftype;
 736     MTRRVar mtrr_var[8];
 737
 738     /* For KVM */
 739     uint32_t mp_state;
 740     int32_t exception_injected;
 741     int32_t interrupt_injected;
 742     uint8_t soft_interrupt;
 743     uint8_t has_error_code;
 744     uint32_t sipi_vector;
 745     uint32_t cpuid_kvm_features;
 746     uint32_t cpuid_svm_features;
 747     bool tsc_valid;
 748     int tsc_khz;
 749
 750     /* in order to simplify APIC support, we leave this pointer to the
 751        user */
 752     struct DeviceState *apic_state;
 753
 754     uint64_t mcg_cap;
 755     uint64_t mcg_ctl;
 756     uint64_t mce_banks[MCE_BANKS_DEF*4];
 757
 758     uint64_t tsc_aux;
 759
 760     /* vmstate */
 761     uint16_t fpus_vmstate;
 762     uint16_t fptag_vmstate;
 763     uint16_t fpregs_format_vmstate;
 764
 765     uint64_t xstate_bv;
 766     XMMReg ymmh_regs[CPU_NB_REGS];
 767
 768     uint64_t xcr0;
 769 } CPUX86State;
 770
 771 CPUX86State *cpu_x86_init(const char *cpu_model);
 772 int cpu_x86_exec(CPUX86State *s);
 773 void cpu_x86_close(CPUX86State *s);
 774 void x86_cpu_list (FILE *f, fprintf_function cpu_fprintf, const char *optarg);
 775 void x86_cpudef_setup(void);
 776 int cpu_x86_support_mca_broadcast(CPUState *env);
 777
 778 int cpu_get_pic_interrupt(CPUX86State *s);
 779 /* MSDOS compatibility mode FPU exception support */
 780 void cpu_set_ferr(CPUX86State *s);
 781
 782 /* this function must always be used to load data in the segment
 783    cache: it synchronizes the hflags with the segment cache values */
 784 static inline void cpu_x86_load_seg_cache(CPUX86State *env,
 785                                           int seg_reg, unsigned int selector,
 786                                           target_ulong base,
 787                                           unsigned int limit,
 788                                           unsigned int flags)
 789 {
 790     SegmentCache *sc;
 791     unsigned int new_hflags;
 792
 793     sc = &env->segs[seg_reg];
 794     sc->selector = selector;
 795     sc->base = base;
 796     sc->limit = limit;
 797     sc->flags = flags;
 798
 799     /* update the hidden flags */
 800     {
 801         if (seg_reg == R_CS) {
 802 #ifdef TARGET_X86_64
 803             if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) {
 804                 /* long mode */
 805                 env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
 806                 env->hflags &= ~(HF_ADDSEG_MASK);
 807             } else
 808 #endif
 809             {
 810                 /* legacy / compatibility case */
 811                 new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
 812                     >> (DESC_B_SHIFT - HF_CS32_SHIFT);
 813                 env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) |
 814                     new_hflags;
 815             }
 816         }
 817         new_hflags = (env->segs[R_SS].flags & DESC_B_MASK)
 818             >> (DESC_B_SHIFT - HF_SS32_SHIFT);
 819         if (env->hflags & HF_CS64_MASK) {
 820             /* zero base assumed for DS, ES and SS in long mode */
 821         } else if (!(env->cr[0] & CR0_PE_MASK) ||
 822                    (env->eflags & VM_MASK) ||
 823                    !(env->hflags & HF_CS32_MASK)) {
 824             /* XXX: try to avoid this test. The problem comes from the
 825                fact that is real mode or vm86 mode we only modify the
 826                'base' and 'selector' fields of the segment cache to go
 827                faster. A solution may be to force addseg to one in
 828                translate-i386.c. */
 829             new_hflags |= HF_ADDSEG_MASK;
 830         } else {
 831             new_hflags |= ((env->segs[R_DS].base |
 832                             env->segs[R_ES].base |
 833                             env->segs[R_SS].base) != 0) <<
 834                 HF_ADDSEG_SHIFT;
 835         }
 836         env->hflags = (env->hflags &
 837                        ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags;
 838     }
 839 }
 840
 841 static inline void cpu_x86_load_seg_cache_sipi(CPUX86State *env,
 842                                                int sipi_vector)
 843 {
 844     env->eip = 0;
 845     cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8,
 846                            sipi_vector << 12,
 847                            env->segs[R_CS].limit,
 848                            env->segs[R_CS].flags);
 849     env->halted = 0;
 850 }
 851
 852 int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector,
 853                             target_ulong *base, unsigned int *limit,
 854                             unsigned int *flags);
 855
 856 /* wrapper, just in case memory mappings must be changed */
 857 static inline void cpu_x86_set_cpl(CPUX86State *s, int cpl)
 858 {
 859 #if HF_CPL_MASK == 3
 860     s->hflags = (s->hflags & ~HF_CPL_MASK) | cpl;
 861 #else
 862 #error HF_CPL_MASK is hardcoded
 863 #endif
 864 }
 865
 866 /* op_helper.c */
 867 /* used for debug or cpu save/restore */
 868 void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, floatx80 f);
 869 floatx80 cpu_set_fp80(uint64_t mant, uint16_t upper);
 870
 871 /* cpu-exec.c */
 872 /* the following helpers are only usable in user mode simulation as
 873    they can trigger unexpected exceptions */
 874 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
 875 void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32);
 876 void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32);
 877
 878 /* you can call this signal handler from your SIGBUS and SIGSEGV
 879    signal handlers to inform the virtual CPU of exceptions. non zero
 880    is returned if the signal was handled by the virtual CPU.  */
 881 int cpu_x86_signal_handler(int host_signum, void *pinfo,
 882                            void *puc);
 883
 884 /* cpuid.c */
 885 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
 886                    uint32_t *eax, uint32_t *ebx,
 887                    uint32_t *ecx, uint32_t *edx);
 888 int cpu_x86_register (CPUX86State *env, const char *cpu_model);
 889 void cpu_clear_apic_feature(CPUX86State *env);
 890 void host_cpuid(uint32_t function, uint32_t count,
 891                 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx);
 892
 893 /* helper.c */
 894 int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
 895                              int is_write, int mmu_idx);
 896 #define cpu_handle_mmu_fault cpu_x86_handle_mmu_fault
 897 void cpu_x86_set_a20(CPUX86State *env, int a20_state);
 898
 899 static inline int hw_breakpoint_enabled(unsigned long dr7, int index)
 900 {
 901     return (dr7 >> (index * 2)) & 3;
 902 }
 903
 904 static inline int hw_breakpoint_type(unsigned long dr7, int index)
 905 {
 906     return (dr7 >> (DR7_TYPE_SHIFT + (index * 4))) & 3;
 907 }
 908
 909 static inline int hw_breakpoint_len(unsigned long dr7, int index)
 910 {
 911     int len = ((dr7 >> (DR7_LEN_SHIFT + (index * 4))) & 3);
 912     return (len == 2) ? 8 : len + 1;
 913 }
 914
 915 void hw_breakpoint_insert(CPUX86State *env, int index);
 916 void hw_breakpoint_remove(CPUX86State *env, int index);
 917 int check_hw_breakpoints(CPUX86State *env, int force_dr6_update);
 918
 919 /* will be suppressed */
 920 void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
 921 void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
 922 void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
 923
 924 /* hw/pc.c */
 925 void cpu_smm_update(CPUX86State *env);
 926 uint64_t cpu_get_tsc(CPUX86State *env);
 927
 928 /* used to debug */
 929 #define X86_DUMP_FPU  0x0001 /* dump FPU state too */
 930 #define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */
 931
 932 #define TARGET_PAGE_BITS 12
 933
 934 #ifdef TARGET_X86_64
 935 #define TARGET_PHYS_ADDR_SPACE_BITS 52
 936 /* ??? This is really 48 bits, sign-extended, but the only thing
 937    accessible to userland with bit 48 set is the VSYSCALL, and that
 938    is handled via other mechanisms.  */
 939 #define TARGET_VIRT_ADDR_SPACE_BITS 47
 940 #else
 941 #define TARGET_PHYS_ADDR_SPACE_BITS 36
 942 #define TARGET_VIRT_ADDR_SPACE_BITS 32
 943 #endif
 944
 945 #define cpu_init cpu_x86_init
 946 #define cpu_exec cpu_x86_exec
 947 #define cpu_gen_code cpu_x86_gen_code
 948 #define cpu_signal_handler cpu_x86_signal_handler
 949 #define cpu_list_id x86_cpu_list
 950 #define cpudef_setup    x86_cpudef_setup
 951
 952 #define CPU_SAVE_VERSION 13
 953
 954 /* MMU modes definitions */
 955 #define MMU_MODE0_SUFFIX _kernel
 956 #define MMU_MODE1_SUFFIX _user
 957 #define MMU_USER_IDX 1
 958 static inline int cpu_mmu_index (CPUState *env)
 959 {
 960     return (env->hflags & HF_CPL_MASK) == 3 ? 1 : 0;
 961 }
 962
 963 #undef EAX
 964 #define EAX (env->regs[R_EAX])
 965 #undef ECX
 966 #define ECX (env->regs[R_ECX])
 967 #undef EDX
 968 #define EDX (env->regs[R_EDX])
 969 #undef EBX
 970 #define EBX (env->regs[R_EBX])
 971 #undef ESP
 972 #define ESP (env->regs[R_ESP])
 973 #undef EBP
 974 #define EBP (env->regs[R_EBP])
 975 #undef ESI
 976 #define ESI (env->regs[R_ESI])
 977 #undef EDI
 978 #define EDI (env->regs[R_EDI])
 979 #undef EIP
 980 #define EIP (env->eip)
 981 #define DF  (env->df)
 982
 983 #define CC_SRC (env->cc_src)
 984 #define CC_DST (env->cc_dst)
 985 #define CC_OP  (env->cc_op)
 986
 987 /* float macros */
 988 #define FT0    (env->ft0)
 989 #define ST0    (env->fpregs[env->fpstt].d)
 990 #define ST(n)  (env->fpregs[(env->fpstt + (n)) & 7].d)
 991 #define ST1    ST(1)
 992
 993 /* translate.c */
 994 void optimize_flags_init(void);
 995
 996 #if defined(CONFIG_USER_ONLY)
 997 static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
 998 {
 999     if (newsp)
1000         env->regs[R_ESP] = newsp;
1001     env->regs[R_EAX] = 0;
1002 }
1003 #endif
1004
1005 #include "cpu-all.h"
1006 #include "svm.h"
1007
1008 #if !defined(CONFIG_USER_ONLY)
1009 #include "hw/apic.h"
1010 #endif
1011
1012 static inline bool cpu_has_work(CPUState *env)
1013 {
1014     return ((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1015             (env->eflags & IF_MASK)) ||
1016            (env->interrupt_request & (CPU_INTERRUPT_NMI |
1017                                       CPU_INTERRUPT_INIT |
1018                                       CPU_INTERRUPT_SIPI |
1019                                       CPU_INTERRUPT_MCE));
1020 }
1021
1022 #include "exec-all.h"
1023
1024 static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
1025 {
1026     env->eip = tb->pc - tb->cs_base;
1027 }
1028
1029 static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
1030                                         target_ulong *cs_base, int *flags)
1031 {
1032     *cs_base = env->segs[R_CS].base;
1033     *pc = *cs_base + env->eip;
1034     *flags = env->hflags |
1035         (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK));
1036 }
1037
1038 void do_cpu_init(CPUState *env);
1039 void do_cpu_sipi(CPUState *env);
1040
1041 #define MCE_INJECT_BROADCAST    1
1042 #define MCE_INJECT_UNCOND_AO    2
1043
1044 void cpu_x86_inject_mce(Monitor *mon, CPUState *cenv, int bank,
1045                         uint64_t status, uint64_t mcg_status, uint64_t addr,
1046                         uint64_t misc, int flags);
1047
1048 /* op_helper.c */
1049 void do_interrupt(CPUState *env);
1050 void do_interrupt_x86_hardirq(CPUState *env, int intno, int is_hw);
1051 void QEMU_NORETURN raise_exception_env(int exception_index, CPUState *nenv);
1052 void QEMU_NORETURN raise_exception_err_env(CPUState *nenv, int exception_index,
1053                                            int error_code);
1054
1055 void do_smm_enter(CPUState *env1);
1056
1057 void svm_check_intercept(CPUState *env1, uint32_t type);
1058
1059 uint32_t cpu_cc_compute_all(CPUState *env1, int op);
1060
1061 #endif /* CPU_I386_H */