2 * QEMU Motorla 680x0 Macintosh hardware System Emulator
4 * Permission is hereby granted, free of charge, to any person obtaining a copy
5 * of this software and associated documentation files (the "Software"), to deal
6 * in the Software without restriction, including without limitation the rights
7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
8 * copies of the Software, and to permit persons to whom the Software is
9 * furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 #include "qemu/osdep.h"
24 #include "qemu/units.h"
25 #include "qemu-common.h"
26 #include "qemu/datadir.h"
27 #include "sysemu/sysemu.h"
29 #include "hw/boards.h"
30 #include "hw/or-irq.h"
33 #include "hw/loader.h"
34 #include "ui/console.h"
35 #include "hw/char/escc.h"
36 #include "hw/sysbus.h"
37 #include "hw/scsi/esp.h"
38 #include "standard-headers/asm-m68k/bootinfo.h"
39 #include "standard-headers/asm-m68k/bootinfo-mac.h"
41 #include "hw/misc/mac_via.h"
42 #include "hw/input/adb.h"
43 #include "hw/nubus/mac-nubus-bridge.h"
44 #include "hw/display/macfb.h"
45 #include "hw/block/swim.h"
47 #include "qapi/error.h"
48 #include "sysemu/qtest.h"
49 #include "sysemu/runstate.h"
50 #include "sysemu/reset.h"
51 #include "migration/vmstate.h"
53 #define MACROM_ADDR 0x40800000
54 #define MACROM_SIZE 0x00100000
56 #define MACROM_FILENAME "MacROM.bin"
58 #define IO_BASE 0x50000000
59 #define IO_SLICE 0x00040000
60 #define IO_SIZE 0x04000000
62 #define VIA_BASE (IO_BASE + 0x00000)
63 #define SONIC_PROM_BASE (IO_BASE + 0x08000)
64 #define SONIC_BASE (IO_BASE + 0x0a000)
65 #define SCC_BASE (IO_BASE + 0x0c020)
66 #define ESP_BASE (IO_BASE + 0x10000)
67 #define ESP_PDMA (IO_BASE + 0x10100)
68 #define ASC_BASE (IO_BASE + 0x14000)
69 #define SWIM_BASE (IO_BASE + 0x1E000)
71 #define SONIC_PROM_SIZE 0x1000
74 * the video base, whereas it a Nubus address,
75 * is needed by the kernel to have early display and
76 * thus provided by the bootloader
78 #define VIDEO_BASE 0xf9000000
80 #define MAC_CLOCK 3686418
83 * Slot 0x9 is reserved for use by the in-built framebuffer whilst only
84 * slots 0xc, 0xd and 0xe physically exist on the Quadra 800
86 #define Q800_NUBUS_SLOTS_AVAILABLE (BIT(0x9) | BIT(0xc) | BIT(0xd) | \
90 * The GLUE (General Logic Unit) is an Apple custom integrated circuit chip
91 * that performs a variety of functions (RAM management, clock generation, ...).
92 * The GLUE chip receives interrupt requests from various devices,
93 * assign priority to each, and asserts one or more interrupt line to the
97 #define TYPE_GLUE "q800-glue"
98 OBJECT_DECLARE_SIMPLE_TYPE(GLUEState
, GLUE
)
101 SysBusDevice parent_obj
;
106 QEMUTimer
*nmi_release
;
109 #define GLUE_IRQ_IN_VIA1 0
110 #define GLUE_IRQ_IN_VIA2 1
111 #define GLUE_IRQ_IN_SONIC 2
112 #define GLUE_IRQ_IN_ESCC 3
113 #define GLUE_IRQ_IN_NMI 4
115 #define GLUE_IRQ_NUBUS_9 0
118 * The GLUE logic on the Quadra 800 supports 2 different IRQ routing modes
119 * controlled from the VIA1 auxmode GPIO (port B bit 6) which are documented
120 * in NetBSD as follows:
122 * A/UX mode (Linux, NetBSD, auxmode GPIO low)
124 * Level 0: Spurious: ignored
126 * Level 2: VIA2 (except ethernet, sound)
128 * Level 4: Serial (SCC)
131 * Level 7: NMIs: parity errors, RESET button, YANCC error
133 * Classic mode (default: used by MacOS, A/UX 3.0.1, auxmode GPIO high)
135 * Level 0: Spurious: ignored
136 * Level 1: VIA1 (clock, ADB)
137 * Level 2: VIA2 (NuBus, SCSI)
139 * Level 4: Serial (SCC)
142 * Level 7: Non-maskable: parity errors, RESET button
144 * Note that despite references to A/UX mode in Linux and NetBSD, at least
145 * A/UX 3.0.1 still uses Classic mode.
148 static void GLUE_set_irq(void *opaque
, int irq
, int level
)
150 GLUEState
*s
= opaque
;
156 case GLUE_IRQ_IN_VIA1
:
160 case GLUE_IRQ_IN_VIA2
:
164 case GLUE_IRQ_IN_SONIC
:
165 /* Route to VIA2 instead */
166 qemu_set_irq(s
->irqs
[GLUE_IRQ_NUBUS_9
], level
);
169 case GLUE_IRQ_IN_ESCC
:
173 case GLUE_IRQ_IN_NMI
:
178 g_assert_not_reached();
183 case GLUE_IRQ_IN_VIA1
:
187 case GLUE_IRQ_IN_VIA2
:
191 case GLUE_IRQ_IN_SONIC
:
195 case GLUE_IRQ_IN_ESCC
:
199 case GLUE_IRQ_IN_NMI
:
204 g_assert_not_reached();
211 s
->ipr
&= ~(1 << irq
);
214 for (i
= 7; i
>= 0; i
--) {
215 if ((s
->ipr
>> i
) & 1) {
216 m68k_set_irq_level(s
->cpu
, i
+ 1, i
+ 25);
220 m68k_set_irq_level(s
->cpu
, 0, 0);
223 static void glue_auxmode_set_irq(void *opaque
, int irq
, int level
)
225 GLUEState
*s
= GLUE(opaque
);
230 static void glue_nmi(NMIState
*n
, int cpu_index
, Error
**errp
)
232 GLUEState
*s
= GLUE(n
);
234 /* Hold NMI active for 100ms */
235 GLUE_set_irq(s
, GLUE_IRQ_IN_NMI
, 1);
236 timer_mod(s
->nmi_release
, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL
) + 100);
239 static void glue_nmi_release(void *opaque
)
241 GLUEState
*s
= GLUE(opaque
);
243 GLUE_set_irq(s
, GLUE_IRQ_IN_NMI
, 0);
246 static void glue_reset(DeviceState
*dev
)
248 GLUEState
*s
= GLUE(dev
);
253 timer_del(s
->nmi_release
);
256 static const VMStateDescription vmstate_glue
= {
259 .minimum_version_id
= 0,
260 .fields
= (VMStateField
[]) {
261 VMSTATE_UINT8(ipr
, GLUEState
),
262 VMSTATE_UINT8(auxmode
, GLUEState
),
263 VMSTATE_TIMER_PTR(nmi_release
, GLUEState
),
264 VMSTATE_END_OF_LIST(),
269 * If the m68k CPU implemented its inbound irq lines as GPIO lines
270 * rather than via the m68k_set_irq_level() function we would not need
271 * this cpu link property and could instead provide outbound IRQ lines
272 * that the board could wire up to the CPU.
274 static Property glue_properties
[] = {
275 DEFINE_PROP_LINK("cpu", GLUEState
, cpu
, TYPE_M68K_CPU
, M68kCPU
*),
276 DEFINE_PROP_END_OF_LIST(),
279 static void glue_finalize(Object
*obj
)
281 GLUEState
*s
= GLUE(obj
);
283 timer_free(s
->nmi_release
);
286 static void glue_init(Object
*obj
)
288 DeviceState
*dev
= DEVICE(obj
);
289 GLUEState
*s
= GLUE(dev
);
291 qdev_init_gpio_in(dev
, GLUE_set_irq
, 8);
292 qdev_init_gpio_in_named(dev
, glue_auxmode_set_irq
, "auxmode", 1);
294 qdev_init_gpio_out(dev
, s
->irqs
, 1);
296 /* NMI release timer */
297 s
->nmi_release
= timer_new_ms(QEMU_CLOCK_VIRTUAL
, glue_nmi_release
, s
);
300 static void glue_class_init(ObjectClass
*klass
, void *data
)
302 DeviceClass
*dc
= DEVICE_CLASS(klass
);
303 NMIClass
*nc
= NMI_CLASS(klass
);
305 dc
->vmsd
= &vmstate_glue
;
306 dc
->reset
= glue_reset
;
307 device_class_set_props(dc
, glue_properties
);
308 nc
->nmi_monitor_handler
= glue_nmi
;
311 static const TypeInfo glue_info
= {
313 .parent
= TYPE_SYS_BUS_DEVICE
,
314 .instance_size
= sizeof(GLUEState
),
315 .instance_init
= glue_init
,
316 .instance_finalize
= glue_finalize
,
317 .class_init
= glue_class_init
,
318 .interfaces
= (InterfaceInfo
[]) {
324 static void main_cpu_reset(void *opaque
)
326 M68kCPU
*cpu
= opaque
;
327 CPUState
*cs
= CPU(cpu
);
330 cpu
->env
.aregs
[7] = ldl_phys(cs
->as
, 0);
331 cpu
->env
.pc
= ldl_phys(cs
->as
, 4);
334 static uint8_t fake_mac_rom
[] = {
335 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
337 /* offset: 0xa - mac_reset */
339 /* via2[vDirB] |= VIA2B_vPower */
340 0x20, 0x7C, 0x50, 0xF0, 0x24, 0x00, /* moveal VIA2_BASE+vDirB,%a0 */
341 0x10, 0x10, /* moveb %a0@,%d0 */
342 0x00, 0x00, 0x00, 0x04, /* orib #4,%d0 */
343 0x10, 0x80, /* moveb %d0,%a0@ */
345 /* via2[vBufB] &= ~VIA2B_vPower */
346 0x20, 0x7C, 0x50, 0xF0, 0x20, 0x00, /* moveal VIA2_BASE+vBufB,%a0 */
347 0x10, 0x10, /* moveb %a0@,%d0 */
348 0x02, 0x00, 0xFF, 0xFB, /* andib #-5,%d0 */
349 0x10, 0x80, /* moveb %d0,%a0@ */
352 0x60, 0xFE /* bras [self] */
355 static void q800_init(MachineState
*machine
)
363 ram_addr_t initrd_base
;
367 MemoryRegion
*dp8393x_prom
= g_new(MemoryRegion
, 1);
369 const int io_slice_nb
= (IO_SIZE
/ IO_SLICE
) - 1;
371 MacFbMode
*macfb_mode
;
372 ram_addr_t ram_size
= machine
->ram_size
;
373 const char *kernel_filename
= machine
->kernel_filename
;
374 const char *initrd_filename
= machine
->initrd_filename
;
375 const char *kernel_cmdline
= machine
->kernel_cmdline
;
376 const char *bios_name
= machine
->firmware
?: MACROM_FILENAME
;
377 hwaddr parameters_base
;
380 DeviceState
*via1_dev
, *via2_dev
;
381 DeviceState
*escc_orgate
;
382 SysBusESPState
*sysbus_esp
;
384 SysBusDevice
*sysbus
;
390 linux_boot
= (kernel_filename
!= NULL
);
392 if (ram_size
> 1 * GiB
) {
393 error_report("Too much memory for this machine: %" PRId64
" MiB, "
394 "maximum 1024 MiB", ram_size
/ MiB
);
399 cpu
= M68K_CPU(cpu_create(machine
->cpu_type
));
400 qemu_register_reset(main_cpu_reset
, cpu
);
403 memory_region_add_subregion(get_system_memory(), 0, machine
->ram
);
406 * Memory from IO_BASE to IO_BASE + IO_SLICE is repeated
407 * from IO_BASE + IO_SLICE to IO_BASE + IO_SIZE
409 io
= g_new(MemoryRegion
, io_slice_nb
);
410 for (i
= 0; i
< io_slice_nb
; i
++) {
411 char *name
= g_strdup_printf("mac_m68k.io[%d]", i
+ 1);
413 memory_region_init_alias(&io
[i
], NULL
, name
, get_system_memory(),
415 memory_region_add_subregion(get_system_memory(),
416 IO_BASE
+ (i
+ 1) * IO_SLICE
, &io
[i
]);
421 glue
= qdev_new(TYPE_GLUE
);
422 object_property_set_link(OBJECT(glue
), "cpu", OBJECT(cpu
), &error_abort
);
423 sysbus_realize_and_unref(SYS_BUS_DEVICE(glue
), &error_fatal
);
426 via1_dev
= qdev_new(TYPE_MOS6522_Q800_VIA1
);
427 dinfo
= drive_get(IF_MTD
, 0, 0);
429 qdev_prop_set_drive(via1_dev
, "drive", blk_by_legacy_dinfo(dinfo
));
431 sysbus
= SYS_BUS_DEVICE(via1_dev
);
432 sysbus_realize_and_unref(sysbus
, &error_fatal
);
433 sysbus_mmio_map(sysbus
, 1, VIA_BASE
);
434 sysbus_connect_irq(sysbus
, 0, qdev_get_gpio_in(glue
, GLUE_IRQ_IN_VIA1
));
436 qdev_connect_gpio_out(via1_dev
, 0,
437 qdev_get_gpio_in_named(glue
, "auxmode", 0));
439 adb_bus
= qdev_get_child_bus(via1_dev
, "adb.0");
440 dev
= qdev_new(TYPE_ADB_KEYBOARD
);
441 qdev_realize_and_unref(dev
, adb_bus
, &error_fatal
);
442 dev
= qdev_new(TYPE_ADB_MOUSE
);
443 qdev_realize_and_unref(dev
, adb_bus
, &error_fatal
);
446 via2_dev
= qdev_new(TYPE_MOS6522_Q800_VIA2
);
447 sysbus
= SYS_BUS_DEVICE(via2_dev
);
448 sysbus_realize_and_unref(sysbus
, &error_fatal
);
449 sysbus_mmio_map(sysbus
, 1, VIA_BASE
+ VIA_SIZE
);
450 sysbus_connect_irq(sysbus
, 0, qdev_get_gpio_in(glue
, GLUE_IRQ_IN_VIA2
));
455 error_report("q800 can only have one ethernet interface");
459 qemu_check_nic_model(&nd_table
[0], "dp83932");
462 * MacSonic driver needs an Apple MAC address
465 * 00:80:19 Dayna Communications, Inc.
468 * (Q800 use the last one)
470 nd_table
[0].macaddr
.a
[0] = 0x08;
471 nd_table
[0].macaddr
.a
[1] = 0x00;
472 nd_table
[0].macaddr
.a
[2] = 0x07;
474 dev
= qdev_new("dp8393x");
475 qdev_set_nic_properties(dev
, &nd_table
[0]);
476 qdev_prop_set_uint8(dev
, "it_shift", 2);
477 qdev_prop_set_bit(dev
, "big_endian", true);
478 object_property_set_link(OBJECT(dev
), "dma_mr",
479 OBJECT(get_system_memory()), &error_abort
);
480 sysbus
= SYS_BUS_DEVICE(dev
);
481 sysbus_realize_and_unref(sysbus
, &error_fatal
);
482 sysbus_mmio_map(sysbus
, 0, SONIC_BASE
);
483 sysbus_connect_irq(sysbus
, 0, qdev_get_gpio_in(glue
, GLUE_IRQ_IN_SONIC
));
485 memory_region_init_rom(dp8393x_prom
, NULL
, "dp8393x-q800.prom",
486 SONIC_PROM_SIZE
, &error_fatal
);
487 memory_region_add_subregion(get_system_memory(), SONIC_PROM_BASE
,
490 /* Add MAC address with valid checksum to PROM */
491 prom
= memory_region_get_ram_ptr(dp8393x_prom
);
493 for (i
= 0; i
< 6; i
++) {
494 prom
[i
] = revbit8(nd_table
[0].macaddr
.a
[i
]);
497 prom
[7] = 0xff - checksum
;
501 dev
= qdev_new(TYPE_ESCC
);
502 qdev_prop_set_uint32(dev
, "disabled", 0);
503 qdev_prop_set_uint32(dev
, "frequency", MAC_CLOCK
);
504 qdev_prop_set_uint32(dev
, "it_shift", 1);
505 qdev_prop_set_bit(dev
, "bit_swap", true);
506 qdev_prop_set_chr(dev
, "chrA", serial_hd(0));
507 qdev_prop_set_chr(dev
, "chrB", serial_hd(1));
508 qdev_prop_set_uint32(dev
, "chnBtype", 0);
509 qdev_prop_set_uint32(dev
, "chnAtype", 0);
510 sysbus
= SYS_BUS_DEVICE(dev
);
511 sysbus_realize_and_unref(sysbus
, &error_fatal
);
513 /* Logically OR both its IRQs together */
514 escc_orgate
= DEVICE(object_new(TYPE_OR_IRQ
));
515 object_property_set_int(OBJECT(escc_orgate
), "num-lines", 2, &error_fatal
);
516 qdev_realize_and_unref(escc_orgate
, NULL
, &error_fatal
);
517 sysbus_connect_irq(sysbus
, 0, qdev_get_gpio_in(escc_orgate
, 0));
518 sysbus_connect_irq(sysbus
, 1, qdev_get_gpio_in(escc_orgate
, 1));
519 qdev_connect_gpio_out(DEVICE(escc_orgate
), 0,
520 qdev_get_gpio_in(glue
, GLUE_IRQ_IN_ESCC
));
521 sysbus_mmio_map(sysbus
, 0, SCC_BASE
);
525 dev
= qdev_new(TYPE_SYSBUS_ESP
);
526 sysbus_esp
= SYSBUS_ESP(dev
);
527 esp
= &sysbus_esp
->esp
;
528 esp
->dma_memory_read
= NULL
;
529 esp
->dma_memory_write
= NULL
;
530 esp
->dma_opaque
= NULL
;
531 sysbus_esp
->it_shift
= 4;
532 esp
->dma_enabled
= 1;
534 sysbus
= SYS_BUS_DEVICE(dev
);
535 sysbus_realize_and_unref(sysbus
, &error_fatal
);
536 sysbus_connect_irq(sysbus
, 0, qdev_get_gpio_in(via2_dev
,
538 sysbus_connect_irq(sysbus
, 1, qdev_get_gpio_in(via2_dev
,
539 VIA2_IRQ_SCSI_DATA_BIT
));
540 sysbus_mmio_map(sysbus
, 0, ESP_BASE
);
541 sysbus_mmio_map(sysbus
, 1, ESP_PDMA
);
543 scsi_bus_legacy_handle_cmdline(&esp
->bus
);
545 /* SWIM floppy controller */
547 dev
= qdev_new(TYPE_SWIM
);
548 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
549 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, SWIM_BASE
);
553 dev
= qdev_new(TYPE_MAC_NUBUS_BRIDGE
);
554 qdev_prop_set_uint32(dev
, "slot-available-mask",
555 Q800_NUBUS_SLOTS_AVAILABLE
);
556 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
557 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0,
558 MAC_NUBUS_FIRST_SLOT
* NUBUS_SUPER_SLOT_SIZE
);
559 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 1, NUBUS_SLOT_BASE
+
560 MAC_NUBUS_FIRST_SLOT
* NUBUS_SLOT_SIZE
);
561 qdev_connect_gpio_out(dev
, 9,
562 qdev_get_gpio_in_named(via2_dev
, "nubus-irq",
563 VIA2_NUBUS_IRQ_INTVIDEO
));
564 for (i
= 1; i
< VIA2_NUBUS_IRQ_NB
; i
++) {
565 qdev_connect_gpio_out(dev
, 9 + i
,
566 qdev_get_gpio_in_named(via2_dev
, "nubus-irq",
567 VIA2_NUBUS_IRQ_9
+ i
));
571 * Since the framebuffer in slot 0x9 uses a separate IRQ, wire the unused
572 * IRQ via GLUE for use by SONIC Ethernet in classic mode
574 qdev_connect_gpio_out(glue
, GLUE_IRQ_NUBUS_9
,
575 qdev_get_gpio_in_named(via2_dev
, "nubus-irq",
578 nubus
= &NUBUS_BRIDGE(dev
)->bus
;
580 /* framebuffer in nubus slot #9 */
582 dev
= qdev_new(TYPE_NUBUS_MACFB
);
583 qdev_prop_set_uint32(dev
, "slot", 9);
584 qdev_prop_set_uint32(dev
, "width", graphic_width
);
585 qdev_prop_set_uint32(dev
, "height", graphic_height
);
586 qdev_prop_set_uint8(dev
, "depth", graphic_depth
);
587 if (graphic_width
== 1152 && graphic_height
== 870) {
588 qdev_prop_set_uint8(dev
, "display", MACFB_DISPLAY_APPLE_21_COLOR
);
590 qdev_prop_set_uint8(dev
, "display", MACFB_DISPLAY_VGA
);
592 qdev_realize_and_unref(dev
, BUS(nubus
), &error_fatal
);
594 macfb_mode
= (NUBUS_MACFB(dev
)->macfb
).mode
;
599 kernel_size
= load_elf(kernel_filename
, NULL
, NULL
, NULL
,
600 &elf_entry
, NULL
, &high
, NULL
, 1,
602 if (kernel_size
< 0) {
603 error_report("could not load kernel '%s'", kernel_filename
);
606 stl_phys(cs
->as
, 4, elf_entry
); /* reset initial PC */
607 parameters_base
= (high
+ 1) & ~1;
609 BOOTINFO1(cs
->as
, parameters_base
, BI_MACHTYPE
, MACH_MAC
);
610 BOOTINFO1(cs
->as
, parameters_base
, BI_FPUTYPE
, FPU_68040
);
611 BOOTINFO1(cs
->as
, parameters_base
, BI_MMUTYPE
, MMU_68040
);
612 BOOTINFO1(cs
->as
, parameters_base
, BI_CPUTYPE
, CPU_68040
);
613 BOOTINFO1(cs
->as
, parameters_base
, BI_MAC_CPUID
, CPUB_68040
);
614 BOOTINFO1(cs
->as
, parameters_base
, BI_MAC_MODEL
, MAC_MODEL_Q800
);
615 BOOTINFO1(cs
->as
, parameters_base
,
616 BI_MAC_MEMSIZE
, ram_size
>> 20); /* in MB */
617 BOOTINFO2(cs
->as
, parameters_base
, BI_MEMCHUNK
, 0, ram_size
);
618 BOOTINFO1(cs
->as
, parameters_base
, BI_MAC_VADDR
,
619 VIDEO_BASE
+ macfb_mode
->offset
);
620 BOOTINFO1(cs
->as
, parameters_base
, BI_MAC_VDEPTH
, graphic_depth
);
621 BOOTINFO1(cs
->as
, parameters_base
, BI_MAC_VDIM
,
622 (graphic_height
<< 16) | graphic_width
);
623 BOOTINFO1(cs
->as
, parameters_base
, BI_MAC_VROW
, macfb_mode
->stride
);
624 BOOTINFO1(cs
->as
, parameters_base
, BI_MAC_SCCBASE
, SCC_BASE
);
626 rom
= g_malloc(sizeof(*rom
));
627 memory_region_init_ram_ptr(rom
, NULL
, "m68k_fake_mac.rom",
628 sizeof(fake_mac_rom
), fake_mac_rom
);
629 memory_region_set_readonly(rom
, true);
630 memory_region_add_subregion(get_system_memory(), MACROM_ADDR
, rom
);
632 if (kernel_cmdline
) {
633 BOOTINFOSTR(cs
->as
, parameters_base
, BI_COMMAND_LINE
,
638 if (initrd_filename
) {
639 initrd_size
= get_image_size(initrd_filename
);
640 if (initrd_size
< 0) {
641 error_report("could not load initial ram disk '%s'",
646 initrd_base
= (ram_size
- initrd_size
) & TARGET_PAGE_MASK
;
647 load_image_targphys(initrd_filename
, initrd_base
,
648 ram_size
- initrd_base
);
649 BOOTINFO2(cs
->as
, parameters_base
, BI_RAMDISK
, initrd_base
,
655 BOOTINFO0(cs
->as
, parameters_base
, BI_LAST
);
658 /* allocate and load BIOS */
659 rom
= g_malloc(sizeof(*rom
));
660 memory_region_init_rom(rom
, NULL
, "m68k_mac.rom", MACROM_SIZE
,
662 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
663 memory_region_add_subregion(get_system_memory(), MACROM_ADDR
, rom
);
665 /* Load MacROM binary */
667 bios_size
= load_image_targphys(filename
, MACROM_ADDR
, MACROM_SIZE
);
673 /* Remove qtest_enabled() check once firmware files are in the tree */
674 if (!qtest_enabled()) {
675 if (bios_size
<= 0 || bios_size
> MACROM_SIZE
) {
676 error_report("could not load MacROM '%s'", bios_name
);
680 ptr
= rom_ptr(MACROM_ADDR
, bios_size
);
682 stl_phys(cs
->as
, 0, ldl_p(ptr
)); /* reset initial SP */
684 MACROM_ADDR
+ ldl_p(ptr
+ 4)); /* reset initial PC */
689 static void q800_machine_class_init(ObjectClass
*oc
, void *data
)
691 MachineClass
*mc
= MACHINE_CLASS(oc
);
692 mc
->desc
= "Macintosh Quadra 800";
693 mc
->init
= q800_init
;
694 mc
->default_cpu_type
= M68K_CPU_TYPE_NAME("m68040");
696 mc
->block_default_type
= IF_SCSI
;
697 mc
->default_ram_id
= "m68k_mac.ram";
700 static const TypeInfo q800_machine_typeinfo
= {
701 .name
= MACHINE_TYPE_NAME("q800"),
702 .parent
= TYPE_MACHINE
,
703 .class_init
= q800_machine_class_init
,
706 static void q800_machine_register_types(void)
708 type_register_static(&q800_machine_typeinfo
);
709 type_register_static(&glue_info
);
712 type_init(q800_machine_register_types
)