3 #include "hw/i386/pc.h"
4 #include "hw/isa/isa.h"
7 #include "sysemu/kvm.h"
9 static const VMStateDescription vmstate_segment
= {
12 .minimum_version_id
= 1,
13 .fields
= (VMStateField
[]) {
14 VMSTATE_UINT32(selector
, SegmentCache
),
15 VMSTATE_UINTTL(base
, SegmentCache
),
16 VMSTATE_UINT32(limit
, SegmentCache
),
17 VMSTATE_UINT32(flags
, SegmentCache
),
22 #define VMSTATE_SEGMENT(_field, _state) { \
23 .name = (stringify(_field)), \
24 .size = sizeof(SegmentCache), \
25 .vmsd = &vmstate_segment, \
26 .flags = VMS_STRUCT, \
27 .offset = offsetof(_state, _field) \
28 + type_check(SegmentCache,typeof_field(_state, _field)) \
31 #define VMSTATE_SEGMENT_ARRAY(_field, _state, _n) \
32 VMSTATE_STRUCT_ARRAY(_field, _state, _n, 0, vmstate_segment, SegmentCache)
34 static const VMStateDescription vmstate_xmm_reg
= {
37 .minimum_version_id
= 1,
38 .fields
= (VMStateField
[]) {
39 VMSTATE_UINT64(XMM_Q(0), XMMReg
),
40 VMSTATE_UINT64(XMM_Q(1), XMMReg
),
45 #define VMSTATE_XMM_REGS(_field, _state, _start) \
46 VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, CPU_NB_REGS, 0, \
47 vmstate_xmm_reg, XMMReg)
49 /* YMMH format is the same as XMM, but for bits 128-255 */
50 static const VMStateDescription vmstate_ymmh_reg
= {
53 .minimum_version_id
= 1,
54 .fields
= (VMStateField
[]) {
55 VMSTATE_UINT64(XMM_Q(2), XMMReg
),
56 VMSTATE_UINT64(XMM_Q(3), XMMReg
),
61 #define VMSTATE_YMMH_REGS_VARS(_field, _state, _start, _v) \
62 VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, CPU_NB_REGS, _v, \
63 vmstate_ymmh_reg, XMMReg)
65 static const VMStateDescription vmstate_zmmh_reg
= {
68 .minimum_version_id
= 1,
69 .fields
= (VMStateField
[]) {
70 VMSTATE_UINT64(XMM_Q(4), XMMReg
),
71 VMSTATE_UINT64(XMM_Q(5), XMMReg
),
72 VMSTATE_UINT64(XMM_Q(6), XMMReg
),
73 VMSTATE_UINT64(XMM_Q(7), XMMReg
),
78 #define VMSTATE_ZMMH_REGS_VARS(_field, _state, _start) \
79 VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, CPU_NB_REGS, 0, \
80 vmstate_zmmh_reg, XMMReg)
83 static const VMStateDescription vmstate_hi16_zmm_reg
= {
84 .name
= "hi16_zmm_reg",
86 .minimum_version_id
= 1,
87 .fields
= (VMStateField
[]) {
88 VMSTATE_UINT64(XMM_Q(0), XMMReg
),
89 VMSTATE_UINT64(XMM_Q(1), XMMReg
),
90 VMSTATE_UINT64(XMM_Q(2), XMMReg
),
91 VMSTATE_UINT64(XMM_Q(3), XMMReg
),
92 VMSTATE_UINT64(XMM_Q(4), XMMReg
),
93 VMSTATE_UINT64(XMM_Q(5), XMMReg
),
94 VMSTATE_UINT64(XMM_Q(6), XMMReg
),
95 VMSTATE_UINT64(XMM_Q(7), XMMReg
),
100 #define VMSTATE_Hi16_ZMM_REGS_VARS(_field, _state, _start) \
101 VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, CPU_NB_REGS, 0, \
102 vmstate_hi16_zmm_reg, XMMReg)
105 static const VMStateDescription vmstate_bnd_regs
= {
108 .minimum_version_id
= 1,
109 .fields
= (VMStateField
[]) {
110 VMSTATE_UINT64(lb
, BNDReg
),
111 VMSTATE_UINT64(ub
, BNDReg
),
112 VMSTATE_END_OF_LIST()
116 #define VMSTATE_BND_REGS(_field, _state, _n) \
117 VMSTATE_STRUCT_ARRAY(_field, _state, _n, 0, vmstate_bnd_regs, BNDReg)
119 static const VMStateDescription vmstate_mtrr_var
= {
122 .minimum_version_id
= 1,
123 .fields
= (VMStateField
[]) {
124 VMSTATE_UINT64(base
, MTRRVar
),
125 VMSTATE_UINT64(mask
, MTRRVar
),
126 VMSTATE_END_OF_LIST()
130 #define VMSTATE_MTRR_VARS(_field, _state, _n, _v) \
131 VMSTATE_STRUCT_ARRAY(_field, _state, _n, _v, vmstate_mtrr_var, MTRRVar)
133 static void put_fpreg_error(QEMUFile
*f
, void *opaque
, size_t size
)
135 fprintf(stderr
, "call put_fpreg() with invalid arguments\n");
139 /* XXX: add that in a FPU generic layer */
140 union x86_longdouble
{
145 #define MANTD1(fp) (fp & ((1LL << 52) - 1))
146 #define EXPBIAS1 1023
147 #define EXPD1(fp) ((fp >> 52) & 0x7FF)
148 #define SIGND1(fp) ((fp >> 32) & 0x80000000)
150 static void fp64_to_fp80(union x86_longdouble
*p
, uint64_t temp
)
154 p
->mant
= (MANTD1(temp
) << 11) | (1LL << 63);
155 /* exponent + sign */
156 e
= EXPD1(temp
) - EXPBIAS1
+ 16383;
157 e
|= SIGND1(temp
) >> 16;
161 static int get_fpreg(QEMUFile
*f
, void *opaque
, size_t size
)
163 FPReg
*fp_reg
= opaque
;
167 qemu_get_be64s(f
, &mant
);
168 qemu_get_be16s(f
, &exp
);
169 fp_reg
->d
= cpu_set_fp80(mant
, exp
);
173 static void put_fpreg(QEMUFile
*f
, void *opaque
, size_t size
)
175 FPReg
*fp_reg
= opaque
;
178 /* we save the real CPU data (in case of MMX usage only 'mant'
179 contains the MMX register */
180 cpu_get_fp80(&mant
, &exp
, fp_reg
->d
);
181 qemu_put_be64s(f
, &mant
);
182 qemu_put_be16s(f
, &exp
);
185 static const VMStateInfo vmstate_fpreg
= {
191 static int get_fpreg_1_mmx(QEMUFile
*f
, void *opaque
, size_t size
)
193 union x86_longdouble
*p
= opaque
;
196 qemu_get_be64s(f
, &mant
);
202 static const VMStateInfo vmstate_fpreg_1_mmx
= {
203 .name
= "fpreg_1_mmx",
204 .get
= get_fpreg_1_mmx
,
205 .put
= put_fpreg_error
,
208 static int get_fpreg_1_no_mmx(QEMUFile
*f
, void *opaque
, size_t size
)
210 union x86_longdouble
*p
= opaque
;
213 qemu_get_be64s(f
, &mant
);
214 fp64_to_fp80(p
, mant
);
218 static const VMStateInfo vmstate_fpreg_1_no_mmx
= {
219 .name
= "fpreg_1_no_mmx",
220 .get
= get_fpreg_1_no_mmx
,
221 .put
= put_fpreg_error
,
224 static bool fpregs_is_0(void *opaque
, int version_id
)
226 X86CPU
*cpu
= opaque
;
227 CPUX86State
*env
= &cpu
->env
;
229 return (env
->fpregs_format_vmstate
== 0);
232 static bool fpregs_is_1_mmx(void *opaque
, int version_id
)
234 X86CPU
*cpu
= opaque
;
235 CPUX86State
*env
= &cpu
->env
;
238 guess_mmx
= ((env
->fptag_vmstate
== 0xff) &&
239 (env
->fpus_vmstate
& 0x3800) == 0);
240 return (guess_mmx
&& (env
->fpregs_format_vmstate
== 1));
243 static bool fpregs_is_1_no_mmx(void *opaque
, int version_id
)
245 X86CPU
*cpu
= opaque
;
246 CPUX86State
*env
= &cpu
->env
;
249 guess_mmx
= ((env
->fptag_vmstate
== 0xff) &&
250 (env
->fpus_vmstate
& 0x3800) == 0);
251 return (!guess_mmx
&& (env
->fpregs_format_vmstate
== 1));
254 #define VMSTATE_FP_REGS(_field, _state, _n) \
255 VMSTATE_ARRAY_TEST(_field, _state, _n, fpregs_is_0, vmstate_fpreg, FPReg), \
256 VMSTATE_ARRAY_TEST(_field, _state, _n, fpregs_is_1_mmx, vmstate_fpreg_1_mmx, FPReg), \
257 VMSTATE_ARRAY_TEST(_field, _state, _n, fpregs_is_1_no_mmx, vmstate_fpreg_1_no_mmx, FPReg)
259 static bool version_is_5(void *opaque
, int version_id
)
261 return version_id
== 5;
265 static bool less_than_7(void *opaque
, int version_id
)
267 return version_id
< 7;
270 static int get_uint64_as_uint32(QEMUFile
*f
, void *pv
, size_t size
)
273 *v
= qemu_get_be32(f
);
277 static void put_uint64_as_uint32(QEMUFile
*f
, void *pv
, size_t size
)
280 qemu_put_be32(f
, *v
);
283 static const VMStateInfo vmstate_hack_uint64_as_uint32
= {
284 .name
= "uint64_as_uint32",
285 .get
= get_uint64_as_uint32
,
286 .put
= put_uint64_as_uint32
,
289 #define VMSTATE_HACK_UINT32(_f, _s, _t) \
290 VMSTATE_SINGLE_TEST(_f, _s, _t, 0, vmstate_hack_uint64_as_uint32, uint64_t)
293 static void cpu_pre_save(void *opaque
)
295 X86CPU
*cpu
= opaque
;
296 CPUX86State
*env
= &cpu
->env
;
300 env
->fpus_vmstate
= (env
->fpus
& ~0x3800) | (env
->fpstt
& 0x7) << 11;
301 env
->fptag_vmstate
= 0;
302 for(i
= 0; i
< 8; i
++) {
303 env
->fptag_vmstate
|= ((!env
->fptags
[i
]) << i
);
306 env
->fpregs_format_vmstate
= 0;
309 * Real mode guest segments register DPL should be zero.
310 * Older KVM version were setting it wrongly.
311 * Fixing it will allow live migration to host with unrestricted guest
312 * support (otherwise the migration will fail with invalid guest state
315 if (!(env
->cr
[0] & CR0_PE_MASK
) &&
316 (env
->segs
[R_CS
].flags
>> DESC_DPL_SHIFT
& 3) != 0) {
317 env
->segs
[R_CS
].flags
&= ~(env
->segs
[R_CS
].flags
& DESC_DPL_MASK
);
318 env
->segs
[R_DS
].flags
&= ~(env
->segs
[R_DS
].flags
& DESC_DPL_MASK
);
319 env
->segs
[R_ES
].flags
&= ~(env
->segs
[R_ES
].flags
& DESC_DPL_MASK
);
320 env
->segs
[R_FS
].flags
&= ~(env
->segs
[R_FS
].flags
& DESC_DPL_MASK
);
321 env
->segs
[R_GS
].flags
&= ~(env
->segs
[R_GS
].flags
& DESC_DPL_MASK
);
322 env
->segs
[R_SS
].flags
&= ~(env
->segs
[R_SS
].flags
& DESC_DPL_MASK
);
327 static int cpu_post_load(void *opaque
, int version_id
)
329 X86CPU
*cpu
= opaque
;
330 CPUState
*cs
= CPU(cpu
);
331 CPUX86State
*env
= &cpu
->env
;
335 * Real mode guest segments register DPL should be zero.
336 * Older KVM version were setting it wrongly.
337 * Fixing it will allow live migration from such host that don't have
338 * restricted guest support to a host with unrestricted guest support
339 * (otherwise the migration will fail with invalid guest state
342 if (!(env
->cr
[0] & CR0_PE_MASK
) &&
343 (env
->segs
[R_CS
].flags
>> DESC_DPL_SHIFT
& 3) != 0) {
344 env
->segs
[R_CS
].flags
&= ~(env
->segs
[R_CS
].flags
& DESC_DPL_MASK
);
345 env
->segs
[R_DS
].flags
&= ~(env
->segs
[R_DS
].flags
& DESC_DPL_MASK
);
346 env
->segs
[R_ES
].flags
&= ~(env
->segs
[R_ES
].flags
& DESC_DPL_MASK
);
347 env
->segs
[R_FS
].flags
&= ~(env
->segs
[R_FS
].flags
& DESC_DPL_MASK
);
348 env
->segs
[R_GS
].flags
&= ~(env
->segs
[R_GS
].flags
& DESC_DPL_MASK
);
349 env
->segs
[R_SS
].flags
&= ~(env
->segs
[R_SS
].flags
& DESC_DPL_MASK
);
352 /* Older versions of QEMU incorrectly used CS.DPL as the CPL when
353 * running under KVM. This is wrong for conforming code segments.
354 * Luckily, in our implementation the CPL field of hflags is redundant
355 * and we can get the right value from the SS descriptor privilege level.
357 env
->hflags
&= ~HF_CPL_MASK
;
358 env
->hflags
|= (env
->segs
[R_SS
].flags
>> DESC_DPL_SHIFT
) & HF_CPL_MASK
;
360 env
->fpstt
= (env
->fpus_vmstate
>> 11) & 7;
361 env
->fpus
= env
->fpus_vmstate
& ~0x3800;
362 env
->fptag_vmstate
^= 0xff;
363 for(i
= 0; i
< 8; i
++) {
364 env
->fptags
[i
] = (env
->fptag_vmstate
>> i
) & 1;
366 update_fp_status(env
);
368 cpu_breakpoint_remove_all(cs
, BP_CPU
);
369 cpu_watchpoint_remove_all(cs
, BP_CPU
);
370 for (i
= 0; i
< DR7_MAX_BP
; i
++) {
371 hw_breakpoint_insert(env
, i
);
381 static bool async_pf_msr_needed(void *opaque
)
383 X86CPU
*cpu
= opaque
;
385 return cpu
->env
.async_pf_en_msr
!= 0;
388 static bool pv_eoi_msr_needed(void *opaque
)
390 X86CPU
*cpu
= opaque
;
392 return cpu
->env
.pv_eoi_en_msr
!= 0;
395 static bool steal_time_msr_needed(void *opaque
)
397 X86CPU
*cpu
= opaque
;
399 return cpu
->env
.steal_time_msr
!= 0;
402 static const VMStateDescription vmstate_steal_time_msr
= {
403 .name
= "cpu/steal_time_msr",
405 .minimum_version_id
= 1,
406 .fields
= (VMStateField
[]) {
407 VMSTATE_UINT64(env
.steal_time_msr
, X86CPU
),
408 VMSTATE_END_OF_LIST()
412 static const VMStateDescription vmstate_async_pf_msr
= {
413 .name
= "cpu/async_pf_msr",
415 .minimum_version_id
= 1,
416 .fields
= (VMStateField
[]) {
417 VMSTATE_UINT64(env
.async_pf_en_msr
, X86CPU
),
418 VMSTATE_END_OF_LIST()
422 static const VMStateDescription vmstate_pv_eoi_msr
= {
423 .name
= "cpu/async_pv_eoi_msr",
425 .minimum_version_id
= 1,
426 .fields
= (VMStateField
[]) {
427 VMSTATE_UINT64(env
.pv_eoi_en_msr
, X86CPU
),
428 VMSTATE_END_OF_LIST()
432 static bool fpop_ip_dp_needed(void *opaque
)
434 X86CPU
*cpu
= opaque
;
435 CPUX86State
*env
= &cpu
->env
;
437 return env
->fpop
!= 0 || env
->fpip
!= 0 || env
->fpdp
!= 0;
440 static const VMStateDescription vmstate_fpop_ip_dp
= {
441 .name
= "cpu/fpop_ip_dp",
443 .minimum_version_id
= 1,
444 .fields
= (VMStateField
[]) {
445 VMSTATE_UINT16(env
.fpop
, X86CPU
),
446 VMSTATE_UINT64(env
.fpip
, X86CPU
),
447 VMSTATE_UINT64(env
.fpdp
, X86CPU
),
448 VMSTATE_END_OF_LIST()
452 static bool tsc_adjust_needed(void *opaque
)
454 X86CPU
*cpu
= opaque
;
455 CPUX86State
*env
= &cpu
->env
;
457 return env
->tsc_adjust
!= 0;
460 static const VMStateDescription vmstate_msr_tsc_adjust
= {
461 .name
= "cpu/msr_tsc_adjust",
463 .minimum_version_id
= 1,
464 .fields
= (VMStateField
[]) {
465 VMSTATE_UINT64(env
.tsc_adjust
, X86CPU
),
466 VMSTATE_END_OF_LIST()
470 static bool tscdeadline_needed(void *opaque
)
472 X86CPU
*cpu
= opaque
;
473 CPUX86State
*env
= &cpu
->env
;
475 return env
->tsc_deadline
!= 0;
478 static const VMStateDescription vmstate_msr_tscdeadline
= {
479 .name
= "cpu/msr_tscdeadline",
481 .minimum_version_id
= 1,
482 .fields
= (VMStateField
[]) {
483 VMSTATE_UINT64(env
.tsc_deadline
, X86CPU
),
484 VMSTATE_END_OF_LIST()
488 static bool misc_enable_needed(void *opaque
)
490 X86CPU
*cpu
= opaque
;
491 CPUX86State
*env
= &cpu
->env
;
493 return env
->msr_ia32_misc_enable
!= MSR_IA32_MISC_ENABLE_DEFAULT
;
496 static bool feature_control_needed(void *opaque
)
498 X86CPU
*cpu
= opaque
;
499 CPUX86State
*env
= &cpu
->env
;
501 return env
->msr_ia32_feature_control
!= 0;
504 static const VMStateDescription vmstate_msr_ia32_misc_enable
= {
505 .name
= "cpu/msr_ia32_misc_enable",
507 .minimum_version_id
= 1,
508 .fields
= (VMStateField
[]) {
509 VMSTATE_UINT64(env
.msr_ia32_misc_enable
, X86CPU
),
510 VMSTATE_END_OF_LIST()
514 static const VMStateDescription vmstate_msr_ia32_feature_control
= {
515 .name
= "cpu/msr_ia32_feature_control",
517 .minimum_version_id
= 1,
518 .fields
= (VMStateField
[]) {
519 VMSTATE_UINT64(env
.msr_ia32_feature_control
, X86CPU
),
520 VMSTATE_END_OF_LIST()
524 static bool pmu_enable_needed(void *opaque
)
526 X86CPU
*cpu
= opaque
;
527 CPUX86State
*env
= &cpu
->env
;
530 if (env
->msr_fixed_ctr_ctrl
|| env
->msr_global_ctrl
||
531 env
->msr_global_status
|| env
->msr_global_ovf_ctrl
) {
534 for (i
= 0; i
< MAX_FIXED_COUNTERS
; i
++) {
535 if (env
->msr_fixed_counters
[i
]) {
539 for (i
= 0; i
< MAX_GP_COUNTERS
; i
++) {
540 if (env
->msr_gp_counters
[i
] || env
->msr_gp_evtsel
[i
]) {
548 static const VMStateDescription vmstate_msr_architectural_pmu
= {
549 .name
= "cpu/msr_architectural_pmu",
551 .minimum_version_id
= 1,
552 .fields
= (VMStateField
[]) {
553 VMSTATE_UINT64(env
.msr_fixed_ctr_ctrl
, X86CPU
),
554 VMSTATE_UINT64(env
.msr_global_ctrl
, X86CPU
),
555 VMSTATE_UINT64(env
.msr_global_status
, X86CPU
),
556 VMSTATE_UINT64(env
.msr_global_ovf_ctrl
, X86CPU
),
557 VMSTATE_UINT64_ARRAY(env
.msr_fixed_counters
, X86CPU
, MAX_FIXED_COUNTERS
),
558 VMSTATE_UINT64_ARRAY(env
.msr_gp_counters
, X86CPU
, MAX_GP_COUNTERS
),
559 VMSTATE_UINT64_ARRAY(env
.msr_gp_evtsel
, X86CPU
, MAX_GP_COUNTERS
),
560 VMSTATE_END_OF_LIST()
564 static bool mpx_needed(void *opaque
)
566 X86CPU
*cpu
= opaque
;
567 CPUX86State
*env
= &cpu
->env
;
570 for (i
= 0; i
< 4; i
++) {
571 if (env
->bnd_regs
[i
].lb
|| env
->bnd_regs
[i
].ub
) {
576 if (env
->bndcs_regs
.cfgu
|| env
->bndcs_regs
.sts
) {
580 return !!env
->msr_bndcfgs
;
583 static const VMStateDescription vmstate_mpx
= {
586 .minimum_version_id
= 1,
587 .fields
= (VMStateField
[]) {
588 VMSTATE_BND_REGS(env
.bnd_regs
, X86CPU
, 4),
589 VMSTATE_UINT64(env
.bndcs_regs
.cfgu
, X86CPU
),
590 VMSTATE_UINT64(env
.bndcs_regs
.sts
, X86CPU
),
591 VMSTATE_UINT64(env
.msr_bndcfgs
, X86CPU
),
592 VMSTATE_END_OF_LIST()
596 static bool hyperv_hypercall_enable_needed(void *opaque
)
598 X86CPU
*cpu
= opaque
;
599 CPUX86State
*env
= &cpu
->env
;
601 return env
->msr_hv_hypercall
!= 0 || env
->msr_hv_guest_os_id
!= 0;
604 static const VMStateDescription vmstate_msr_hypercall_hypercall
= {
605 .name
= "cpu/msr_hyperv_hypercall",
607 .minimum_version_id
= 1,
608 .fields
= (VMStateField
[]) {
609 VMSTATE_UINT64(env
.msr_hv_guest_os_id
, X86CPU
),
610 VMSTATE_UINT64(env
.msr_hv_hypercall
, X86CPU
),
611 VMSTATE_END_OF_LIST()
615 static bool hyperv_vapic_enable_needed(void *opaque
)
617 X86CPU
*cpu
= opaque
;
618 CPUX86State
*env
= &cpu
->env
;
620 return env
->msr_hv_vapic
!= 0;
623 static const VMStateDescription vmstate_msr_hyperv_vapic
= {
624 .name
= "cpu/msr_hyperv_vapic",
626 .minimum_version_id
= 1,
627 .fields
= (VMStateField
[]) {
628 VMSTATE_UINT64(env
.msr_hv_vapic
, X86CPU
),
629 VMSTATE_END_OF_LIST()
633 static bool hyperv_time_enable_needed(void *opaque
)
635 X86CPU
*cpu
= opaque
;
636 CPUX86State
*env
= &cpu
->env
;
638 return env
->msr_hv_tsc
!= 0;
641 static const VMStateDescription vmstate_msr_hyperv_time
= {
642 .name
= "cpu/msr_hyperv_time",
644 .minimum_version_id
= 1,
645 .fields
= (VMStateField
[]) {
646 VMSTATE_UINT64(env
.msr_hv_tsc
, X86CPU
),
647 VMSTATE_END_OF_LIST()
651 static bool avx512_needed(void *opaque
)
653 X86CPU
*cpu
= opaque
;
654 CPUX86State
*env
= &cpu
->env
;
657 for (i
= 0; i
< NB_OPMASK_REGS
; i
++) {
658 if (env
->opmask_regs
[i
]) {
663 for (i
= 0; i
< CPU_NB_REGS
; i
++) {
664 #define ENV_XMM(reg, field) (env->xmm_regs[reg].XMM_Q(field))
665 if (ENV_XMM(i
, 4) || ENV_XMM(i
, 6) ||
666 ENV_XMM(i
, 5) || ENV_XMM(i
, 7)) {
670 if (ENV_XMM(i
+16, 0) || ENV_XMM(i
+16, 1) ||
671 ENV_XMM(i
+16, 2) || ENV_XMM(i
+16, 3) ||
672 ENV_XMM(i
+16, 4) || ENV_XMM(i
+16, 5) ||
673 ENV_XMM(i
+16, 6) || ENV_XMM(i
+16, 7)) {
682 static const VMStateDescription vmstate_avx512
= {
683 .name
= "cpu/avx512",
685 .minimum_version_id
= 1,
686 .fields
= (VMStateField
[]) {
687 VMSTATE_UINT64_ARRAY(env
.opmask_regs
, X86CPU
, NB_OPMASK_REGS
),
688 VMSTATE_ZMMH_REGS_VARS(env
.xmm_regs
, X86CPU
, 0),
690 VMSTATE_Hi16_ZMM_REGS_VARS(env
.xmm_regs
, X86CPU
, 16),
692 VMSTATE_END_OF_LIST()
696 static bool xss_needed(void *opaque
)
698 X86CPU
*cpu
= opaque
;
699 CPUX86State
*env
= &cpu
->env
;
701 return env
->xss
!= 0;
704 static const VMStateDescription vmstate_xss
= {
707 .minimum_version_id
= 1,
708 .fields
= (VMStateField
[]) {
709 VMSTATE_UINT64(env
.xss
, X86CPU
),
710 VMSTATE_END_OF_LIST()
714 VMStateDescription vmstate_x86_cpu
= {
717 .minimum_version_id
= 3,
718 .pre_save
= cpu_pre_save
,
719 .post_load
= cpu_post_load
,
720 .fields
= (VMStateField
[]) {
721 VMSTATE_UINTTL_ARRAY(env
.regs
, X86CPU
, CPU_NB_REGS
),
722 VMSTATE_UINTTL(env
.eip
, X86CPU
),
723 VMSTATE_UINTTL(env
.eflags
, X86CPU
),
724 VMSTATE_UINT32(env
.hflags
, X86CPU
),
726 VMSTATE_UINT16(env
.fpuc
, X86CPU
),
727 VMSTATE_UINT16(env
.fpus_vmstate
, X86CPU
),
728 VMSTATE_UINT16(env
.fptag_vmstate
, X86CPU
),
729 VMSTATE_UINT16(env
.fpregs_format_vmstate
, X86CPU
),
730 VMSTATE_FP_REGS(env
.fpregs
, X86CPU
, 8),
732 VMSTATE_SEGMENT_ARRAY(env
.segs
, X86CPU
, 6),
733 VMSTATE_SEGMENT(env
.ldt
, X86CPU
),
734 VMSTATE_SEGMENT(env
.tr
, X86CPU
),
735 VMSTATE_SEGMENT(env
.gdt
, X86CPU
),
736 VMSTATE_SEGMENT(env
.idt
, X86CPU
),
738 VMSTATE_UINT32(env
.sysenter_cs
, X86CPU
),
740 /* Hack: In v7 size changed from 32 to 64 bits on x86_64 */
741 VMSTATE_HACK_UINT32(env
.sysenter_esp
, X86CPU
, less_than_7
),
742 VMSTATE_HACK_UINT32(env
.sysenter_eip
, X86CPU
, less_than_7
),
743 VMSTATE_UINTTL_V(env
.sysenter_esp
, X86CPU
, 7),
744 VMSTATE_UINTTL_V(env
.sysenter_eip
, X86CPU
, 7),
746 VMSTATE_UINTTL(env
.sysenter_esp
, X86CPU
),
747 VMSTATE_UINTTL(env
.sysenter_eip
, X86CPU
),
750 VMSTATE_UINTTL(env
.cr
[0], X86CPU
),
751 VMSTATE_UINTTL(env
.cr
[2], X86CPU
),
752 VMSTATE_UINTTL(env
.cr
[3], X86CPU
),
753 VMSTATE_UINTTL(env
.cr
[4], X86CPU
),
754 VMSTATE_UINTTL_ARRAY(env
.dr
, X86CPU
, 8),
756 VMSTATE_INT32(env
.a20_mask
, X86CPU
),
758 VMSTATE_UINT32(env
.mxcsr
, X86CPU
),
759 VMSTATE_XMM_REGS(env
.xmm_regs
, X86CPU
, 0),
762 VMSTATE_UINT64(env
.efer
, X86CPU
),
763 VMSTATE_UINT64(env
.star
, X86CPU
),
764 VMSTATE_UINT64(env
.lstar
, X86CPU
),
765 VMSTATE_UINT64(env
.cstar
, X86CPU
),
766 VMSTATE_UINT64(env
.fmask
, X86CPU
),
767 VMSTATE_UINT64(env
.kernelgsbase
, X86CPU
),
769 VMSTATE_UINT32_V(env
.smbase
, X86CPU
, 4),
771 VMSTATE_UINT64_V(env
.pat
, X86CPU
, 5),
772 VMSTATE_UINT32_V(env
.hflags2
, X86CPU
, 5),
774 VMSTATE_UINT32_TEST(parent_obj
.halted
, X86CPU
, version_is_5
),
775 VMSTATE_UINT64_V(env
.vm_hsave
, X86CPU
, 5),
776 VMSTATE_UINT64_V(env
.vm_vmcb
, X86CPU
, 5),
777 VMSTATE_UINT64_V(env
.tsc_offset
, X86CPU
, 5),
778 VMSTATE_UINT64_V(env
.intercept
, X86CPU
, 5),
779 VMSTATE_UINT16_V(env
.intercept_cr_read
, X86CPU
, 5),
780 VMSTATE_UINT16_V(env
.intercept_cr_write
, X86CPU
, 5),
781 VMSTATE_UINT16_V(env
.intercept_dr_read
, X86CPU
, 5),
782 VMSTATE_UINT16_V(env
.intercept_dr_write
, X86CPU
, 5),
783 VMSTATE_UINT32_V(env
.intercept_exceptions
, X86CPU
, 5),
784 VMSTATE_UINT8_V(env
.v_tpr
, X86CPU
, 5),
786 VMSTATE_UINT64_ARRAY_V(env
.mtrr_fixed
, X86CPU
, 11, 8),
787 VMSTATE_UINT64_V(env
.mtrr_deftype
, X86CPU
, 8),
788 VMSTATE_MTRR_VARS(env
.mtrr_var
, X86CPU
, MSR_MTRRcap_VCNT
, 8),
789 /* KVM-related states */
790 VMSTATE_INT32_V(env
.interrupt_injected
, X86CPU
, 9),
791 VMSTATE_UINT32_V(env
.mp_state
, X86CPU
, 9),
792 VMSTATE_UINT64_V(env
.tsc
, X86CPU
, 9),
793 VMSTATE_INT32_V(env
.exception_injected
, X86CPU
, 11),
794 VMSTATE_UINT8_V(env
.soft_interrupt
, X86CPU
, 11),
795 VMSTATE_UINT8_V(env
.nmi_injected
, X86CPU
, 11),
796 VMSTATE_UINT8_V(env
.nmi_pending
, X86CPU
, 11),
797 VMSTATE_UINT8_V(env
.has_error_code
, X86CPU
, 11),
798 VMSTATE_UINT32_V(env
.sipi_vector
, X86CPU
, 11),
800 VMSTATE_UINT64_V(env
.mcg_cap
, X86CPU
, 10),
801 VMSTATE_UINT64_V(env
.mcg_status
, X86CPU
, 10),
802 VMSTATE_UINT64_V(env
.mcg_ctl
, X86CPU
, 10),
803 VMSTATE_UINT64_ARRAY_V(env
.mce_banks
, X86CPU
, MCE_BANKS_DEF
* 4, 10),
805 VMSTATE_UINT64_V(env
.tsc_aux
, X86CPU
, 11),
806 /* KVM pvclock msr */
807 VMSTATE_UINT64_V(env
.system_time_msr
, X86CPU
, 11),
808 VMSTATE_UINT64_V(env
.wall_clock_msr
, X86CPU
, 11),
809 /* XSAVE related fields */
810 VMSTATE_UINT64_V(env
.xcr0
, X86CPU
, 12),
811 VMSTATE_UINT64_V(env
.xstate_bv
, X86CPU
, 12),
812 VMSTATE_YMMH_REGS_VARS(env
.xmm_regs
, X86CPU
, 0, 12),
813 VMSTATE_END_OF_LIST()
814 /* The above list is not sorted /wrt version numbers, watch out! */
816 .subsections
= (VMStateSubsection
[]) {
818 .vmsd
= &vmstate_async_pf_msr
,
819 .needed
= async_pf_msr_needed
,
821 .vmsd
= &vmstate_pv_eoi_msr
,
822 .needed
= pv_eoi_msr_needed
,
824 .vmsd
= &vmstate_steal_time_msr
,
825 .needed
= steal_time_msr_needed
,
827 .vmsd
= &vmstate_fpop_ip_dp
,
828 .needed
= fpop_ip_dp_needed
,
830 .vmsd
= &vmstate_msr_tsc_adjust
,
831 .needed
= tsc_adjust_needed
,
833 .vmsd
= &vmstate_msr_tscdeadline
,
834 .needed
= tscdeadline_needed
,
836 .vmsd
= &vmstate_msr_ia32_misc_enable
,
837 .needed
= misc_enable_needed
,
839 .vmsd
= &vmstate_msr_ia32_feature_control
,
840 .needed
= feature_control_needed
,
842 .vmsd
= &vmstate_msr_architectural_pmu
,
843 .needed
= pmu_enable_needed
,
845 .vmsd
= &vmstate_mpx
,
846 .needed
= mpx_needed
,
848 .vmsd
= &vmstate_msr_hypercall_hypercall
,
849 .needed
= hyperv_hypercall_enable_needed
,
851 .vmsd
= &vmstate_msr_hyperv_vapic
,
852 .needed
= hyperv_vapic_enable_needed
,
854 .vmsd
= &vmstate_msr_hyperv_time
,
855 .needed
= hyperv_time_enable_needed
,
857 .vmsd
= &vmstate_avx512
,
858 .needed
= avx512_needed
,
860 .vmsd
= &vmstate_xss
,
861 .needed
= xss_needed
,