target-i386/kvm.c

   1 /*
   2  * QEMU KVM support
   3  *
   4  * Copyright (C) 2006-2008 Qumranet Technologies
   5  * Copyright IBM, Corp. 2008
   6  *
   7  * Authors:
   8  *  Anthony Liguori   <aliguori@us.ibm.com>
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  11  * See the COPYING file in the top-level directory.
  12  *
  13  */
  14
  15 #include <sys/types.h>
  16 #include <sys/ioctl.h>
  17 #include <sys/mman.h>
  18
  19 #include <linux/kvm.h>
  20
  21 #include "qemu-common.h"
  22 #include "sysemu.h"
  23 #include "kvm.h"
  24 #include "cpu.h"
  25 #include "gdbstub.h"
  26 #include "host-utils.h"
  27
  28 //#define DEBUG_KVM
  29
  30 #ifdef DEBUG_KVM
  31 #define dprintf(fmt, ...) \
  32     do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
  33 #else
  34 #define dprintf(fmt, ...) \
  35     do { } while (0)
  36 #endif
  37
  38 #define MSR_KVM_WALL_CLOCK  0x11
  39 #define MSR_KVM_SYSTEM_TIME 0x12
  40
  41 #ifdef KVM_CAP_EXT_CPUID
  42
  43 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
  44 {
  45     struct kvm_cpuid2 *cpuid;
  46     int r, size;
  47
  48     size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
  49     cpuid = (struct kvm_cpuid2 *)qemu_mallocz(size);
  50     cpuid->nent = max;
  51     r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
  52     if (r == 0 && cpuid->nent >= max) {
  53         r = -E2BIG;
  54     }
  55     if (r < 0) {
  56         if (r == -E2BIG) {
  57             qemu_free(cpuid);
  58             return NULL;
  59         } else {
  60             fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
  61                     strerror(-r));
  62             exit(1);
  63         }
  64     }
  65     return cpuid;
  66 }
  67
  68 uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function, int reg)
  69 {
  70     struct kvm_cpuid2 *cpuid;
  71     int i, max;
  72     uint32_t ret = 0;
  73     uint32_t cpuid_1_edx;
  74
  75     if (!kvm_check_extension(env->kvm_state, KVM_CAP_EXT_CPUID)) {
  76         return -1U;
  77     }
  78
  79     max = 1;
  80     while ((cpuid = try_get_cpuid(env->kvm_state, max)) == NULL) {
  81         max *= 2;
  82     }
  83
  84     for (i = 0; i < cpuid->nent; ++i) {
  85         if (cpuid->entries[i].function == function) {
  86             switch (reg) {
  87             case R_EAX:
  88                 ret = cpuid->entries[i].eax;
  89                 break;
  90             case R_EBX:
  91                 ret = cpuid->entries[i].ebx;
  92                 break;
  93             case R_ECX:
  94                 ret = cpuid->entries[i].ecx;
  95                 break;
  96             case R_EDX:
  97                 ret = cpuid->entries[i].edx;
  98                 if (function == 0x80000001) {
  99                     /* On Intel, kvm returns cpuid according to the Intel spec,
 100                      * so add missing bits according to the AMD spec:
 101                      */
 102                     cpuid_1_edx = kvm_arch_get_supported_cpuid(env, 1, R_EDX);
 103                     ret |= cpuid_1_edx & 0xdfeff7ff;
 104                 }
 105                 break;
 106             }
 107         }
 108     }
 109
 110     qemu_free(cpuid);
 111
 112     return ret;
 113 }
 114
 115 #else
 116
 117 uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function, int reg)
 118 {
 119     return -1U;
 120 }
 121
 122 #endif
 123
 124 static void kvm_trim_features(uint32_t *features, uint32_t supported)
 125 {
 126     int i;
 127     uint32_t mask;
 128
 129     for (i = 0; i < 32; ++i) {
 130         mask = 1U << i;
 131         if ((*features & mask) && !(supported & mask)) {
 132             *features &= ~mask;
 133         }
 134     }
 135 }
 136
 137 int kvm_arch_init_vcpu(CPUState *env)
 138 {
 139     struct {
 140         struct kvm_cpuid2 cpuid;
 141         struct kvm_cpuid_entry2 entries[100];
 142     } __attribute__((packed)) cpuid_data;
 143     uint32_t limit, i, j, cpuid_i;
 144     uint32_t unused;
 145
 146     env->mp_state = KVM_MP_STATE_RUNNABLE;
 147
 148     kvm_trim_features(&env->cpuid_features,
 149         kvm_arch_get_supported_cpuid(env, 1, R_EDX));
 150
 151     i = env->cpuid_ext_features & CPUID_EXT_HYPERVISOR;
 152     kvm_trim_features(&env->cpuid_ext_features,
 153         kvm_arch_get_supported_cpuid(env, 1, R_ECX));
 154     env->cpuid_ext_features |= i;
 155
 156     kvm_trim_features(&env->cpuid_ext2_features,
 157         kvm_arch_get_supported_cpuid(env, 0x80000001, R_EDX));
 158     kvm_trim_features(&env->cpuid_ext3_features,
 159         kvm_arch_get_supported_cpuid(env, 0x80000001, R_ECX));
 160
 161     cpuid_i = 0;
 162
 163     cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
 164
 165     for (i = 0; i <= limit; i++) {
 166         struct kvm_cpuid_entry2 *c = &cpuid_data.entries[cpuid_i++];
 167
 168         switch (i) {
 169         case 2: {
 170             /* Keep reading function 2 till all the input is received */
 171             int times;
 172
 173             c->function = i;
 174             c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
 175                        KVM_CPUID_FLAG_STATE_READ_NEXT;
 176             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 177             times = c->eax & 0xff;
 178
 179             for (j = 1; j < times; ++j) {
 180                 c = &cpuid_data.entries[cpuid_i++];
 181                 c->function = i;
 182                 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
 183                 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 184             }
 185             break;
 186         }
 187         case 4:
 188         case 0xb:
 189         case 0xd:
 190             for (j = 0; ; j++) {
 191                 c->function = i;
 192                 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
 193                 c->index = j;
 194                 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
 195
 196                 if (i == 4 && c->eax == 0)
 197                     break;
 198                 if (i == 0xb && !(c->ecx & 0xff00))
 199                     break;
 200                 if (i == 0xd && c->eax == 0)
 201                     break;
 202
 203                 c = &cpuid_data.entries[cpuid_i++];
 204             }
 205             break;
 206         default:
 207             c->function = i;
 208             c->flags = 0;
 209             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 210             break;
 211         }
 212     }
 213     cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
 214
 215     for (i = 0x80000000; i <= limit; i++) {
 216         struct kvm_cpuid_entry2 *c = &cpuid_data.entries[cpuid_i++];
 217
 218         c->function = i;
 219         c->flags = 0;
 220         cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 221     }
 222
 223     cpuid_data.cpuid.nent = cpuid_i;
 224
 225     return kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data);
 226 }
 227
 228 void kvm_arch_reset_vcpu(CPUState *env)
 229 {
 230     env->interrupt_injected = -1;
 231     env->nmi_injected = 0;
 232     env->nmi_pending = 0;
 233 }
 234
 235 static int kvm_has_msr_star(CPUState *env)
 236 {
 237     static int has_msr_star;
 238     int ret;
 239
 240     /* first time */
 241     if (has_msr_star == 0) {
 242         struct kvm_msr_list msr_list, *kvm_msr_list;
 243
 244         has_msr_star = -1;
 245
 246         /* Obtain MSR list from KVM.  These are the MSRs that we must
 247          * save/restore */
 248         msr_list.nmsrs = 0;
 249         ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, &msr_list);
 250         if (ret < 0 && ret != -E2BIG) {
 251             return 0;
 252         }
 253         /* Old kernel modules had a bug and could write beyond the provided
 254            memory. Allocate at least a safe amount of 1K. */
 255         kvm_msr_list = qemu_mallocz(MAX(1024, sizeof(msr_list) +
 256                                               msr_list.nmsrs *
 257                                               sizeof(msr_list.indices[0])));
 258
 259         kvm_msr_list->nmsrs = msr_list.nmsrs;
 260         ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
 261         if (ret >= 0) {
 262             int i;
 263
 264             for (i = 0; i < kvm_msr_list->nmsrs; i++) {
 265                 if (kvm_msr_list->indices[i] == MSR_STAR) {
 266                     has_msr_star = 1;
 267                     break;
 268                 }
 269             }
 270         }
 271
 272         free(kvm_msr_list);
 273     }
 274
 275     if (has_msr_star == 1)
 276         return 1;
 277     return 0;
 278 }
 279
 280 int kvm_arch_init(KVMState *s, int smp_cpus)
 281 {
 282     int ret;
 283
 284     /* create vm86 tss.  KVM uses vm86 mode to emulate 16-bit code
 285      * directly.  In order to use vm86 mode, a TSS is needed.  Since this
 286      * must be part of guest physical memory, we need to allocate it.  Older
 287      * versions of KVM just assumed that it would be at the end of physical
 288      * memory but that doesn't work with more than 4GB of memory.  We simply
 289      * refuse to work with those older versions of KVM. */
 290     ret = kvm_ioctl(s, KVM_CHECK_EXTENSION, KVM_CAP_SET_TSS_ADDR);
 291     if (ret <= 0) {
 292         fprintf(stderr, "kvm does not support KVM_CAP_SET_TSS_ADDR\n");
 293         return ret;
 294     }
 295
 296     /* this address is 3 pages before the bios, and the bios should present
 297      * as unavaible memory.  FIXME, need to ensure the e820 map deals with
 298      * this?
 299      */
 300     return kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, 0xfffbd000);
 301 }
 302
 303 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 304 {
 305     lhs->selector = rhs->selector;
 306     lhs->base = rhs->base;
 307     lhs->limit = rhs->limit;
 308     lhs->type = 3;
 309     lhs->present = 1;
 310     lhs->dpl = 3;
 311     lhs->db = 0;
 312     lhs->s = 1;
 313     lhs->l = 0;
 314     lhs->g = 0;
 315     lhs->avl = 0;
 316     lhs->unusable = 0;
 317 }
 318
 319 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 320 {
 321     unsigned flags = rhs->flags;
 322     lhs->selector = rhs->selector;
 323     lhs->base = rhs->base;
 324     lhs->limit = rhs->limit;
 325     lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
 326     lhs->present = (flags & DESC_P_MASK) != 0;
 327     lhs->dpl = rhs->selector & 3;
 328     lhs->db = (flags >> DESC_B_SHIFT) & 1;
 329     lhs->s = (flags & DESC_S_MASK) != 0;
 330     lhs->l = (flags >> DESC_L_SHIFT) & 1;
 331     lhs->g = (flags & DESC_G_MASK) != 0;
 332     lhs->avl = (flags & DESC_AVL_MASK) != 0;
 333     lhs->unusable = 0;
 334 }
 335
 336 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
 337 {
 338     lhs->selector = rhs->selector;
 339     lhs->base = rhs->base;
 340     lhs->limit = rhs->limit;
 341     lhs->flags =
 342         (rhs->type << DESC_TYPE_SHIFT)
 343         | (rhs->present * DESC_P_MASK)
 344         | (rhs->dpl << DESC_DPL_SHIFT)
 345         | (rhs->db << DESC_B_SHIFT)
 346         | (rhs->s * DESC_S_MASK)
 347         | (rhs->l << DESC_L_SHIFT)
 348         | (rhs->g * DESC_G_MASK)
 349         | (rhs->avl * DESC_AVL_MASK);
 350 }
 351
 352 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
 353 {
 354     if (set)
 355         *kvm_reg = *qemu_reg;
 356     else
 357         *qemu_reg = *kvm_reg;
 358 }
 359
 360 static int kvm_getput_regs(CPUState *env, int set)
 361 {
 362     struct kvm_regs regs;
 363     int ret = 0;
 364
 365     if (!set) {
 366         ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
 367         if (ret < 0)
 368             return ret;
 369     }
 370
 371     kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
 372     kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
 373     kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
 374     kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
 375     kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
 376     kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
 377     kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
 378     kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
 379 #ifdef TARGET_X86_64
 380     kvm_getput_reg(&regs.r8, &env->regs[8], set);
 381     kvm_getput_reg(&regs.r9, &env->regs[9], set);
 382     kvm_getput_reg(&regs.r10, &env->regs[10], set);
 383     kvm_getput_reg(&regs.r11, &env->regs[11], set);
 384     kvm_getput_reg(&regs.r12, &env->regs[12], set);
 385     kvm_getput_reg(&regs.r13, &env->regs[13], set);
 386     kvm_getput_reg(&regs.r14, &env->regs[14], set);
 387     kvm_getput_reg(&regs.r15, &env->regs[15], set);
 388 #endif
 389
 390     kvm_getput_reg(&regs.rflags, &env->eflags, set);
 391     kvm_getput_reg(&regs.rip, &env->eip, set);
 392
 393     if (set)
 394         ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);
 395
 396     return ret;
 397 }
 398
 399 static int kvm_put_fpu(CPUState *env)
 400 {
 401     struct kvm_fpu fpu;
 402     int i;
 403
 404     memset(&fpu, 0, sizeof fpu);
 405     fpu.fsw = env->fpus & ~(7 << 11);
 406     fpu.fsw |= (env->fpstt & 7) << 11;
 407     fpu.fcw = env->fpuc;
 408     for (i = 0; i < 8; ++i)
 409         fpu.ftwx |= (!env->fptags[i]) << i;
 410     memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
 411     memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
 412     fpu.mxcsr = env->mxcsr;
 413
 414     return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu);
 415 }
 416
 417 static int kvm_put_sregs(CPUState *env)
 418 {
 419     struct kvm_sregs sregs;
 420
 421     memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
 422     if (env->interrupt_injected >= 0) {
 423         sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
 424                 (uint64_t)1 << (env->interrupt_injected % 64);
 425     }
 426
 427     if ((env->eflags & VM_MASK)) {
 428             set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
 429             set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
 430             set_v8086_seg(&sregs.es, &env->segs[R_ES]);
 431             set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
 432             set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
 433             set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
 434     } else {
 435             set_seg(&sregs.cs, &env->segs[R_CS]);
 436             set_seg(&sregs.ds, &env->segs[R_DS]);
 437             set_seg(&sregs.es, &env->segs[R_ES]);
 438             set_seg(&sregs.fs, &env->segs[R_FS]);
 439             set_seg(&sregs.gs, &env->segs[R_GS]);
 440             set_seg(&sregs.ss, &env->segs[R_SS]);
 441
 442             if (env->cr[0] & CR0_PE_MASK) {
 443                 /* force ss cpl to cs cpl */
 444                 sregs.ss.selector = (sregs.ss.selector & ~3) |
 445                         (sregs.cs.selector & 3);
 446                 sregs.ss.dpl = sregs.ss.selector & 3;
 447             }
 448     }
 449
 450     set_seg(&sregs.tr, &env->tr);
 451     set_seg(&sregs.ldt, &env->ldt);
 452
 453     sregs.idt.limit = env->idt.limit;
 454     sregs.idt.base = env->idt.base;
 455     sregs.gdt.limit = env->gdt.limit;
 456     sregs.gdt.base = env->gdt.base;
 457
 458     sregs.cr0 = env->cr[0];
 459     sregs.cr2 = env->cr[2];
 460     sregs.cr3 = env->cr[3];
 461     sregs.cr4 = env->cr[4];
 462
 463     sregs.cr8 = cpu_get_apic_tpr(env);
 464     sregs.apic_base = cpu_get_apic_base(env);
 465
 466     sregs.efer = env->efer;
 467
 468     return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
 469 }
 470
 471 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
 472                               uint32_t index, uint64_t value)
 473 {
 474     entry->index = index;
 475     entry->data = value;
 476 }
 477
 478 static int kvm_put_msrs(CPUState *env)
 479 {
 480     struct {
 481         struct kvm_msrs info;
 482         struct kvm_msr_entry entries[100];
 483     } msr_data;
 484     struct kvm_msr_entry *msrs = msr_data.entries;
 485     int n = 0;
 486
 487     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
 488     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
 489     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
 490     if (kvm_has_msr_star(env))
 491         kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
 492     kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
 493 #ifdef TARGET_X86_64
 494     /* FIXME if lm capable */
 495     kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
 496     kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
 497     kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
 498     kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
 499 #endif
 500     kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,  env->system_time_msr);
 501     kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK,  env->wall_clock_msr);
 502
 503     msr_data.info.nmsrs = n;
 504
 505     return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
 506
 507 }
 508
 509
 510 static int kvm_get_fpu(CPUState *env)
 511 {
 512     struct kvm_fpu fpu;
 513     int i, ret;
 514
 515     ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu);
 516     if (ret < 0)
 517         return ret;
 518
 519     env->fpstt = (fpu.fsw >> 11) & 7;
 520     env->fpus = fpu.fsw;
 521     env->fpuc = fpu.fcw;
 522     for (i = 0; i < 8; ++i)
 523         env->fptags[i] = !((fpu.ftwx >> i) & 1);
 524     memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
 525     memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
 526     env->mxcsr = fpu.mxcsr;
 527
 528     return 0;
 529 }
 530
 531 static int kvm_get_sregs(CPUState *env)
 532 {
 533     struct kvm_sregs sregs;
 534     uint32_t hflags;
 535     int bit, i, ret;
 536
 537     ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
 538     if (ret < 0)
 539         return ret;
 540
 541     /* There can only be one pending IRQ set in the bitmap at a time, so try
 542        to find it and save its number instead (-1 for none). */
 543     env->interrupt_injected = -1;
 544     for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
 545         if (sregs.interrupt_bitmap[i]) {
 546             bit = ctz64(sregs.interrupt_bitmap[i]);
 547             env->interrupt_injected = i * 64 + bit;
 548             break;
 549         }
 550     }
 551
 552     get_seg(&env->segs[R_CS], &sregs.cs);
 553     get_seg(&env->segs[R_DS], &sregs.ds);
 554     get_seg(&env->segs[R_ES], &sregs.es);
 555     get_seg(&env->segs[R_FS], &sregs.fs);
 556     get_seg(&env->segs[R_GS], &sregs.gs);
 557     get_seg(&env->segs[R_SS], &sregs.ss);
 558
 559     get_seg(&env->tr, &sregs.tr);
 560     get_seg(&env->ldt, &sregs.ldt);
 561
 562     env->idt.limit = sregs.idt.limit;
 563     env->idt.base = sregs.idt.base;
 564     env->gdt.limit = sregs.gdt.limit;
 565     env->gdt.base = sregs.gdt.base;
 566
 567     env->cr[0] = sregs.cr0;
 568     env->cr[2] = sregs.cr2;
 569     env->cr[3] = sregs.cr3;
 570     env->cr[4] = sregs.cr4;
 571
 572     cpu_set_apic_base(env, sregs.apic_base);
 573
 574     env->efer = sregs.efer;
 575     //cpu_set_apic_tpr(env, sregs.cr8);
 576
 577 #define HFLAG_COPY_MASK ~( \
 578                         HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
 579                         HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
 580                         HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
 581                         HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
 582
 583
 584
 585     hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
 586     hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
 587     hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
 588             (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
 589     hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
 590     hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
 591             (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
 592
 593     if (env->efer & MSR_EFER_LMA) {
 594         hflags |= HF_LMA_MASK;
 595     }
 596
 597     if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
 598         hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
 599     } else {
 600         hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
 601                 (DESC_B_SHIFT - HF_CS32_SHIFT);
 602         hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
 603                 (DESC_B_SHIFT - HF_SS32_SHIFT);
 604         if (!(env->cr[0] & CR0_PE_MASK) ||
 605                    (env->eflags & VM_MASK) ||
 606                    !(hflags & HF_CS32_MASK)) {
 607                 hflags |= HF_ADDSEG_MASK;
 608             } else {
 609                 hflags |= ((env->segs[R_DS].base |
 610                                 env->segs[R_ES].base |
 611                                 env->segs[R_SS].base) != 0) <<
 612                     HF_ADDSEG_SHIFT;
 613             }
 614     }
 615     env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
 616
 617     return 0;
 618 }
 619
 620 static int kvm_get_msrs(CPUState *env)
 621 {
 622     struct {
 623         struct kvm_msrs info;
 624         struct kvm_msr_entry entries[100];
 625     } msr_data;
 626     struct kvm_msr_entry *msrs = msr_data.entries;
 627     int ret, i, n;
 628
 629     n = 0;
 630     msrs[n++].index = MSR_IA32_SYSENTER_CS;
 631     msrs[n++].index = MSR_IA32_SYSENTER_ESP;
 632     msrs[n++].index = MSR_IA32_SYSENTER_EIP;
 633     if (kvm_has_msr_star(env))
 634         msrs[n++].index = MSR_STAR;
 635     msrs[n++].index = MSR_IA32_TSC;
 636 #ifdef TARGET_X86_64
 637     /* FIXME lm_capable_kernel */
 638     msrs[n++].index = MSR_CSTAR;
 639     msrs[n++].index = MSR_KERNELGSBASE;
 640     msrs[n++].index = MSR_FMASK;
 641     msrs[n++].index = MSR_LSTAR;
 642 #endif
 643     msrs[n++].index = MSR_KVM_SYSTEM_TIME;
 644     msrs[n++].index = MSR_KVM_WALL_CLOCK;
 645
 646     msr_data.info.nmsrs = n;
 647     ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);
 648     if (ret < 0)
 649         return ret;
 650
 651     for (i = 0; i < ret; i++) {
 652         switch (msrs[i].index) {
 653         case MSR_IA32_SYSENTER_CS:
 654             env->sysenter_cs = msrs[i].data;
 655             break;
 656         case MSR_IA32_SYSENTER_ESP:
 657             env->sysenter_esp = msrs[i].data;
 658             break;
 659         case MSR_IA32_SYSENTER_EIP:
 660             env->sysenter_eip = msrs[i].data;
 661             break;
 662         case MSR_STAR:
 663             env->star = msrs[i].data;
 664             break;
 665 #ifdef TARGET_X86_64
 666         case MSR_CSTAR:
 667             env->cstar = msrs[i].data;
 668             break;
 669         case MSR_KERNELGSBASE:
 670             env->kernelgsbase = msrs[i].data;
 671             break;
 672         case MSR_FMASK:
 673             env->fmask = msrs[i].data;
 674             break;
 675         case MSR_LSTAR:
 676             env->lstar = msrs[i].data;
 677             break;
 678 #endif
 679         case MSR_IA32_TSC:
 680             env->tsc = msrs[i].data;
 681             break;
 682         case MSR_KVM_SYSTEM_TIME:
 683             env->system_time_msr = msrs[i].data;
 684             break;
 685         case MSR_KVM_WALL_CLOCK:
 686             env->wall_clock_msr = msrs[i].data;
 687             break;
 688         }
 689     }
 690
 691     return 0;
 692 }
 693
 694 static int kvm_put_mp_state(CPUState *env)
 695 {
 696     struct kvm_mp_state mp_state = { .mp_state = env->mp_state };
 697
 698     return kvm_vcpu_ioctl(env, KVM_SET_MP_STATE, &mp_state);
 699 }
 700
 701 static int kvm_get_mp_state(CPUState *env)
 702 {
 703     struct kvm_mp_state mp_state;
 704     int ret;
 705
 706     ret = kvm_vcpu_ioctl(env, KVM_GET_MP_STATE, &mp_state);
 707     if (ret < 0) {
 708         return ret;
 709     }
 710     env->mp_state = mp_state.mp_state;
 711     return 0;
 712 }
 713
 714 static int kvm_put_vcpu_events(CPUState *env)
 715 {
 716 #ifdef KVM_CAP_VCPU_EVENTS
 717     struct kvm_vcpu_events events;
 718
 719     if (!kvm_has_vcpu_events()) {
 720         return 0;
 721     }
 722
 723     events.exception.injected = (env->exception_injected >= 0);
 724     events.exception.nr = env->exception_injected;
 725     events.exception.has_error_code = env->has_error_code;
 726     events.exception.error_code = env->error_code;
 727
 728     events.interrupt.injected = (env->interrupt_injected >= 0);
 729     events.interrupt.nr = env->interrupt_injected;
 730     events.interrupt.soft = env->soft_interrupt;
 731
 732     events.nmi.injected = env->nmi_injected;
 733     events.nmi.pending = env->nmi_pending;
 734     events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
 735
 736     events.sipi_vector = env->sipi_vector;
 737
 738     return kvm_vcpu_ioctl(env, KVM_SET_VCPU_EVENTS, &events);
 739 #else
 740     return 0;
 741 #endif
 742 }
 743
 744 static int kvm_get_vcpu_events(CPUState *env)
 745 {
 746 #ifdef KVM_CAP_VCPU_EVENTS
 747     struct kvm_vcpu_events events;
 748     int ret;
 749
 750     if (!kvm_has_vcpu_events()) {
 751         return 0;
 752     }
 753
 754     ret = kvm_vcpu_ioctl(env, KVM_GET_VCPU_EVENTS, &events);
 755     if (ret < 0) {
 756        return ret;
 757     }
 758     env->exception_injected =
 759        events.exception.injected ? events.exception.nr : -1;
 760     env->has_error_code = events.exception.has_error_code;
 761     env->error_code = events.exception.error_code;
 762
 763     env->interrupt_injected =
 764         events.interrupt.injected ? events.interrupt.nr : -1;
 765     env->soft_interrupt = events.interrupt.soft;
 766
 767     env->nmi_injected = events.nmi.injected;
 768     env->nmi_pending = events.nmi.pending;
 769     if (events.nmi.masked) {
 770         env->hflags2 |= HF2_NMI_MASK;
 771     } else {
 772         env->hflags2 &= ~HF2_NMI_MASK;
 773     }
 774
 775     env->sipi_vector = events.sipi_vector;
 776 #endif
 777
 778     return 0;
 779 }
 780
 781 int kvm_arch_put_registers(CPUState *env)
 782 {
 783     int ret;
 784
 785     ret = kvm_getput_regs(env, 1);
 786     if (ret < 0)
 787         return ret;
 788
 789     ret = kvm_put_fpu(env);
 790     if (ret < 0)
 791         return ret;
 792
 793     ret = kvm_put_sregs(env);
 794     if (ret < 0)
 795         return ret;
 796
 797     ret = kvm_put_msrs(env);
 798     if (ret < 0)
 799         return ret;
 800
 801     ret = kvm_put_mp_state(env);
 802     if (ret < 0)
 803         return ret;
 804
 805     ret = kvm_put_vcpu_events(env);
 806     if (ret < 0)
 807         return ret;
 808
 809     return 0;
 810 }
 811
 812 int kvm_arch_get_registers(CPUState *env)
 813 {
 814     int ret;
 815
 816     ret = kvm_getput_regs(env, 0);
 817     if (ret < 0)
 818         return ret;
 819
 820     ret = kvm_get_fpu(env);
 821     if (ret < 0)
 822         return ret;
 823
 824     ret = kvm_get_sregs(env);
 825     if (ret < 0)
 826         return ret;
 827
 828     ret = kvm_get_msrs(env);
 829     if (ret < 0)
 830         return ret;
 831
 832     ret = kvm_get_mp_state(env);
 833     if (ret < 0)
 834         return ret;
 835
 836     ret = kvm_get_vcpu_events(env);
 837     if (ret < 0)
 838         return ret;
 839
 840     return 0;
 841 }
 842
 843 int kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
 844 {
 845     /* Try to inject an interrupt if the guest can accept it */
 846     if (run->ready_for_interrupt_injection &&
 847         (env->interrupt_request & CPU_INTERRUPT_HARD) &&
 848         (env->eflags & IF_MASK)) {
 849         int irq;
 850
 851         env->interrupt_request &= ~CPU_INTERRUPT_HARD;
 852         irq = cpu_get_pic_interrupt(env);
 853         if (irq >= 0) {
 854             struct kvm_interrupt intr;
 855             intr.irq = irq;
 856             /* FIXME: errors */
 857             dprintf("injected interrupt %d\n", irq);
 858             kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr);
 859         }
 860     }
 861
 862     /* If we have an interrupt but the guest is not ready to receive an
 863      * interrupt, request an interrupt window exit.  This will
 864      * cause a return to userspace as soon as the guest is ready to
 865      * receive interrupts. */
 866     if ((env->interrupt_request & CPU_INTERRUPT_HARD))
 867         run->request_interrupt_window = 1;
 868     else
 869         run->request_interrupt_window = 0;
 870
 871     dprintf("setting tpr\n");
 872     run->cr8 = cpu_get_apic_tpr(env);
 873
 874     return 0;
 875 }
 876
 877 int kvm_arch_post_run(CPUState *env, struct kvm_run *run)
 878 {
 879     if (run->if_flag)
 880         env->eflags |= IF_MASK;
 881     else
 882         env->eflags &= ~IF_MASK;
 883
 884     cpu_set_apic_tpr(env, run->cr8);
 885     cpu_set_apic_base(env, run->apic_base);
 886
 887     return 0;
 888 }
 889
 890 static int kvm_handle_halt(CPUState *env)
 891 {
 892     if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
 893           (env->eflags & IF_MASK)) &&
 894         !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
 895         env->halted = 1;
 896         env->exception_index = EXCP_HLT;
 897         return 0;
 898     }
 899
 900     return 1;
 901 }
 902
 903 int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run)
 904 {
 905     int ret = 0;
 906
 907     switch (run->exit_reason) {
 908     case KVM_EXIT_HLT:
 909         dprintf("handle_hlt\n");
 910         ret = kvm_handle_halt(env);
 911         break;
 912     }
 913
 914     return ret;
 915 }
 916
 917 #ifdef KVM_CAP_SET_GUEST_DEBUG
 918 int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
 919 {
 920     static const uint8_t int3 = 0xcc;
 921
 922     if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
 923         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1))
 924         return -EINVAL;
 925     return 0;
 926 }
 927
 928 int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
 929 {
 930     uint8_t int3;
 931
 932     if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
 933         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1))
 934         return -EINVAL;
 935     return 0;
 936 }
 937
 938 static struct {
 939     target_ulong addr;
 940     int len;
 941     int type;
 942 } hw_breakpoint[4];
 943
 944 static int nb_hw_breakpoint;
 945
 946 static int find_hw_breakpoint(target_ulong addr, int len, int type)
 947 {
 948     int n;
 949
 950     for (n = 0; n < nb_hw_breakpoint; n++)
 951         if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
 952             (hw_breakpoint[n].len == len || len == -1))
 953             return n;
 954     return -1;
 955 }
 956
 957 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
 958                                   target_ulong len, int type)
 959 {
 960     switch (type) {
 961     case GDB_BREAKPOINT_HW:
 962         len = 1;
 963         break;
 964     case GDB_WATCHPOINT_WRITE:
 965     case GDB_WATCHPOINT_ACCESS:
 966         switch (len) {
 967         case 1:
 968             break;
 969         case 2:
 970         case 4:
 971         case 8:
 972             if (addr & (len - 1))
 973                 return -EINVAL;
 974             break;
 975         default:
 976             return -EINVAL;
 977         }
 978         break;
 979     default:
 980         return -ENOSYS;
 981     }
 982
 983     if (nb_hw_breakpoint == 4)
 984         return -ENOBUFS;
 985
 986     if (find_hw_breakpoint(addr, len, type) >= 0)
 987         return -EEXIST;
 988
 989     hw_breakpoint[nb_hw_breakpoint].addr = addr;
 990     hw_breakpoint[nb_hw_breakpoint].len = len;
 991     hw_breakpoint[nb_hw_breakpoint].type = type;
 992     nb_hw_breakpoint++;
 993
 994     return 0;
 995 }
 996
 997 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
 998                                   target_ulong len, int type)
 999 {
1000     int n;
1001
1002     n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
1003     if (n < 0)
1004         return -ENOENT;
1005
1006     nb_hw_breakpoint--;
1007     hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
1008
1009     return 0;
1010 }
1011
1012 void kvm_arch_remove_all_hw_breakpoints(void)
1013 {
1014     nb_hw_breakpoint = 0;
1015 }
1016
1017 static CPUWatchpoint hw_watchpoint;
1018
1019 int kvm_arch_debug(struct kvm_debug_exit_arch *arch_info)
1020 {
1021     int handle = 0;
1022     int n;
1023
1024     if (arch_info->exception == 1) {
1025         if (arch_info->dr6 & (1 << 14)) {
1026             if (cpu_single_env->singlestep_enabled)
1027                 handle = 1;
1028         } else {
1029             for (n = 0; n < 4; n++)
1030                 if (arch_info->dr6 & (1 << n))
1031                     switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
1032                     case 0x0:
1033                         handle = 1;
1034                         break;
1035                     case 0x1:
1036                         handle = 1;
1037                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
1038                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1039                         hw_watchpoint.flags = BP_MEM_WRITE;
1040                         break;
1041                     case 0x3:
1042                         handle = 1;
1043                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
1044                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1045                         hw_watchpoint.flags = BP_MEM_ACCESS;
1046                         break;
1047                     }
1048         }
1049     } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc))
1050         handle = 1;
1051
1052     if (!handle)
1053         kvm_update_guest_debug(cpu_single_env,
1054                         (arch_info->exception == 1) ?
1055                         KVM_GUESTDBG_INJECT_DB : KVM_GUESTDBG_INJECT_BP);
1056
1057     return handle;
1058 }
1059
1060 void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg)
1061 {
1062     const uint8_t type_code[] = {
1063         [GDB_BREAKPOINT_HW] = 0x0,
1064         [GDB_WATCHPOINT_WRITE] = 0x1,
1065         [GDB_WATCHPOINT_ACCESS] = 0x3
1066     };
1067     const uint8_t len_code[] = {
1068         [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
1069     };
1070     int n;
1071
1072     if (kvm_sw_breakpoints_active(env))
1073         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
1074
1075     if (nb_hw_breakpoint > 0) {
1076         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
1077         dbg->arch.debugreg[7] = 0x0600;
1078         for (n = 0; n < nb_hw_breakpoint; n++) {
1079             dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
1080             dbg->arch.debugreg[7] |= (2 << (n * 2)) |
1081                 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
1082                 (len_code[hw_breakpoint[n].len] << (18 + n*4));
1083         }
1084     }
1085 }
1086 #endif /* KVM_CAP_SET_GUEST_DEBUG */