hw/timer/tusb6010.c

   1 /*
   2  * Texas Instruments TUSB6010 emulation.
   3  * Based on reverse-engineering of a linux driver.
   4  *
   5  * Copyright (C) 2008 Nokia Corporation
   6  * Written by Andrzej Zaborowski <andrew@openedhand.com>
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 or
  11  * (at your option) version 3 of the License.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License along
  19  * with this program; if not, see <http://www.gnu.org/licenses/>.
  20  */
  21 #include "qemu-common.h"
  22 #include "qemu/timer.h"
  23 #include "hw/usb.h"
  24 #include "hw/arm/omap.h"
  25 #include "hw/irq.h"
  26 #include "hw/devices.h"
  27 #include "hw/sysbus.h"
  28
  29 #define TYPE_TUSB6010 "tusb6010"
  30 #define TUSB(obj) OBJECT_CHECK(TUSBState, (obj), TYPE_TUSB6010)
  31
  32 typedef struct TUSBState {
  33     SysBusDevice parent_obj;
  34
  35     MemoryRegion iomem[2];
  36     qemu_irq irq;
  37     MUSBState *musb;
  38     QEMUTimer *otg_timer;
  39     QEMUTimer *pwr_timer;
  40
  41     int power;
  42     uint32_t scratch;
  43     uint16_t test_reset;
  44     uint32_t prcm_config;
  45     uint32_t prcm_mngmt;
  46     uint16_t otg_status;
  47     uint32_t dev_config;
  48     int host_mode;
  49     uint32_t intr;
  50     uint32_t intr_ok;
  51     uint32_t mask;
  52     uint32_t usbip_intr;
  53     uint32_t usbip_mask;
  54     uint32_t gpio_intr;
  55     uint32_t gpio_mask;
  56     uint32_t gpio_config;
  57     uint32_t dma_intr;
  58     uint32_t dma_mask;
  59     uint32_t dma_map;
  60     uint32_t dma_config;
  61     uint32_t ep0_config;
  62     uint32_t rx_config[15];
  63     uint32_t tx_config[15];
  64     uint32_t wkup_mask;
  65     uint32_t pullup[2];
  66     uint32_t control_config;
  67     uint32_t otg_timer_val;
  68 } TUSBState;
  69
  70 #define TUSB_DEVCLOCK                   60000000        /* 60 MHz */
  71
  72 #define TUSB_VLYNQ_CTRL                 0x004
  73
  74 /* Mentor Graphics OTG core registers.  */
  75 #define TUSB_BASE_OFFSET                0x400
  76
  77 /* FIFO registers, 32-bit.  */
  78 #define TUSB_FIFO_BASE                  0x600
  79
  80 /* Device System & Control registers, 32-bit.  */
  81 #define TUSB_SYS_REG_BASE               0x800
  82
  83 #define TUSB_DEV_CONF                   (TUSB_SYS_REG_BASE + 0x000)
  84 #define TUSB_DEV_CONF_USB_HOST_MODE     (1 << 16)
  85 #define TUSB_DEV_CONF_PROD_TEST_MODE    (1 << 15)
  86 #define TUSB_DEV_CONF_SOFT_ID           (1 << 1)
  87 #define TUSB_DEV_CONF_ID_SEL            (1 << 0)
  88
  89 #define TUSB_PHY_OTG_CTRL_ENABLE        (TUSB_SYS_REG_BASE + 0x004)
  90 #define TUSB_PHY_OTG_CTRL               (TUSB_SYS_REG_BASE + 0x008)
  91 #define TUSB_PHY_OTG_CTRL_WRPROTECT     (0xa5 << 24)
  92 #define TUSB_PHY_OTG_CTRL_O_ID_PULLUP   (1 << 23)
  93 #define TUSB_PHY_OTG_CTRL_O_VBUS_DET_EN (1 << 19)
  94 #define TUSB_PHY_OTG_CTRL_O_SESS_END_EN (1 << 18)
  95 #define TUSB_PHY_OTG_CTRL_TESTM2        (1 << 17)
  96 #define TUSB_PHY_OTG_CTRL_TESTM1        (1 << 16)
  97 #define TUSB_PHY_OTG_CTRL_TESTM0        (1 << 15)
  98 #define TUSB_PHY_OTG_CTRL_TX_DATA2      (1 << 14)
  99 #define TUSB_PHY_OTG_CTRL_TX_GZ2        (1 << 13)
 100 #define TUSB_PHY_OTG_CTRL_TX_ENABLE2    (1 << 12)
 101 #define TUSB_PHY_OTG_CTRL_DM_PULLDOWN   (1 << 11)
 102 #define TUSB_PHY_OTG_CTRL_DP_PULLDOWN   (1 << 10)
 103 #define TUSB_PHY_OTG_CTRL_OSC_EN        (1 << 9)
 104 #define TUSB_PHY_OTG_CTRL_PHYREF_CLK(v) (((v) & 3) << 7)
 105 #define TUSB_PHY_OTG_CTRL_PD            (1 << 6)
 106 #define TUSB_PHY_OTG_CTRL_PLL_ON        (1 << 5)
 107 #define TUSB_PHY_OTG_CTRL_EXT_RPU       (1 << 4)
 108 #define TUSB_PHY_OTG_CTRL_PWR_GOOD      (1 << 3)
 109 #define TUSB_PHY_OTG_CTRL_RESET         (1 << 2)
 110 #define TUSB_PHY_OTG_CTRL_SUSPENDM      (1 << 1)
 111 #define TUSB_PHY_OTG_CTRL_CLK_MODE      (1 << 0)
 112
 113 /* OTG status register */
 114 #define TUSB_DEV_OTG_STAT               (TUSB_SYS_REG_BASE + 0x00c)
 115 #define TUSB_DEV_OTG_STAT_PWR_CLK_GOOD  (1 << 8)
 116 #define TUSB_DEV_OTG_STAT_SESS_END      (1 << 7)
 117 #define TUSB_DEV_OTG_STAT_SESS_VALID    (1 << 6)
 118 #define TUSB_DEV_OTG_STAT_VBUS_VALID    (1 << 5)
 119 #define TUSB_DEV_OTG_STAT_VBUS_SENSE    (1 << 4)
 120 #define TUSB_DEV_OTG_STAT_ID_STATUS     (1 << 3)
 121 #define TUSB_DEV_OTG_STAT_HOST_DISCON   (1 << 2)
 122 #define TUSB_DEV_OTG_STAT_LINE_STATE    (3 << 0)
 123 #define TUSB_DEV_OTG_STAT_DP_ENABLE     (1 << 1)
 124 #define TUSB_DEV_OTG_STAT_DM_ENABLE     (1 << 0)
 125
 126 #define TUSB_DEV_OTG_TIMER              (TUSB_SYS_REG_BASE + 0x010)
 127 #define TUSB_DEV_OTG_TIMER_ENABLE       (1 << 31)
 128 #define TUSB_DEV_OTG_TIMER_VAL(v)       ((v) & 0x07ffffff)
 129 #define TUSB_PRCM_REV                   (TUSB_SYS_REG_BASE + 0x014)
 130
 131 /* PRCM configuration register */
 132 #define TUSB_PRCM_CONF                  (TUSB_SYS_REG_BASE + 0x018)
 133 #define TUSB_PRCM_CONF_SFW_CPEN         (1 << 24)
 134 #define TUSB_PRCM_CONF_SYS_CLKSEL(v)    (((v) & 3) << 16)
 135
 136 /* PRCM management register */
 137 #define TUSB_PRCM_MNGMT                 (TUSB_SYS_REG_BASE + 0x01c)
 138 #define TUSB_PRCM_MNGMT_SRP_FIX_TMR(v)  (((v) & 0xf) << 25)
 139 #define TUSB_PRCM_MNGMT_SRP_FIX_EN      (1 << 24)
 140 #define TUSB_PRCM_MNGMT_VBUS_VAL_TMR(v) (((v) & 0xf) << 20)
 141 #define TUSB_PRCM_MNGMT_VBUS_VAL_FLT_EN (1 << 19)
 142 #define TUSB_PRCM_MNGMT_DFT_CLK_DIS     (1 << 18)
 143 #define TUSB_PRCM_MNGMT_VLYNQ_CLK_DIS   (1 << 17)
 144 #define TUSB_PRCM_MNGMT_OTG_SESS_END_EN (1 << 10)
 145 #define TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN (1 << 9)
 146 #define TUSB_PRCM_MNGMT_OTG_ID_PULLUP   (1 << 8)
 147 #define TUSB_PRCM_MNGMT_15_SW_EN        (1 << 4)
 148 #define TUSB_PRCM_MNGMT_33_SW_EN        (1 << 3)
 149 #define TUSB_PRCM_MNGMT_5V_CPEN         (1 << 2)
 150 #define TUSB_PRCM_MNGMT_PM_IDLE         (1 << 1)
 151 #define TUSB_PRCM_MNGMT_DEV_IDLE        (1 << 0)
 152
 153 /* Wake-up source clear and mask registers */
 154 #define TUSB_PRCM_WAKEUP_SOURCE         (TUSB_SYS_REG_BASE + 0x020)
 155 #define TUSB_PRCM_WAKEUP_CLEAR          (TUSB_SYS_REG_BASE + 0x028)
 156 #define TUSB_PRCM_WAKEUP_MASK           (TUSB_SYS_REG_BASE + 0x02c)
 157 #define TUSB_PRCM_WAKEUP_RESERVED_BITS  (0xffffe << 13)
 158 #define TUSB_PRCM_WGPIO_7               (1 << 12)
 159 #define TUSB_PRCM_WGPIO_6               (1 << 11)
 160 #define TUSB_PRCM_WGPIO_5               (1 << 10)
 161 #define TUSB_PRCM_WGPIO_4               (1 << 9)
 162 #define TUSB_PRCM_WGPIO_3               (1 << 8)
 163 #define TUSB_PRCM_WGPIO_2               (1 << 7)
 164 #define TUSB_PRCM_WGPIO_1               (1 << 6)
 165 #define TUSB_PRCM_WGPIO_0               (1 << 5)
 166 #define TUSB_PRCM_WHOSTDISCON           (1 << 4)        /* Host disconnect */
 167 #define TUSB_PRCM_WBUS                  (1 << 3)        /* USB bus resume */
 168 #define TUSB_PRCM_WNORCS                (1 << 2)        /* NOR chip select */
 169 #define TUSB_PRCM_WVBUS                 (1 << 1)        /* OTG PHY VBUS */
 170 #define TUSB_PRCM_WID                   (1 << 0)        /* OTG PHY ID detect */
 171
 172 #define TUSB_PULLUP_1_CTRL              (TUSB_SYS_REG_BASE + 0x030)
 173 #define TUSB_PULLUP_2_CTRL              (TUSB_SYS_REG_BASE + 0x034)
 174 #define TUSB_INT_CTRL_REV               (TUSB_SYS_REG_BASE + 0x038)
 175 #define TUSB_INT_CTRL_CONF              (TUSB_SYS_REG_BASE + 0x03c)
 176 #define TUSB_USBIP_INT_SRC              (TUSB_SYS_REG_BASE + 0x040)
 177 #define TUSB_USBIP_INT_SET              (TUSB_SYS_REG_BASE + 0x044)
 178 #define TUSB_USBIP_INT_CLEAR            (TUSB_SYS_REG_BASE + 0x048)
 179 #define TUSB_USBIP_INT_MASK             (TUSB_SYS_REG_BASE + 0x04c)
 180 #define TUSB_DMA_INT_SRC                (TUSB_SYS_REG_BASE + 0x050)
 181 #define TUSB_DMA_INT_SET                (TUSB_SYS_REG_BASE + 0x054)
 182 #define TUSB_DMA_INT_CLEAR              (TUSB_SYS_REG_BASE + 0x058)
 183 #define TUSB_DMA_INT_MASK               (TUSB_SYS_REG_BASE + 0x05c)
 184 #define TUSB_GPIO_INT_SRC               (TUSB_SYS_REG_BASE + 0x060)
 185 #define TUSB_GPIO_INT_SET               (TUSB_SYS_REG_BASE + 0x064)
 186 #define TUSB_GPIO_INT_CLEAR             (TUSB_SYS_REG_BASE + 0x068)
 187 #define TUSB_GPIO_INT_MASK              (TUSB_SYS_REG_BASE + 0x06c)
 188
 189 /* NOR flash interrupt source registers */
 190 #define TUSB_INT_SRC                    (TUSB_SYS_REG_BASE + 0x070)
 191 #define TUSB_INT_SRC_SET                (TUSB_SYS_REG_BASE + 0x074)
 192 #define TUSB_INT_SRC_CLEAR              (TUSB_SYS_REG_BASE + 0x078)
 193 #define TUSB_INT_MASK                   (TUSB_SYS_REG_BASE + 0x07c)
 194 #define TUSB_INT_SRC_TXRX_DMA_DONE      (1 << 24)
 195 #define TUSB_INT_SRC_USB_IP_CORE        (1 << 17)
 196 #define TUSB_INT_SRC_OTG_TIMEOUT        (1 << 16)
 197 #define TUSB_INT_SRC_VBUS_SENSE_CHNG    (1 << 15)
 198 #define TUSB_INT_SRC_ID_STATUS_CHNG     (1 << 14)
 199 #define TUSB_INT_SRC_DEV_WAKEUP         (1 << 13)
 200 #define TUSB_INT_SRC_DEV_READY          (1 << 12)
 201 #define TUSB_INT_SRC_USB_IP_TX          (1 << 9)
 202 #define TUSB_INT_SRC_USB_IP_RX          (1 << 8)
 203 #define TUSB_INT_SRC_USB_IP_VBUS_ERR    (1 << 7)
 204 #define TUSB_INT_SRC_USB_IP_VBUS_REQ    (1 << 6)
 205 #define TUSB_INT_SRC_USB_IP_DISCON      (1 << 5)
 206 #define TUSB_INT_SRC_USB_IP_CONN        (1 << 4)
 207 #define TUSB_INT_SRC_USB_IP_SOF         (1 << 3)
 208 #define TUSB_INT_SRC_USB_IP_RST_BABBLE  (1 << 2)
 209 #define TUSB_INT_SRC_USB_IP_RESUME      (1 << 1)
 210 #define TUSB_INT_SRC_USB_IP_SUSPEND     (1 << 0)
 211
 212 #define TUSB_GPIO_REV                   (TUSB_SYS_REG_BASE + 0x080)
 213 #define TUSB_GPIO_CONF                  (TUSB_SYS_REG_BASE + 0x084)
 214 #define TUSB_DMA_CTRL_REV               (TUSB_SYS_REG_BASE + 0x100)
 215 #define TUSB_DMA_REQ_CONF               (TUSB_SYS_REG_BASE + 0x104)
 216 #define TUSB_EP0_CONF                   (TUSB_SYS_REG_BASE + 0x108)
 217 #define TUSB_EP_IN_SIZE                 (TUSB_SYS_REG_BASE + 0x10c)
 218 #define TUSB_DMA_EP_MAP                 (TUSB_SYS_REG_BASE + 0x148)
 219 #define TUSB_EP_OUT_SIZE                (TUSB_SYS_REG_BASE + 0x14c)
 220 #define TUSB_EP_MAX_PACKET_SIZE_OFFSET  (TUSB_SYS_REG_BASE + 0x188)
 221 #define TUSB_SCRATCH_PAD                (TUSB_SYS_REG_BASE + 0x1c4)
 222 #define TUSB_WAIT_COUNT                 (TUSB_SYS_REG_BASE + 0x1c8)
 223 #define TUSB_PROD_TEST_RESET            (TUSB_SYS_REG_BASE + 0x1d8)
 224
 225 #define TUSB_DIDR1_LO                   (TUSB_SYS_REG_BASE + 0x1f8)
 226 #define TUSB_DIDR1_HI                   (TUSB_SYS_REG_BASE + 0x1fc)
 227
 228 /* Device System & Control register bitfields */
 229 #define TUSB_INT_CTRL_CONF_INT_RLCYC(v) (((v) & 0x7) << 18)
 230 #define TUSB_INT_CTRL_CONF_INT_POLARITY (1 << 17)
 231 #define TUSB_INT_CTRL_CONF_INT_MODE     (1 << 16)
 232 #define TUSB_GPIO_CONF_DMAREQ(v)        (((v) & 0x3f) << 24)
 233 #define TUSB_DMA_REQ_CONF_BURST_SIZE(v) (((v) & 3) << 26)
 234 #define TUSB_DMA_REQ_CONF_DMA_RQ_EN(v)  (((v) & 0x3f) << 20)
 235 #define TUSB_DMA_REQ_CONF_DMA_RQ_ASR(v) (((v) & 0xf) << 16)
 236 #define TUSB_EP0_CONFIG_SW_EN           (1 << 8)
 237 #define TUSB_EP0_CONFIG_DIR_TX          (1 << 7)
 238 #define TUSB_EP0_CONFIG_XFR_SIZE(v)     ((v) & 0x7f)
 239 #define TUSB_EP_CONFIG_SW_EN            (1 << 31)
 240 #define TUSB_EP_CONFIG_XFR_SIZE(v)      ((v) & 0x7fffffff)
 241 #define TUSB_PROD_TEST_RESET_VAL        0xa596
 242
 243 static void tusb_intr_update(TUSBState *s)
 244 {
 245     if (s->control_config & TUSB_INT_CTRL_CONF_INT_POLARITY)
 246         qemu_set_irq(s->irq, s->intr & ~s->mask & s->intr_ok);
 247     else
 248         qemu_set_irq(s->irq, (!(s->intr & ~s->mask)) & s->intr_ok);
 249 }
 250
 251 static void tusb_usbip_intr_update(TUSBState *s)
 252 {
 253     /* TX interrupt in the MUSB */
 254     if (s->usbip_intr & 0x0000ffff & ~s->usbip_mask)
 255         s->intr |= TUSB_INT_SRC_USB_IP_TX;
 256     else
 257         s->intr &= ~TUSB_INT_SRC_USB_IP_TX;
 258
 259     /* RX interrupt in the MUSB */
 260     if (s->usbip_intr & 0xffff0000 & ~s->usbip_mask)
 261         s->intr |= TUSB_INT_SRC_USB_IP_RX;
 262     else
 263         s->intr &= ~TUSB_INT_SRC_USB_IP_RX;
 264
 265     /* XXX: What about TUSB_INT_SRC_USB_IP_CORE?  */
 266
 267     tusb_intr_update(s);
 268 }
 269
 270 static void tusb_dma_intr_update(TUSBState *s)
 271 {
 272     if (s->dma_intr & ~s->dma_mask)
 273         s->intr |= TUSB_INT_SRC_TXRX_DMA_DONE;
 274     else
 275         s->intr &= ~TUSB_INT_SRC_TXRX_DMA_DONE;
 276
 277     tusb_intr_update(s);
 278 }
 279
 280 static void tusb_gpio_intr_update(TUSBState *s)
 281 {
 282     /* TODO: How is this signalled?  */
 283 }
 284
 285 extern CPUReadMemoryFunc * const musb_read[];
 286 extern CPUWriteMemoryFunc * const musb_write[];
 287
 288 static uint32_t tusb_async_readb(void *opaque, hwaddr addr)
 289 {
 290     TUSBState *s = (TUSBState *) opaque;
 291
 292     switch (addr & 0xfff) {
 293     case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff):
 294         return musb_read[0](s->musb, addr & 0x1ff);
 295
 296     case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff):
 297         return musb_read[0](s->musb, 0x20 + ((addr >> 3) & 0x3c));
 298     }
 299
 300     printf("%s: unknown register at %03x\n",
 301                     __FUNCTION__, (int) (addr & 0xfff));
 302     return 0;
 303 }
 304
 305 static uint32_t tusb_async_readh(void *opaque, hwaddr addr)
 306 {
 307     TUSBState *s = (TUSBState *) opaque;
 308
 309     switch (addr & 0xfff) {
 310     case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff):
 311         return musb_read[1](s->musb, addr & 0x1ff);
 312
 313     case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff):
 314         return musb_read[1](s->musb, 0x20 + ((addr >> 3) & 0x3c));
 315     }
 316
 317     printf("%s: unknown register at %03x\n",
 318                     __FUNCTION__, (int) (addr & 0xfff));
 319     return 0;
 320 }
 321
 322 static uint32_t tusb_async_readw(void *opaque, hwaddr addr)
 323 {
 324     TUSBState *s = (TUSBState *) opaque;
 325     int offset = addr & 0xfff;
 326     int epnum;
 327     uint32_t ret;
 328
 329     switch (offset) {
 330     case TUSB_DEV_CONF:
 331         return s->dev_config;
 332
 333     case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff):
 334         return musb_read[2](s->musb, offset & 0x1ff);
 335
 336     case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff):
 337         return musb_read[2](s->musb, 0x20 + ((addr >> 3) & 0x3c));
 338
 339     case TUSB_PHY_OTG_CTRL_ENABLE:
 340     case TUSB_PHY_OTG_CTRL:
 341         return 0x00;    /* TODO */
 342
 343     case TUSB_DEV_OTG_STAT:
 344         ret = s->otg_status;
 345 #if 0
 346         if (!(s->prcm_mngmt & TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN))
 347             ret &= ~TUSB_DEV_OTG_STAT_VBUS_VALID;
 348 #endif
 349         return ret;
 350     case TUSB_DEV_OTG_TIMER:
 351         return s->otg_timer_val;
 352
 353     case TUSB_PRCM_REV:
 354         return 0x20;
 355     case TUSB_PRCM_CONF:
 356         return s->prcm_config;
 357     case TUSB_PRCM_MNGMT:
 358         return s->prcm_mngmt;
 359     case TUSB_PRCM_WAKEUP_SOURCE:
 360     case TUSB_PRCM_WAKEUP_CLEAR:        /* TODO: What does this one return?  */
 361         return 0x00000000;
 362     case TUSB_PRCM_WAKEUP_MASK:
 363         return s->wkup_mask;
 364
 365     case TUSB_PULLUP_1_CTRL:
 366         return s->pullup[0];
 367     case TUSB_PULLUP_2_CTRL:
 368         return s->pullup[1];
 369
 370     case TUSB_INT_CTRL_REV:
 371         return 0x20;
 372     case TUSB_INT_CTRL_CONF:
 373         return s->control_config;
 374
 375     case TUSB_USBIP_INT_SRC:
 376     case TUSB_USBIP_INT_SET:    /* TODO: What do these two return?  */
 377     case TUSB_USBIP_INT_CLEAR:
 378         return s->usbip_intr;
 379     case TUSB_USBIP_INT_MASK:
 380         return s->usbip_mask;
 381
 382     case TUSB_DMA_INT_SRC:
 383     case TUSB_DMA_INT_SET:      /* TODO: What do these two return?  */
 384     case TUSB_DMA_INT_CLEAR:
 385         return s->dma_intr;
 386     case TUSB_DMA_INT_MASK:
 387         return s->dma_mask;
 388
 389     case TUSB_GPIO_INT_SRC:     /* TODO: What do these two return?  */
 390     case TUSB_GPIO_INT_SET:
 391     case TUSB_GPIO_INT_CLEAR:
 392         return s->gpio_intr;
 393     case TUSB_GPIO_INT_MASK:
 394         return s->gpio_mask;
 395
 396     case TUSB_INT_SRC:
 397     case TUSB_INT_SRC_SET:      /* TODO: What do these two return?  */
 398     case TUSB_INT_SRC_CLEAR:
 399         return s->intr;
 400     case TUSB_INT_MASK:
 401         return s->mask;
 402
 403     case TUSB_GPIO_REV:
 404         return 0x30;
 405     case TUSB_GPIO_CONF:
 406         return s->gpio_config;
 407
 408     case TUSB_DMA_CTRL_REV:
 409         return 0x30;
 410     case TUSB_DMA_REQ_CONF:
 411         return s->dma_config;
 412     case TUSB_EP0_CONF:
 413         return s->ep0_config;
 414     case TUSB_EP_IN_SIZE ... (TUSB_EP_IN_SIZE + 0x3b):
 415         epnum = (offset - TUSB_EP_IN_SIZE) >> 2;
 416         return s->tx_config[epnum];
 417     case TUSB_DMA_EP_MAP:
 418         return s->dma_map;
 419     case TUSB_EP_OUT_SIZE ... (TUSB_EP_OUT_SIZE + 0x3b):
 420         epnum = (offset - TUSB_EP_OUT_SIZE) >> 2;
 421         return s->rx_config[epnum];
 422     case TUSB_EP_MAX_PACKET_SIZE_OFFSET ...
 423             (TUSB_EP_MAX_PACKET_SIZE_OFFSET + 0x3b):
 424         return 0x00000000;      /* TODO */
 425     case TUSB_WAIT_COUNT:
 426         return 0x00;            /* TODO */
 427
 428     case TUSB_SCRATCH_PAD:
 429         return s->scratch;
 430
 431     case TUSB_PROD_TEST_RESET:
 432         return s->test_reset;
 433
 434     /* DIE IDs */
 435     case TUSB_DIDR1_LO:
 436         return 0xa9453c59;
 437     case TUSB_DIDR1_HI:
 438         return 0x54059adf;
 439     }
 440
 441     printf("%s: unknown register at %03x\n", __FUNCTION__, offset);
 442     return 0;
 443 }
 444
 445 static void tusb_async_writeb(void *opaque, hwaddr addr,
 446                 uint32_t value)
 447 {
 448     TUSBState *s = (TUSBState *) opaque;
 449
 450     switch (addr & 0xfff) {
 451     case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff):
 452         musb_write[0](s->musb, addr & 0x1ff, value);
 453         break;
 454
 455     case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff):
 456         musb_write[0](s->musb, 0x20 + ((addr >> 3) & 0x3c), value);
 457         break;
 458
 459     default:
 460         printf("%s: unknown register at %03x\n",
 461                         __FUNCTION__, (int) (addr & 0xfff));
 462         return;
 463     }
 464 }
 465
 466 static void tusb_async_writeh(void *opaque, hwaddr addr,
 467                 uint32_t value)
 468 {
 469     TUSBState *s = (TUSBState *) opaque;
 470
 471     switch (addr & 0xfff) {
 472     case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff):
 473         musb_write[1](s->musb, addr & 0x1ff, value);
 474         break;
 475
 476     case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff):
 477         musb_write[1](s->musb, 0x20 + ((addr >> 3) & 0x3c), value);
 478         break;
 479
 480     default:
 481         printf("%s: unknown register at %03x\n",
 482                         __FUNCTION__, (int) (addr & 0xfff));
 483         return;
 484     }
 485 }
 486
 487 static void tusb_async_writew(void *opaque, hwaddr addr,
 488                 uint32_t value)
 489 {
 490     TUSBState *s = (TUSBState *) opaque;
 491     int offset = addr & 0xfff;
 492     int epnum;
 493
 494     switch (offset) {
 495     case TUSB_VLYNQ_CTRL:
 496         break;
 497
 498     case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff):
 499         musb_write[2](s->musb, offset & 0x1ff, value);
 500         break;
 501
 502     case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff):
 503         musb_write[2](s->musb, 0x20 + ((addr >> 3) & 0x3c), value);
 504         break;
 505
 506     case TUSB_DEV_CONF:
 507         s->dev_config = value;
 508         s->host_mode = (value & TUSB_DEV_CONF_USB_HOST_MODE);
 509         if (value & TUSB_DEV_CONF_PROD_TEST_MODE)
 510             hw_error("%s: Product Test mode not allowed\n", __FUNCTION__);
 511         break;
 512
 513     case TUSB_PHY_OTG_CTRL_ENABLE:
 514     case TUSB_PHY_OTG_CTRL:
 515         return;         /* TODO */
 516     case TUSB_DEV_OTG_TIMER:
 517         s->otg_timer_val = value;
 518         if (value & TUSB_DEV_OTG_TIMER_ENABLE)
 519             timer_mod(s->otg_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
 520                             muldiv64(TUSB_DEV_OTG_TIMER_VAL(value),
 521                                      get_ticks_per_sec(), TUSB_DEVCLOCK));
 522         else
 523             timer_del(s->otg_timer);
 524         break;
 525
 526     case TUSB_PRCM_CONF:
 527         s->prcm_config = value;
 528         break;
 529     case TUSB_PRCM_MNGMT:
 530         s->prcm_mngmt = value;
 531         break;
 532     case TUSB_PRCM_WAKEUP_CLEAR:
 533         break;
 534     case TUSB_PRCM_WAKEUP_MASK:
 535         s->wkup_mask = value;
 536         break;
 537
 538     case TUSB_PULLUP_1_CTRL:
 539         s->pullup[0] = value;
 540         break;
 541     case TUSB_PULLUP_2_CTRL:
 542         s->pullup[1] = value;
 543         break;
 544     case TUSB_INT_CTRL_CONF:
 545         s->control_config = value;
 546         tusb_intr_update(s);
 547         break;
 548
 549     case TUSB_USBIP_INT_SET:
 550         s->usbip_intr |= value;
 551         tusb_usbip_intr_update(s);
 552         break;
 553     case TUSB_USBIP_INT_CLEAR:
 554         s->usbip_intr &= ~value;
 555         tusb_usbip_intr_update(s);
 556         musb_core_intr_clear(s->musb, ~value);
 557         break;
 558     case TUSB_USBIP_INT_MASK:
 559         s->usbip_mask = value;
 560         tusb_usbip_intr_update(s);
 561         break;
 562
 563     case TUSB_DMA_INT_SET:
 564         s->dma_intr |= value;
 565         tusb_dma_intr_update(s);
 566         break;
 567     case TUSB_DMA_INT_CLEAR:
 568         s->dma_intr &= ~value;
 569         tusb_dma_intr_update(s);
 570         break;
 571     case TUSB_DMA_INT_MASK:
 572         s->dma_mask = value;
 573         tusb_dma_intr_update(s);
 574         break;
 575
 576     case TUSB_GPIO_INT_SET:
 577         s->gpio_intr |= value;
 578         tusb_gpio_intr_update(s);
 579         break;
 580     case TUSB_GPIO_INT_CLEAR:
 581         s->gpio_intr &= ~value;
 582         tusb_gpio_intr_update(s);
 583         break;
 584     case TUSB_GPIO_INT_MASK:
 585         s->gpio_mask = value;
 586         tusb_gpio_intr_update(s);
 587         break;
 588
 589     case TUSB_INT_SRC_SET:
 590         s->intr |= value;
 591         tusb_intr_update(s);
 592         break;
 593     case TUSB_INT_SRC_CLEAR:
 594         s->intr &= ~value;
 595         tusb_intr_update(s);
 596         break;
 597     case TUSB_INT_MASK:
 598         s->mask = value;
 599         tusb_intr_update(s);
 600         break;
 601
 602     case TUSB_GPIO_CONF:
 603         s->gpio_config = value;
 604         break;
 605     case TUSB_DMA_REQ_CONF:
 606         s->dma_config = value;
 607         break;
 608     case TUSB_EP0_CONF:
 609         s->ep0_config = value & 0x1ff;
 610         musb_set_size(s->musb, 0, TUSB_EP0_CONFIG_XFR_SIZE(value),
 611                         value & TUSB_EP0_CONFIG_DIR_TX);
 612         break;
 613     case TUSB_EP_IN_SIZE ... (TUSB_EP_IN_SIZE + 0x3b):
 614         epnum = (offset - TUSB_EP_IN_SIZE) >> 2;
 615         s->tx_config[epnum] = value;
 616         musb_set_size(s->musb, epnum + 1, TUSB_EP_CONFIG_XFR_SIZE(value), 1);
 617         break;
 618     case TUSB_DMA_EP_MAP:
 619         s->dma_map = value;
 620         break;
 621     case TUSB_EP_OUT_SIZE ... (TUSB_EP_OUT_SIZE + 0x3b):
 622         epnum = (offset - TUSB_EP_OUT_SIZE) >> 2;
 623         s->rx_config[epnum] = value;
 624         musb_set_size(s->musb, epnum + 1, TUSB_EP_CONFIG_XFR_SIZE(value), 0);
 625         break;
 626     case TUSB_EP_MAX_PACKET_SIZE_OFFSET ...
 627             (TUSB_EP_MAX_PACKET_SIZE_OFFSET + 0x3b):
 628         return;         /* TODO */
 629     case TUSB_WAIT_COUNT:
 630         return;         /* TODO */
 631
 632     case TUSB_SCRATCH_PAD:
 633         s->scratch = value;
 634         break;
 635
 636     case TUSB_PROD_TEST_RESET:
 637         s->test_reset = value;
 638         break;
 639
 640     default:
 641         printf("%s: unknown register at %03x\n", __FUNCTION__, offset);
 642         return;
 643     }
 644 }
 645
 646 static const MemoryRegionOps tusb_async_ops = {
 647     .old_mmio = {
 648         .read = { tusb_async_readb, tusb_async_readh, tusb_async_readw, },
 649         .write =  { tusb_async_writeb, tusb_async_writeh, tusb_async_writew, },
 650     },
 651     .endianness = DEVICE_NATIVE_ENDIAN,
 652 };
 653
 654 static void tusb_otg_tick(void *opaque)
 655 {
 656     TUSBState *s = (TUSBState *) opaque;
 657
 658     s->otg_timer_val = 0;
 659     s->intr |= TUSB_INT_SRC_OTG_TIMEOUT;
 660     tusb_intr_update(s);
 661 }
 662
 663 static void tusb_power_tick(void *opaque)
 664 {
 665     TUSBState *s = (TUSBState *) opaque;
 666
 667     if (s->power) {
 668         s->intr_ok = ~0;
 669         tusb_intr_update(s);
 670     }
 671 }
 672
 673 static void tusb_musb_core_intr(void *opaque, int source, int level)
 674 {
 675     TUSBState *s = (TUSBState *) opaque;
 676     uint16_t otg_status = s->otg_status;
 677
 678     switch (source) {
 679     case musb_set_vbus:
 680         if (level)
 681             otg_status |= TUSB_DEV_OTG_STAT_VBUS_VALID;
 682         else
 683             otg_status &= ~TUSB_DEV_OTG_STAT_VBUS_VALID;
 684
 685         /* XXX: only if TUSB_PHY_OTG_CTRL_OTG_VBUS_DET_EN set?  */
 686         /* XXX: only if TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN set?  */
 687         if (s->otg_status != otg_status) {
 688             s->otg_status = otg_status;
 689             s->intr |= TUSB_INT_SRC_VBUS_SENSE_CHNG;
 690             tusb_intr_update(s);
 691         }
 692         break;
 693
 694     case musb_set_session:
 695         /* XXX: only if TUSB_PHY_OTG_CTRL_OTG_SESS_END_EN set?  */
 696         /* XXX: only if TUSB_PRCM_MNGMT_OTG_SESS_END_EN set?  */
 697         if (level) {
 698             s->otg_status |= TUSB_DEV_OTG_STAT_SESS_VALID;
 699             s->otg_status &= ~TUSB_DEV_OTG_STAT_SESS_END;
 700         } else {
 701             s->otg_status &= ~TUSB_DEV_OTG_STAT_SESS_VALID;
 702             s->otg_status |= TUSB_DEV_OTG_STAT_SESS_END;
 703         }
 704
 705         /* XXX: some IRQ or anything?  */
 706         break;
 707
 708     case musb_irq_tx:
 709     case musb_irq_rx:
 710         s->usbip_intr = musb_core_intr_get(s->musb);
 711         /* Fall through.  */
 712     default:
 713         if (level)
 714             s->intr |= 1 << source;
 715         else
 716             s->intr &= ~(1 << source);
 717         tusb_intr_update(s);
 718         break;
 719     }
 720 }
 721
 722 static void tusb6010_power(TUSBState *s, int on)
 723 {
 724     if (!on) {
 725         s->power = 0;
 726     } else if (!s->power && on) {
 727         s->power = 1;
 728         /* Pull the interrupt down after TUSB6010 comes up.  */
 729         s->intr_ok = 0;
 730         tusb_intr_update(s);
 731         timer_mod(s->pwr_timer,
 732                        qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + get_ticks_per_sec() / 2);
 733     }
 734 }
 735
 736 static void tusb6010_irq(void *opaque, int source, int level)
 737 {
 738     if (source) {
 739         tusb_musb_core_intr(opaque, source - 1, level);
 740     } else {
 741         tusb6010_power(opaque, level);
 742     }
 743 }
 744
 745 static void tusb6010_reset(DeviceState *dev)
 746 {
 747     TUSBState *s = TUSB(dev);
 748     int i;
 749
 750     s->test_reset = TUSB_PROD_TEST_RESET_VAL;
 751     s->host_mode = 0;
 752     s->dev_config = 0;
 753     s->otg_status = 0;  /* !TUSB_DEV_OTG_STAT_ID_STATUS means host mode */
 754     s->power = 0;
 755     s->mask = 0xffffffff;
 756     s->intr = 0x00000000;
 757     s->otg_timer_val = 0;
 758     s->scratch = 0;
 759     s->prcm_config = 0;
 760     s->prcm_mngmt = 0;
 761     s->intr_ok = 0;
 762     s->usbip_intr = 0;
 763     s->usbip_mask = 0;
 764     s->gpio_intr = 0;
 765     s->gpio_mask = 0;
 766     s->gpio_config = 0;
 767     s->dma_intr = 0;
 768     s->dma_mask = 0;
 769     s->dma_map = 0;
 770     s->dma_config = 0;
 771     s->ep0_config = 0;
 772     s->wkup_mask = 0;
 773     s->pullup[0] = s->pullup[1] = 0;
 774     s->control_config = 0;
 775     for (i = 0; i < 15; i++) {
 776         s->rx_config[i] = s->tx_config[i] = 0;
 777     }
 778     musb_reset(s->musb);
 779 }
 780
 781 static int tusb6010_init(SysBusDevice *sbd)
 782 {
 783     DeviceState *dev = DEVICE(sbd);
 784     TUSBState *s = TUSB(dev);
 785
 786     s->otg_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, tusb_otg_tick, s);
 787     s->pwr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, tusb_power_tick, s);
 788     memory_region_init_io(&s->iomem[1], OBJECT(s), &tusb_async_ops, s,
 789                           "tusb-async", UINT32_MAX);
 790     sysbus_init_mmio(sbd, &s->iomem[0]);
 791     sysbus_init_mmio(sbd, &s->iomem[1]);
 792     sysbus_init_irq(sbd, &s->irq);
 793     qdev_init_gpio_in(dev, tusb6010_irq, musb_irq_max + 1);
 794     s->musb = musb_init(dev, 1);
 795     return 0;
 796 }
 797
 798 static void tusb6010_class_init(ObjectClass *klass, void *data)
 799 {
 800     DeviceClass *dc = DEVICE_CLASS(klass);
 801     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 802
 803     k->init = tusb6010_init;
 804     dc->reset = tusb6010_reset;
 805 }
 806
 807 static const TypeInfo tusb6010_info = {
 808     .name          = TYPE_TUSB6010,
 809     .parent        = TYPE_SYS_BUS_DEVICE,
 810     .instance_size = sizeof(TUSBState),
 811     .class_init    = tusb6010_class_init,
 812 };
 813
 814 static void tusb6010_register_types(void)
 815 {
 816     type_register_static(&tusb6010_info);
 817 }
 818
 819 type_init(tusb6010_register_types)