2 * SMSC LAN9118 Ethernet interface emulation
4 * Copyright (c) 2009 CodeSourcery, LLC.
5 * Written by Paul Brook
7 * This code is licensed under the GNU GPL v2
9 * Contributions after 2012-01-13 are licensed under the terms of the
10 * GNU GPL, version 2 or (at your option) any later version.
13 #include "qemu/osdep.h"
14 #include "hw/sysbus.h"
15 #include "migration/vmstate.h"
20 #include "hw/net/lan9118.h"
21 #include "hw/ptimer.h"
22 #include "hw/qdev-properties.h"
23 #include "qapi/error.h"
25 #include "qemu/module.h"
28 #include "qom/object.h"
30 //#define DEBUG_LAN9118
33 #define DPRINTF(fmt, ...) \
34 do { printf("lan9118: " fmt , ## __VA_ARGS__); } while (0)
35 #define BADF(fmt, ...) \
36 do { hw_error("lan9118: error: " fmt , ## __VA_ARGS__);} while (0)
38 #define DPRINTF(fmt, ...) do {} while(0)
39 #define BADF(fmt, ...) \
40 do { fprintf(stderr, "lan9118: error: " fmt , ## __VA_ARGS__);} while (0)
43 /* The tx and rx fifo ports are a range of aliased 32-bit registers */
44 #define RX_DATA_FIFO_PORT_FIRST 0x00
45 #define RX_DATA_FIFO_PORT_LAST 0x1f
46 #define TX_DATA_FIFO_PORT_FIRST 0x20
47 #define TX_DATA_FIFO_PORT_LAST 0x3f
49 #define RX_STATUS_FIFO_PORT 0x40
50 #define RX_STATUS_FIFO_PEEK 0x44
51 #define TX_STATUS_FIFO_PORT 0x48
52 #define TX_STATUS_FIFO_PEEK 0x4c
54 #define CSR_ID_REV 0x50
55 #define CSR_IRQ_CFG 0x54
56 #define CSR_INT_STS 0x58
57 #define CSR_INT_EN 0x5c
58 #define CSR_BYTE_TEST 0x64
59 #define CSR_FIFO_INT 0x68
60 #define CSR_RX_CFG 0x6c
61 #define CSR_TX_CFG 0x70
62 #define CSR_HW_CFG 0x74
63 #define CSR_RX_DP_CTRL 0x78
64 #define CSR_RX_FIFO_INF 0x7c
65 #define CSR_TX_FIFO_INF 0x80
66 #define CSR_PMT_CTRL 0x84
67 #define CSR_GPIO_CFG 0x88
68 #define CSR_GPT_CFG 0x8c
69 #define CSR_GPT_CNT 0x90
70 #define CSR_WORD_SWAP 0x98
71 #define CSR_FREE_RUN 0x9c
72 #define CSR_RX_DROP 0xa0
73 #define CSR_MAC_CSR_CMD 0xa4
74 #define CSR_MAC_CSR_DATA 0xa8
75 #define CSR_AFC_CFG 0xac
76 #define CSR_E2P_CMD 0xb0
77 #define CSR_E2P_DATA 0xb4
79 #define E2P_CMD_MAC_ADDR_LOADED 0x100
82 #define IRQ_INT 0x00001000
83 #define IRQ_EN 0x00000100
84 #define IRQ_POL 0x00000010
85 #define IRQ_TYPE 0x00000001
88 #define SW_INT 0x80000000
89 #define TXSTOP_INT 0x02000000
90 #define RXSTOP_INT 0x01000000
91 #define RXDFH_INT 0x00800000
92 #define TX_IOC_INT 0x00200000
93 #define RXD_INT 0x00100000
94 #define GPT_INT 0x00080000
95 #define PHY_INT 0x00040000
96 #define PME_INT 0x00020000
97 #define TXSO_INT 0x00010000
98 #define RWT_INT 0x00008000
99 #define RXE_INT 0x00004000
100 #define TXE_INT 0x00002000
101 #define TDFU_INT 0x00000800
102 #define TDFO_INT 0x00000400
103 #define TDFA_INT 0x00000200
104 #define TSFF_INT 0x00000100
105 #define TSFL_INT 0x00000080
106 #define RXDF_INT 0x00000040
107 #define RDFL_INT 0x00000020
108 #define RSFF_INT 0x00000010
109 #define RSFL_INT 0x00000008
110 #define GPIO2_INT 0x00000004
111 #define GPIO1_INT 0x00000002
112 #define GPIO0_INT 0x00000001
113 #define RESERVED_INT 0x7c001000
120 #define MAC_MII_ACC 6
121 #define MAC_MII_DATA 7
123 #define MAC_VLAN1 9 /* TODO */
124 #define MAC_VLAN2 10 /* TODO */
125 #define MAC_WUFF 11 /* TODO */
126 #define MAC_WUCSR 12 /* TODO */
128 #define MAC_CR_RXALL 0x80000000
129 #define MAC_CR_RCVOWN 0x00800000
130 #define MAC_CR_LOOPBK 0x00200000
131 #define MAC_CR_FDPX 0x00100000
132 #define MAC_CR_MCPAS 0x00080000
133 #define MAC_CR_PRMS 0x00040000
134 #define MAC_CR_INVFILT 0x00020000
135 #define MAC_CR_PASSBAD 0x00010000
136 #define MAC_CR_HO 0x00008000
137 #define MAC_CR_HPFILT 0x00002000
138 #define MAC_CR_LCOLL 0x00001000
139 #define MAC_CR_BCAST 0x00000800
140 #define MAC_CR_DISRTY 0x00000400
141 #define MAC_CR_PADSTR 0x00000100
142 #define MAC_CR_BOLMT 0x000000c0
143 #define MAC_CR_DFCHK 0x00000020
144 #define MAC_CR_TXEN 0x00000008
145 #define MAC_CR_RXEN 0x00000004
146 #define MAC_CR_RESERVED 0x7f404213
148 #define PHY_INT_ENERGYON 0x80
149 #define PHY_INT_AUTONEG_COMPLETE 0x40
150 #define PHY_INT_FAULT 0x20
151 #define PHY_INT_DOWN 0x10
152 #define PHY_INT_AUTONEG_LP 0x08
153 #define PHY_INT_PARFAULT 0x04
154 #define PHY_INT_AUTONEG_PAGE 0x02
156 #define GPT_TIMER_EN 0x20000000
165 /* state is a tx_state but we can't put enums in VMStateDescriptions. */
177 static const VMStateDescription vmstate_lan9118_packet
= {
178 .name
= "lan9118_packet",
180 .minimum_version_id
= 1,
181 .fields
= (VMStateField
[]) {
182 VMSTATE_UINT32(state
, LAN9118Packet
),
183 VMSTATE_UINT32(cmd_a
, LAN9118Packet
),
184 VMSTATE_UINT32(cmd_b
, LAN9118Packet
),
185 VMSTATE_INT32(buffer_size
, LAN9118Packet
),
186 VMSTATE_INT32(offset
, LAN9118Packet
),
187 VMSTATE_INT32(pad
, LAN9118Packet
),
188 VMSTATE_INT32(fifo_used
, LAN9118Packet
),
189 VMSTATE_INT32(len
, LAN9118Packet
),
190 VMSTATE_UINT8_ARRAY(data
, LAN9118Packet
, 2048),
191 VMSTATE_END_OF_LIST()
195 OBJECT_DECLARE_SIMPLE_TYPE(lan9118_state
, LAN9118
)
197 struct lan9118_state
{
198 SysBusDevice parent_obj
;
217 uint32_t free_timer_start
;
227 uint32_t mac_mii_acc
;
228 uint32_t mac_mii_data
;
232 uint32_t phy_control
;
233 uint32_t phy_advertise
;
235 uint32_t phy_int_mask
;
237 int32_t eeprom_writable
;
240 int32_t tx_fifo_size
;
242 LAN9118Packet tx_packet
;
244 int32_t tx_status_fifo_used
;
245 int32_t tx_status_fifo_head
;
246 uint32_t tx_status_fifo
[512];
248 int32_t rx_status_fifo_size
;
249 int32_t rx_status_fifo_used
;
250 int32_t rx_status_fifo_head
;
251 uint32_t rx_status_fifo
[896];
252 int32_t rx_fifo_size
;
253 int32_t rx_fifo_used
;
254 int32_t rx_fifo_head
;
255 uint32_t rx_fifo
[3360];
256 int32_t rx_packet_size_head
;
257 int32_t rx_packet_size_tail
;
258 int32_t rx_packet_size
[1024];
264 uint32_t write_word_prev_offset
;
265 uint32_t write_word_n
;
266 uint16_t write_word_l
;
267 uint16_t write_word_h
;
268 uint32_t read_word_prev_offset
;
269 uint32_t read_word_n
;
275 static const VMStateDescription vmstate_lan9118
= {
278 .minimum_version_id
= 1,
279 .fields
= (VMStateField
[]) {
280 VMSTATE_PTIMER(timer
, lan9118_state
),
281 VMSTATE_UINT32(irq_cfg
, lan9118_state
),
282 VMSTATE_UINT32(int_sts
, lan9118_state
),
283 VMSTATE_UINT32(int_en
, lan9118_state
),
284 VMSTATE_UINT32(fifo_int
, lan9118_state
),
285 VMSTATE_UINT32(rx_cfg
, lan9118_state
),
286 VMSTATE_UINT32(tx_cfg
, lan9118_state
),
287 VMSTATE_UINT32(hw_cfg
, lan9118_state
),
288 VMSTATE_UINT32(pmt_ctrl
, lan9118_state
),
289 VMSTATE_UINT32(gpio_cfg
, lan9118_state
),
290 VMSTATE_UINT32(gpt_cfg
, lan9118_state
),
291 VMSTATE_UINT32(word_swap
, lan9118_state
),
292 VMSTATE_UINT32(free_timer_start
, lan9118_state
),
293 VMSTATE_UINT32(mac_cmd
, lan9118_state
),
294 VMSTATE_UINT32(mac_data
, lan9118_state
),
295 VMSTATE_UINT32(afc_cfg
, lan9118_state
),
296 VMSTATE_UINT32(e2p_cmd
, lan9118_state
),
297 VMSTATE_UINT32(e2p_data
, lan9118_state
),
298 VMSTATE_UINT32(mac_cr
, lan9118_state
),
299 VMSTATE_UINT32(mac_hashh
, lan9118_state
),
300 VMSTATE_UINT32(mac_hashl
, lan9118_state
),
301 VMSTATE_UINT32(mac_mii_acc
, lan9118_state
),
302 VMSTATE_UINT32(mac_mii_data
, lan9118_state
),
303 VMSTATE_UINT32(mac_flow
, lan9118_state
),
304 VMSTATE_UINT32(phy_status
, lan9118_state
),
305 VMSTATE_UINT32(phy_control
, lan9118_state
),
306 VMSTATE_UINT32(phy_advertise
, lan9118_state
),
307 VMSTATE_UINT32(phy_int
, lan9118_state
),
308 VMSTATE_UINT32(phy_int_mask
, lan9118_state
),
309 VMSTATE_INT32(eeprom_writable
, lan9118_state
),
310 VMSTATE_UINT8_ARRAY(eeprom
, lan9118_state
, 128),
311 VMSTATE_INT32(tx_fifo_size
, lan9118_state
),
312 /* txp always points at tx_packet so need not be saved */
313 VMSTATE_STRUCT(tx_packet
, lan9118_state
, 0,
314 vmstate_lan9118_packet
, LAN9118Packet
),
315 VMSTATE_INT32(tx_status_fifo_used
, lan9118_state
),
316 VMSTATE_INT32(tx_status_fifo_head
, lan9118_state
),
317 VMSTATE_UINT32_ARRAY(tx_status_fifo
, lan9118_state
, 512),
318 VMSTATE_INT32(rx_status_fifo_size
, lan9118_state
),
319 VMSTATE_INT32(rx_status_fifo_used
, lan9118_state
),
320 VMSTATE_INT32(rx_status_fifo_head
, lan9118_state
),
321 VMSTATE_UINT32_ARRAY(rx_status_fifo
, lan9118_state
, 896),
322 VMSTATE_INT32(rx_fifo_size
, lan9118_state
),
323 VMSTATE_INT32(rx_fifo_used
, lan9118_state
),
324 VMSTATE_INT32(rx_fifo_head
, lan9118_state
),
325 VMSTATE_UINT32_ARRAY(rx_fifo
, lan9118_state
, 3360),
326 VMSTATE_INT32(rx_packet_size_head
, lan9118_state
),
327 VMSTATE_INT32(rx_packet_size_tail
, lan9118_state
),
328 VMSTATE_INT32_ARRAY(rx_packet_size
, lan9118_state
, 1024),
329 VMSTATE_INT32(rxp_offset
, lan9118_state
),
330 VMSTATE_INT32(rxp_size
, lan9118_state
),
331 VMSTATE_INT32(rxp_pad
, lan9118_state
),
332 VMSTATE_UINT32_V(write_word_prev_offset
, lan9118_state
, 2),
333 VMSTATE_UINT32_V(write_word_n
, lan9118_state
, 2),
334 VMSTATE_UINT16_V(write_word_l
, lan9118_state
, 2),
335 VMSTATE_UINT16_V(write_word_h
, lan9118_state
, 2),
336 VMSTATE_UINT32_V(read_word_prev_offset
, lan9118_state
, 2),
337 VMSTATE_UINT32_V(read_word_n
, lan9118_state
, 2),
338 VMSTATE_UINT32_V(read_long
, lan9118_state
, 2),
339 VMSTATE_UINT32_V(mode_16bit
, lan9118_state
, 2),
340 VMSTATE_END_OF_LIST()
344 static void lan9118_update(lan9118_state
*s
)
348 /* TODO: Implement FIFO level IRQs. */
349 level
= (s
->int_sts
& s
->int_en
) != 0;
351 s
->irq_cfg
|= IRQ_INT
;
353 s
->irq_cfg
&= ~IRQ_INT
;
355 if ((s
->irq_cfg
& IRQ_EN
) == 0) {
358 if ((s
->irq_cfg
& (IRQ_TYPE
| IRQ_POL
)) != (IRQ_TYPE
| IRQ_POL
)) {
359 /* Interrupt is active low unless we're configured as
360 * active-high polarity, push-pull type.
364 qemu_set_irq(s
->irq
, level
);
367 static void lan9118_mac_changed(lan9118_state
*s
)
369 qemu_format_nic_info_str(qemu_get_queue(s
->nic
), s
->conf
.macaddr
.a
);
372 static void lan9118_reload_eeprom(lan9118_state
*s
)
375 if (s
->eeprom
[0] != 0xa5) {
376 s
->e2p_cmd
&= ~E2P_CMD_MAC_ADDR_LOADED
;
377 DPRINTF("MACADDR load failed\n");
380 for (i
= 0; i
< 6; i
++) {
381 s
->conf
.macaddr
.a
[i
] = s
->eeprom
[i
+ 1];
383 s
->e2p_cmd
|= E2P_CMD_MAC_ADDR_LOADED
;
384 DPRINTF("MACADDR loaded from eeprom\n");
385 lan9118_mac_changed(s
);
388 static void phy_update_irq(lan9118_state
*s
)
390 if (s
->phy_int
& s
->phy_int_mask
) {
391 s
->int_sts
|= PHY_INT
;
393 s
->int_sts
&= ~PHY_INT
;
398 static void phy_update_link(lan9118_state
*s
)
400 /* Autonegotiation status mirrors link status. */
401 if (qemu_get_queue(s
->nic
)->link_down
) {
402 s
->phy_status
&= ~0x0024;
403 s
->phy_int
|= PHY_INT_DOWN
;
405 s
->phy_status
|= 0x0024;
406 s
->phy_int
|= PHY_INT_ENERGYON
;
407 s
->phy_int
|= PHY_INT_AUTONEG_COMPLETE
;
412 static void lan9118_set_link(NetClientState
*nc
)
414 phy_update_link(qemu_get_nic_opaque(nc
));
417 static void phy_reset(lan9118_state
*s
)
419 s
->phy_status
= 0x7809;
420 s
->phy_control
= 0x3000;
421 s
->phy_advertise
= 0x01e1;
427 static void lan9118_reset(DeviceState
*d
)
429 lan9118_state
*s
= LAN9118(d
);
431 s
->irq_cfg
&= (IRQ_TYPE
| IRQ_POL
);
434 s
->fifo_int
= 0x48000000;
437 s
->hw_cfg
= s
->mode_16bit
? 0x00050000 : 0x00050004;
440 s
->txp
->fifo_used
= 0;
441 s
->txp
->state
= TX_IDLE
;
442 s
->txp
->cmd_a
= 0xffffffffu
;
443 s
->txp
->cmd_b
= 0xffffffffu
;
445 s
->txp
->fifo_used
= 0;
446 s
->tx_fifo_size
= 4608;
447 s
->tx_status_fifo_used
= 0;
448 s
->rx_status_fifo_size
= 704;
449 s
->rx_fifo_size
= 2640;
451 s
->rx_status_fifo_size
= 176;
452 s
->rx_status_fifo_used
= 0;
456 s
->rx_packet_size_tail
= s
->rx_packet_size_head
;
457 s
->rx_packet_size
[s
->rx_packet_size_head
] = 0;
463 s
->free_timer_start
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) / 40;
465 ptimer_transaction_begin(s
->timer
);
466 ptimer_stop(s
->timer
);
467 ptimer_set_count(s
->timer
, 0xffff);
468 ptimer_transaction_commit(s
->timer
);
471 s
->mac_cr
= MAC_CR_PRMS
;
483 s
->eeprom_writable
= 0;
484 lan9118_reload_eeprom(s
);
487 static void rx_fifo_push(lan9118_state
*s
, uint32_t val
)
490 fifo_pos
= s
->rx_fifo_head
+ s
->rx_fifo_used
;
491 if (fifo_pos
>= s
->rx_fifo_size
)
492 fifo_pos
-= s
->rx_fifo_size
;
493 s
->rx_fifo
[fifo_pos
] = val
;
497 /* Return nonzero if the packet is accepted by the filter. */
498 static int lan9118_filter(lan9118_state
*s
, const uint8_t *addr
)
503 if (s
->mac_cr
& MAC_CR_PRMS
) {
506 if (addr
[0] == 0xff && addr
[1] == 0xff && addr
[2] == 0xff &&
507 addr
[3] == 0xff && addr
[4] == 0xff && addr
[5] == 0xff) {
508 return (s
->mac_cr
& MAC_CR_BCAST
) == 0;
511 multicast
= addr
[0] & 1;
512 if (multicast
&&s
->mac_cr
& MAC_CR_MCPAS
) {
515 if (multicast
? (s
->mac_cr
& MAC_CR_HPFILT
) == 0
516 : (s
->mac_cr
& MAC_CR_HO
) == 0) {
517 /* Exact matching. */
518 hash
= memcmp(addr
, s
->conf
.macaddr
.a
, 6);
519 if (s
->mac_cr
& MAC_CR_INVFILT
) {
526 hash
= net_crc32(addr
, ETH_ALEN
) >> 26;
528 return (s
->mac_hashh
>> (hash
& 0x1f)) & 1;
530 return (s
->mac_hashl
>> (hash
& 0x1f)) & 1;
535 static ssize_t
lan9118_receive(NetClientState
*nc
, const uint8_t *buf
,
538 lan9118_state
*s
= qemu_get_nic_opaque(nc
);
548 if ((s
->mac_cr
& MAC_CR_RXEN
) == 0) {
552 if (size
>= 2048 || size
< 14) {
556 /* TODO: Implement FIFO overflow notification. */
557 if (s
->rx_status_fifo_used
== s
->rx_status_fifo_size
) {
561 filter
= lan9118_filter(s
, buf
);
562 if (!filter
&& (s
->mac_cr
& MAC_CR_RXALL
) == 0) {
566 offset
= (s
->rx_cfg
>> 8) & 0x1f;
568 fifo_len
= (size
+ n
+ 3) >> 2;
569 /* Add a word for the CRC. */
571 if (s
->rx_fifo_size
- s
->rx_fifo_used
< fifo_len
) {
575 DPRINTF("Got packet len:%d fifo:%d filter:%s\n",
576 (int)size
, fifo_len
, filter
? "pass" : "fail");
578 crc
= bswap32(crc32(~0, buf
, size
));
579 for (src_pos
= 0; src_pos
< size
; src_pos
++) {
580 val
= (val
>> 8) | ((uint32_t)buf
[src_pos
] << 24);
584 rx_fifo_push(s
, val
);
589 val
>>= ((4 - n
) * 8);
590 val
|= crc
<< (n
* 8);
591 rx_fifo_push(s
, val
);
592 val
= crc
>> ((4 - n
) * 8);
593 rx_fifo_push(s
, val
);
595 rx_fifo_push(s
, crc
);
597 n
= s
->rx_status_fifo_head
+ s
->rx_status_fifo_used
;
598 if (n
>= s
->rx_status_fifo_size
) {
599 n
-= s
->rx_status_fifo_size
;
601 s
->rx_packet_size
[s
->rx_packet_size_tail
] = fifo_len
;
602 s
->rx_packet_size_tail
= (s
->rx_packet_size_tail
+ 1023) & 1023;
603 s
->rx_status_fifo_used
++;
605 status
= (size
+ 4) << 16;
606 if (buf
[0] == 0xff && buf
[1] == 0xff && buf
[2] == 0xff &&
607 buf
[3] == 0xff && buf
[4] == 0xff && buf
[5] == 0xff) {
608 status
|= 0x00002000;
609 } else if (buf
[0] & 1) {
610 status
|= 0x00000400;
613 status
|= 0x40000000;
615 s
->rx_status_fifo
[n
] = status
;
617 if (s
->rx_status_fifo_used
> (s
->fifo_int
& 0xff)) {
618 s
->int_sts
|= RSFL_INT
;
625 static uint32_t rx_fifo_pop(lan9118_state
*s
)
630 if (s
->rxp_size
== 0 && s
->rxp_pad
== 0) {
631 s
->rxp_size
= s
->rx_packet_size
[s
->rx_packet_size_head
];
632 s
->rx_packet_size
[s
->rx_packet_size_head
] = 0;
633 if (s
->rxp_size
!= 0) {
634 s
->rx_packet_size_head
= (s
->rx_packet_size_head
+ 1023) & 1023;
635 s
->rxp_offset
= (s
->rx_cfg
>> 10) & 7;
636 n
= s
->rxp_offset
+ s
->rxp_size
;
637 switch (s
->rx_cfg
>> 30) {
649 DPRINTF("Pop packet size:%d offset:%d pad: %d\n",
650 s
->rxp_size
, s
->rxp_offset
, s
->rxp_pad
);
653 if (s
->rxp_offset
> 0) {
656 } else if (s
->rxp_size
> 0) {
658 val
= s
->rx_fifo
[s
->rx_fifo_head
++];
659 if (s
->rx_fifo_head
>= s
->rx_fifo_size
) {
660 s
->rx_fifo_head
-= s
->rx_fifo_size
;
663 } else if (s
->rxp_pad
> 0) {
667 DPRINTF("RX underflow\n");
668 s
->int_sts
|= RXE_INT
;
675 static void do_tx_packet(lan9118_state
*s
)
680 /* FIXME: Honor TX disable, and allow queueing of packets. */
681 if (s
->phy_control
& 0x4000) {
682 /* This assumes the receive routine doesn't touch the VLANClient. */
683 qemu_receive_packet(qemu_get_queue(s
->nic
), s
->txp
->data
, s
->txp
->len
);
685 qemu_send_packet(qemu_get_queue(s
->nic
), s
->txp
->data
, s
->txp
->len
);
687 s
->txp
->fifo_used
= 0;
689 if (s
->tx_status_fifo_used
== 512) {
690 /* Status FIFO full */
693 /* Add entry to status FIFO. */
694 status
= s
->txp
->cmd_b
& 0xffff0000u
;
695 DPRINTF("Sent packet tag:%04x len %d\n", status
>> 16, s
->txp
->len
);
696 n
= (s
->tx_status_fifo_head
+ s
->tx_status_fifo_used
) & 511;
697 s
->tx_status_fifo
[n
] = status
;
698 s
->tx_status_fifo_used
++;
699 if (s
->tx_status_fifo_used
== 512) {
700 s
->int_sts
|= TSFF_INT
;
701 /* TODO: Stop transmission. */
705 static uint32_t rx_status_fifo_pop(lan9118_state
*s
)
709 val
= s
->rx_status_fifo
[s
->rx_status_fifo_head
];
710 if (s
->rx_status_fifo_used
!= 0) {
711 s
->rx_status_fifo_used
--;
712 s
->rx_status_fifo_head
++;
713 if (s
->rx_status_fifo_head
>= s
->rx_status_fifo_size
) {
714 s
->rx_status_fifo_head
-= s
->rx_status_fifo_size
;
716 /* ??? What value should be returned when the FIFO is empty? */
717 DPRINTF("RX status pop 0x%08x\n", val
);
722 static uint32_t tx_status_fifo_pop(lan9118_state
*s
)
726 val
= s
->tx_status_fifo
[s
->tx_status_fifo_head
];
727 if (s
->tx_status_fifo_used
!= 0) {
728 s
->tx_status_fifo_used
--;
729 s
->tx_status_fifo_head
= (s
->tx_status_fifo_head
+ 1) & 511;
730 /* ??? What value should be returned when the FIFO is empty? */
735 static void tx_fifo_push(lan9118_state
*s
, uint32_t val
)
739 if (s
->txp
->fifo_used
== s
->tx_fifo_size
) {
740 s
->int_sts
|= TDFO_INT
;
743 switch (s
->txp
->state
) {
745 s
->txp
->cmd_a
= val
& 0x831f37ff;
747 s
->txp
->state
= TX_B
;
748 s
->txp
->buffer_size
= extract32(s
->txp
->cmd_a
, 0, 11);
749 s
->txp
->offset
= extract32(s
->txp
->cmd_a
, 16, 5);
752 if (s
->txp
->cmd_a
& 0x2000) {
756 /* End alignment does not include command words. */
757 n
= (s
->txp
->buffer_size
+ s
->txp
->offset
+ 3) >> 2;
758 switch ((n
>> 24) & 3) {
771 DPRINTF("Block len:%d offset:%d pad:%d cmd %08x\n",
772 s
->txp
->buffer_size
, s
->txp
->offset
, s
->txp
->pad
,
774 s
->txp
->state
= TX_DATA
;
777 if (s
->txp
->offset
>= 4) {
781 if (s
->txp
->buffer_size
<= 0 && s
->txp
->pad
!= 0) {
784 n
= MIN(4, s
->txp
->buffer_size
+ s
->txp
->offset
);
785 while (s
->txp
->offset
) {
790 /* Documentation is somewhat unclear on the ordering of bytes
791 in FIFO words. Empirical results show it to be little-endian.
793 /* TODO: FIFO overflow checking. */
795 s
->txp
->data
[s
->txp
->len
] = val
& 0xff;
798 s
->txp
->buffer_size
--;
802 if (s
->txp
->buffer_size
<= 0 && s
->txp
->pad
== 0) {
803 if (s
->txp
->cmd_a
& 0x1000) {
806 if (s
->txp
->cmd_a
& 0x80000000) {
807 s
->int_sts
|= TX_IOC_INT
;
809 s
->txp
->state
= TX_IDLE
;
815 static uint32_t do_phy_read(lan9118_state
*s
, int reg
)
820 case 0: /* Basic Control */
821 return s
->phy_control
;
822 case 1: /* Basic Status */
823 return s
->phy_status
;
828 case 4: /* Auto-neg advertisement */
829 return s
->phy_advertise
;
830 case 5: /* Auto-neg Link Partner Ability */
832 case 6: /* Auto-neg Expansion */
834 /* TODO 17, 18, 27, 29, 30, 31 */
835 case 29: /* Interrupt source. */
840 case 30: /* Interrupt mask */
841 return s
->phy_int_mask
;
843 BADF("PHY read reg %d\n", reg
);
848 static void do_phy_write(lan9118_state
*s
, int reg
, uint32_t val
)
851 case 0: /* Basic Control */
856 s
->phy_control
= val
& 0x7980;
857 /* Complete autonegotiation immediately. */
859 s
->phy_status
|= 0x0020;
862 case 4: /* Auto-neg advertisement */
863 s
->phy_advertise
= (val
& 0x2d7f) | 0x80;
865 /* TODO 17, 18, 27, 31 */
866 case 30: /* Interrupt mask */
867 s
->phy_int_mask
= val
& 0xff;
871 BADF("PHY write reg %d = 0x%04x\n", reg
, val
);
875 static void do_mac_write(lan9118_state
*s
, int reg
, uint32_t val
)
879 if ((s
->mac_cr
& MAC_CR_RXEN
) != 0 && (val
& MAC_CR_RXEN
) == 0) {
880 s
->int_sts
|= RXSTOP_INT
;
882 s
->mac_cr
= val
& ~MAC_CR_RESERVED
;
883 DPRINTF("MAC_CR: %08x\n", val
);
886 s
->conf
.macaddr
.a
[4] = val
& 0xff;
887 s
->conf
.macaddr
.a
[5] = (val
>> 8) & 0xff;
888 lan9118_mac_changed(s
);
891 s
->conf
.macaddr
.a
[0] = val
& 0xff;
892 s
->conf
.macaddr
.a
[1] = (val
>> 8) & 0xff;
893 s
->conf
.macaddr
.a
[2] = (val
>> 16) & 0xff;
894 s
->conf
.macaddr
.a
[3] = (val
>> 24) & 0xff;
895 lan9118_mac_changed(s
);
904 s
->mac_mii_acc
= val
& 0xffc2;
906 DPRINTF("PHY write %d = 0x%04x\n",
907 (val
>> 6) & 0x1f, s
->mac_mii_data
);
908 do_phy_write(s
, (val
>> 6) & 0x1f, s
->mac_mii_data
);
910 s
->mac_mii_data
= do_phy_read(s
, (val
>> 6) & 0x1f);
911 DPRINTF("PHY read %d = 0x%04x\n",
912 (val
>> 6) & 0x1f, s
->mac_mii_data
);
916 s
->mac_mii_data
= val
& 0xffff;
919 s
->mac_flow
= val
& 0xffff0000;
922 /* Writing to this register changes a condition for
923 * FrameTooLong bit in rx_status. Since we do not set
924 * FrameTooLong anyway, just ignore write to this.
928 qemu_log_mask(LOG_GUEST_ERROR
,
929 "lan9118: Unimplemented MAC register write: %d = 0x%x\n",
930 s
->mac_cmd
& 0xf, val
);
934 static uint32_t do_mac_read(lan9118_state
*s
, int reg
)
940 return s
->conf
.macaddr
.a
[4] | (s
->conf
.macaddr
.a
[5] << 8);
942 return s
->conf
.macaddr
.a
[0] | (s
->conf
.macaddr
.a
[1] << 8)
943 | (s
->conf
.macaddr
.a
[2] << 16) | (s
->conf
.macaddr
.a
[3] << 24);
949 return s
->mac_mii_acc
;
951 return s
->mac_mii_data
;
955 qemu_log_mask(LOG_GUEST_ERROR
,
956 "lan9118: Unimplemented MAC register read: %d\n",
962 static void lan9118_eeprom_cmd(lan9118_state
*s
, int cmd
, int addr
)
964 s
->e2p_cmd
= (s
->e2p_cmd
& E2P_CMD_MAC_ADDR_LOADED
) | (cmd
<< 28) | addr
;
967 s
->e2p_data
= s
->eeprom
[addr
];
968 DPRINTF("EEPROM Read %d = 0x%02x\n", addr
, s
->e2p_data
);
971 s
->eeprom_writable
= 0;
972 DPRINTF("EEPROM Write Disable\n");
975 s
->eeprom_writable
= 1;
976 DPRINTF("EEPROM Write Enable\n");
979 if (s
->eeprom_writable
) {
980 s
->eeprom
[addr
] &= s
->e2p_data
;
981 DPRINTF("EEPROM Write %d = 0x%02x\n", addr
, s
->e2p_data
);
983 DPRINTF("EEPROM Write %d (ignored)\n", addr
);
987 if (s
->eeprom_writable
) {
988 for (addr
= 0; addr
< 128; addr
++) {
989 s
->eeprom
[addr
] &= s
->e2p_data
;
991 DPRINTF("EEPROM Write All 0x%02x\n", s
->e2p_data
);
993 DPRINTF("EEPROM Write All (ignored)\n");
997 if (s
->eeprom_writable
) {
998 s
->eeprom
[addr
] = 0xff;
999 DPRINTF("EEPROM Erase %d\n", addr
);
1001 DPRINTF("EEPROM Erase %d (ignored)\n", addr
);
1005 if (s
->eeprom_writable
) {
1006 memset(s
->eeprom
, 0xff, 128);
1007 DPRINTF("EEPROM Erase All\n");
1009 DPRINTF("EEPROM Erase All (ignored)\n");
1012 case 7: /* RELOAD */
1013 lan9118_reload_eeprom(s
);
1018 static void lan9118_tick(void *opaque
)
1020 lan9118_state
*s
= (lan9118_state
*)opaque
;
1021 if (s
->int_en
& GPT_INT
) {
1022 s
->int_sts
|= GPT_INT
;
1027 static void lan9118_writel(void *opaque
, hwaddr offset
,
1028 uint64_t val
, unsigned size
)
1030 lan9118_state
*s
= (lan9118_state
*)opaque
;
1033 //DPRINTF("Write reg 0x%02x = 0x%08x\n", (int)offset, val);
1034 if (offset
>= TX_DATA_FIFO_PORT_FIRST
&&
1035 offset
<= TX_DATA_FIFO_PORT_LAST
) {
1037 tx_fifo_push(s
, val
);
1042 /* TODO: Implement interrupt deassertion intervals. */
1043 val
&= (IRQ_EN
| IRQ_POL
| IRQ_TYPE
);
1044 s
->irq_cfg
= (s
->irq_cfg
& IRQ_INT
) | val
;
1050 s
->int_en
= val
& ~RESERVED_INT
;
1051 s
->int_sts
|= val
& SW_INT
;
1054 DPRINTF("FIFO INT levels %08x\n", val
);
1060 s
->rx_fifo_used
= 0;
1061 s
->rx_status_fifo_used
= 0;
1062 s
->rx_packet_size_tail
= s
->rx_packet_size_head
;
1063 s
->rx_packet_size
[s
->rx_packet_size_head
] = 0;
1065 s
->rx_cfg
= val
& 0xcfff1ff0;
1069 s
->tx_status_fifo_used
= 0;
1072 s
->txp
->state
= TX_IDLE
;
1073 s
->txp
->fifo_used
= 0;
1074 s
->txp
->cmd_a
= 0xffffffff;
1076 s
->tx_cfg
= val
& 6;
1081 lan9118_reset(DEVICE(s
));
1083 s
->hw_cfg
= (val
& 0x003f300) | (s
->hw_cfg
& 0x4);
1086 case CSR_RX_DP_CTRL
:
1087 if (val
& 0x80000000) {
1088 /* Skip forward to next packet. */
1091 if (s
->rxp_size
== 0) {
1092 /* Pop a word to start the next packet. */
1097 s
->rx_fifo_head
+= s
->rxp_size
;
1098 if (s
->rx_fifo_head
>= s
->rx_fifo_size
) {
1099 s
->rx_fifo_head
-= s
->rx_fifo_size
;
1107 s
->pmt_ctrl
&= ~0x34e;
1108 s
->pmt_ctrl
|= (val
& 0x34e);
1111 /* Probably just enabling LEDs. */
1112 s
->gpio_cfg
= val
& 0x7777071f;
1115 if ((s
->gpt_cfg
^ val
) & GPT_TIMER_EN
) {
1116 ptimer_transaction_begin(s
->timer
);
1117 if (val
& GPT_TIMER_EN
) {
1118 ptimer_set_count(s
->timer
, val
& 0xffff);
1119 ptimer_run(s
->timer
, 0);
1121 ptimer_stop(s
->timer
);
1122 ptimer_set_count(s
->timer
, 0xffff);
1124 ptimer_transaction_commit(s
->timer
);
1126 s
->gpt_cfg
= val
& (GPT_TIMER_EN
| 0xffff);
1129 /* Ignored because we're in 32-bit mode. */
1132 case CSR_MAC_CSR_CMD
:
1133 s
->mac_cmd
= val
& 0x4000000f;
1134 if (val
& 0x80000000) {
1135 if (val
& 0x40000000) {
1136 s
->mac_data
= do_mac_read(s
, val
& 0xf);
1137 DPRINTF("MAC read %d = 0x%08x\n", val
& 0xf, s
->mac_data
);
1139 DPRINTF("MAC write %d = 0x%08x\n", val
& 0xf, s
->mac_data
);
1140 do_mac_write(s
, val
& 0xf, s
->mac_data
);
1144 case CSR_MAC_CSR_DATA
:
1148 s
->afc_cfg
= val
& 0x00ffffff;
1151 lan9118_eeprom_cmd(s
, (val
>> 28) & 7, val
& 0x7f);
1154 s
->e2p_data
= val
& 0xff;
1158 qemu_log_mask(LOG_GUEST_ERROR
, "lan9118_write: Bad reg 0x%x = %x\n",
1159 (int)offset
, (int)val
);
1165 static void lan9118_writew(void *opaque
, hwaddr offset
,
1168 lan9118_state
*s
= (lan9118_state
*)opaque
;
1171 if (s
->write_word_prev_offset
!= (offset
& ~0x3)) {
1172 /* New offset, reset word counter */
1173 s
->write_word_n
= 0;
1174 s
->write_word_prev_offset
= offset
& ~0x3;
1178 s
->write_word_h
= val
;
1180 s
->write_word_l
= val
;
1183 //DPRINTF("Writew reg 0x%02x = 0x%08x\n", (int)offset, val);
1185 if (s
->write_word_n
== 2) {
1186 s
->write_word_n
= 0;
1187 lan9118_writel(s
, offset
& ~3, s
->write_word_l
+
1188 (s
->write_word_h
<< 16), 4);
1192 static void lan9118_16bit_mode_write(void *opaque
, hwaddr offset
,
1193 uint64_t val
, unsigned size
)
1197 lan9118_writew(opaque
, offset
, (uint32_t)val
);
1200 lan9118_writel(opaque
, offset
, val
, size
);
1204 hw_error("lan9118_write: Bad size 0x%x\n", size
);
1207 static uint64_t lan9118_readl(void *opaque
, hwaddr offset
,
1210 lan9118_state
*s
= (lan9118_state
*)opaque
;
1212 //DPRINTF("Read reg 0x%02x\n", (int)offset);
1213 if (offset
<= RX_DATA_FIFO_PORT_LAST
) {
1215 return rx_fifo_pop(s
);
1218 case RX_STATUS_FIFO_PORT
:
1219 return rx_status_fifo_pop(s
);
1220 case RX_STATUS_FIFO_PEEK
:
1221 return s
->rx_status_fifo
[s
->rx_status_fifo_head
];
1222 case TX_STATUS_FIFO_PORT
:
1223 return tx_status_fifo_pop(s
);
1224 case TX_STATUS_FIFO_PEEK
:
1225 return s
->tx_status_fifo
[s
->tx_status_fifo_head
];
1244 case CSR_RX_DP_CTRL
:
1246 case CSR_RX_FIFO_INF
:
1247 return (s
->rx_status_fifo_used
<< 16) | (s
->rx_fifo_used
<< 2);
1248 case CSR_TX_FIFO_INF
:
1249 return (s
->tx_status_fifo_used
<< 16)
1250 | (s
->tx_fifo_size
- s
->txp
->fifo_used
);
1258 return ptimer_get_count(s
->timer
);
1260 return s
->word_swap
;
1262 return (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) / 40) - s
->free_timer_start
;
1264 /* TODO: Implement dropped frames counter. */
1266 case CSR_MAC_CSR_CMD
:
1268 case CSR_MAC_CSR_DATA
:
1277 qemu_log_mask(LOG_GUEST_ERROR
, "lan9118_read: Bad reg 0x%x\n", (int)offset
);
1281 static uint32_t lan9118_readw(void *opaque
, hwaddr offset
)
1283 lan9118_state
*s
= (lan9118_state
*)opaque
;
1286 if (s
->read_word_prev_offset
!= (offset
& ~0x3)) {
1287 /* New offset, reset word counter */
1289 s
->read_word_prev_offset
= offset
& ~0x3;
1293 if (s
->read_word_n
== 1) {
1294 s
->read_long
= lan9118_readl(s
, offset
& ~3, 4);
1300 val
= s
->read_long
>> 16;
1302 val
= s
->read_long
& 0xFFFF;
1305 //DPRINTF("Readw reg 0x%02x, val 0x%x\n", (int)offset, val);
1309 static uint64_t lan9118_16bit_mode_read(void *opaque
, hwaddr offset
,
1314 return lan9118_readw(opaque
, offset
);
1316 return lan9118_readl(opaque
, offset
, size
);
1319 hw_error("lan9118_read: Bad size 0x%x\n", size
);
1323 static const MemoryRegionOps lan9118_mem_ops
= {
1324 .read
= lan9118_readl
,
1325 .write
= lan9118_writel
,
1326 .endianness
= DEVICE_NATIVE_ENDIAN
,
1329 static const MemoryRegionOps lan9118_16bit_mem_ops
= {
1330 .read
= lan9118_16bit_mode_read
,
1331 .write
= lan9118_16bit_mode_write
,
1332 .endianness
= DEVICE_NATIVE_ENDIAN
,
1335 static NetClientInfo net_lan9118_info
= {
1336 .type
= NET_CLIENT_DRIVER_NIC
,
1337 .size
= sizeof(NICState
),
1338 .receive
= lan9118_receive
,
1339 .link_status_changed
= lan9118_set_link
,
1342 static void lan9118_realize(DeviceState
*dev
, Error
**errp
)
1344 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
1345 lan9118_state
*s
= LAN9118(dev
);
1347 const MemoryRegionOps
*mem_ops
=
1348 s
->mode_16bit
? &lan9118_16bit_mem_ops
: &lan9118_mem_ops
;
1350 memory_region_init_io(&s
->mmio
, OBJECT(dev
), mem_ops
, s
,
1351 "lan9118-mmio", 0x100);
1352 sysbus_init_mmio(sbd
, &s
->mmio
);
1353 sysbus_init_irq(sbd
, &s
->irq
);
1354 qemu_macaddr_default_if_unset(&s
->conf
.macaddr
);
1356 s
->nic
= qemu_new_nic(&net_lan9118_info
, &s
->conf
,
1357 object_get_typename(OBJECT(dev
)), dev
->id
, s
);
1358 qemu_format_nic_info_str(qemu_get_queue(s
->nic
), s
->conf
.macaddr
.a
);
1359 s
->eeprom
[0] = 0xa5;
1360 for (i
= 0; i
< 6; i
++) {
1361 s
->eeprom
[i
+ 1] = s
->conf
.macaddr
.a
[i
];
1364 s
->txp
= &s
->tx_packet
;
1366 s
->timer
= ptimer_init(lan9118_tick
, s
, PTIMER_POLICY_LEGACY
);
1367 ptimer_transaction_begin(s
->timer
);
1368 ptimer_set_freq(s
->timer
, 10000);
1369 ptimer_set_limit(s
->timer
, 0xffff, 1);
1370 ptimer_transaction_commit(s
->timer
);
1373 static Property lan9118_properties
[] = {
1374 DEFINE_NIC_PROPERTIES(lan9118_state
, conf
),
1375 DEFINE_PROP_UINT32("mode_16bit", lan9118_state
, mode_16bit
, 0),
1376 DEFINE_PROP_END_OF_LIST(),
1379 static void lan9118_class_init(ObjectClass
*klass
, void *data
)
1381 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1383 dc
->reset
= lan9118_reset
;
1384 device_class_set_props(dc
, lan9118_properties
);
1385 dc
->vmsd
= &vmstate_lan9118
;
1386 dc
->realize
= lan9118_realize
;
1389 static const TypeInfo lan9118_info
= {
1390 .name
= TYPE_LAN9118
,
1391 .parent
= TYPE_SYS_BUS_DEVICE
,
1392 .instance_size
= sizeof(lan9118_state
),
1393 .class_init
= lan9118_class_init
,
1396 static void lan9118_register_types(void)
1398 type_register_static(&lan9118_info
);
1401 /* Legacy helper function. Should go away when machine config files are
1403 void lan9118_init(NICInfo
*nd
, uint32_t base
, qemu_irq irq
)
1408 qemu_check_nic_model(nd
, "lan9118");
1409 dev
= qdev_new(TYPE_LAN9118
);
1410 qdev_set_nic_properties(dev
, nd
);
1411 s
= SYS_BUS_DEVICE(dev
);
1412 sysbus_realize_and_unref(s
, &error_fatal
);
1413 sysbus_mmio_map(s
, 0, base
);
1414 sysbus_connect_irq(s
, 0, irq
);
1417 type_init(lan9118_register_types
)