target-arm/internals.h

   1 /*
   2  * QEMU ARM CPU -- internal functions and types
   3  *
   4  * Copyright (c) 2014 Linaro Ltd
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  *
  20  * This header defines functions, types, etc which need to be shared
  21  * between different source files within target-arm/ but which are
  22  * private to it and not required by the rest of QEMU.
  23  */
  24
  25 #ifndef TARGET_ARM_INTERNALS_H
  26 #define TARGET_ARM_INTERNALS_H
  27
  28 static inline bool excp_is_internal(int excp)
  29 {
  30     /* Return true if this exception number represents a QEMU-internal
  31      * exception that will not be passed to the guest.
  32      */
  33     return excp == EXCP_INTERRUPT
  34         || excp == EXCP_HLT
  35         || excp == EXCP_DEBUG
  36         || excp == EXCP_HALTED
  37         || excp == EXCP_EXCEPTION_EXIT
  38         || excp == EXCP_KERNEL_TRAP
  39         || excp == EXCP_STREX;
  40 }
  41
  42 /* Exception names for debug logging; note that not all of these
  43  * precisely correspond to architectural exceptions.
  44  */
  45 static const char * const excnames[] = {
  46     [EXCP_UDEF] = "Undefined Instruction",
  47     [EXCP_SWI] = "SVC",
  48     [EXCP_PREFETCH_ABORT] = "Prefetch Abort",
  49     [EXCP_DATA_ABORT] = "Data Abort",
  50     [EXCP_IRQ] = "IRQ",
  51     [EXCP_FIQ] = "FIQ",
  52     [EXCP_BKPT] = "Breakpoint",
  53     [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit",
  54     [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage",
  55     [EXCP_STREX] = "QEMU intercept of STREX",
  56 };
  57
  58 static inline void arm_log_exception(int idx)
  59 {
  60     if (qemu_loglevel_mask(CPU_LOG_INT)) {
  61         const char *exc = NULL;
  62
  63         if (idx >= 0 && idx < ARRAY_SIZE(excnames)) {
  64             exc = excnames[idx];
  65         }
  66         if (!exc) {
  67             exc = "unknown";
  68         }
  69         qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s]\n", idx, exc);
  70     }
  71 }
  72
  73 /* Scale factor for generic timers, ie number of ns per tick.
  74  * This gives a 62.5MHz timer.
  75  */
  76 #define GTIMER_SCALE 16
  77
  78 int bank_number(int mode);
  79 void switch_mode(CPUARMState *, int);
  80 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu);
  81 void arm_translate_init(void);
  82
  83 enum arm_fprounding {
  84     FPROUNDING_TIEEVEN,
  85     FPROUNDING_POSINF,
  86     FPROUNDING_NEGINF,
  87     FPROUNDING_ZERO,
  88     FPROUNDING_TIEAWAY,
  89     FPROUNDING_ODD
  90 };
  91
  92 int arm_rmode_to_sf(int rmode);
  93
  94 static inline void update_spsel(CPUARMState *env, uint32_t imm)
  95 {
  96     /* Update PSTATE SPSel bit; this requires us to update the
  97      * working stack pointer in xregs[31].
  98      */
  99     if (!((imm ^ env->pstate) & PSTATE_SP)) {
 100         return;
 101     }
 102     env->pstate = deposit32(env->pstate, 0, 1, imm);
 103
 104     /* EL0 has no access rights to update SPSel, and this code
 105      * assumes we are updating SP for EL1 while running as EL1.
 106      */
 107     assert(arm_current_pl(env) == 1);
 108     if (env->pstate & PSTATE_SP) {
 109         /* Switch from using SP_EL0 to using SP_ELx */
 110         env->sp_el[0] = env->xregs[31];
 111         env->xregs[31] = env->sp_el[1];
 112     } else {
 113         /* Switch from SP_EL0 to SP_ELx */
 114         env->sp_el[1] = env->xregs[31];
 115         env->xregs[31] = env->sp_el[0];
 116     }
 117 }
 118
 119 /* Valid Syndrome Register EC field values */
 120 enum arm_exception_class {
 121     EC_UNCATEGORIZED          = 0x00,
 122     EC_WFX_TRAP               = 0x01,
 123     EC_CP15RTTRAP             = 0x03,
 124     EC_CP15RRTTRAP            = 0x04,
 125     EC_CP14RTTRAP             = 0x05,
 126     EC_CP14DTTRAP             = 0x06,
 127     EC_ADVSIMDFPACCESSTRAP    = 0x07,
 128     EC_FPIDTRAP               = 0x08,
 129     EC_CP14RRTTRAP            = 0x0c,
 130     EC_ILLEGALSTATE           = 0x0e,
 131     EC_AA32_SVC               = 0x11,
 132     EC_AA32_HVC               = 0x12,
 133     EC_AA32_SMC               = 0x13,
 134     EC_AA64_SVC               = 0x15,
 135     EC_AA64_HVC               = 0x16,
 136     EC_AA64_SMC               = 0x17,
 137     EC_SYSTEMREGISTERTRAP     = 0x18,
 138     EC_INSNABORT              = 0x20,
 139     EC_INSNABORT_SAME_EL      = 0x21,
 140     EC_PCALIGNMENT            = 0x22,
 141     EC_DATAABORT              = 0x24,
 142     EC_DATAABORT_SAME_EL      = 0x25,
 143     EC_SPALIGNMENT            = 0x26,
 144     EC_AA32_FPTRAP            = 0x28,
 145     EC_AA64_FPTRAP            = 0x2c,
 146     EC_SERROR                 = 0x2f,
 147     EC_BREAKPOINT             = 0x30,
 148     EC_BREAKPOINT_SAME_EL     = 0x31,
 149     EC_SOFTWARESTEP           = 0x32,
 150     EC_SOFTWARESTEP_SAME_EL   = 0x33,
 151     EC_WATCHPOINT             = 0x34,
 152     EC_WATCHPOINT_SAME_EL     = 0x35,
 153     EC_AA32_BKPT              = 0x38,
 154     EC_VECTORCATCH            = 0x3a,
 155     EC_AA64_BKPT              = 0x3c,
 156 };
 157
 158 #define ARM_EL_EC_SHIFT 26
 159 #define ARM_EL_IL_SHIFT 25
 160 #define ARM_EL_IL (1 << ARM_EL_IL_SHIFT)
 161
 162 /* Utility functions for constructing various kinds of syndrome value.
 163  * Note that in general we follow the AArch64 syndrome values; in a
 164  * few cases the value in HSR for exceptions taken to AArch32 Hyp
 165  * mode differs slightly, so if we ever implemented Hyp mode then the
 166  * syndrome value would need some massaging on exception entry.
 167  * (One example of this is that AArch64 defaults to IL bit set for
 168  * exceptions which don't specifically indicate information about the
 169  * trapping instruction, whereas AArch32 defaults to IL bit clear.)
 170  */
 171 static inline uint32_t syn_uncategorized(void)
 172 {
 173     return (EC_UNCATEGORIZED << ARM_EL_EC_SHIFT) | ARM_EL_IL;
 174 }
 175
 176 static inline uint32_t syn_aa64_svc(uint32_t imm16)
 177 {
 178     return (EC_AA64_SVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
 179 }
 180
 181 static inline uint32_t syn_aa32_svc(uint32_t imm16, bool is_thumb)
 182 {
 183     return (EC_AA32_SVC << ARM_EL_EC_SHIFT) | (imm16 & 0xffff)
 184         | (is_thumb ? 0 : ARM_EL_IL);
 185 }
 186
 187 static inline uint32_t syn_aa64_bkpt(uint32_t imm16)
 188 {
 189     return (EC_AA64_BKPT << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
 190 }
 191
 192 static inline uint32_t syn_aa32_bkpt(uint32_t imm16, bool is_thumb)
 193 {
 194     return (EC_AA32_BKPT << ARM_EL_EC_SHIFT) | (imm16 & 0xffff)
 195         | (is_thumb ? 0 : ARM_EL_IL);
 196 }
 197
 198 static inline uint32_t syn_aa64_sysregtrap(int op0, int op1, int op2,
 199                                            int crn, int crm, int rt,
 200                                            int isread)
 201 {
 202     return (EC_SYSTEMREGISTERTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL
 203         | (op0 << 20) | (op2 << 17) | (op1 << 14) | (crn << 10) | (rt << 5)
 204         | (crm << 1) | isread;
 205 }
 206
 207 static inline uint32_t syn_cp14_rt_trap(int cv, int cond, int opc1, int opc2,
 208                                         int crn, int crm, int rt, int isread,
 209                                         bool is_thumb)
 210 {
 211     return (EC_CP14RTTRAP << ARM_EL_EC_SHIFT)
 212         | (is_thumb ? 0 : ARM_EL_IL)
 213         | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14)
 214         | (crn << 10) | (rt << 5) | (crm << 1) | isread;
 215 }
 216
 217 static inline uint32_t syn_cp15_rt_trap(int cv, int cond, int opc1, int opc2,
 218                                         int crn, int crm, int rt, int isread,
 219                                         bool is_thumb)
 220 {
 221     return (EC_CP15RTTRAP << ARM_EL_EC_SHIFT)
 222         | (is_thumb ? 0 : ARM_EL_IL)
 223         | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14)
 224         | (crn << 10) | (rt << 5) | (crm << 1) | isread;
 225 }
 226
 227 static inline uint32_t syn_cp14_rrt_trap(int cv, int cond, int opc1, int crm,
 228                                          int rt, int rt2, int isread,
 229                                          bool is_thumb)
 230 {
 231     return (EC_CP14RRTTRAP << ARM_EL_EC_SHIFT)
 232         | (is_thumb ? 0 : ARM_EL_IL)
 233         | (cv << 24) | (cond << 20) | (opc1 << 16)
 234         | (rt2 << 10) | (rt << 5) | (crm << 1) | isread;
 235 }
 236
 237 static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int crm,
 238                                          int rt, int rt2, int isread,
 239                                          bool is_thumb)
 240 {
 241     return (EC_CP15RRTTRAP << ARM_EL_EC_SHIFT)
 242         | (is_thumb ? 0 : ARM_EL_IL)
 243         | (cv << 24) | (cond << 20) | (opc1 << 16)
 244         | (rt2 << 10) | (rt << 5) | (crm << 1) | isread;
 245 }
 246
 247 static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_thumb)
 248 {
 249     return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT)
 250         | (is_thumb ? 0 : ARM_EL_IL)
 251         | (cv << 24) | (cond << 20);
 252 }
 253
 254 static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc)
 255 {
 256     return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
 257         | (ea << 9) | (s1ptw << 7) | fsc;
 258 }
 259
 260 static inline uint32_t syn_data_abort(int same_el, int ea, int cm, int s1ptw,
 261                                       int wnr, int fsc)
 262 {
 263     return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
 264         | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc;
 265 }
 266
 267 #endif