4 * Copyright (c) 2005 Samuel Tardieu
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
28 #if !defined(CONFIG_USER_ONLY)
29 #include "hw/sh4/sh_intc.h"
32 #if defined(CONFIG_USER_ONLY)
34 void superh_cpu_do_interrupt(CPUState
*cs
)
36 cs
->exception_index
= -1;
39 int superh_cpu_handle_mmu_fault(CPUState
*cs
, vaddr address
, int rw
,
42 SuperHCPU
*cpu
= SUPERH_CPU(cs
);
43 CPUSH4State
*env
= &cpu
->env
;
46 cs
->exception_index
= -1;
49 cs
->exception_index
= 0x0a0;
52 cs
->exception_index
= 0x0c0;
55 cs
->exception_index
= 0x0a0;
61 int cpu_sh4_is_cached(CPUSH4State
* env
, target_ulong addr
)
63 /* For user mode, only U0 area is cachable. */
64 return !(addr
& 0x80000000);
67 #else /* !CONFIG_USER_ONLY */
70 #define MMU_ITLB_MISS (-1)
71 #define MMU_ITLB_MULTIPLE (-2)
72 #define MMU_ITLB_VIOLATION (-3)
73 #define MMU_DTLB_MISS_READ (-4)
74 #define MMU_DTLB_MISS_WRITE (-5)
75 #define MMU_DTLB_INITIAL_WRITE (-6)
76 #define MMU_DTLB_VIOLATION_READ (-7)
77 #define MMU_DTLB_VIOLATION_WRITE (-8)
78 #define MMU_DTLB_MULTIPLE (-9)
79 #define MMU_DTLB_MISS (-10)
80 #define MMU_IADDR_ERROR (-11)
81 #define MMU_DADDR_ERROR_READ (-12)
82 #define MMU_DADDR_ERROR_WRITE (-13)
84 void superh_cpu_do_interrupt(CPUState
*cs
)
86 SuperHCPU
*cpu
= SUPERH_CPU(cs
);
87 CPUSH4State
*env
= &cpu
->env
;
88 int do_irq
= cs
->interrupt_request
& CPU_INTERRUPT_HARD
;
89 int do_exp
, irq_vector
= cs
->exception_index
;
91 /* prioritize exceptions over interrupts */
93 do_exp
= cs
->exception_index
!= -1;
94 do_irq
= do_irq
&& (cs
->exception_index
== -1);
96 if (env
->sr
& SR_BL
) {
97 if (do_exp
&& cs
->exception_index
!= 0x1e0) {
98 cs
->exception_index
= 0x000; /* masked exception -> reset */
100 if (do_irq
&& !env
->in_sleep
) {
107 irq_vector
= sh_intc_get_pending_vector(env
->intc_handle
,
108 (env
->sr
>> 4) & 0xf);
109 if (irq_vector
== -1) {
114 if (qemu_loglevel_mask(CPU_LOG_INT
)) {
116 switch (cs
->exception_index
) {
118 expname
= "addr_error";
121 expname
= "tlb_miss";
124 expname
= "tlb_violation";
127 expname
= "illegal_instruction";
130 expname
= "slot_illegal_instruction";
133 expname
= "fpu_disable";
136 expname
= "slot_fpu";
139 expname
= "data_write";
142 expname
= "dtlb_miss_write";
145 expname
= "dtlb_violation_write";
148 expname
= "fpu_exception";
151 expname
= "initial_page_write";
157 expname
= do_irq
? "interrupt" : "???";
160 qemu_log("exception 0x%03x [%s] raised\n",
161 irq_vector
, expname
);
162 log_cpu_state(cs
, 0);
167 env
->sgr
= env
->gregs
[15];
168 env
->sr
|= SR_BL
| SR_MD
| SR_RB
;
170 if (env
->flags
& (DELAY_SLOT
| DELAY_SLOT_CONDITIONAL
)) {
171 /* Branch instruction should be executed again before delay slot. */
173 /* Clear flags for exception/interrupt routine. */
174 env
->flags
&= ~(DELAY_SLOT
| DELAY_SLOT_CONDITIONAL
| DELAY_SLOT_TRUE
);
176 if (env
->flags
& DELAY_SLOT_CLEARME
)
180 env
->expevt
= cs
->exception_index
;
181 switch (cs
->exception_index
) {
186 env
->sr
|= 0xf << 4; /* IMASK */
187 env
->pc
= 0xa0000000;
191 env
->pc
= env
->vbr
+ 0x400;
194 env
->spc
+= 2; /* special case for TRAPA */
197 env
->pc
= env
->vbr
+ 0x100;
204 env
->intevt
= irq_vector
;
205 env
->pc
= env
->vbr
+ 0x600;
210 static void update_itlb_use(CPUSH4State
* env
, int itlbnb
)
212 uint8_t or_mask
= 0, and_mask
= (uint8_t) - 1;
231 env
->mmucr
&= (and_mask
<< 24) | 0x00ffffff;
232 env
->mmucr
|= (or_mask
<< 24);
235 static int itlb_replacement(CPUSH4State
* env
)
237 SuperHCPU
*cpu
= sh_env_get_cpu(env
);
239 if ((env
->mmucr
& 0xe0000000) == 0xe0000000) {
242 if ((env
->mmucr
& 0x98000000) == 0x18000000) {
245 if ((env
->mmucr
& 0x54000000) == 0x04000000) {
248 if ((env
->mmucr
& 0x2c000000) == 0x00000000) {
251 cpu_abort(CPU(cpu
), "Unhandled itlb_replacement");
254 /* Find the corresponding entry in the right TLB
255 Return entry, MMU_DTLB_MISS or MMU_DTLB_MULTIPLE
257 static int find_tlb_entry(CPUSH4State
* env
, target_ulong address
,
258 tlb_t
* entries
, uint8_t nbtlb
, int use_asid
)
260 int match
= MMU_DTLB_MISS
;
265 asid
= env
->pteh
& 0xff;
267 for (i
= 0; i
< nbtlb
; i
++) {
269 continue; /* Invalid entry */
270 if (!entries
[i
].sh
&& use_asid
&& entries
[i
].asid
!= asid
)
271 continue; /* Bad ASID */
272 start
= (entries
[i
].vpn
<< 10) & ~(entries
[i
].size
- 1);
273 end
= start
+ entries
[i
].size
- 1;
274 if (address
>= start
&& address
<= end
) { /* Match */
275 if (match
!= MMU_DTLB_MISS
)
276 return MMU_DTLB_MULTIPLE
; /* Multiple match */
283 static void increment_urc(CPUSH4State
* env
)
288 urb
= ((env
->mmucr
) >> 18) & 0x3f;
289 urc
= ((env
->mmucr
) >> 10) & 0x3f;
291 if ((urb
> 0 && urc
> urb
) || urc
> (UTLB_SIZE
- 1))
293 env
->mmucr
= (env
->mmucr
& 0xffff03ff) | (urc
<< 10);
296 /* Copy and utlb entry into itlb
299 static int copy_utlb_entry_itlb(CPUSH4State
*env
, int utlb
)
304 itlb
= itlb_replacement(env
);
305 ientry
= &env
->itlb
[itlb
];
307 tlb_flush_page(CPU(sh_env_get_cpu(env
)), ientry
->vpn
<< 10);
309 *ientry
= env
->utlb
[utlb
];
310 update_itlb_use(env
, itlb
);
315 Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE
317 static int find_itlb_entry(CPUSH4State
* env
, target_ulong address
,
322 e
= find_tlb_entry(env
, address
, env
->itlb
, ITLB_SIZE
, use_asid
);
323 if (e
== MMU_DTLB_MULTIPLE
) {
324 e
= MMU_ITLB_MULTIPLE
;
325 } else if (e
== MMU_DTLB_MISS
) {
328 update_itlb_use(env
, e
);
334 Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */
335 static int find_utlb_entry(CPUSH4State
* env
, target_ulong address
, int use_asid
)
337 /* per utlb access */
341 return find_tlb_entry(env
, address
, env
->utlb
, UTLB_SIZE
, use_asid
);
344 /* Match address against MMU
345 Return MMU_OK, MMU_DTLB_MISS_READ, MMU_DTLB_MISS_WRITE,
346 MMU_DTLB_INITIAL_WRITE, MMU_DTLB_VIOLATION_READ,
347 MMU_DTLB_VIOLATION_WRITE, MMU_ITLB_MISS,
348 MMU_ITLB_MULTIPLE, MMU_ITLB_VIOLATION,
349 MMU_IADDR_ERROR, MMU_DADDR_ERROR_READ, MMU_DADDR_ERROR_WRITE.
351 static int get_mmu_address(CPUSH4State
* env
, target_ulong
* physical
,
352 int *prot
, target_ulong address
,
353 int rw
, int access_type
)
356 tlb_t
*matching
= NULL
;
358 use_asid
= (env
->mmucr
& MMUCR_SV
) == 0 || (env
->sr
& SR_MD
) == 0;
361 n
= find_itlb_entry(env
, address
, use_asid
);
363 matching
= &env
->itlb
[n
];
364 if (!(env
->sr
& SR_MD
) && !(matching
->pr
& 2))
365 n
= MMU_ITLB_VIOLATION
;
369 n
= find_utlb_entry(env
, address
, use_asid
);
371 n
= copy_utlb_entry_itlb(env
, n
);
372 matching
= &env
->itlb
[n
];
373 if (!(env
->sr
& SR_MD
) && !(matching
->pr
& 2)) {
374 n
= MMU_ITLB_VIOLATION
;
376 *prot
= PAGE_READ
| PAGE_EXEC
;
377 if ((matching
->pr
& 1) && matching
->d
) {
381 } else if (n
== MMU_DTLB_MULTIPLE
) {
382 n
= MMU_ITLB_MULTIPLE
;
383 } else if (n
== MMU_DTLB_MISS
) {
388 n
= find_utlb_entry(env
, address
, use_asid
);
390 matching
= &env
->utlb
[n
];
391 if (!(env
->sr
& SR_MD
) && !(matching
->pr
& 2)) {
392 n
= (rw
== 1) ? MMU_DTLB_VIOLATION_WRITE
:
393 MMU_DTLB_VIOLATION_READ
;
394 } else if ((rw
== 1) && !(matching
->pr
& 1)) {
395 n
= MMU_DTLB_VIOLATION_WRITE
;
396 } else if ((rw
== 1) && !matching
->d
) {
397 n
= MMU_DTLB_INITIAL_WRITE
;
400 if ((matching
->pr
& 1) && matching
->d
) {
404 } else if (n
== MMU_DTLB_MISS
) {
405 n
= (rw
== 1) ? MMU_DTLB_MISS_WRITE
:
411 *physical
= ((matching
->ppn
<< 10) & ~(matching
->size
- 1)) |
412 (address
& (matching
->size
- 1));
417 static int get_physical_address(CPUSH4State
* env
, target_ulong
* physical
,
418 int *prot
, target_ulong address
,
419 int rw
, int access_type
)
421 /* P1, P2 and P4 areas do not use translation */
422 if ((address
>= 0x80000000 && address
< 0xc0000000) ||
423 address
>= 0xe0000000) {
424 if (!(env
->sr
& SR_MD
)
425 && (address
< 0xe0000000 || address
>= 0xe4000000)) {
426 /* Unauthorized access in user mode (only store queues are available) */
427 fprintf(stderr
, "Unauthorized access\n");
429 return MMU_DADDR_ERROR_READ
;
431 return MMU_DADDR_ERROR_WRITE
;
433 return MMU_IADDR_ERROR
;
435 if (address
>= 0x80000000 && address
< 0xc0000000) {
436 /* Mask upper 3 bits for P1 and P2 areas */
437 *physical
= address
& 0x1fffffff;
441 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
445 /* If MMU is disabled, return the corresponding physical page */
446 if (!(env
->mmucr
& MMUCR_AT
)) {
447 *physical
= address
& 0x1FFFFFFF;
448 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
452 /* We need to resort to the MMU */
453 return get_mmu_address(env
, physical
, prot
, address
, rw
, access_type
);
456 int superh_cpu_handle_mmu_fault(CPUState
*cs
, vaddr address
, int rw
,
459 SuperHCPU
*cpu
= SUPERH_CPU(cs
);
460 CPUSH4State
*env
= &cpu
->env
;
461 target_ulong physical
;
462 int prot
, ret
, access_type
;
464 access_type
= ACCESS_INT
;
466 get_physical_address(env
, &physical
, &prot
, address
, rw
,
471 if (ret
!= MMU_DTLB_MULTIPLE
&& ret
!= MMU_ITLB_MULTIPLE
) {
472 env
->pteh
= (env
->pteh
& PTEH_ASID_MASK
) |
473 (address
& PTEH_VPN_MASK
);
477 case MMU_DTLB_MISS_READ
:
478 cs
->exception_index
= 0x040;
480 case MMU_DTLB_MULTIPLE
:
481 case MMU_ITLB_MULTIPLE
:
482 cs
->exception_index
= 0x140;
484 case MMU_ITLB_VIOLATION
:
485 cs
->exception_index
= 0x0a0;
487 case MMU_DTLB_MISS_WRITE
:
488 cs
->exception_index
= 0x060;
490 case MMU_DTLB_INITIAL_WRITE
:
491 cs
->exception_index
= 0x080;
493 case MMU_DTLB_VIOLATION_READ
:
494 cs
->exception_index
= 0x0a0;
496 case MMU_DTLB_VIOLATION_WRITE
:
497 cs
->exception_index
= 0x0c0;
499 case MMU_IADDR_ERROR
:
500 case MMU_DADDR_ERROR_READ
:
501 cs
->exception_index
= 0x0e0;
503 case MMU_DADDR_ERROR_WRITE
:
504 cs
->exception_index
= 0x100;
507 cpu_abort(cs
, "Unhandled MMU fault");
512 address
&= TARGET_PAGE_MASK
;
513 physical
&= TARGET_PAGE_MASK
;
515 tlb_set_page(cs
, address
, physical
, prot
, mmu_idx
, TARGET_PAGE_SIZE
);
519 hwaddr
superh_cpu_get_phys_page_debug(CPUState
*cs
, vaddr addr
)
521 SuperHCPU
*cpu
= SUPERH_CPU(cs
);
522 target_ulong physical
;
525 get_physical_address(&cpu
->env
, &physical
, &prot
, addr
, 0, 0);
529 void cpu_load_tlb(CPUSH4State
* env
)
531 SuperHCPU
*cpu
= sh_env_get_cpu(env
);
532 int n
= cpu_mmucr_urc(env
->mmucr
);
533 tlb_t
* entry
= &env
->utlb
[n
];
536 /* Overwriting valid entry in utlb. */
537 target_ulong address
= entry
->vpn
<< 10;
538 tlb_flush_page(CPU(cpu
), address
);
541 /* Take values into cpu status from registers. */
542 entry
->asid
= (uint8_t)cpu_pteh_asid(env
->pteh
);
543 entry
->vpn
= cpu_pteh_vpn(env
->pteh
);
544 entry
->v
= (uint8_t)cpu_ptel_v(env
->ptel
);
545 entry
->ppn
= cpu_ptel_ppn(env
->ptel
);
546 entry
->sz
= (uint8_t)cpu_ptel_sz(env
->ptel
);
549 entry
->size
= 1024; /* 1K */
552 entry
->size
= 1024 * 4; /* 4K */
555 entry
->size
= 1024 * 64; /* 64K */
558 entry
->size
= 1024 * 1024; /* 1M */
561 cpu_abort(CPU(cpu
), "Unhandled load_tlb");
564 entry
->sh
= (uint8_t)cpu_ptel_sh(env
->ptel
);
565 entry
->c
= (uint8_t)cpu_ptel_c(env
->ptel
);
566 entry
->pr
= (uint8_t)cpu_ptel_pr(env
->ptel
);
567 entry
->d
= (uint8_t)cpu_ptel_d(env
->ptel
);
568 entry
->wt
= (uint8_t)cpu_ptel_wt(env
->ptel
);
569 entry
->sa
= (uint8_t)cpu_ptea_sa(env
->ptea
);
570 entry
->tc
= (uint8_t)cpu_ptea_tc(env
->ptea
);
573 void cpu_sh4_invalidate_tlb(CPUSH4State
*s
)
578 for (i
= 0; i
< UTLB_SIZE
; i
++) {
579 tlb_t
* entry
= &s
->utlb
[i
];
583 for (i
= 0; i
< ITLB_SIZE
; i
++) {
584 tlb_t
* entry
= &s
->itlb
[i
];
588 tlb_flush(CPU(sh_env_get_cpu(s
)), 1);
591 uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State
*s
,
594 int index
= (addr
& 0x00000300) >> 8;
595 tlb_t
* entry
= &s
->itlb
[index
];
597 return (entry
->vpn
<< 10) |
602 void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State
*s
, hwaddr addr
,
605 uint32_t vpn
= (mem_value
& 0xfffffc00) >> 10;
606 uint8_t v
= (uint8_t)((mem_value
& 0x00000100) >> 8);
607 uint8_t asid
= (uint8_t)(mem_value
& 0x000000ff);
609 int index
= (addr
& 0x00000300) >> 8;
610 tlb_t
* entry
= &s
->itlb
[index
];
612 /* Overwriting valid entry in itlb. */
613 target_ulong address
= entry
->vpn
<< 10;
614 tlb_flush_page(CPU(sh_env_get_cpu(s
)), address
);
621 uint32_t cpu_sh4_read_mmaped_itlb_data(CPUSH4State
*s
,
624 int array
= (addr
& 0x00800000) >> 23;
625 int index
= (addr
& 0x00000300) >> 8;
626 tlb_t
* entry
= &s
->itlb
[index
];
629 /* ITLB Data Array 1 */
630 return (entry
->ppn
<< 10) |
633 ((entry
->sz
& 1) << 6) |
634 ((entry
->sz
& 2) << 4) |
638 /* ITLB Data Array 2 */
639 return (entry
->tc
<< 1) |
644 void cpu_sh4_write_mmaped_itlb_data(CPUSH4State
*s
, hwaddr addr
,
647 int array
= (addr
& 0x00800000) >> 23;
648 int index
= (addr
& 0x00000300) >> 8;
649 tlb_t
* entry
= &s
->itlb
[index
];
652 /* ITLB Data Array 1 */
654 /* Overwriting valid entry in utlb. */
655 target_ulong address
= entry
->vpn
<< 10;
656 tlb_flush_page(CPU(sh_env_get_cpu(s
)), address
);
658 entry
->ppn
= (mem_value
& 0x1ffffc00) >> 10;
659 entry
->v
= (mem_value
& 0x00000100) >> 8;
660 entry
->sz
= (mem_value
& 0x00000080) >> 6 |
661 (mem_value
& 0x00000010) >> 4;
662 entry
->pr
= (mem_value
& 0x00000040) >> 5;
663 entry
->c
= (mem_value
& 0x00000008) >> 3;
664 entry
->sh
= (mem_value
& 0x00000002) >> 1;
666 /* ITLB Data Array 2 */
667 entry
->tc
= (mem_value
& 0x00000008) >> 3;
668 entry
->sa
= (mem_value
& 0x00000007);
672 uint32_t cpu_sh4_read_mmaped_utlb_addr(CPUSH4State
*s
,
675 int index
= (addr
& 0x00003f00) >> 8;
676 tlb_t
* entry
= &s
->utlb
[index
];
678 increment_urc(s
); /* per utlb access */
680 return (entry
->vpn
<< 10) |
685 void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State
*s
, hwaddr addr
,
688 int associate
= addr
& 0x0000080;
689 uint32_t vpn
= (mem_value
& 0xfffffc00) >> 10;
690 uint8_t d
= (uint8_t)((mem_value
& 0x00000200) >> 9);
691 uint8_t v
= (uint8_t)((mem_value
& 0x00000100) >> 8);
692 uint8_t asid
= (uint8_t)(mem_value
& 0x000000ff);
693 int use_asid
= (s
->mmucr
& MMUCR_SV
) == 0 || (s
->sr
& SR_MD
) == 0;
697 tlb_t
* utlb_match_entry
= NULL
;
698 int needs_tlb_flush
= 0;
701 for (i
= 0; i
< UTLB_SIZE
; i
++) {
702 tlb_t
* entry
= &s
->utlb
[i
];
706 if (entry
->vpn
== vpn
707 && (!use_asid
|| entry
->asid
== asid
|| entry
->sh
)) {
708 if (utlb_match_entry
) {
709 CPUState
*cs
= CPU(sh_env_get_cpu(s
));
711 /* Multiple TLB Exception */
712 cs
->exception_index
= 0x140;
720 utlb_match_entry
= entry
;
722 increment_urc(s
); /* per utlb access */
726 for (i
= 0; i
< ITLB_SIZE
; i
++) {
727 tlb_t
* entry
= &s
->itlb
[i
];
728 if (entry
->vpn
== vpn
729 && (!use_asid
|| entry
->asid
== asid
|| entry
->sh
)) {
732 if (utlb_match_entry
)
733 *entry
= *utlb_match_entry
;
740 if (needs_tlb_flush
) {
741 tlb_flush_page(CPU(sh_env_get_cpu(s
)), vpn
<< 10);
745 int index
= (addr
& 0x00003f00) >> 8;
746 tlb_t
* entry
= &s
->utlb
[index
];
748 CPUState
*cs
= CPU(sh_env_get_cpu(s
));
750 /* Overwriting valid entry in utlb. */
751 target_ulong address
= entry
->vpn
<< 10;
752 tlb_flush_page(cs
, address
);
762 uint32_t cpu_sh4_read_mmaped_utlb_data(CPUSH4State
*s
,
765 int array
= (addr
& 0x00800000) >> 23;
766 int index
= (addr
& 0x00003f00) >> 8;
767 tlb_t
* entry
= &s
->utlb
[index
];
769 increment_urc(s
); /* per utlb access */
772 /* ITLB Data Array 1 */
773 return (entry
->ppn
<< 10) |
776 ((entry
->sz
& 1) << 6) |
777 ((entry
->sz
& 2) << 4) |
783 /* ITLB Data Array 2 */
784 return (entry
->tc
<< 1) |
789 void cpu_sh4_write_mmaped_utlb_data(CPUSH4State
*s
, hwaddr addr
,
792 int array
= (addr
& 0x00800000) >> 23;
793 int index
= (addr
& 0x00003f00) >> 8;
794 tlb_t
* entry
= &s
->utlb
[index
];
796 increment_urc(s
); /* per utlb access */
799 /* UTLB Data Array 1 */
801 /* Overwriting valid entry in utlb. */
802 target_ulong address
= entry
->vpn
<< 10;
803 tlb_flush_page(CPU(sh_env_get_cpu(s
)), address
);
805 entry
->ppn
= (mem_value
& 0x1ffffc00) >> 10;
806 entry
->v
= (mem_value
& 0x00000100) >> 8;
807 entry
->sz
= (mem_value
& 0x00000080) >> 6 |
808 (mem_value
& 0x00000010) >> 4;
809 entry
->pr
= (mem_value
& 0x00000060) >> 5;
810 entry
->c
= (mem_value
& 0x00000008) >> 3;
811 entry
->d
= (mem_value
& 0x00000004) >> 2;
812 entry
->sh
= (mem_value
& 0x00000002) >> 1;
813 entry
->wt
= (mem_value
& 0x00000001);
815 /* UTLB Data Array 2 */
816 entry
->tc
= (mem_value
& 0x00000008) >> 3;
817 entry
->sa
= (mem_value
& 0x00000007);
821 int cpu_sh4_is_cached(CPUSH4State
* env
, target_ulong addr
)
824 int use_asid
= (env
->mmucr
& MMUCR_SV
) == 0 || (env
->sr
& SR_MD
) == 0;
827 if (env
->sr
& SR_MD
) {
828 /* For previledged mode, P2 and P4 area is not cachable. */
829 if ((0xA0000000 <= addr
&& addr
< 0xC0000000) || 0xE0000000 <= addr
)
832 /* For user mode, only U0 area is cachable. */
833 if (0x80000000 <= addr
)
838 * TODO : Evaluate CCR and check if the cache is on or off.
839 * Now CCR is not in CPUSH4State, but in SH7750State.
840 * When you move the ccr into CPUSH4State, the code will be
844 /* check if operand cache is enabled or not. */
849 /* if MMU is off, no check for TLB. */
850 if (env
->mmucr
& MMUCR_AT
)
854 n
= find_tlb_entry(env
, addr
, env
->itlb
, ITLB_SIZE
, use_asid
);
856 return env
->itlb
[n
].c
;
858 n
= find_tlb_entry(env
, addr
, env
->utlb
, UTLB_SIZE
, use_asid
);
860 return env
->utlb
[n
].c
;