target-ppc/monitor.c

   1 /*
   2  * QEMU monitor
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "cpu.h"
  25 #include "monitor/monitor.h"
  26 #include "monitor/hmp-target.h"
  27 #include "hmp.h"
  28
  29 static target_long monitor_get_ccr (const struct MonitorDef *md, int val)
  30 {
  31     CPUArchState *env = mon_get_cpu_env();
  32     unsigned int u;
  33     int i;
  34
  35     u = 0;
  36     for (i = 0; i < 8; i++)
  37         u |= env->crf[i] << (32 - (4 * (i + 1)));
  38
  39     return u;
  40 }
  41
  42 static target_long monitor_get_msr (const struct MonitorDef *md, int val)
  43 {
  44     CPUArchState *env = mon_get_cpu_env();
  45     return env->msr;
  46 }
  47
  48 static target_long monitor_get_xer (const struct MonitorDef *md, int val)
  49 {
  50     CPUArchState *env = mon_get_cpu_env();
  51     return env->xer;
  52 }
  53
  54 static target_long monitor_get_decr (const struct MonitorDef *md, int val)
  55 {
  56     CPUArchState *env = mon_get_cpu_env();
  57     return cpu_ppc_load_decr(env);
  58 }
  59
  60 static target_long monitor_get_tbu (const struct MonitorDef *md, int val)
  61 {
  62     CPUArchState *env = mon_get_cpu_env();
  63     return cpu_ppc_load_tbu(env);
  64 }
  65
  66 static target_long monitor_get_tbl (const struct MonitorDef *md, int val)
  67 {
  68     CPUArchState *env = mon_get_cpu_env();
  69     return cpu_ppc_load_tbl(env);
  70 }
  71
  72 void hmp_info_tlb(Monitor *mon, const QDict *qdict)
  73 {
  74     CPUArchState *env1 = mon_get_cpu_env();
  75
  76     dump_mmu((FILE*)mon, (fprintf_function)monitor_printf, env1);
  77 }
  78
  79
  80 const MonitorDef monitor_defs[] = {
  81     /* General purpose registers */
  82     { "r0", offsetof(CPUPPCState, gpr[0]) },
  83     { "r1", offsetof(CPUPPCState, gpr[1]) },
  84     { "r2", offsetof(CPUPPCState, gpr[2]) },
  85     { "r3", offsetof(CPUPPCState, gpr[3]) },
  86     { "r4", offsetof(CPUPPCState, gpr[4]) },
  87     { "r5", offsetof(CPUPPCState, gpr[5]) },
  88     { "r6", offsetof(CPUPPCState, gpr[6]) },
  89     { "r7", offsetof(CPUPPCState, gpr[7]) },
  90     { "r8", offsetof(CPUPPCState, gpr[8]) },
  91     { "r9", offsetof(CPUPPCState, gpr[9]) },
  92     { "r10", offsetof(CPUPPCState, gpr[10]) },
  93     { "r11", offsetof(CPUPPCState, gpr[11]) },
  94     { "r12", offsetof(CPUPPCState, gpr[12]) },
  95     { "r13", offsetof(CPUPPCState, gpr[13]) },
  96     { "r14", offsetof(CPUPPCState, gpr[14]) },
  97     { "r15", offsetof(CPUPPCState, gpr[15]) },
  98     { "r16", offsetof(CPUPPCState, gpr[16]) },
  99     { "r17", offsetof(CPUPPCState, gpr[17]) },
 100     { "r18", offsetof(CPUPPCState, gpr[18]) },
 101     { "r19", offsetof(CPUPPCState, gpr[19]) },
 102     { "r20", offsetof(CPUPPCState, gpr[20]) },
 103     { "r21", offsetof(CPUPPCState, gpr[21]) },
 104     { "r22", offsetof(CPUPPCState, gpr[22]) },
 105     { "r23", offsetof(CPUPPCState, gpr[23]) },
 106     { "r24", offsetof(CPUPPCState, gpr[24]) },
 107     { "r25", offsetof(CPUPPCState, gpr[25]) },
 108     { "r26", offsetof(CPUPPCState, gpr[26]) },
 109     { "r27", offsetof(CPUPPCState, gpr[27]) },
 110     { "r28", offsetof(CPUPPCState, gpr[28]) },
 111     { "r29", offsetof(CPUPPCState, gpr[29]) },
 112     { "r30", offsetof(CPUPPCState, gpr[30]) },
 113     { "r31", offsetof(CPUPPCState, gpr[31]) },
 114     /* Floating point registers */
 115     { "f0", offsetof(CPUPPCState, fpr[0]) },
 116     { "f1", offsetof(CPUPPCState, fpr[1]) },
 117     { "f2", offsetof(CPUPPCState, fpr[2]) },
 118     { "f3", offsetof(CPUPPCState, fpr[3]) },
 119     { "f4", offsetof(CPUPPCState, fpr[4]) },
 120     { "f5", offsetof(CPUPPCState, fpr[5]) },
 121     { "f6", offsetof(CPUPPCState, fpr[6]) },
 122     { "f7", offsetof(CPUPPCState, fpr[7]) },
 123     { "f8", offsetof(CPUPPCState, fpr[8]) },
 124     { "f9", offsetof(CPUPPCState, fpr[9]) },
 125     { "f10", offsetof(CPUPPCState, fpr[10]) },
 126     { "f11", offsetof(CPUPPCState, fpr[11]) },
 127     { "f12", offsetof(CPUPPCState, fpr[12]) },
 128     { "f13", offsetof(CPUPPCState, fpr[13]) },
 129     { "f14", offsetof(CPUPPCState, fpr[14]) },
 130     { "f15", offsetof(CPUPPCState, fpr[15]) },
 131     { "f16", offsetof(CPUPPCState, fpr[16]) },
 132     { "f17", offsetof(CPUPPCState, fpr[17]) },
 133     { "f18", offsetof(CPUPPCState, fpr[18]) },
 134     { "f19", offsetof(CPUPPCState, fpr[19]) },
 135     { "f20", offsetof(CPUPPCState, fpr[20]) },
 136     { "f21", offsetof(CPUPPCState, fpr[21]) },
 137     { "f22", offsetof(CPUPPCState, fpr[22]) },
 138     { "f23", offsetof(CPUPPCState, fpr[23]) },
 139     { "f24", offsetof(CPUPPCState, fpr[24]) },
 140     { "f25", offsetof(CPUPPCState, fpr[25]) },
 141     { "f26", offsetof(CPUPPCState, fpr[26]) },
 142     { "f27", offsetof(CPUPPCState, fpr[27]) },
 143     { "f28", offsetof(CPUPPCState, fpr[28]) },
 144     { "f29", offsetof(CPUPPCState, fpr[29]) },
 145     { "f30", offsetof(CPUPPCState, fpr[30]) },
 146     { "f31", offsetof(CPUPPCState, fpr[31]) },
 147     { "fpscr", offsetof(CPUPPCState, fpscr) },
 148     /* Next instruction pointer */
 149     { "nip|pc", offsetof(CPUPPCState, nip) },
 150     { "lr", offsetof(CPUPPCState, lr) },
 151     { "ctr", offsetof(CPUPPCState, ctr) },
 152     { "decr", 0, &monitor_get_decr, },
 153     { "ccr", 0, &monitor_get_ccr, },
 154     /* Machine state register */
 155     { "msr", 0, &monitor_get_msr, },
 156     { "xer", 0, &monitor_get_xer, },
 157     { "tbu", 0, &monitor_get_tbu, },
 158     { "tbl", 0, &monitor_get_tbl, },
 159     /* Segment registers */
 160     { "sdr1", offsetof(CPUPPCState, spr[SPR_SDR1]) },
 161     { "sr0", offsetof(CPUPPCState, sr[0]) },
 162     { "sr1", offsetof(CPUPPCState, sr[1]) },
 163     { "sr2", offsetof(CPUPPCState, sr[2]) },
 164     { "sr3", offsetof(CPUPPCState, sr[3]) },
 165     { "sr4", offsetof(CPUPPCState, sr[4]) },
 166     { "sr5", offsetof(CPUPPCState, sr[5]) },
 167     { "sr6", offsetof(CPUPPCState, sr[6]) },
 168     { "sr7", offsetof(CPUPPCState, sr[7]) },
 169     { "sr8", offsetof(CPUPPCState, sr[8]) },
 170     { "sr9", offsetof(CPUPPCState, sr[9]) },
 171     { "sr10", offsetof(CPUPPCState, sr[10]) },
 172     { "sr11", offsetof(CPUPPCState, sr[11]) },
 173     { "sr12", offsetof(CPUPPCState, sr[12]) },
 174     { "sr13", offsetof(CPUPPCState, sr[13]) },
 175     { "sr14", offsetof(CPUPPCState, sr[14]) },
 176     { "sr15", offsetof(CPUPPCState, sr[15]) },
 177     /* Too lazy to put BATs... */
 178     { "pvr", offsetof(CPUPPCState, spr[SPR_PVR]) },
 179
 180     { "srr0", offsetof(CPUPPCState, spr[SPR_SRR0]) },
 181     { "srr1", offsetof(CPUPPCState, spr[SPR_SRR1]) },
 182     { "dar", offsetof(CPUPPCState, spr[SPR_DAR]) },
 183     { "dsisr", offsetof(CPUPPCState, spr[SPR_DSISR]) },
 184     { "cfar", offsetof(CPUPPCState, spr[SPR_CFAR]) },
 185     { "sprg0", offsetof(CPUPPCState, spr[SPR_SPRG0]) },
 186     { "sprg1", offsetof(CPUPPCState, spr[SPR_SPRG1]) },
 187     { "sprg2", offsetof(CPUPPCState, spr[SPR_SPRG2]) },
 188     { "sprg3", offsetof(CPUPPCState, spr[SPR_SPRG3]) },
 189     { "sprg4", offsetof(CPUPPCState, spr[SPR_SPRG4]) },
 190     { "sprg5", offsetof(CPUPPCState, spr[SPR_SPRG5]) },
 191     { "sprg6", offsetof(CPUPPCState, spr[SPR_SPRG6]) },
 192     { "sprg7", offsetof(CPUPPCState, spr[SPR_SPRG7]) },
 193     { "pid", offsetof(CPUPPCState, spr[SPR_BOOKE_PID]) },
 194     { "csrr0", offsetof(CPUPPCState, spr[SPR_BOOKE_CSRR0]) },
 195     { "csrr1", offsetof(CPUPPCState, spr[SPR_BOOKE_CSRR1]) },
 196     { "esr", offsetof(CPUPPCState, spr[SPR_BOOKE_ESR]) },
 197     { "dear", offsetof(CPUPPCState, spr[SPR_BOOKE_DEAR]) },
 198     { "mcsr", offsetof(CPUPPCState, spr[SPR_BOOKE_MCSR]) },
 199     { "tsr", offsetof(CPUPPCState, spr[SPR_BOOKE_TSR]) },
 200     { "tcr", offsetof(CPUPPCState, spr[SPR_BOOKE_TCR]) },
 201     { "vrsave", offsetof(CPUPPCState, spr[SPR_VRSAVE]) },
 202     { "pir", offsetof(CPUPPCState, spr[SPR_BOOKE_PIR]) },
 203     { "mcsrr0", offsetof(CPUPPCState, spr[SPR_BOOKE_MCSRR0]) },
 204     { "mcsrr1", offsetof(CPUPPCState, spr[SPR_BOOKE_MCSRR1]) },
 205     { "decar", offsetof(CPUPPCState, spr[SPR_BOOKE_DECAR]) },
 206     { "ivpr", offsetof(CPUPPCState, spr[SPR_BOOKE_IVPR]) },
 207     { "epcr", offsetof(CPUPPCState, spr[SPR_BOOKE_EPCR]) },
 208     { "sprg8", offsetof(CPUPPCState, spr[SPR_BOOKE_SPRG8]) },
 209     { "ivor0", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR0]) },
 210     { "ivor1", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR1]) },
 211     { "ivor2", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR2]) },
 212     { "ivor3", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR3]) },
 213     { "ivor4", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR4]) },
 214     { "ivor5", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR5]) },
 215     { "ivor6", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR6]) },
 216     { "ivor7", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR7]) },
 217     { "ivor8", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR8]) },
 218     { "ivor9", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR9]) },
 219     { "ivor10", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR10]) },
 220     { "ivor11", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR11]) },
 221     { "ivor12", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR12]) },
 222     { "ivor13", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR13]) },
 223     { "ivor14", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR14]) },
 224     { "ivor15", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR15]) },
 225     { "ivor32", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR32]) },
 226     { "ivor33", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR33]) },
 227     { "ivor34", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR34]) },
 228     { "ivor35", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR35]) },
 229     { "ivor36", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR36]) },
 230     { "ivor37", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR37]) },
 231     { "mas0", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS0]) },
 232     { "mas1", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS1]) },
 233     { "mas2", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS2]) },
 234     { "mas3", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS3]) },
 235     { "mas4", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS4]) },
 236     { "mas6", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS6]) },
 237     { "mas7", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS7]) },
 238     { "mmucfg", offsetof(CPUPPCState, spr[SPR_MMUCFG]) },
 239     { "tlb0cfg", offsetof(CPUPPCState, spr[SPR_BOOKE_TLB0CFG]) },
 240     { "tlb1cfg", offsetof(CPUPPCState, spr[SPR_BOOKE_TLB1CFG]) },
 241     { "epr", offsetof(CPUPPCState, spr[SPR_BOOKE_EPR]) },
 242     { "eplc", offsetof(CPUPPCState, spr[SPR_BOOKE_EPLC]) },
 243     { "epsc", offsetof(CPUPPCState, spr[SPR_BOOKE_EPSC]) },
 244     { "svr", offsetof(CPUPPCState, spr[SPR_E500_SVR]) },
 245     { "mcar", offsetof(CPUPPCState, spr[SPR_Exxx_MCAR]) },
 246     { "pid1", offsetof(CPUPPCState, spr[SPR_BOOKE_PID1]) },
 247     { "pid2", offsetof(CPUPPCState, spr[SPR_BOOKE_PID2]) },
 248     { "hid0", offsetof(CPUPPCState, spr[SPR_HID0]) },
 249     { NULL },
 250 };
 251
 252 const MonitorDef *target_monitor_defs(void)
 253 {
 254     return monitor_defs;
 255 }