hw/pc.h

   1 #ifndef HW_PC_H
   2 #define HW_PC_H
   3
   4 #include "qemu-common.h"
   5 #include "memory.h"
   6 #include "ioport.h"
   7 #include "isa.h"
   8 #include "fdc.h"
   9 #include "net.h"
  10 #include "memory.h"
  11 #include "ioapic.h"
  12
  13 /* PC-style peripherals (also used by other machines).  */
  14
  15 /* serial.c */
  16
  17 SerialState *serial_init(int base, qemu_irq irq, int baudbase,
  18                          CharDriverState *chr);
  19 SerialState *serial_mm_init(MemoryRegion *address_space,
  20                             target_phys_addr_t base, int it_shift,
  21                             qemu_irq irq, int baudbase,
  22                             CharDriverState *chr, enum device_endian);
  23 static inline bool serial_isa_init(int index, CharDriverState *chr)
  24 {
  25     ISADevice *dev;
  26
  27     dev = isa_try_create("isa-serial");
  28     if (!dev) {
  29         return false;
  30     }
  31     qdev_prop_set_uint32(&dev->qdev, "index", index);
  32     qdev_prop_set_chr(&dev->qdev, "chardev", chr);
  33     if (qdev_init(&dev->qdev) < 0) {
  34         return false;
  35     }
  36     return true;
  37 }
  38
  39 void serial_set_frequency(SerialState *s, uint32_t frequency);
  40
  41 /* parallel.c */
  42 static inline bool parallel_init(int index, CharDriverState *chr)
  43 {
  44     ISADevice *dev;
  45
  46     dev = isa_try_create("isa-parallel");
  47     if (!dev) {
  48         return false;
  49     }
  50     qdev_prop_set_uint32(&dev->qdev, "index", index);
  51     qdev_prop_set_chr(&dev->qdev, "chardev", chr);
  52     if (qdev_init(&dev->qdev) < 0) {
  53         return false;
  54     }
  55     return true;
  56 }
  57
  58 bool parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq,
  59                       CharDriverState *chr);
  60
  61 /* i8259.c */
  62
  63 typedef struct PicState PicState;
  64 extern PicState *isa_pic;
  65 qemu_irq *i8259_init(qemu_irq parent_irq);
  66 int pic_read_irq(PicState *s);
  67 int pic_get_output(PicState *s);
  68 void pic_info(Monitor *mon);
  69 void irq_info(Monitor *mon);
  70
  71 /* Global System Interrupts */
  72
  73 #define GSI_NUM_PINS IOAPIC_NUM_PINS
  74
  75 typedef struct GSIState {
  76     qemu_irq i8259_irq[ISA_NUM_IRQS];
  77     qemu_irq ioapic_irq[IOAPIC_NUM_PINS];
  78 } GSIState;
  79
  80 void gsi_handler(void *opaque, int n, int level);
  81
  82 /* i8254.c */
  83
  84 #define PIT_FREQ 1193182
  85
  86 static inline ISADevice *pit_init(int base, int irq)
  87 {
  88     ISADevice *dev;
  89
  90     dev = isa_create("isa-pit");
  91     qdev_prop_set_uint32(&dev->qdev, "iobase", base);
  92     qdev_prop_set_uint32(&dev->qdev, "irq", irq);
  93     qdev_init_nofail(&dev->qdev);
  94
  95     return dev;
  96 }
  97
  98 void pit_set_gate(ISADevice *dev, int channel, int val);
  99 int pit_get_gate(ISADevice *dev, int channel);
 100 int pit_get_initial_count(ISADevice *dev, int channel);
 101 int pit_get_mode(ISADevice *dev, int channel);
 102 int pit_get_out(ISADevice *dev, int channel, int64_t current_time);
 103
 104 void hpet_pit_disable(void);
 105 void hpet_pit_enable(void);
 106
 107 /* vmport.c */
 108 static inline void vmport_init(void)
 109 {
 110     isa_create_simple("vmport");
 111 }
 112 void vmport_register(unsigned char command, IOPortReadFunc *func, void *opaque);
 113 void vmmouse_get_data(uint32_t *data);
 114 void vmmouse_set_data(const uint32_t *data);
 115
 116 /* pckbd.c */
 117
 118 void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
 119 void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
 120                    MemoryRegion *region, ram_addr_t size,
 121                    target_phys_addr_t mask);
 122 void i8042_isa_mouse_fake_event(void *opaque);
 123 void i8042_setup_a20_line(ISADevice *dev, qemu_irq *a20_out);
 124
 125 /* pc.c */
 126 extern int fd_bootchk;
 127
 128 void pc_register_ferr_irq(qemu_irq irq);
 129 void pc_cmos_set_s3_resume(void *opaque, int irq, int level);
 130 void pc_acpi_smi_interrupt(void *opaque, int irq, int level);
 131
 132 void pc_cpus_init(const char *cpu_model);
 133 void pc_memory_init(MemoryRegion *system_memory,
 134                     const char *kernel_filename,
 135                     const char *kernel_cmdline,
 136                     const char *initrd_filename,
 137                     ram_addr_t below_4g_mem_size,
 138                     ram_addr_t above_4g_mem_size,
 139                     MemoryRegion *rom_memory,
 140                     MemoryRegion **ram_memory);
 141 qemu_irq *pc_allocate_cpu_irq(void);
 142 void pc_vga_init(PCIBus *pci_bus);
 143 void pc_basic_device_init(qemu_irq *gsi,
 144                           ISADevice **rtc_state,
 145                           bool no_vmport);
 146 void pc_init_ne2k_isa(NICInfo *nd);
 147 void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
 148                   const char *boot_device,
 149                   BusState *ide0, BusState *ide1,
 150                   ISADevice *s);
 151 void pc_pci_device_init(PCIBus *pci_bus);
 152
 153 typedef void (*cpu_set_smm_t)(int smm, void *arg);
 154 void cpu_smm_register(cpu_set_smm_t callback, void *arg);
 155
 156 /* acpi.c */
 157 extern int acpi_enabled;
 158 extern char *acpi_tables;
 159 extern size_t acpi_tables_len;
 160
 161 void acpi_bios_init(void);
 162 int acpi_table_add(const char *table_desc);
 163
 164 /* acpi_piix.c */
 165
 166 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 167                        qemu_irq sci_irq, qemu_irq cmos_s3, qemu_irq smi_irq,
 168                        int kvm_enabled);
 169 void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
 170
 171 /* hpet.c */
 172 extern int no_hpet;
 173
 174 /* pcspk.c */
 175 void pcspk_init(ISADevice *pit);
 176 int pcspk_audio_init(qemu_irq *pic);
 177
 178 /* piix_pci.c */
 179 struct PCII440FXState;
 180 typedef struct PCII440FXState PCII440FXState;
 181
 182 PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix_devfn,
 183                     qemu_irq *pic,
 184                     MemoryRegion *address_space_mem,
 185                     MemoryRegion *address_space_io,
 186                     ram_addr_t ram_size,
 187                     target_phys_addr_t pci_hole_start,
 188                     target_phys_addr_t pci_hole_size,
 189                     target_phys_addr_t pci_hole64_start,
 190                     target_phys_addr_t pci_hole64_size,
 191                     MemoryRegion *pci_memory,
 192                     MemoryRegion *ram_memory);
 193
 194 /* piix4.c */
 195 extern PCIDevice *piix4_dev;
 196 int piix4_init(PCIBus *bus, int devfn);
 197
 198 /* vga.c */
 199 enum vga_retrace_method {
 200     VGA_RETRACE_DUMB,
 201     VGA_RETRACE_PRECISE
 202 };
 203
 204 extern enum vga_retrace_method vga_retrace_method;
 205
 206 static inline int isa_vga_init(void)
 207 {
 208     ISADevice *dev;
 209
 210     dev = isa_try_create("isa-vga");
 211     if (!dev) {
 212         fprintf(stderr, "Warning: isa-vga not available\n");
 213         return 0;
 214     }
 215     qdev_init_nofail(&dev->qdev);
 216     return 1;
 217 }
 218
 219 int pci_vga_init(PCIBus *bus);
 220 int isa_vga_mm_init(target_phys_addr_t vram_base,
 221                     target_phys_addr_t ctrl_base, int it_shift,
 222                     MemoryRegion *address_space);
 223
 224 /* cirrus_vga.c */
 225 void pci_cirrus_vga_init(PCIBus *bus);
 226 void isa_cirrus_vga_init(MemoryRegion *address_space);
 227
 228 /* ne2000.c */
 229 static inline bool isa_ne2000_init(int base, int irq, NICInfo *nd)
 230 {
 231     ISADevice *dev;
 232
 233     qemu_check_nic_model(nd, "ne2k_isa");
 234
 235     dev = isa_try_create("ne2k_isa");
 236     if (!dev) {
 237         return false;
 238     }
 239     qdev_prop_set_uint32(&dev->qdev, "iobase", base);
 240     qdev_prop_set_uint32(&dev->qdev, "irq",    irq);
 241     qdev_set_nic_properties(&dev->qdev, nd);
 242     qdev_init_nofail(&dev->qdev);
 243     return true;
 244 }
 245
 246 /* e820 types */
 247 #define E820_RAM        1
 248 #define E820_RESERVED   2
 249 #define E820_ACPI       3
 250 #define E820_NVS        4
 251 #define E820_UNUSABLE   5
 252
 253 int e820_add_entry(uint64_t, uint64_t, uint32_t);
 254
 255 #endif