target-openrisc/sys_helper.c

   1 /*
   2  * OpenRISC system instructions helper routines
   3  *
   4  * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
   5  *                         Zhizhou Zhang <etouzh@gmail.com>
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "cpu.h"
  23 #include "exec/helper-proto.h"
  24
  25 #define TO_SPR(group, number) (((group) << 11) + (number))
  26
  27 void HELPER(mtspr)(CPUOpenRISCState *env,
  28                    target_ulong ra, target_ulong rb, target_ulong offset)
  29 {
  30 #ifndef CONFIG_USER_ONLY
  31     int spr = (ra | offset);
  32     int idx;
  33
  34     OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
  35     CPUState *cs = CPU(cpu);
  36
  37     switch (spr) {
  38     case TO_SPR(0, 0): /* VR */
  39         env->vr = rb;
  40         break;
  41
  42     case TO_SPR(0, 16): /* NPC */
  43         env->npc = rb;
  44         break;
  45
  46     case TO_SPR(0, 17): /* SR */
  47         if ((env->sr & (SR_IME | SR_DME | SR_SM)) ^
  48             (rb & (SR_IME | SR_DME | SR_SM))) {
  49             tlb_flush(cs, 1);
  50         }
  51         env->sr = rb;
  52         env->sr |= SR_FO;      /* FO is const equal to 1 */
  53         if (env->sr & SR_DME) {
  54             env->tlb->cpu_openrisc_map_address_data =
  55                 &cpu_openrisc_get_phys_data;
  56         } else {
  57             env->tlb->cpu_openrisc_map_address_data =
  58                 &cpu_openrisc_get_phys_nommu;
  59         }
  60
  61         if (env->sr & SR_IME) {
  62             env->tlb->cpu_openrisc_map_address_code =
  63                 &cpu_openrisc_get_phys_code;
  64         } else {
  65             env->tlb->cpu_openrisc_map_address_code =
  66                 &cpu_openrisc_get_phys_nommu;
  67         }
  68         break;
  69
  70     case TO_SPR(0, 18): /* PPC */
  71         env->ppc = rb;
  72         break;
  73
  74     case TO_SPR(0, 32): /* EPCR */
  75         env->epcr = rb;
  76         break;
  77
  78     case TO_SPR(0, 48): /* EEAR */
  79         env->eear = rb;
  80         break;
  81
  82     case TO_SPR(0, 64): /* ESR */
  83         env->esr = rb;
  84         break;
  85     case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */
  86         idx = spr - TO_SPR(1, 512);
  87         if (!(rb & 1)) {
  88             tlb_flush_page(cs, env->tlb->dtlb[0][idx].mr & TARGET_PAGE_MASK);
  89         }
  90         env->tlb->dtlb[0][idx].mr = rb;
  91         break;
  92
  93     case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */
  94         idx = spr - TO_SPR(1, 640);
  95         env->tlb->dtlb[0][idx].tr = rb;
  96         break;
  97     case TO_SPR(1, 768) ... TO_SPR(1, 895):   /* DTLBW1MR 0-127 */
  98     case TO_SPR(1, 896) ... TO_SPR(1, 1023):  /* DTLBW1TR 0-127 */
  99     case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */
 100     case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */
 101     case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */
 102     case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */
 103         break;
 104     case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1):   /* ITLBW0MR 0-127 */
 105         idx = spr - TO_SPR(2, 512);
 106         if (!(rb & 1)) {
 107             tlb_flush_page(cs, env->tlb->itlb[0][idx].mr & TARGET_PAGE_MASK);
 108         }
 109         env->tlb->itlb[0][idx].mr = rb;
 110         break;
 111
 112     case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */
 113         idx = spr - TO_SPR(2, 640);
 114         env->tlb->itlb[0][idx].tr = rb;
 115         break;
 116     case TO_SPR(2, 768) ... TO_SPR(2, 895):   /* ITLBW1MR 0-127 */
 117     case TO_SPR(2, 896) ... TO_SPR(2, 1023):  /* ITLBW1TR 0-127 */
 118     case TO_SPR(2, 1024) ... TO_SPR(2, 1151): /* ITLBW2MR 0-127 */
 119     case TO_SPR(2, 1152) ... TO_SPR(2, 1279): /* ITLBW2TR 0-127 */
 120     case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */
 121     case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */
 122         break;
 123     case TO_SPR(9, 0):  /* PICMR */
 124         env->picmr |= rb;
 125         break;
 126     case TO_SPR(9, 2):  /* PICSR */
 127         env->picsr &= ~rb;
 128         break;
 129     case TO_SPR(10, 0): /* TTMR */
 130         {
 131             if ((env->ttmr & TTMR_M) ^ (rb & TTMR_M)) {
 132                 switch (rb & TTMR_M) {
 133                 case TIMER_NONE:
 134                     cpu_openrisc_count_stop(cpu);
 135                     break;
 136                 case TIMER_INTR:
 137                 case TIMER_SHOT:
 138                 case TIMER_CONT:
 139                     cpu_openrisc_count_start(cpu);
 140                     break;
 141                 default:
 142                     break;
 143                 }
 144             }
 145
 146             int ip = env->ttmr & TTMR_IP;
 147
 148             if (rb & TTMR_IP) {    /* Keep IP bit.  */
 149                 env->ttmr = (rb & ~TTMR_IP) | ip;
 150             } else {    /* Clear IP bit.  */
 151                 env->ttmr = rb & ~TTMR_IP;
 152                 cs->interrupt_request &= ~CPU_INTERRUPT_TIMER;
 153             }
 154
 155             cpu_openrisc_timer_update(cpu);
 156         }
 157         break;
 158
 159     case TO_SPR(10, 1): /* TTCR */
 160         env->ttcr = rb;
 161         if (env->ttmr & TIMER_NONE) {
 162             return;
 163         }
 164         cpu_openrisc_timer_update(cpu);
 165         break;
 166     default:
 167
 168         break;
 169     }
 170 #endif
 171 }
 172
 173 target_ulong HELPER(mfspr)(CPUOpenRISCState *env,
 174                            target_ulong rd, target_ulong ra, uint32_t offset)
 175 {
 176 #ifndef CONFIG_USER_ONLY
 177     int spr = (ra | offset);
 178     int idx;
 179
 180     OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
 181
 182     switch (spr) {
 183     case TO_SPR(0, 0): /* VR */
 184         return env->vr & SPR_VR;
 185
 186     case TO_SPR(0, 1): /* UPR */
 187         return env->upr;    /* TT, DM, IM, UP present */
 188
 189     case TO_SPR(0, 2): /* CPUCFGR */
 190         return env->cpucfgr;
 191
 192     case TO_SPR(0, 3): /* DMMUCFGR */
 193         return env->dmmucfgr;    /* 1Way, 64 entries */
 194
 195     case TO_SPR(0, 4): /* IMMUCFGR */
 196         return env->immucfgr;
 197
 198     case TO_SPR(0, 16): /* NPC */
 199         return env->npc;
 200
 201     case TO_SPR(0, 17): /* SR */
 202         return env->sr;
 203
 204     case TO_SPR(0, 18): /* PPC */
 205         return env->ppc;
 206
 207     case TO_SPR(0, 32): /* EPCR */
 208         return env->epcr;
 209
 210     case TO_SPR(0, 48): /* EEAR */
 211         return env->eear;
 212
 213     case TO_SPR(0, 64): /* ESR */
 214         return env->esr;
 215
 216     case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */
 217         idx = spr - TO_SPR(1, 512);
 218         return env->tlb->dtlb[0][idx].mr;
 219
 220     case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */
 221         idx = spr - TO_SPR(1, 640);
 222         return env->tlb->dtlb[0][idx].tr;
 223
 224     case TO_SPR(1, 768) ... TO_SPR(1, 895):   /* DTLBW1MR 0-127 */
 225     case TO_SPR(1, 896) ... TO_SPR(1, 1023):  /* DTLBW1TR 0-127 */
 226     case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */
 227     case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */
 228     case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */
 229     case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */
 230         break;
 231
 232     case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 */
 233         idx = spr - TO_SPR(2, 512);
 234         return env->tlb->itlb[0][idx].mr;
 235
 236     case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */
 237         idx = spr - TO_SPR(2, 640);
 238         return env->tlb->itlb[0][idx].tr;
 239
 240     case TO_SPR(2, 768) ... TO_SPR(2, 895):   /* ITLBW1MR 0-127 */
 241     case TO_SPR(2, 896) ... TO_SPR(2, 1023):  /* ITLBW1TR 0-127 */
 242     case TO_SPR(2, 1024) ... TO_SPR(2, 1151): /* ITLBW2MR 0-127 */
 243     case TO_SPR(2, 1152) ... TO_SPR(2, 1279): /* ITLBW2TR 0-127 */
 244     case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */
 245     case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */
 246         break;
 247
 248     case TO_SPR(9, 0):  /* PICMR */
 249         return env->picmr;
 250
 251     case TO_SPR(9, 2):  /* PICSR */
 252         return env->picsr;
 253
 254     case TO_SPR(10, 0): /* TTMR */
 255         return env->ttmr;
 256
 257     case TO_SPR(10, 1): /* TTCR */
 258         cpu_openrisc_count_update(cpu);
 259         return env->ttcr;
 260
 261     default:
 262         break;
 263     }
 264 #endif
 265
 266 /*If we later need to add tracepoints (or debug printfs) for the return
 267 value, it may be useful to structure the code like this:
 268
 269 target_ulong ret = 0;
 270
 271 switch() {
 272 case x:
 273  ret = y;
 274  break;
 275 case z:
 276  ret = 42;
 277  break;
 278 ...
 279 }
 280
 281 later something like trace_spr_read(ret);
 282
 283 return ret;*/
 284
 285     /* for rd is passed in, if rd unchanged, just keep it back.  */
 286     return rd;
 287 }