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target/ppc: optimize gen_write_xer()
[qemu.git] / target / ppc / translate.c
blobb09e16ff769270937c7afc71c9e849532b9f89f2
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "internal.h"
24 #include "disas/disas.h"
25 #include "exec/exec-all.h"
26 #include "tcg-op.h"
27 #include "qemu/host-utils.h"
28 #include "exec/cpu_ldst.h"
29
30 #include "exec/helper-proto.h"
31 #include "exec/helper-gen.h"
32
33 #include "trace-tcg.h"
34 #include "exec/log.h"
35
36
37 #define CPU_SINGLE_STEP 0x1
38 #define CPU_BRANCH_STEP 0x2
39 #define GDBSTUB_SINGLE_STEP 0x4
40
41 /* Include definitions for instructions classes and implementations flags */
42 //#define PPC_DEBUG_DISAS
43 //#define DO_PPC_STATISTICS
44
45 #ifdef PPC_DEBUG_DISAS
46 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
47 #else
48 # define LOG_DISAS(...) do { } while (0)
49 #endif
50 /*****************************************************************************/
51 /* Code translation helpers */
52
53 /* global register indexes */
54 static TCGv_env cpu_env;
55 static char cpu_reg_names[10*3 + 22*4 /* GPR */
56 + 10*4 + 22*5 /* SPE GPRh */
57 + 10*4 + 22*5 /* FPR */
58 + 2*(10*6 + 22*7) /* AVRh, AVRl */
59 + 10*5 + 22*6 /* VSR */
60 + 8*5 /* CRF */];
61 static TCGv cpu_gpr[32];
62 static TCGv cpu_gprh[32];
63 static TCGv_i64 cpu_fpr[32];
64 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
65 static TCGv_i64 cpu_vsr[32];
66 static TCGv_i32 cpu_crf[8];
67 static TCGv cpu_nip;
68 static TCGv cpu_msr;
69 static TCGv cpu_ctr;
70 static TCGv cpu_lr;
71 #if defined(TARGET_PPC64)
72 static TCGv cpu_cfar;
73 #endif
74 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
75 static TCGv cpu_reserve;
76 static TCGv cpu_fpscr;
77 static TCGv_i32 cpu_access_type;
78
79 #include "exec/gen-icount.h"
80
81 void ppc_translate_init(void)
82 {
83 int i;
84 char* p;
85 size_t cpu_reg_names_size;
86 static int done_init = 0;
87
88 if (done_init)
89 return;
90
91 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
92 tcg_ctx.tcg_env = cpu_env;
93
94 p = cpu_reg_names;
95 cpu_reg_names_size = sizeof(cpu_reg_names);
96
97 for (i = 0; i < 8; i++) {
98 snprintf(p, cpu_reg_names_size, "crf%d", i);
99 cpu_crf[i] = tcg_global_mem_new_i32(cpu_env,
100 offsetof(CPUPPCState, crf[i]), p);
101 p += 5;
102 cpu_reg_names_size -= 5;
103 }
104
105 for (i = 0; i < 32; i++) {
106 snprintf(p, cpu_reg_names_size, "r%d", i);
107 cpu_gpr[i] = tcg_global_mem_new(cpu_env,
108 offsetof(CPUPPCState, gpr[i]), p);
109 p += (i < 10) ? 3 : 4;
110 cpu_reg_names_size -= (i < 10) ? 3 : 4;
111 snprintf(p, cpu_reg_names_size, "r%dH", i);
112 cpu_gprh[i] = tcg_global_mem_new(cpu_env,
113 offsetof(CPUPPCState, gprh[i]), p);
114 p += (i < 10) ? 4 : 5;
115 cpu_reg_names_size -= (i < 10) ? 4 : 5;
116
117 snprintf(p, cpu_reg_names_size, "fp%d", i);
118 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
119 offsetof(CPUPPCState, fpr[i]), p);
120 p += (i < 10) ? 4 : 5;
121 cpu_reg_names_size -= (i < 10) ? 4 : 5;
122
123 snprintf(p, cpu_reg_names_size, "avr%dH", i);
124 #ifdef HOST_WORDS_BIGENDIAN
125 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
126 offsetof(CPUPPCState, avr[i].u64[0]), p);
127 #else
128 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
129 offsetof(CPUPPCState, avr[i].u64[1]), p);
130 #endif
131 p += (i < 10) ? 6 : 7;
132 cpu_reg_names_size -= (i < 10) ? 6 : 7;
133
134 snprintf(p, cpu_reg_names_size, "avr%dL", i);
135 #ifdef HOST_WORDS_BIGENDIAN
136 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
137 offsetof(CPUPPCState, avr[i].u64[1]), p);
138 #else
139 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
140 offsetof(CPUPPCState, avr[i].u64[0]), p);
141 #endif
142 p += (i < 10) ? 6 : 7;
143 cpu_reg_names_size -= (i < 10) ? 6 : 7;
144 snprintf(p, cpu_reg_names_size, "vsr%d", i);
145 cpu_vsr[i] = tcg_global_mem_new_i64(cpu_env,
146 offsetof(CPUPPCState, vsr[i]), p);
147 p += (i < 10) ? 5 : 6;
148 cpu_reg_names_size -= (i < 10) ? 5 : 6;
149 }
150
151 cpu_nip = tcg_global_mem_new(cpu_env,
152 offsetof(CPUPPCState, nip), "nip");
153
154 cpu_msr = tcg_global_mem_new(cpu_env,
155 offsetof(CPUPPCState, msr), "msr");
156
157 cpu_ctr = tcg_global_mem_new(cpu_env,
158 offsetof(CPUPPCState, ctr), "ctr");
159
160 cpu_lr = tcg_global_mem_new(cpu_env,
161 offsetof(CPUPPCState, lr), "lr");
162
163 #if defined(TARGET_PPC64)
164 cpu_cfar = tcg_global_mem_new(cpu_env,
165 offsetof(CPUPPCState, cfar), "cfar");
166 #endif
167
168 cpu_xer = tcg_global_mem_new(cpu_env,
169 offsetof(CPUPPCState, xer), "xer");
170 cpu_so = tcg_global_mem_new(cpu_env,
171 offsetof(CPUPPCState, so), "SO");
172 cpu_ov = tcg_global_mem_new(cpu_env,
173 offsetof(CPUPPCState, ov), "OV");
174 cpu_ca = tcg_global_mem_new(cpu_env,
175 offsetof(CPUPPCState, ca), "CA");
176
177 cpu_reserve = tcg_global_mem_new(cpu_env,
178 offsetof(CPUPPCState, reserve_addr),
179 "reserve_addr");
180
181 cpu_fpscr = tcg_global_mem_new(cpu_env,
182 offsetof(CPUPPCState, fpscr), "fpscr");
183
184 cpu_access_type = tcg_global_mem_new_i32(cpu_env,
185 offsetof(CPUPPCState, access_type), "access_type");
186
187 done_init = 1;
188 }
189
190 /* internal defines */
191 struct DisasContext {
192 struct TranslationBlock *tb;
193 target_ulong nip;
194 uint32_t opcode;
195 uint32_t exception;
196 /* Routine used to access memory */
197 bool pr, hv, dr, le_mode;
198 bool lazy_tlb_flush;
199 bool need_access_type;
200 int mem_idx;
201 int access_type;
202 /* Translation flags */
203 TCGMemOp default_tcg_memop_mask;
204 #if defined(TARGET_PPC64)
205 bool sf_mode;
206 bool has_cfar;
207 #endif
208 bool fpu_enabled;
209 bool altivec_enabled;
210 bool vsx_enabled;
211 bool spe_enabled;
212 bool tm_enabled;
213 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
214 int singlestep_enabled;
215 uint64_t insns_flags;
216 uint64_t insns_flags2;
217 };
218
219 /* Return true iff byteswap is needed in a scalar memop */
220 static inline bool need_byteswap(const DisasContext *ctx)
221 {
222 #if defined(TARGET_WORDS_BIGENDIAN)
223 return ctx->le_mode;
224 #else
225 return !ctx->le_mode;
226 #endif
227 }
228
229 /* True when active word size < size of target_long. */
230 #ifdef TARGET_PPC64
231 # define NARROW_MODE(C) (!(C)->sf_mode)
232 #else
233 # define NARROW_MODE(C) 0
234 #endif
235
236 struct opc_handler_t {
237 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
238 uint32_t inval1;
239 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
240 uint32_t inval2;
241 /* instruction type */
242 uint64_t type;
243 /* extended instruction type */
244 uint64_t type2;
245 /* handler */
246 void (*handler)(DisasContext *ctx);
247 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
248 const char *oname;
249 #endif
250 #if defined(DO_PPC_STATISTICS)
251 uint64_t count;
252 #endif
253 };
254
255 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
256 {
257 if (ctx->need_access_type && ctx->access_type != access_type) {
258 tcg_gen_movi_i32(cpu_access_type, access_type);
259 ctx->access_type = access_type;
260 }
261 }
262
263 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
264 {
265 if (NARROW_MODE(ctx)) {
266 nip = (uint32_t)nip;
267 }
268 tcg_gen_movi_tl(cpu_nip, nip);
269 }
270
271 static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
272 {
273 TCGv_i32 t0, t1;
274
275 /* These are all synchronous exceptions, we set the PC back to
276 * the faulting instruction
277 */
278 if (ctx->exception == POWERPC_EXCP_NONE) {
279 gen_update_nip(ctx, ctx->nip - 4);
280 }
281 t0 = tcg_const_i32(excp);
282 t1 = tcg_const_i32(error);
283 gen_helper_raise_exception_err(cpu_env, t0, t1);
284 tcg_temp_free_i32(t0);
285 tcg_temp_free_i32(t1);
286 ctx->exception = (excp);
287 }
288
289 static void gen_exception(DisasContext *ctx, uint32_t excp)
290 {
291 TCGv_i32 t0;
292
293 /* These are all synchronous exceptions, we set the PC back to
294 * the faulting instruction
295 */
296 if (ctx->exception == POWERPC_EXCP_NONE) {
297 gen_update_nip(ctx, ctx->nip - 4);
298 }
299 t0 = tcg_const_i32(excp);
300 gen_helper_raise_exception(cpu_env, t0);
301 tcg_temp_free_i32(t0);
302 ctx->exception = (excp);
303 }
304
305 static void gen_exception_nip(DisasContext *ctx, uint32_t excp,
306 target_ulong nip)
307 {
308 TCGv_i32 t0;
309
310 gen_update_nip(ctx, nip);
311 t0 = tcg_const_i32(excp);
312 gen_helper_raise_exception(cpu_env, t0);
313 tcg_temp_free_i32(t0);
314 ctx->exception = (excp);
315 }
316
317 static void gen_debug_exception(DisasContext *ctx)
318 {
319 TCGv_i32 t0;
320
321 /* These are all synchronous exceptions, we set the PC back to
322 * the faulting instruction
323 */
324 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
325 (ctx->exception != POWERPC_EXCP_SYNC)) {
326 gen_update_nip(ctx, ctx->nip);
327 }
328 t0 = tcg_const_i32(EXCP_DEBUG);
329 gen_helper_raise_exception(cpu_env, t0);
330 tcg_temp_free_i32(t0);
331 }
332
333 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
334 {
335 /* Will be converted to program check if needed */
336 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error);
337 }
338
339 static inline void gen_priv_exception(DisasContext *ctx, uint32_t error)
340 {
341 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error);
342 }
343
344 static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error)
345 {
346 /* Will be converted to program check if needed */
347 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error);
348 }
349
350 /* Stop translation */
351 static inline void gen_stop_exception(DisasContext *ctx)
352 {
353 gen_update_nip(ctx, ctx->nip);
354 ctx->exception = POWERPC_EXCP_STOP;
355 }
356
357 #ifndef CONFIG_USER_ONLY
358 /* No need to update nip here, as execution flow will change */
359 static inline void gen_sync_exception(DisasContext *ctx)
360 {
361 ctx->exception = POWERPC_EXCP_SYNC;
362 }
363 #endif
364
365 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
366 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
367
368 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
369 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
370
371 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
372 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
373
374 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
375 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
376
377 #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \
378 GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2)
379
380 #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \
381 GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2)
382
383 typedef struct opcode_t {
384 unsigned char opc1, opc2, opc3, opc4;
385 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
386 unsigned char pad[4];
387 #endif
388 opc_handler_t handler;
389 const char *oname;
390 } opcode_t;
391
392 /* Helpers for priv. check */
393 #define GEN_PRIV \
394 do { \
395 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \
396 } while (0)
397
398 #if defined(CONFIG_USER_ONLY)
399 #define CHK_HV GEN_PRIV
400 #define CHK_SV GEN_PRIV
401 #define CHK_HVRM GEN_PRIV
402 #else
403 #define CHK_HV \
404 do { \
405 if (unlikely(ctx->pr || !ctx->hv)) { \
406 GEN_PRIV; \
407 } \
408 } while (0)
409 #define CHK_SV \
410 do { \
411 if (unlikely(ctx->pr)) { \
412 GEN_PRIV; \
413 } \
414 } while (0)
415 #define CHK_HVRM \
416 do { \
417 if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \
418 GEN_PRIV; \
419 } \
420 } while (0)
421 #endif
422
423 #define CHK_NONE
424
425 /*****************************************************************************/
426 /* PowerPC instructions table */
427
428 #if defined(DO_PPC_STATISTICS)
429 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
430 { \
431 .opc1 = op1, \
432 .opc2 = op2, \
433 .opc3 = op3, \
434 .opc4 = 0xff, \
435 .handler = { \
436 .inval1 = invl, \
437 .type = _typ, \
438 .type2 = _typ2, \
439 .handler = &gen_##name, \
440 .oname = stringify(name), \
441 }, \
442 .oname = stringify(name), \
443 }
444 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
445 { \
446 .opc1 = op1, \
447 .opc2 = op2, \
448 .opc3 = op3, \
449 .opc4 = 0xff, \
450 .handler = { \
451 .inval1 = invl1, \
452 .inval2 = invl2, \
453 .type = _typ, \
454 .type2 = _typ2, \
455 .handler = &gen_##name, \
456 .oname = stringify(name), \
457 }, \
458 .oname = stringify(name), \
459 }
460 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
461 { \
462 .opc1 = op1, \
463 .opc2 = op2, \
464 .opc3 = op3, \
465 .opc4 = 0xff, \
466 .handler = { \
467 .inval1 = invl, \
468 .type = _typ, \
469 .type2 = _typ2, \
470 .handler = &gen_##name, \
471 .oname = onam, \
472 }, \
473 .oname = onam, \
474 }
475 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
476 { \
477 .opc1 = op1, \
478 .opc2 = op2, \
479 .opc3 = op3, \
480 .opc4 = op4, \
481 .handler = { \
482 .inval1 = invl, \
483 .type = _typ, \
484 .type2 = _typ2, \
485 .handler = &gen_##name, \
486 .oname = stringify(name), \
487 }, \
488 .oname = stringify(name), \
489 }
490 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \
491 { \
492 .opc1 = op1, \
493 .opc2 = op2, \
494 .opc3 = op3, \
495 .opc4 = op4, \
496 .handler = { \
497 .inval1 = invl, \
498 .type = _typ, \
499 .type2 = _typ2, \
500 .handler = &gen_##name, \
501 .oname = onam, \
502 }, \
503 .oname = onam, \
504 }
505 #else
506 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
507 { \
508 .opc1 = op1, \
509 .opc2 = op2, \
510 .opc3 = op3, \
511 .opc4 = 0xff, \
512 .handler = { \
513 .inval1 = invl, \
514 .type = _typ, \
515 .type2 = _typ2, \
516 .handler = &gen_##name, \
517 }, \
518 .oname = stringify(name), \
519 }
520 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
521 { \
522 .opc1 = op1, \
523 .opc2 = op2, \
524 .opc3 = op3, \
525 .opc4 = 0xff, \
526 .handler = { \
527 .inval1 = invl1, \
528 .inval2 = invl2, \
529 .type = _typ, \
530 .type2 = _typ2, \
531 .handler = &gen_##name, \
532 }, \
533 .oname = stringify(name), \
534 }
535 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
536 { \
537 .opc1 = op1, \
538 .opc2 = op2, \
539 .opc3 = op3, \
540 .opc4 = 0xff, \
541 .handler = { \
542 .inval1 = invl, \
543 .type = _typ, \
544 .type2 = _typ2, \
545 .handler = &gen_##name, \
546 }, \
547 .oname = onam, \
548 }
549 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
550 { \
551 .opc1 = op1, \
552 .opc2 = op2, \
553 .opc3 = op3, \
554 .opc4 = op4, \
555 .handler = { \
556 .inval1 = invl, \
557 .type = _typ, \
558 .type2 = _typ2, \
559 .handler = &gen_##name, \
560 }, \
561 .oname = stringify(name), \
562 }
563 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \
564 { \
565 .opc1 = op1, \
566 .opc2 = op2, \
567 .opc3 = op3, \
568 .opc4 = op4, \
569 .handler = { \
570 .inval1 = invl, \
571 .type = _typ, \
572 .type2 = _typ2, \
573 .handler = &gen_##name, \
574 }, \
575 .oname = onam, \
576 }
577 #endif
578
579 /* SPR load/store helpers */
580 static inline void gen_load_spr(TCGv t, int reg)
581 {
582 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
583 }
584
585 static inline void gen_store_spr(int reg, TCGv t)
586 {
587 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
588 }
589
590 /* Invalid instruction */
591 static void gen_invalid(DisasContext *ctx)
592 {
593 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
594 }
595
596 static opc_handler_t invalid_handler = {
597 .inval1 = 0xFFFFFFFF,
598 .inval2 = 0xFFFFFFFF,
599 .type = PPC_NONE,
600 .type2 = PPC_NONE,
601 .handler = gen_invalid,
602 };
603
604 /*** Integer comparison ***/
605
606 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
607 {
608 TCGv t0 = tcg_temp_new();
609 TCGv_i32 t1 = tcg_temp_new_i32();
610
611 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
612
613 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
614 tcg_gen_trunc_tl_i32(t1, t0);
615 tcg_gen_shli_i32(t1, t1, CRF_LT_BIT);
616 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
617
618 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
619 tcg_gen_trunc_tl_i32(t1, t0);
620 tcg_gen_shli_i32(t1, t1, CRF_GT_BIT);
621 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
622
623 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
624 tcg_gen_trunc_tl_i32(t1, t0);
625 tcg_gen_shli_i32(t1, t1, CRF_EQ_BIT);
626 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
627
628 tcg_temp_free(t0);
629 tcg_temp_free_i32(t1);
630 }
631
632 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
633 {
634 TCGv t0 = tcg_const_tl(arg1);
635 gen_op_cmp(arg0, t0, s, crf);
636 tcg_temp_free(t0);
637 }
638
639 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
640 {
641 TCGv t0, t1;
642 t0 = tcg_temp_new();
643 t1 = tcg_temp_new();
644 if (s) {
645 tcg_gen_ext32s_tl(t0, arg0);
646 tcg_gen_ext32s_tl(t1, arg1);
647 } else {
648 tcg_gen_ext32u_tl(t0, arg0);
649 tcg_gen_ext32u_tl(t1, arg1);
650 }
651 gen_op_cmp(t0, t1, s, crf);
652 tcg_temp_free(t1);
653 tcg_temp_free(t0);
654 }
655
656 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
657 {
658 TCGv t0 = tcg_const_tl(arg1);
659 gen_op_cmp32(arg0, t0, s, crf);
660 tcg_temp_free(t0);
661 }
662
663 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
664 {
665 if (NARROW_MODE(ctx)) {
666 gen_op_cmpi32(reg, 0, 1, 0);
667 } else {
668 gen_op_cmpi(reg, 0, 1, 0);
669 }
670 }
671
672 /* cmp */
673 static void gen_cmp(DisasContext *ctx)
674 {
675 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
676 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
677 1, crfD(ctx->opcode));
678 } else {
679 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
680 1, crfD(ctx->opcode));
681 }
682 }
683
684 /* cmpi */
685 static void gen_cmpi(DisasContext *ctx)
686 {
687 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
688 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
689 1, crfD(ctx->opcode));
690 } else {
691 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
692 1, crfD(ctx->opcode));
693 }
694 }
695
696 /* cmpl */
697 static void gen_cmpl(DisasContext *ctx)
698 {
699 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
700 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
701 0, crfD(ctx->opcode));
702 } else {
703 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
704 0, crfD(ctx->opcode));
705 }
706 }
707
708 /* cmpli */
709 static void gen_cmpli(DisasContext *ctx)
710 {
711 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
712 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
713 0, crfD(ctx->opcode));
714 } else {
715 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
716 0, crfD(ctx->opcode));
717 }
718 }
719
720 /* cmprb - range comparison: isupper, isaplha, islower*/
721 static void gen_cmprb(DisasContext *ctx)
722 {
723 TCGv_i32 src1 = tcg_temp_new_i32();
724 TCGv_i32 src2 = tcg_temp_new_i32();
725 TCGv_i32 src2lo = tcg_temp_new_i32();
726 TCGv_i32 src2hi = tcg_temp_new_i32();
727 TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)];
728
729 tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]);
730 tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]);
731
732 tcg_gen_andi_i32(src1, src1, 0xFF);
733 tcg_gen_ext8u_i32(src2lo, src2);
734 tcg_gen_shri_i32(src2, src2, 8);
735 tcg_gen_ext8u_i32(src2hi, src2);
736
737 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
738 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
739 tcg_gen_and_i32(crf, src2lo, src2hi);
740
741 if (ctx->opcode & 0x00200000) {
742 tcg_gen_shri_i32(src2, src2, 8);
743 tcg_gen_ext8u_i32(src2lo, src2);
744 tcg_gen_shri_i32(src2, src2, 8);
745 tcg_gen_ext8u_i32(src2hi, src2);
746 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
747 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
748 tcg_gen_and_i32(src2lo, src2lo, src2hi);
749 tcg_gen_or_i32(crf, crf, src2lo);
750 }
751 tcg_gen_shli_i32(crf, crf, CRF_GT_BIT);
752 tcg_temp_free_i32(src1);
753 tcg_temp_free_i32(src2);
754 tcg_temp_free_i32(src2lo);
755 tcg_temp_free_i32(src2hi);
756 }
757
758 #if defined(TARGET_PPC64)
759 /* cmpeqb */
760 static void gen_cmpeqb(DisasContext *ctx)
761 {
762 gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
763 cpu_gpr[rB(ctx->opcode)]);
764 }
765 #endif
766
767 /* isel (PowerPC 2.03 specification) */
768 static void gen_isel(DisasContext *ctx)
769 {
770 uint32_t bi = rC(ctx->opcode);
771 uint32_t mask = 0x08 >> (bi & 0x03);
772 TCGv t0 = tcg_temp_new();
773 TCGv zr;
774
775 tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]);
776 tcg_gen_andi_tl(t0, t0, mask);
777
778 zr = tcg_const_tl(0);
779 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr,
780 rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr,
781 cpu_gpr[rB(ctx->opcode)]);
782 tcg_temp_free(zr);
783 tcg_temp_free(t0);
784 }
785
786 /* cmpb: PowerPC 2.05 specification */
787 static void gen_cmpb(DisasContext *ctx)
788 {
789 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
790 cpu_gpr[rB(ctx->opcode)]);
791 }
792
793 /*** Integer arithmetic ***/
794
795 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
796 TCGv arg1, TCGv arg2, int sub)
797 {
798 TCGv t0 = tcg_temp_new();
799
800 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
801 tcg_gen_xor_tl(t0, arg1, arg2);
802 if (sub) {
803 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
804 } else {
805 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
806 }
807 tcg_temp_free(t0);
808 if (NARROW_MODE(ctx)) {
809 tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
810 }
811 tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
812 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
813 }
814
815 /* Common add function */
816 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
817 TCGv arg2, bool add_ca, bool compute_ca,
818 bool compute_ov, bool compute_rc0)
819 {
820 TCGv t0 = ret;
821
822 if (compute_ca || compute_ov) {
823 t0 = tcg_temp_new();
824 }
825
826 if (compute_ca) {
827 if (NARROW_MODE(ctx)) {
828 /* Caution: a non-obvious corner case of the spec is that we
829 must produce the *entire* 64-bit addition, but produce the
830 carry into bit 32. */
831 TCGv t1 = tcg_temp_new();
832 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
833 tcg_gen_add_tl(t0, arg1, arg2);
834 if (add_ca) {
835 tcg_gen_add_tl(t0, t0, cpu_ca);
836 }
837 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
838 tcg_temp_free(t1);
839 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
840 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
841 } else {
842 TCGv zero = tcg_const_tl(0);
843 if (add_ca) {
844 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
845 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
846 } else {
847 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
848 }
849 tcg_temp_free(zero);
850 }
851 } else {
852 tcg_gen_add_tl(t0, arg1, arg2);
853 if (add_ca) {
854 tcg_gen_add_tl(t0, t0, cpu_ca);
855 }
856 }
857
858 if (compute_ov) {
859 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
860 }
861 if (unlikely(compute_rc0)) {
862 gen_set_Rc0(ctx, t0);
863 }
864
865 if (!TCGV_EQUAL(t0, ret)) {
866 tcg_gen_mov_tl(ret, t0);
867 tcg_temp_free(t0);
868 }
869 }
870 /* Add functions with two operands */
871 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
872 static void glue(gen_, name)(DisasContext *ctx) \
873 { \
874 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
875 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
876 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
877 }
878 /* Add functions with one operand and one immediate */
879 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
880 add_ca, compute_ca, compute_ov) \
881 static void glue(gen_, name)(DisasContext *ctx) \
882 { \
883 TCGv t0 = tcg_const_tl(const_val); \
884 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
885 cpu_gpr[rA(ctx->opcode)], t0, \
886 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
887 tcg_temp_free(t0); \
888 }
889
890 /* add add. addo addo. */
891 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
892 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
893 /* addc addc. addco addco. */
894 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
895 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
896 /* adde adde. addeo addeo. */
897 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
898 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
899 /* addme addme. addmeo addmeo. */
900 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
901 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
902 /* addze addze. addzeo addzeo.*/
903 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
904 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
905 /* addi */
906 static void gen_addi(DisasContext *ctx)
907 {
908 target_long simm = SIMM(ctx->opcode);
909
910 if (rA(ctx->opcode) == 0) {
911 /* li case */
912 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
913 } else {
914 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
915 cpu_gpr[rA(ctx->opcode)], simm);
916 }
917 }
918 /* addic addic.*/
919 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
920 {
921 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
922 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
923 c, 0, 1, 0, compute_rc0);
924 tcg_temp_free(c);
925 }
926
927 static void gen_addic(DisasContext *ctx)
928 {
929 gen_op_addic(ctx, 0);
930 }
931
932 static void gen_addic_(DisasContext *ctx)
933 {
934 gen_op_addic(ctx, 1);
935 }
936
937 /* addis */
938 static void gen_addis(DisasContext *ctx)
939 {
940 target_long simm = SIMM(ctx->opcode);
941
942 if (rA(ctx->opcode) == 0) {
943 /* lis case */
944 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
945 } else {
946 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
947 cpu_gpr[rA(ctx->opcode)], simm << 16);
948 }
949 }
950
951 /* addpcis */
952 static void gen_addpcis(DisasContext *ctx)
953 {
954 target_long d = DX(ctx->opcode);
955
956 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->nip + (d << 16));
957 }
958
959 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
960 TCGv arg2, int sign, int compute_ov)
961 {
962 TCGv_i32 t0 = tcg_temp_new_i32();
963 TCGv_i32 t1 = tcg_temp_new_i32();
964 TCGv_i32 t2 = tcg_temp_new_i32();
965 TCGv_i32 t3 = tcg_temp_new_i32();
966
967 tcg_gen_trunc_tl_i32(t0, arg1);
968 tcg_gen_trunc_tl_i32(t1, arg2);
969 if (sign) {
970 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN);
971 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1);
972 tcg_gen_and_i32(t2, t2, t3);
973 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0);
974 tcg_gen_or_i32(t2, t2, t3);
975 tcg_gen_movi_i32(t3, 0);
976 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
977 tcg_gen_div_i32(t3, t0, t1);
978 tcg_gen_extu_i32_tl(ret, t3);
979 } else {
980 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0);
981 tcg_gen_movi_i32(t3, 0);
982 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
983 tcg_gen_divu_i32(t3, t0, t1);
984 tcg_gen_extu_i32_tl(ret, t3);
985 }
986 if (compute_ov) {
987 tcg_gen_extu_i32_tl(cpu_ov, t2);
988 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
989 }
990 tcg_temp_free_i32(t0);
991 tcg_temp_free_i32(t1);
992 tcg_temp_free_i32(t2);
993 tcg_temp_free_i32(t3);
994
995 if (unlikely(Rc(ctx->opcode) != 0))
996 gen_set_Rc0(ctx, ret);
997 }
998 /* Div functions */
999 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1000 static void glue(gen_, name)(DisasContext *ctx) \
1001 { \
1002 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1003 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1004 sign, compute_ov); \
1005 }
1006 /* divwu divwu. divwuo divwuo. */
1007 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1008 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1009 /* divw divw. divwo divwo. */
1010 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1011 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1012
1013 /* div[wd]eu[o][.] */
1014 #define GEN_DIVE(name, hlpr, compute_ov) \
1015 static void gen_##name(DisasContext *ctx) \
1016 { \
1017 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1018 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1019 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1020 tcg_temp_free_i32(t0); \
1021 if (unlikely(Rc(ctx->opcode) != 0)) { \
1022 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1023 } \
1024 }
1025
1026 GEN_DIVE(divweu, divweu, 0);
1027 GEN_DIVE(divweuo, divweu, 1);
1028 GEN_DIVE(divwe, divwe, 0);
1029 GEN_DIVE(divweo, divwe, 1);
1030
1031 #if defined(TARGET_PPC64)
1032 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1033 TCGv arg2, int sign, int compute_ov)
1034 {
1035 TCGv_i64 t0 = tcg_temp_new_i64();
1036 TCGv_i64 t1 = tcg_temp_new_i64();
1037 TCGv_i64 t2 = tcg_temp_new_i64();
1038 TCGv_i64 t3 = tcg_temp_new_i64();
1039
1040 tcg_gen_mov_i64(t0, arg1);
1041 tcg_gen_mov_i64(t1, arg2);
1042 if (sign) {
1043 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN);
1044 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1);
1045 tcg_gen_and_i64(t2, t2, t3);
1046 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0);
1047 tcg_gen_or_i64(t2, t2, t3);
1048 tcg_gen_movi_i64(t3, 0);
1049 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1050 tcg_gen_div_i64(ret, t0, t1);
1051 } else {
1052 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0);
1053 tcg_gen_movi_i64(t3, 0);
1054 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1055 tcg_gen_divu_i64(ret, t0, t1);
1056 }
1057 if (compute_ov) {
1058 tcg_gen_mov_tl(cpu_ov, t2);
1059 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1060 }
1061 tcg_temp_free_i64(t0);
1062 tcg_temp_free_i64(t1);
1063 tcg_temp_free_i64(t2);
1064 tcg_temp_free_i64(t3);
1065
1066 if (unlikely(Rc(ctx->opcode) != 0))
1067 gen_set_Rc0(ctx, ret);
1068 }
1069
1070 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1071 static void glue(gen_, name)(DisasContext *ctx) \
1072 { \
1073 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1074 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1075 sign, compute_ov); \
1076 }
1077 /* divwu divwu. divwuo divwuo. */
1078 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1079 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1080 /* divw divw. divwo divwo. */
1081 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1082 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1083
1084 GEN_DIVE(divdeu, divdeu, 0);
1085 GEN_DIVE(divdeuo, divdeu, 1);
1086 GEN_DIVE(divde, divde, 0);
1087 GEN_DIVE(divdeo, divde, 1);
1088 #endif
1089
1090 static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1,
1091 TCGv arg2, int sign)
1092 {
1093 TCGv_i32 t0 = tcg_temp_new_i32();
1094 TCGv_i32 t1 = tcg_temp_new_i32();
1095
1096 tcg_gen_trunc_tl_i32(t0, arg1);
1097 tcg_gen_trunc_tl_i32(t1, arg2);
1098 if (sign) {
1099 TCGv_i32 t2 = tcg_temp_new_i32();
1100 TCGv_i32 t3 = tcg_temp_new_i32();
1101 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN);
1102 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1);
1103 tcg_gen_and_i32(t2, t2, t3);
1104 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0);
1105 tcg_gen_or_i32(t2, t2, t3);
1106 tcg_gen_movi_i32(t3, 0);
1107 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1108 tcg_gen_rem_i32(t3, t0, t1);
1109 tcg_gen_ext_i32_tl(ret, t3);
1110 tcg_temp_free_i32(t2);
1111 tcg_temp_free_i32(t3);
1112 } else {
1113 TCGv_i32 t2 = tcg_const_i32(1);
1114 TCGv_i32 t3 = tcg_const_i32(0);
1115 tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1);
1116 tcg_gen_remu_i32(t3, t0, t1);
1117 tcg_gen_extu_i32_tl(ret, t3);
1118 tcg_temp_free_i32(t2);
1119 tcg_temp_free_i32(t3);
1120 }
1121 tcg_temp_free_i32(t0);
1122 tcg_temp_free_i32(t1);
1123 }
1124
1125 #define GEN_INT_ARITH_MODW(name, opc3, sign) \
1126 static void glue(gen_, name)(DisasContext *ctx) \
1127 { \
1128 gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \
1129 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1130 sign); \
1131 }
1132
1133 GEN_INT_ARITH_MODW(moduw, 0x08, 0);
1134 GEN_INT_ARITH_MODW(modsw, 0x18, 1);
1135
1136 #if defined(TARGET_PPC64)
1137 static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1,
1138 TCGv arg2, int sign)
1139 {
1140 TCGv_i64 t0 = tcg_temp_new_i64();
1141 TCGv_i64 t1 = tcg_temp_new_i64();
1142
1143 tcg_gen_mov_i64(t0, arg1);
1144 tcg_gen_mov_i64(t1, arg2);
1145 if (sign) {
1146 TCGv_i64 t2 = tcg_temp_new_i64();
1147 TCGv_i64 t3 = tcg_temp_new_i64();
1148 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN);
1149 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1);
1150 tcg_gen_and_i64(t2, t2, t3);
1151 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0);
1152 tcg_gen_or_i64(t2, t2, t3);
1153 tcg_gen_movi_i64(t3, 0);
1154 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1155 tcg_gen_rem_i64(ret, t0, t1);
1156 tcg_temp_free_i64(t2);
1157 tcg_temp_free_i64(t3);
1158 } else {
1159 TCGv_i64 t2 = tcg_const_i64(1);
1160 TCGv_i64 t3 = tcg_const_i64(0);
1161 tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1);
1162 tcg_gen_remu_i64(ret, t0, t1);
1163 tcg_temp_free_i64(t2);
1164 tcg_temp_free_i64(t3);
1165 }
1166 tcg_temp_free_i64(t0);
1167 tcg_temp_free_i64(t1);
1168 }
1169
1170 #define GEN_INT_ARITH_MODD(name, opc3, sign) \
1171 static void glue(gen_, name)(DisasContext *ctx) \
1172 { \
1173 gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \
1174 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1175 sign); \
1176 }
1177
1178 GEN_INT_ARITH_MODD(modud, 0x08, 0);
1179 GEN_INT_ARITH_MODD(modsd, 0x18, 1);
1180 #endif
1181
1182 /* mulhw mulhw. */
1183 static void gen_mulhw(DisasContext *ctx)
1184 {
1185 TCGv_i32 t0 = tcg_temp_new_i32();
1186 TCGv_i32 t1 = tcg_temp_new_i32();
1187
1188 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1189 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1190 tcg_gen_muls2_i32(t0, t1, t0, t1);
1191 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1192 tcg_temp_free_i32(t0);
1193 tcg_temp_free_i32(t1);
1194 if (unlikely(Rc(ctx->opcode) != 0))
1195 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1196 }
1197
1198 /* mulhwu mulhwu. */
1199 static void gen_mulhwu(DisasContext *ctx)
1200 {
1201 TCGv_i32 t0 = tcg_temp_new_i32();
1202 TCGv_i32 t1 = tcg_temp_new_i32();
1203
1204 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1205 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1206 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1207 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1208 tcg_temp_free_i32(t0);
1209 tcg_temp_free_i32(t1);
1210 if (unlikely(Rc(ctx->opcode) != 0))
1211 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1212 }
1213
1214 /* mullw mullw. */
1215 static void gen_mullw(DisasContext *ctx)
1216 {
1217 #if defined(TARGET_PPC64)
1218 TCGv_i64 t0, t1;
1219 t0 = tcg_temp_new_i64();
1220 t1 = tcg_temp_new_i64();
1221 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1222 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1223 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1224 tcg_temp_free(t0);
1225 tcg_temp_free(t1);
1226 #else
1227 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1228 cpu_gpr[rB(ctx->opcode)]);
1229 #endif
1230 if (unlikely(Rc(ctx->opcode) != 0))
1231 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1232 }
1233
1234 /* mullwo mullwo. */
1235 static void gen_mullwo(DisasContext *ctx)
1236 {
1237 TCGv_i32 t0 = tcg_temp_new_i32();
1238 TCGv_i32 t1 = tcg_temp_new_i32();
1239
1240 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1241 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1242 tcg_gen_muls2_i32(t0, t1, t0, t1);
1243 #if defined(TARGET_PPC64)
1244 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1245 #else
1246 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0);
1247 #endif
1248
1249 tcg_gen_sari_i32(t0, t0, 31);
1250 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1251 tcg_gen_extu_i32_tl(cpu_ov, t0);
1252 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1253
1254 tcg_temp_free_i32(t0);
1255 tcg_temp_free_i32(t1);
1256 if (unlikely(Rc(ctx->opcode) != 0))
1257 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1258 }
1259
1260 /* mulli */
1261 static void gen_mulli(DisasContext *ctx)
1262 {
1263 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1264 SIMM(ctx->opcode));
1265 }
1266
1267 #if defined(TARGET_PPC64)
1268 /* mulhd mulhd. */
1269 static void gen_mulhd(DisasContext *ctx)
1270 {
1271 TCGv lo = tcg_temp_new();
1272 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1273 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1274 tcg_temp_free(lo);
1275 if (unlikely(Rc(ctx->opcode) != 0)) {
1276 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1277 }
1278 }
1279
1280 /* mulhdu mulhdu. */
1281 static void gen_mulhdu(DisasContext *ctx)
1282 {
1283 TCGv lo = tcg_temp_new();
1284 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1285 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1286 tcg_temp_free(lo);
1287 if (unlikely(Rc(ctx->opcode) != 0)) {
1288 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1289 }
1290 }
1291
1292 /* mulld mulld. */
1293 static void gen_mulld(DisasContext *ctx)
1294 {
1295 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1296 cpu_gpr[rB(ctx->opcode)]);
1297 if (unlikely(Rc(ctx->opcode) != 0))
1298 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1299 }
1300
1301 /* mulldo mulldo. */
1302 static void gen_mulldo(DisasContext *ctx)
1303 {
1304 TCGv_i64 t0 = tcg_temp_new_i64();
1305 TCGv_i64 t1 = tcg_temp_new_i64();
1306
1307 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)],
1308 cpu_gpr[rB(ctx->opcode)]);
1309 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0);
1310
1311 tcg_gen_sari_i64(t0, t0, 63);
1312 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1);
1313 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1314
1315 tcg_temp_free_i64(t0);
1316 tcg_temp_free_i64(t1);
1317
1318 if (unlikely(Rc(ctx->opcode) != 0)) {
1319 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1320 }
1321 }
1322 #endif
1323
1324 /* Common subf function */
1325 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1326 TCGv arg2, bool add_ca, bool compute_ca,
1327 bool compute_ov, bool compute_rc0)
1328 {
1329 TCGv t0 = ret;
1330
1331 if (compute_ca || compute_ov) {
1332 t0 = tcg_temp_new();
1333 }
1334
1335 if (compute_ca) {
1336 /* dest = ~arg1 + arg2 [+ ca]. */
1337 if (NARROW_MODE(ctx)) {
1338 /* Caution: a non-obvious corner case of the spec is that we
1339 must produce the *entire* 64-bit addition, but produce the
1340 carry into bit 32. */
1341 TCGv inv1 = tcg_temp_new();
1342 TCGv t1 = tcg_temp_new();
1343 tcg_gen_not_tl(inv1, arg1);
1344 if (add_ca) {
1345 tcg_gen_add_tl(t0, arg2, cpu_ca);
1346 } else {
1347 tcg_gen_addi_tl(t0, arg2, 1);
1348 }
1349 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
1350 tcg_gen_add_tl(t0, t0, inv1);
1351 tcg_temp_free(inv1);
1352 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1353 tcg_temp_free(t1);
1354 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
1355 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
1356 } else if (add_ca) {
1357 TCGv zero, inv1 = tcg_temp_new();
1358 tcg_gen_not_tl(inv1, arg1);
1359 zero = tcg_const_tl(0);
1360 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1361 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
1362 tcg_temp_free(zero);
1363 tcg_temp_free(inv1);
1364 } else {
1365 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1366 tcg_gen_sub_tl(t0, arg2, arg1);
1367 }
1368 } else if (add_ca) {
1369 /* Since we're ignoring carry-out, we can simplify the
1370 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1371 tcg_gen_sub_tl(t0, arg2, arg1);
1372 tcg_gen_add_tl(t0, t0, cpu_ca);
1373 tcg_gen_subi_tl(t0, t0, 1);
1374 } else {
1375 tcg_gen_sub_tl(t0, arg2, arg1);
1376 }
1377
1378 if (compute_ov) {
1379 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1380 }
1381 if (unlikely(compute_rc0)) {
1382 gen_set_Rc0(ctx, t0);
1383 }
1384
1385 if (!TCGV_EQUAL(t0, ret)) {
1386 tcg_gen_mov_tl(ret, t0);
1387 tcg_temp_free(t0);
1388 }
1389 }
1390 /* Sub functions with Two operands functions */
1391 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1392 static void glue(gen_, name)(DisasContext *ctx) \
1393 { \
1394 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1395 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1396 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1397 }
1398 /* Sub functions with one operand and one immediate */
1399 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1400 add_ca, compute_ca, compute_ov) \
1401 static void glue(gen_, name)(DisasContext *ctx) \
1402 { \
1403 TCGv t0 = tcg_const_tl(const_val); \
1404 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1405 cpu_gpr[rA(ctx->opcode)], t0, \
1406 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1407 tcg_temp_free(t0); \
1408 }
1409 /* subf subf. subfo subfo. */
1410 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1411 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1412 /* subfc subfc. subfco subfco. */
1413 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1414 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1415 /* subfe subfe. subfeo subfo. */
1416 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1417 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1418 /* subfme subfme. subfmeo subfmeo. */
1419 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1420 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1421 /* subfze subfze. subfzeo subfzeo.*/
1422 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1423 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1424
1425 /* subfic */
1426 static void gen_subfic(DisasContext *ctx)
1427 {
1428 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1429 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1430 c, 0, 1, 0, 0);
1431 tcg_temp_free(c);
1432 }
1433
1434 /* neg neg. nego nego. */
1435 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1436 {
1437 TCGv zero = tcg_const_tl(0);
1438 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1439 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1440 tcg_temp_free(zero);
1441 }
1442
1443 static void gen_neg(DisasContext *ctx)
1444 {
1445 gen_op_arith_neg(ctx, 0);
1446 }
1447
1448 static void gen_nego(DisasContext *ctx)
1449 {
1450 gen_op_arith_neg(ctx, 1);
1451 }
1452
1453 /*** Integer logical ***/
1454 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1455 static void glue(gen_, name)(DisasContext *ctx) \
1456 { \
1457 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1458 cpu_gpr[rB(ctx->opcode)]); \
1459 if (unlikely(Rc(ctx->opcode) != 0)) \
1460 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1461 }
1462
1463 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1464 static void glue(gen_, name)(DisasContext *ctx) \
1465 { \
1466 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1467 if (unlikely(Rc(ctx->opcode) != 0)) \
1468 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1469 }
1470
1471 /* and & and. */
1472 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1473 /* andc & andc. */
1474 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1475
1476 /* andi. */
1477 static void gen_andi_(DisasContext *ctx)
1478 {
1479 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1480 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1481 }
1482
1483 /* andis. */
1484 static void gen_andis_(DisasContext *ctx)
1485 {
1486 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1487 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1488 }
1489
1490 /* cntlzw */
1491 static void gen_cntlzw(DisasContext *ctx)
1492 {
1493 TCGv_i32 t = tcg_temp_new_i32();
1494
1495 tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]);
1496 tcg_gen_clzi_i32(t, t, 32);
1497 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t);
1498 tcg_temp_free_i32(t);
1499
1500 if (unlikely(Rc(ctx->opcode) != 0))
1501 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1502 }
1503
1504 /* cnttzw */
1505 static void gen_cnttzw(DisasContext *ctx)
1506 {
1507 TCGv_i32 t = tcg_temp_new_i32();
1508
1509 tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]);
1510 tcg_gen_ctzi_i32(t, t, 32);
1511 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t);
1512 tcg_temp_free_i32(t);
1513
1514 if (unlikely(Rc(ctx->opcode) != 0)) {
1515 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1516 }
1517 }
1518
1519 /* eqv & eqv. */
1520 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1521 /* extsb & extsb. */
1522 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1523 /* extsh & extsh. */
1524 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1525 /* nand & nand. */
1526 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1527 /* nor & nor. */
1528 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1529
1530 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
1531 static void gen_pause(DisasContext *ctx)
1532 {
1533 TCGv_i32 t0 = tcg_const_i32(0);
1534 tcg_gen_st_i32(t0, cpu_env,
1535 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
1536 tcg_temp_free_i32(t0);
1537
1538 /* Stop translation, this gives other CPUs a chance to run */
1539 gen_exception_nip(ctx, EXCP_HLT, ctx->nip);
1540 }
1541 #endif /* defined(TARGET_PPC64) */
1542
1543 /* or & or. */
1544 static void gen_or(DisasContext *ctx)
1545 {
1546 int rs, ra, rb;
1547
1548 rs = rS(ctx->opcode);
1549 ra = rA(ctx->opcode);
1550 rb = rB(ctx->opcode);
1551 /* Optimisation for mr. ri case */
1552 if (rs != ra || rs != rb) {
1553 if (rs != rb)
1554 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1555 else
1556 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1557 if (unlikely(Rc(ctx->opcode) != 0))
1558 gen_set_Rc0(ctx, cpu_gpr[ra]);
1559 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1560 gen_set_Rc0(ctx, cpu_gpr[rs]);
1561 #if defined(TARGET_PPC64)
1562 } else if (rs != 0) { /* 0 is nop */
1563 int prio = 0;
1564
1565 switch (rs) {
1566 case 1:
1567 /* Set process priority to low */
1568 prio = 2;
1569 break;
1570 case 6:
1571 /* Set process priority to medium-low */
1572 prio = 3;
1573 break;
1574 case 2:
1575 /* Set process priority to normal */
1576 prio = 4;
1577 break;
1578 #if !defined(CONFIG_USER_ONLY)
1579 case 31:
1580 if (!ctx->pr) {
1581 /* Set process priority to very low */
1582 prio = 1;
1583 }
1584 break;
1585 case 5:
1586 if (!ctx->pr) {
1587 /* Set process priority to medium-hight */
1588 prio = 5;
1589 }
1590 break;
1591 case 3:
1592 if (!ctx->pr) {
1593 /* Set process priority to high */
1594 prio = 6;
1595 }
1596 break;
1597 case 7:
1598 if (ctx->hv && !ctx->pr) {
1599 /* Set process priority to very high */
1600 prio = 7;
1601 }
1602 break;
1603 #endif
1604 default:
1605 break;
1606 }
1607 if (prio) {
1608 TCGv t0 = tcg_temp_new();
1609 gen_load_spr(t0, SPR_PPR);
1610 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1611 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1612 gen_store_spr(SPR_PPR, t0);
1613 tcg_temp_free(t0);
1614 }
1615 #if !defined(CONFIG_USER_ONLY)
1616 /* Pause out of TCG otherwise spin loops with smt_low eat too much
1617 * CPU and the kernel hangs. This applies to all encodings other
1618 * than no-op, e.g., miso(rs=26), yield(27), mdoio(29), mdoom(30),
1619 * and all currently undefined.
1620 */
1621 gen_pause(ctx);
1622 #endif
1623 #endif
1624 }
1625 }
1626 /* orc & orc. */
1627 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1628
1629 /* xor & xor. */
1630 static void gen_xor(DisasContext *ctx)
1631 {
1632 /* Optimisation for "set to zero" case */
1633 if (rS(ctx->opcode) != rB(ctx->opcode))
1634 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1635 else
1636 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1637 if (unlikely(Rc(ctx->opcode) != 0))
1638 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1639 }
1640
1641 /* ori */
1642 static void gen_ori(DisasContext *ctx)
1643 {
1644 target_ulong uimm = UIMM(ctx->opcode);
1645
1646 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1647 return;
1648 }
1649 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1650 }
1651
1652 /* oris */
1653 static void gen_oris(DisasContext *ctx)
1654 {
1655 target_ulong uimm = UIMM(ctx->opcode);
1656
1657 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1658 /* NOP */
1659 return;
1660 }
1661 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1662 }
1663
1664 /* xori */
1665 static void gen_xori(DisasContext *ctx)
1666 {
1667 target_ulong uimm = UIMM(ctx->opcode);
1668
1669 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1670 /* NOP */
1671 return;
1672 }
1673 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1674 }
1675
1676 /* xoris */
1677 static void gen_xoris(DisasContext *ctx)
1678 {
1679 target_ulong uimm = UIMM(ctx->opcode);
1680
1681 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1682 /* NOP */
1683 return;
1684 }
1685 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1686 }
1687
1688 /* popcntb : PowerPC 2.03 specification */
1689 static void gen_popcntb(DisasContext *ctx)
1690 {
1691 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1692 }
1693
1694 static void gen_popcntw(DisasContext *ctx)
1695 {
1696 #if defined(TARGET_PPC64)
1697 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1698 #else
1699 tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1700 #endif
1701 }
1702
1703 #if defined(TARGET_PPC64)
1704 /* popcntd: PowerPC 2.06 specification */
1705 static void gen_popcntd(DisasContext *ctx)
1706 {
1707 tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1708 }
1709 #endif
1710
1711 /* prtyw: PowerPC 2.05 specification */
1712 static void gen_prtyw(DisasContext *ctx)
1713 {
1714 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1715 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1716 TCGv t0 = tcg_temp_new();
1717 tcg_gen_shri_tl(t0, rs, 16);
1718 tcg_gen_xor_tl(ra, rs, t0);
1719 tcg_gen_shri_tl(t0, ra, 8);
1720 tcg_gen_xor_tl(ra, ra, t0);
1721 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1722 tcg_temp_free(t0);
1723 }
1724
1725 #if defined(TARGET_PPC64)
1726 /* prtyd: PowerPC 2.05 specification */
1727 static void gen_prtyd(DisasContext *ctx)
1728 {
1729 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1730 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1731 TCGv t0 = tcg_temp_new();
1732 tcg_gen_shri_tl(t0, rs, 32);
1733 tcg_gen_xor_tl(ra, rs, t0);
1734 tcg_gen_shri_tl(t0, ra, 16);
1735 tcg_gen_xor_tl(ra, ra, t0);
1736 tcg_gen_shri_tl(t0, ra, 8);
1737 tcg_gen_xor_tl(ra, ra, t0);
1738 tcg_gen_andi_tl(ra, ra, 1);
1739 tcg_temp_free(t0);
1740 }
1741 #endif
1742
1743 #if defined(TARGET_PPC64)
1744 /* bpermd */
1745 static void gen_bpermd(DisasContext *ctx)
1746 {
1747 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
1748 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1749 }
1750 #endif
1751
1752 #if defined(TARGET_PPC64)
1753 /* extsw & extsw. */
1754 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1755
1756 /* cntlzd */
1757 static void gen_cntlzd(DisasContext *ctx)
1758 {
1759 tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64);
1760 if (unlikely(Rc(ctx->opcode) != 0))
1761 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1762 }
1763
1764 /* cnttzd */
1765 static void gen_cnttzd(DisasContext *ctx)
1766 {
1767 tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64);
1768 if (unlikely(Rc(ctx->opcode) != 0)) {
1769 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1770 }
1771 }
1772
1773 /* darn */
1774 static void gen_darn(DisasContext *ctx)
1775 {
1776 int l = L(ctx->opcode);
1777
1778 if (l == 0) {
1779 gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]);
1780 } else if (l <= 2) {
1781 /* Return 64-bit random for both CRN and RRN */
1782 gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]);
1783 } else {
1784 tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1);
1785 }
1786 }
1787 #endif
1788
1789 /*** Integer rotate ***/
1790
1791 /* rlwimi & rlwimi. */
1792 static void gen_rlwimi(DisasContext *ctx)
1793 {
1794 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1795 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1796 uint32_t sh = SH(ctx->opcode);
1797 uint32_t mb = MB(ctx->opcode);
1798 uint32_t me = ME(ctx->opcode);
1799
1800 if (sh == (31-me) && mb <= me) {
1801 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
1802 } else {
1803 target_ulong mask;
1804 TCGv t1;
1805
1806 #if defined(TARGET_PPC64)
1807 mb += 32;
1808 me += 32;
1809 #endif
1810 mask = MASK(mb, me);
1811
1812 t1 = tcg_temp_new();
1813 if (mask <= 0xffffffffu) {
1814 TCGv_i32 t0 = tcg_temp_new_i32();
1815 tcg_gen_trunc_tl_i32(t0, t_rs);
1816 tcg_gen_rotli_i32(t0, t0, sh);
1817 tcg_gen_extu_i32_tl(t1, t0);
1818 tcg_temp_free_i32(t0);
1819 } else {
1820 #if defined(TARGET_PPC64)
1821 tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32);
1822 tcg_gen_rotli_i64(t1, t1, sh);
1823 #else
1824 g_assert_not_reached();
1825 #endif
1826 }
1827
1828 tcg_gen_andi_tl(t1, t1, mask);
1829 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
1830 tcg_gen_or_tl(t_ra, t_ra, t1);
1831 tcg_temp_free(t1);
1832 }
1833 if (unlikely(Rc(ctx->opcode) != 0)) {
1834 gen_set_Rc0(ctx, t_ra);
1835 }
1836 }
1837
1838 /* rlwinm & rlwinm. */
1839 static void gen_rlwinm(DisasContext *ctx)
1840 {
1841 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1842 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1843 int sh = SH(ctx->opcode);
1844 int mb = MB(ctx->opcode);
1845 int me = ME(ctx->opcode);
1846 int len = me - mb + 1;
1847 int rsh = (32 - sh) & 31;
1848
1849 if (sh != 0 && len > 0 && me == (31 - sh)) {
1850 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len);
1851 } else if (me == 31 && rsh + len <= 32) {
1852 tcg_gen_extract_tl(t_ra, t_rs, rsh, len);
1853 } else {
1854 target_ulong mask;
1855 #if defined(TARGET_PPC64)
1856 mb += 32;
1857 me += 32;
1858 #endif
1859 mask = MASK(mb, me);
1860 if (sh == 0) {
1861 tcg_gen_andi_tl(t_ra, t_rs, mask);
1862 } else if (mask <= 0xffffffffu) {
1863 TCGv_i32 t0 = tcg_temp_new_i32();
1864 tcg_gen_trunc_tl_i32(t0, t_rs);
1865 tcg_gen_rotli_i32(t0, t0, sh);
1866 tcg_gen_andi_i32(t0, t0, mask);
1867 tcg_gen_extu_i32_tl(t_ra, t0);
1868 tcg_temp_free_i32(t0);
1869 } else {
1870 #if defined(TARGET_PPC64)
1871 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
1872 tcg_gen_rotli_i64(t_ra, t_ra, sh);
1873 tcg_gen_andi_i64(t_ra, t_ra, mask);
1874 #else
1875 g_assert_not_reached();
1876 #endif
1877 }
1878 }
1879 if (unlikely(Rc(ctx->opcode) != 0)) {
1880 gen_set_Rc0(ctx, t_ra);
1881 }
1882 }
1883
1884 /* rlwnm & rlwnm. */
1885 static void gen_rlwnm(DisasContext *ctx)
1886 {
1887 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1888 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1889 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
1890 uint32_t mb = MB(ctx->opcode);
1891 uint32_t me = ME(ctx->opcode);
1892 target_ulong mask;
1893
1894 #if defined(TARGET_PPC64)
1895 mb += 32;
1896 me += 32;
1897 #endif
1898 mask = MASK(mb, me);
1899
1900 if (mask <= 0xffffffffu) {
1901 TCGv_i32 t0 = tcg_temp_new_i32();
1902 TCGv_i32 t1 = tcg_temp_new_i32();
1903 tcg_gen_trunc_tl_i32(t0, t_rb);
1904 tcg_gen_trunc_tl_i32(t1, t_rs);
1905 tcg_gen_andi_i32(t0, t0, 0x1f);
1906 tcg_gen_rotl_i32(t1, t1, t0);
1907 tcg_gen_extu_i32_tl(t_ra, t1);
1908 tcg_temp_free_i32(t0);
1909 tcg_temp_free_i32(t1);
1910 } else {
1911 #if defined(TARGET_PPC64)
1912 TCGv_i64 t0 = tcg_temp_new_i64();
1913 tcg_gen_andi_i64(t0, t_rb, 0x1f);
1914 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
1915 tcg_gen_rotl_i64(t_ra, t_ra, t0);
1916 tcg_temp_free_i64(t0);
1917 #else
1918 g_assert_not_reached();
1919 #endif
1920 }
1921
1922 tcg_gen_andi_tl(t_ra, t_ra, mask);
1923
1924 if (unlikely(Rc(ctx->opcode) != 0)) {
1925 gen_set_Rc0(ctx, t_ra);
1926 }
1927 }
1928
1929 #if defined(TARGET_PPC64)
1930 #define GEN_PPC64_R2(name, opc1, opc2) \
1931 static void glue(gen_, name##0)(DisasContext *ctx) \
1932 { \
1933 gen_##name(ctx, 0); \
1934 } \
1935 \
1936 static void glue(gen_, name##1)(DisasContext *ctx) \
1937 { \
1938 gen_##name(ctx, 1); \
1939 }
1940 #define GEN_PPC64_R4(name, opc1, opc2) \
1941 static void glue(gen_, name##0)(DisasContext *ctx) \
1942 { \
1943 gen_##name(ctx, 0, 0); \
1944 } \
1945 \
1946 static void glue(gen_, name##1)(DisasContext *ctx) \
1947 { \
1948 gen_##name(ctx, 0, 1); \
1949 } \
1950 \
1951 static void glue(gen_, name##2)(DisasContext *ctx) \
1952 { \
1953 gen_##name(ctx, 1, 0); \
1954 } \
1955 \
1956 static void glue(gen_, name##3)(DisasContext *ctx) \
1957 { \
1958 gen_##name(ctx, 1, 1); \
1959 }
1960
1961 static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh)
1962 {
1963 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1964 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1965 int len = me - mb + 1;
1966 int rsh = (64 - sh) & 63;
1967
1968 if (sh != 0 && len > 0 && me == (63 - sh)) {
1969 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len);
1970 } else if (me == 63 && rsh + len <= 64) {
1971 tcg_gen_extract_tl(t_ra, t_rs, rsh, len);
1972 } else {
1973 tcg_gen_rotli_tl(t_ra, t_rs, sh);
1974 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
1975 }
1976 if (unlikely(Rc(ctx->opcode) != 0)) {
1977 gen_set_Rc0(ctx, t_ra);
1978 }
1979 }
1980
1981 /* rldicl - rldicl. */
1982 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
1983 {
1984 uint32_t sh, mb;
1985
1986 sh = SH(ctx->opcode) | (shn << 5);
1987 mb = MB(ctx->opcode) | (mbn << 5);
1988 gen_rldinm(ctx, mb, 63, sh);
1989 }
1990 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1991
1992 /* rldicr - rldicr. */
1993 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
1994 {
1995 uint32_t sh, me;
1996
1997 sh = SH(ctx->opcode) | (shn << 5);
1998 me = MB(ctx->opcode) | (men << 5);
1999 gen_rldinm(ctx, 0, me, sh);
2000 }
2001 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
2002
2003 /* rldic - rldic. */
2004 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
2005 {
2006 uint32_t sh, mb;
2007
2008 sh = SH(ctx->opcode) | (shn << 5);
2009 mb = MB(ctx->opcode) | (mbn << 5);
2010 gen_rldinm(ctx, mb, 63 - sh, sh);
2011 }
2012 GEN_PPC64_R4(rldic, 0x1E, 0x04);
2013
2014 static void gen_rldnm(DisasContext *ctx, int mb, int me)
2015 {
2016 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2017 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2018 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
2019 TCGv t0;
2020
2021 t0 = tcg_temp_new();
2022 tcg_gen_andi_tl(t0, t_rb, 0x3f);
2023 tcg_gen_rotl_tl(t_ra, t_rs, t0);
2024 tcg_temp_free(t0);
2025
2026 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
2027 if (unlikely(Rc(ctx->opcode) != 0)) {
2028 gen_set_Rc0(ctx, t_ra);
2029 }
2030 }
2031
2032 /* rldcl - rldcl. */
2033 static inline void gen_rldcl(DisasContext *ctx, int mbn)
2034 {
2035 uint32_t mb;
2036
2037 mb = MB(ctx->opcode) | (mbn << 5);
2038 gen_rldnm(ctx, mb, 63);
2039 }
2040 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
2041
2042 /* rldcr - rldcr. */
2043 static inline void gen_rldcr(DisasContext *ctx, int men)
2044 {
2045 uint32_t me;
2046
2047 me = MB(ctx->opcode) | (men << 5);
2048 gen_rldnm(ctx, 0, me);
2049 }
2050 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
2051
2052 /* rldimi - rldimi. */
2053 static void gen_rldimi(DisasContext *ctx, int mbn, int shn)
2054 {
2055 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2056 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2057 uint32_t sh = SH(ctx->opcode) | (shn << 5);
2058 uint32_t mb = MB(ctx->opcode) | (mbn << 5);
2059 uint32_t me = 63 - sh;
2060
2061 if (mb <= me) {
2062 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
2063 } else {
2064 target_ulong mask = MASK(mb, me);
2065 TCGv t1 = tcg_temp_new();
2066
2067 tcg_gen_rotli_tl(t1, t_rs, sh);
2068 tcg_gen_andi_tl(t1, t1, mask);
2069 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
2070 tcg_gen_or_tl(t_ra, t_ra, t1);
2071 tcg_temp_free(t1);
2072 }
2073 if (unlikely(Rc(ctx->opcode) != 0)) {
2074 gen_set_Rc0(ctx, t_ra);
2075 }
2076 }
2077 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
2078 #endif
2079
2080 /*** Integer shift ***/
2081
2082 /* slw & slw. */
2083 static void gen_slw(DisasContext *ctx)
2084 {
2085 TCGv t0, t1;
2086
2087 t0 = tcg_temp_new();
2088 /* AND rS with a mask that is 0 when rB >= 0x20 */
2089 #if defined(TARGET_PPC64)
2090 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
2091 tcg_gen_sari_tl(t0, t0, 0x3f);
2092 #else
2093 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
2094 tcg_gen_sari_tl(t0, t0, 0x1f);
2095 #endif
2096 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2097 t1 = tcg_temp_new();
2098 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
2099 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2100 tcg_temp_free(t1);
2101 tcg_temp_free(t0);
2102 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
2103 if (unlikely(Rc(ctx->opcode) != 0))
2104 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2105 }
2106
2107 /* sraw & sraw. */
2108 static void gen_sraw(DisasContext *ctx)
2109 {
2110 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
2111 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2112 if (unlikely(Rc(ctx->opcode) != 0))
2113 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2114 }
2115
2116 /* srawi & srawi. */
2117 static void gen_srawi(DisasContext *ctx)
2118 {
2119 int sh = SH(ctx->opcode);
2120 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2121 TCGv src = cpu_gpr[rS(ctx->opcode)];
2122 if (sh == 0) {
2123 tcg_gen_ext32s_tl(dst, src);
2124 tcg_gen_movi_tl(cpu_ca, 0);
2125 } else {
2126 TCGv t0;
2127 tcg_gen_ext32s_tl(dst, src);
2128 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
2129 t0 = tcg_temp_new();
2130 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
2131 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2132 tcg_temp_free(t0);
2133 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2134 tcg_gen_sari_tl(dst, dst, sh);
2135 }
2136 if (unlikely(Rc(ctx->opcode) != 0)) {
2137 gen_set_Rc0(ctx, dst);
2138 }
2139 }
2140
2141 /* srw & srw. */
2142 static void gen_srw(DisasContext *ctx)
2143 {
2144 TCGv t0, t1;
2145
2146 t0 = tcg_temp_new();
2147 /* AND rS with a mask that is 0 when rB >= 0x20 */
2148 #if defined(TARGET_PPC64)
2149 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
2150 tcg_gen_sari_tl(t0, t0, 0x3f);
2151 #else
2152 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
2153 tcg_gen_sari_tl(t0, t0, 0x1f);
2154 #endif
2155 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2156 tcg_gen_ext32u_tl(t0, t0);
2157 t1 = tcg_temp_new();
2158 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
2159 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2160 tcg_temp_free(t1);
2161 tcg_temp_free(t0);
2162 if (unlikely(Rc(ctx->opcode) != 0))
2163 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2164 }
2165
2166 #if defined(TARGET_PPC64)
2167 /* sld & sld. */
2168 static void gen_sld(DisasContext *ctx)
2169 {
2170 TCGv t0, t1;
2171
2172 t0 = tcg_temp_new();
2173 /* AND rS with a mask that is 0 when rB >= 0x40 */
2174 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2175 tcg_gen_sari_tl(t0, t0, 0x3f);
2176 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2177 t1 = tcg_temp_new();
2178 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2179 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2180 tcg_temp_free(t1);
2181 tcg_temp_free(t0);
2182 if (unlikely(Rc(ctx->opcode) != 0))
2183 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2184 }
2185
2186 /* srad & srad. */
2187 static void gen_srad(DisasContext *ctx)
2188 {
2189 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
2190 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2191 if (unlikely(Rc(ctx->opcode) != 0))
2192 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2193 }
2194 /* sradi & sradi. */
2195 static inline void gen_sradi(DisasContext *ctx, int n)
2196 {
2197 int sh = SH(ctx->opcode) + (n << 5);
2198 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2199 TCGv src = cpu_gpr[rS(ctx->opcode)];
2200 if (sh == 0) {
2201 tcg_gen_mov_tl(dst, src);
2202 tcg_gen_movi_tl(cpu_ca, 0);
2203 } else {
2204 TCGv t0;
2205 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
2206 t0 = tcg_temp_new();
2207 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
2208 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2209 tcg_temp_free(t0);
2210 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2211 tcg_gen_sari_tl(dst, src, sh);
2212 }
2213 if (unlikely(Rc(ctx->opcode) != 0)) {
2214 gen_set_Rc0(ctx, dst);
2215 }
2216 }
2217
2218 static void gen_sradi0(DisasContext *ctx)
2219 {
2220 gen_sradi(ctx, 0);
2221 }
2222
2223 static void gen_sradi1(DisasContext *ctx)
2224 {
2225 gen_sradi(ctx, 1);
2226 }
2227
2228 /* extswsli & extswsli. */
2229 static inline void gen_extswsli(DisasContext *ctx, int n)
2230 {
2231 int sh = SH(ctx->opcode) + (n << 5);
2232 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2233 TCGv src = cpu_gpr[rS(ctx->opcode)];
2234
2235 tcg_gen_ext32s_tl(dst, src);
2236 tcg_gen_shli_tl(dst, dst, sh);
2237 if (unlikely(Rc(ctx->opcode) != 0)) {
2238 gen_set_Rc0(ctx, dst);
2239 }
2240 }
2241
2242 static void gen_extswsli0(DisasContext *ctx)
2243 {
2244 gen_extswsli(ctx, 0);
2245 }
2246
2247 static void gen_extswsli1(DisasContext *ctx)
2248 {
2249 gen_extswsli(ctx, 1);
2250 }
2251
2252 /* srd & srd. */
2253 static void gen_srd(DisasContext *ctx)
2254 {
2255 TCGv t0, t1;
2256
2257 t0 = tcg_temp_new();
2258 /* AND rS with a mask that is 0 when rB >= 0x40 */
2259 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2260 tcg_gen_sari_tl(t0, t0, 0x3f);
2261 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2262 t1 = tcg_temp_new();
2263 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2264 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2265 tcg_temp_free(t1);
2266 tcg_temp_free(t0);
2267 if (unlikely(Rc(ctx->opcode) != 0))
2268 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2269 }
2270 #endif
2271
2272 /*** Addressing modes ***/
2273 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2274 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2275 target_long maskl)
2276 {
2277 target_long simm = SIMM(ctx->opcode);
2278
2279 simm &= ~maskl;
2280 if (rA(ctx->opcode) == 0) {
2281 if (NARROW_MODE(ctx)) {
2282 simm = (uint32_t)simm;
2283 }
2284 tcg_gen_movi_tl(EA, simm);
2285 } else if (likely(simm != 0)) {
2286 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2287 if (NARROW_MODE(ctx)) {
2288 tcg_gen_ext32u_tl(EA, EA);
2289 }
2290 } else {
2291 if (NARROW_MODE(ctx)) {
2292 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2293 } else {
2294 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2295 }
2296 }
2297 }
2298
2299 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2300 {
2301 if (rA(ctx->opcode) == 0) {
2302 if (NARROW_MODE(ctx)) {
2303 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2304 } else {
2305 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2306 }
2307 } else {
2308 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2309 if (NARROW_MODE(ctx)) {
2310 tcg_gen_ext32u_tl(EA, EA);
2311 }
2312 }
2313 }
2314
2315 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2316 {
2317 if (rA(ctx->opcode) == 0) {
2318 tcg_gen_movi_tl(EA, 0);
2319 } else if (NARROW_MODE(ctx)) {
2320 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2321 } else {
2322 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2323 }
2324 }
2325
2326 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2327 target_long val)
2328 {
2329 tcg_gen_addi_tl(ret, arg1, val);
2330 if (NARROW_MODE(ctx)) {
2331 tcg_gen_ext32u_tl(ret, ret);
2332 }
2333 }
2334
2335 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2336 {
2337 TCGLabel *l1 = gen_new_label();
2338 TCGv t0 = tcg_temp_new();
2339 TCGv_i32 t1, t2;
2340 tcg_gen_andi_tl(t0, EA, mask);
2341 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2342 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2343 t2 = tcg_const_i32(ctx->opcode & 0x03FF0000);
2344 gen_update_nip(ctx, ctx->nip - 4);
2345 gen_helper_raise_exception_err(cpu_env, t1, t2);
2346 tcg_temp_free_i32(t1);
2347 tcg_temp_free_i32(t2);
2348 gen_set_label(l1);
2349 tcg_temp_free(t0);
2350 }
2351
2352 static inline void gen_align_no_le(DisasContext *ctx)
2353 {
2354 gen_exception_err(ctx, POWERPC_EXCP_ALIGN,
2355 (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE);
2356 }
2357
2358 /*** Integer load ***/
2359 #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask)
2360 #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP))
2361
2362 #define GEN_QEMU_LOAD_TL(ldop, op) \
2363 static void glue(gen_qemu_, ldop)(DisasContext *ctx, \
2364 TCGv val, \
2365 TCGv addr) \
2366 { \
2367 tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \
2368 }
2369
2370 GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB))
2371 GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW))
2372 GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW))
2373 GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL))
2374 GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL))
2375
2376 GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW))
2377 GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL))
2378
2379 #define GEN_QEMU_LOAD_64(ldop, op) \
2380 static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \
2381 TCGv_i64 val, \
2382 TCGv addr) \
2383 { \
2384 tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \
2385 }
2386
2387 GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB))
2388 GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW))
2389 GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL))
2390 GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL))
2391 GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_Q))
2392
2393 #if defined(TARGET_PPC64)
2394 GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_Q))
2395 #endif
2396
2397 #define GEN_QEMU_STORE_TL(stop, op) \
2398 static void glue(gen_qemu_, stop)(DisasContext *ctx, \
2399 TCGv val, \
2400 TCGv addr) \
2401 { \
2402 tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \
2403 }
2404
2405 GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB))
2406 GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW))
2407 GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL))
2408
2409 GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW))
2410 GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL))
2411
2412 #define GEN_QEMU_STORE_64(stop, op) \
2413 static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \
2414 TCGv_i64 val, \
2415 TCGv addr) \
2416 { \
2417 tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \
2418 }
2419
2420 GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB))
2421 GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW))
2422 GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL))
2423 GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q))
2424
2425 #if defined(TARGET_PPC64)
2426 GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q))
2427 #endif
2428
2429 #define GEN_LD(name, ldop, opc, type) \
2430 static void glue(gen_, name)(DisasContext *ctx) \
2431 { \
2432 TCGv EA; \
2433 gen_set_access_type(ctx, ACCESS_INT); \
2434 EA = tcg_temp_new(); \
2435 gen_addr_imm_index(ctx, EA, 0); \
2436 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2437 tcg_temp_free(EA); \
2438 }
2439
2440 #define GEN_LDU(name, ldop, opc, type) \
2441 static void glue(gen_, name##u)(DisasContext *ctx) \
2442 { \
2443 TCGv EA; \
2444 if (unlikely(rA(ctx->opcode) == 0 || \
2445 rA(ctx->opcode) == rD(ctx->opcode))) { \
2446 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2447 return; \
2448 } \
2449 gen_set_access_type(ctx, ACCESS_INT); \
2450 EA = tcg_temp_new(); \
2451 if (type == PPC_64B) \
2452 gen_addr_imm_index(ctx, EA, 0x03); \
2453 else \
2454 gen_addr_imm_index(ctx, EA, 0); \
2455 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2456 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2457 tcg_temp_free(EA); \
2458 }
2459
2460 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2461 static void glue(gen_, name##ux)(DisasContext *ctx) \
2462 { \
2463 TCGv EA; \
2464 if (unlikely(rA(ctx->opcode) == 0 || \
2465 rA(ctx->opcode) == rD(ctx->opcode))) { \
2466 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2467 return; \
2468 } \
2469 gen_set_access_type(ctx, ACCESS_INT); \
2470 EA = tcg_temp_new(); \
2471 gen_addr_reg_index(ctx, EA); \
2472 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2473 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2474 tcg_temp_free(EA); \
2475 }
2476
2477 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
2478 static void glue(gen_, name##x)(DisasContext *ctx) \
2479 { \
2480 TCGv EA; \
2481 chk; \
2482 gen_set_access_type(ctx, ACCESS_INT); \
2483 EA = tcg_temp_new(); \
2484 gen_addr_reg_index(ctx, EA); \
2485 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2486 tcg_temp_free(EA); \
2487 }
2488
2489 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2490 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2491
2492 #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \
2493 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2494
2495 #define GEN_LDS(name, ldop, op, type) \
2496 GEN_LD(name, ldop, op | 0x20, type); \
2497 GEN_LDU(name, ldop, op | 0x21, type); \
2498 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2499 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2500
2501 /* lbz lbzu lbzux lbzx */
2502 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2503 /* lha lhau lhaux lhax */
2504 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2505 /* lhz lhzu lhzux lhzx */
2506 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2507 /* lwz lwzu lwzux lwzx */
2508 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2509 #if defined(TARGET_PPC64)
2510 /* lwaux */
2511 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2512 /* lwax */
2513 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2514 /* ldux */
2515 GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B);
2516 /* ldx */
2517 GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B);
2518
2519 /* CI load/store variants */
2520 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST)
2521 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST)
2522 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
2523 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
2524
2525 static void gen_ld(DisasContext *ctx)
2526 {
2527 TCGv EA;
2528 if (Rc(ctx->opcode)) {
2529 if (unlikely(rA(ctx->opcode) == 0 ||
2530 rA(ctx->opcode) == rD(ctx->opcode))) {
2531 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2532 return;
2533 }
2534 }
2535 gen_set_access_type(ctx, ACCESS_INT);
2536 EA = tcg_temp_new();
2537 gen_addr_imm_index(ctx, EA, 0x03);
2538 if (ctx->opcode & 0x02) {
2539 /* lwa (lwau is undefined) */
2540 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2541 } else {
2542 /* ld - ldu */
2543 gen_qemu_ld64_i64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2544 }
2545 if (Rc(ctx->opcode))
2546 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2547 tcg_temp_free(EA);
2548 }
2549
2550 /* lq */
2551 static void gen_lq(DisasContext *ctx)
2552 {
2553 int ra, rd;
2554 TCGv EA;
2555
2556 /* lq is a legal user mode instruction starting in ISA 2.07 */
2557 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2558 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2559
2560 if (!legal_in_user_mode && ctx->pr) {
2561 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2562 return;
2563 }
2564
2565 if (!le_is_supported && ctx->le_mode) {
2566 gen_align_no_le(ctx);
2567 return;
2568 }
2569 ra = rA(ctx->opcode);
2570 rd = rD(ctx->opcode);
2571 if (unlikely((rd & 1) || rd == ra)) {
2572 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2573 return;
2574 }
2575
2576 gen_set_access_type(ctx, ACCESS_INT);
2577 EA = tcg_temp_new();
2578 gen_addr_imm_index(ctx, EA, 0x0F);
2579
2580 /* We only need to swap high and low halves. gen_qemu_ld64_i64 does
2581 necessary 64-bit byteswap already. */
2582 if (unlikely(ctx->le_mode)) {
2583 gen_qemu_ld64_i64(ctx, cpu_gpr[rd + 1], EA);
2584 gen_addr_add(ctx, EA, EA, 8);
2585 gen_qemu_ld64_i64(ctx, cpu_gpr[rd], EA);
2586 } else {
2587 gen_qemu_ld64_i64(ctx, cpu_gpr[rd], EA);
2588 gen_addr_add(ctx, EA, EA, 8);
2589 gen_qemu_ld64_i64(ctx, cpu_gpr[rd + 1], EA);
2590 }
2591 tcg_temp_free(EA);
2592 }
2593 #endif
2594
2595 /*** Integer store ***/
2596 #define GEN_ST(name, stop, opc, type) \
2597 static void glue(gen_, name)(DisasContext *ctx) \
2598 { \
2599 TCGv EA; \
2600 gen_set_access_type(ctx, ACCESS_INT); \
2601 EA = tcg_temp_new(); \
2602 gen_addr_imm_index(ctx, EA, 0); \
2603 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2604 tcg_temp_free(EA); \
2605 }
2606
2607 #define GEN_STU(name, stop, opc, type) \
2608 static void glue(gen_, stop##u)(DisasContext *ctx) \
2609 { \
2610 TCGv EA; \
2611 if (unlikely(rA(ctx->opcode) == 0)) { \
2612 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2613 return; \
2614 } \
2615 gen_set_access_type(ctx, ACCESS_INT); \
2616 EA = tcg_temp_new(); \
2617 if (type == PPC_64B) \
2618 gen_addr_imm_index(ctx, EA, 0x03); \
2619 else \
2620 gen_addr_imm_index(ctx, EA, 0); \
2621 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2622 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2623 tcg_temp_free(EA); \
2624 }
2625
2626 #define GEN_STUX(name, stop, opc2, opc3, type) \
2627 static void glue(gen_, name##ux)(DisasContext *ctx) \
2628 { \
2629 TCGv EA; \
2630 if (unlikely(rA(ctx->opcode) == 0)) { \
2631 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2632 return; \
2633 } \
2634 gen_set_access_type(ctx, ACCESS_INT); \
2635 EA = tcg_temp_new(); \
2636 gen_addr_reg_index(ctx, EA); \
2637 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2638 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2639 tcg_temp_free(EA); \
2640 }
2641
2642 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
2643 static void glue(gen_, name##x)(DisasContext *ctx) \
2644 { \
2645 TCGv EA; \
2646 chk; \
2647 gen_set_access_type(ctx, ACCESS_INT); \
2648 EA = tcg_temp_new(); \
2649 gen_addr_reg_index(ctx, EA); \
2650 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2651 tcg_temp_free(EA); \
2652 }
2653 #define GEN_STX(name, stop, opc2, opc3, type) \
2654 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2655
2656 #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \
2657 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2658
2659 #define GEN_STS(name, stop, op, type) \
2660 GEN_ST(name, stop, op | 0x20, type); \
2661 GEN_STU(name, stop, op | 0x21, type); \
2662 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2663 GEN_STX(name, stop, 0x17, op | 0x00, type)
2664
2665 /* stb stbu stbux stbx */
2666 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2667 /* sth sthu sthux sthx */
2668 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2669 /* stw stwu stwux stwx */
2670 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2671 #if defined(TARGET_PPC64)
2672 GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B);
2673 GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B);
2674 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
2675 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
2676 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
2677 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
2678
2679 static void gen_std(DisasContext *ctx)
2680 {
2681 int rs;
2682 TCGv EA;
2683
2684 rs = rS(ctx->opcode);
2685 if ((ctx->opcode & 0x3) == 0x2) { /* stq */
2686 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2687 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2688
2689 if (!(ctx->insns_flags & PPC_64BX)) {
2690 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2691 }
2692
2693 if (!legal_in_user_mode && ctx->pr) {
2694 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2695 return;
2696 }
2697
2698 if (!le_is_supported && ctx->le_mode) {
2699 gen_align_no_le(ctx);
2700 return;
2701 }
2702
2703 if (unlikely(rs & 1)) {
2704 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2705 return;
2706 }
2707 gen_set_access_type(ctx, ACCESS_INT);
2708 EA = tcg_temp_new();
2709 gen_addr_imm_index(ctx, EA, 0x03);
2710
2711 /* We only need to swap high and low halves. gen_qemu_st64_i64 does
2712 necessary 64-bit byteswap already. */
2713 if (unlikely(ctx->le_mode)) {
2714 gen_qemu_st64_i64(ctx, cpu_gpr[rs + 1], EA);
2715 gen_addr_add(ctx, EA, EA, 8);
2716 gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA);
2717 } else {
2718 gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA);
2719 gen_addr_add(ctx, EA, EA, 8);
2720 gen_qemu_st64_i64(ctx, cpu_gpr[rs + 1], EA);
2721 }
2722 tcg_temp_free(EA);
2723 } else {
2724 /* std / stdu*/
2725 if (Rc(ctx->opcode)) {
2726 if (unlikely(rA(ctx->opcode) == 0)) {
2727 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2728 return;
2729 }
2730 }
2731 gen_set_access_type(ctx, ACCESS_INT);
2732 EA = tcg_temp_new();
2733 gen_addr_imm_index(ctx, EA, 0x03);
2734 gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA);
2735 if (Rc(ctx->opcode))
2736 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2737 tcg_temp_free(EA);
2738 }
2739 }
2740 #endif
2741 /*** Integer load and store with byte reverse ***/
2742
2743 /* lhbrx */
2744 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
2745
2746 /* lwbrx */
2747 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
2748
2749 #if defined(TARGET_PPC64)
2750 /* ldbrx */
2751 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE);
2752 /* stdbrx */
2753 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE);
2754 #endif /* TARGET_PPC64 */
2755
2756 /* sthbrx */
2757 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
2758 /* stwbrx */
2759 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
2760
2761 /*** Integer load and store multiple ***/
2762
2763 /* lmw */
2764 static void gen_lmw(DisasContext *ctx)
2765 {
2766 TCGv t0;
2767 TCGv_i32 t1;
2768
2769 if (ctx->le_mode) {
2770 gen_align_no_le(ctx);
2771 return;
2772 }
2773 gen_set_access_type(ctx, ACCESS_INT);
2774 t0 = tcg_temp_new();
2775 t1 = tcg_const_i32(rD(ctx->opcode));
2776 gen_addr_imm_index(ctx, t0, 0);
2777 gen_helper_lmw(cpu_env, t0, t1);
2778 tcg_temp_free(t0);
2779 tcg_temp_free_i32(t1);
2780 }
2781
2782 /* stmw */
2783 static void gen_stmw(DisasContext *ctx)
2784 {
2785 TCGv t0;
2786 TCGv_i32 t1;
2787
2788 if (ctx->le_mode) {
2789 gen_align_no_le(ctx);
2790 return;
2791 }
2792 gen_set_access_type(ctx, ACCESS_INT);
2793 t0 = tcg_temp_new();
2794 t1 = tcg_const_i32(rS(ctx->opcode));
2795 gen_addr_imm_index(ctx, t0, 0);
2796 gen_helper_stmw(cpu_env, t0, t1);
2797 tcg_temp_free(t0);
2798 tcg_temp_free_i32(t1);
2799 }
2800
2801 /*** Integer load and store strings ***/
2802
2803 /* lswi */
2804 /* PowerPC32 specification says we must generate an exception if
2805 * rA is in the range of registers to be loaded.
2806 * In an other hand, IBM says this is valid, but rA won't be loaded.
2807 * For now, I'll follow the spec...
2808 */
2809 static void gen_lswi(DisasContext *ctx)
2810 {
2811 TCGv t0;
2812 TCGv_i32 t1, t2;
2813 int nb = NB(ctx->opcode);
2814 int start = rD(ctx->opcode);
2815 int ra = rA(ctx->opcode);
2816 int nr;
2817
2818 if (ctx->le_mode) {
2819 gen_align_no_le(ctx);
2820 return;
2821 }
2822 if (nb == 0)
2823 nb = 32;
2824 nr = (nb + 3) / 4;
2825 if (unlikely(lsw_reg_in_range(start, nr, ra))) {
2826 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
2827 return;
2828 }
2829 gen_set_access_type(ctx, ACCESS_INT);
2830 t0 = tcg_temp_new();
2831 gen_addr_register(ctx, t0);
2832 t1 = tcg_const_i32(nb);
2833 t2 = tcg_const_i32(start);
2834 gen_helper_lsw(cpu_env, t0, t1, t2);
2835 tcg_temp_free(t0);
2836 tcg_temp_free_i32(t1);
2837 tcg_temp_free_i32(t2);
2838 }
2839
2840 /* lswx */
2841 static void gen_lswx(DisasContext *ctx)
2842 {
2843 TCGv t0;
2844 TCGv_i32 t1, t2, t3;
2845
2846 if (ctx->le_mode) {
2847 gen_align_no_le(ctx);
2848 return;
2849 }
2850 gen_set_access_type(ctx, ACCESS_INT);
2851 t0 = tcg_temp_new();
2852 gen_addr_reg_index(ctx, t0);
2853 t1 = tcg_const_i32(rD(ctx->opcode));
2854 t2 = tcg_const_i32(rA(ctx->opcode));
2855 t3 = tcg_const_i32(rB(ctx->opcode));
2856 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
2857 tcg_temp_free(t0);
2858 tcg_temp_free_i32(t1);
2859 tcg_temp_free_i32(t2);
2860 tcg_temp_free_i32(t3);
2861 }
2862
2863 /* stswi */
2864 static void gen_stswi(DisasContext *ctx)
2865 {
2866 TCGv t0;
2867 TCGv_i32 t1, t2;
2868 int nb = NB(ctx->opcode);
2869
2870 if (ctx->le_mode) {
2871 gen_align_no_le(ctx);
2872 return;
2873 }
2874 gen_set_access_type(ctx, ACCESS_INT);
2875 t0 = tcg_temp_new();
2876 gen_addr_register(ctx, t0);
2877 if (nb == 0)
2878 nb = 32;
2879 t1 = tcg_const_i32(nb);
2880 t2 = tcg_const_i32(rS(ctx->opcode));
2881 gen_helper_stsw(cpu_env, t0, t1, t2);
2882 tcg_temp_free(t0);
2883 tcg_temp_free_i32(t1);
2884 tcg_temp_free_i32(t2);
2885 }
2886
2887 /* stswx */
2888 static void gen_stswx(DisasContext *ctx)
2889 {
2890 TCGv t0;
2891 TCGv_i32 t1, t2;
2892
2893 if (ctx->le_mode) {
2894 gen_align_no_le(ctx);
2895 return;
2896 }
2897 gen_set_access_type(ctx, ACCESS_INT);
2898 t0 = tcg_temp_new();
2899 gen_addr_reg_index(ctx, t0);
2900 t1 = tcg_temp_new_i32();
2901 tcg_gen_trunc_tl_i32(t1, cpu_xer);
2902 tcg_gen_andi_i32(t1, t1, 0x7F);
2903 t2 = tcg_const_i32(rS(ctx->opcode));
2904 gen_helper_stsw(cpu_env, t0, t1, t2);
2905 tcg_temp_free(t0);
2906 tcg_temp_free_i32(t1);
2907 tcg_temp_free_i32(t2);
2908 }
2909
2910 /*** Memory synchronisation ***/
2911 /* eieio */
2912 static void gen_eieio(DisasContext *ctx)
2913 {
2914 }
2915
2916 #if !defined(CONFIG_USER_ONLY)
2917 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global)
2918 {
2919 TCGv_i32 t;
2920 TCGLabel *l;
2921
2922 if (!ctx->lazy_tlb_flush) {
2923 return;
2924 }
2925 l = gen_new_label();
2926 t = tcg_temp_new_i32();
2927 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
2928 tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l);
2929 if (global) {
2930 gen_helper_check_tlb_flush_global(cpu_env);
2931 } else {
2932 gen_helper_check_tlb_flush_local(cpu_env);
2933 }
2934 gen_set_label(l);
2935 tcg_temp_free_i32(t);
2936 }
2937 #else
2938 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { }
2939 #endif
2940
2941 /* isync */
2942 static void gen_isync(DisasContext *ctx)
2943 {
2944 /*
2945 * We need to check for a pending TLB flush. This can only happen in
2946 * kernel mode however so check MSR_PR
2947 */
2948 if (!ctx->pr) {
2949 gen_check_tlb_flush(ctx, false);
2950 }
2951 gen_stop_exception(ctx);
2952 }
2953
2954 #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE))
2955
2956 #define LARX(name, memop) \
2957 static void gen_##name(DisasContext *ctx) \
2958 { \
2959 TCGv t0; \
2960 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \
2961 int len = MEMOP_GET_SIZE(memop); \
2962 gen_set_access_type(ctx, ACCESS_RES); \
2963 t0 = tcg_temp_local_new(); \
2964 gen_addr_reg_index(ctx, t0); \
2965 if ((len) > 1) { \
2966 gen_check_align(ctx, t0, (len)-1); \
2967 } \
2968 tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop); \
2969 tcg_gen_mov_tl(cpu_reserve, t0); \
2970 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \
2971 tcg_temp_free(t0); \
2972 }
2973
2974 /* lwarx */
2975 LARX(lbarx, DEF_MEMOP(MO_UB))
2976 LARX(lharx, DEF_MEMOP(MO_UW))
2977 LARX(lwarx, DEF_MEMOP(MO_UL))
2978
2979 #define LD_ATOMIC(name, memop, tp, op, eop) \
2980 static void gen_##name(DisasContext *ctx) \
2981 { \
2982 int len = MEMOP_GET_SIZE(memop); \
2983 uint32_t gpr_FC = FC(ctx->opcode); \
2984 TCGv EA = tcg_temp_local_new(); \
2985 TCGv_##tp t0, t1; \
2986 \
2987 gen_addr_register(ctx, EA); \
2988 if (len > 1) { \
2989 gen_check_align(ctx, EA, len - 1); \
2990 } \
2991 t0 = tcg_temp_new_##tp(); \
2992 t1 = tcg_temp_new_##tp(); \
2993 tcg_gen_##op(t0, cpu_gpr[rD(ctx->opcode) + 1]); \
2994 \
2995 switch (gpr_FC) { \
2996 case 0: /* Fetch and add */ \
2997 tcg_gen_atomic_fetch_add_##tp(t1, EA, t0, ctx->mem_idx, memop); \
2998 break; \
2999 case 1: /* Fetch and xor */ \
3000 tcg_gen_atomic_fetch_xor_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3001 break; \
3002 case 2: /* Fetch and or */ \
3003 tcg_gen_atomic_fetch_or_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3004 break; \
3005 case 3: /* Fetch and 'and' */ \
3006 tcg_gen_atomic_fetch_and_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3007 break; \
3008 case 8: /* Swap */ \
3009 tcg_gen_atomic_xchg_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3010 break; \
3011 case 4: /* Fetch and max unsigned */ \
3012 case 5: /* Fetch and max signed */ \
3013 case 6: /* Fetch and min unsigned */ \
3014 case 7: /* Fetch and min signed */ \
3015 case 16: /* compare and swap not equal */ \
3016 case 24: /* Fetch and increment bounded */ \
3017 case 25: /* Fetch and increment equal */ \
3018 case 28: /* Fetch and decrement bounded */ \
3019 gen_invalid(ctx); \
3020 break; \
3021 default: \
3022 /* invoke data storage error handler */ \
3023 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); \
3024 } \
3025 tcg_gen_##eop(cpu_gpr[rD(ctx->opcode)], t1); \
3026 tcg_temp_free_##tp(t0); \
3027 tcg_temp_free_##tp(t1); \
3028 tcg_temp_free(EA); \
3029 }
3030
3031 LD_ATOMIC(lwat, DEF_MEMOP(MO_UL), i32, trunc_tl_i32, extu_i32_tl)
3032 #if defined(TARGET_PPC64)
3033 LD_ATOMIC(ldat, DEF_MEMOP(MO_Q), i64, mov_i64, mov_i64)
3034 #endif
3035
3036 #define ST_ATOMIC(name, memop, tp, op) \
3037 static void gen_##name(DisasContext *ctx) \
3038 { \
3039 int len = MEMOP_GET_SIZE(memop); \
3040 uint32_t gpr_FC = FC(ctx->opcode); \
3041 TCGv EA = tcg_temp_local_new(); \
3042 TCGv_##tp t0, t1; \
3043 \
3044 gen_addr_register(ctx, EA); \
3045 if (len > 1) { \
3046 gen_check_align(ctx, EA, len - 1); \
3047 } \
3048 t0 = tcg_temp_new_##tp(); \
3049 t1 = tcg_temp_new_##tp(); \
3050 tcg_gen_##op(t0, cpu_gpr[rD(ctx->opcode) + 1]); \
3051 \
3052 switch (gpr_FC) { \
3053 case 0: /* add and Store */ \
3054 tcg_gen_atomic_add_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3055 break; \
3056 case 1: /* xor and Store */ \
3057 tcg_gen_atomic_xor_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3058 break; \
3059 case 2: /* Or and Store */ \
3060 tcg_gen_atomic_or_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3061 break; \
3062 case 3: /* 'and' and Store */ \
3063 tcg_gen_atomic_and_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3064 break; \
3065 case 4: /* Store max unsigned */ \
3066 case 5: /* Store max signed */ \
3067 case 6: /* Store min unsigned */ \
3068 case 7: /* Store min signed */ \
3069 case 24: /* Store twin */ \
3070 gen_invalid(ctx); \
3071 break; \
3072 default: \
3073 /* invoke data storage error handler */ \
3074 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); \
3075 } \
3076 tcg_temp_free_##tp(t0); \
3077 tcg_temp_free_##tp(t1); \
3078 tcg_temp_free(EA); \
3079 }
3080
3081 ST_ATOMIC(stwat, DEF_MEMOP(MO_UL), i32, trunc_tl_i32)
3082 #if defined(TARGET_PPC64)
3083 ST_ATOMIC(stdat, DEF_MEMOP(MO_Q), i64, mov_i64)
3084 #endif
3085
3086 #if defined(CONFIG_USER_ONLY)
3087 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3088 int reg, int memop)
3089 {
3090 TCGv t0 = tcg_temp_new();
3091
3092 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3093 tcg_gen_movi_tl(t0, (MEMOP_GET_SIZE(memop) << 5) | reg);
3094 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3095 tcg_temp_free(t0);
3096 gen_exception_err(ctx, POWERPC_EXCP_STCX, 0);
3097 }
3098 #else
3099 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3100 int reg, int memop)
3101 {
3102 TCGLabel *l1;
3103
3104 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3105 l1 = gen_new_label();
3106 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
3107 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ);
3108 tcg_gen_qemu_st_tl(cpu_gpr[reg], EA, ctx->mem_idx, memop);
3109 gen_set_label(l1);
3110 tcg_gen_movi_tl(cpu_reserve, -1);
3111 }
3112 #endif
3113
3114 #define STCX(name, memop) \
3115 static void gen_##name(DisasContext *ctx) \
3116 { \
3117 TCGv t0; \
3118 int len = MEMOP_GET_SIZE(memop); \
3119 gen_set_access_type(ctx, ACCESS_RES); \
3120 t0 = tcg_temp_local_new(); \
3121 gen_addr_reg_index(ctx, t0); \
3122 if (len > 1) { \
3123 gen_check_align(ctx, t0, (len) - 1); \
3124 } \
3125 gen_conditional_store(ctx, t0, rS(ctx->opcode), memop); \
3126 tcg_temp_free(t0); \
3127 }
3128
3129 STCX(stbcx_, DEF_MEMOP(MO_UB))
3130 STCX(sthcx_, DEF_MEMOP(MO_UW))
3131 STCX(stwcx_, DEF_MEMOP(MO_UL))
3132
3133 #if defined(TARGET_PPC64)
3134 /* ldarx */
3135 LARX(ldarx, DEF_MEMOP(MO_Q))
3136 /* stdcx. */
3137 STCX(stdcx_, DEF_MEMOP(MO_Q))
3138
3139 /* lqarx */
3140 static void gen_lqarx(DisasContext *ctx)
3141 {
3142 TCGv EA;
3143 int rd = rD(ctx->opcode);
3144 TCGv gpr1, gpr2;
3145
3146 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
3147 (rd == rB(ctx->opcode)))) {
3148 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3149 return;
3150 }
3151
3152 gen_set_access_type(ctx, ACCESS_RES);
3153 EA = tcg_temp_local_new();
3154 gen_addr_reg_index(ctx, EA);
3155 gen_check_align(ctx, EA, 15);
3156 if (unlikely(ctx->le_mode)) {
3157 gpr1 = cpu_gpr[rd+1];
3158 gpr2 = cpu_gpr[rd];
3159 } else {
3160 gpr1 = cpu_gpr[rd];
3161 gpr2 = cpu_gpr[rd+1];
3162 }
3163 tcg_gen_qemu_ld_i64(gpr1, EA, ctx->mem_idx, DEF_MEMOP(MO_Q));
3164 tcg_gen_mov_tl(cpu_reserve, EA);
3165 gen_addr_add(ctx, EA, EA, 8);
3166 tcg_gen_qemu_ld_i64(gpr2, EA, ctx->mem_idx, DEF_MEMOP(MO_Q));
3167
3168 tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val));
3169 tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2));
3170 tcg_temp_free(EA);
3171 }
3172
3173 /* stqcx. */
3174 static void gen_stqcx_(DisasContext *ctx)
3175 {
3176 TCGv EA;
3177 int reg = rS(ctx->opcode);
3178 int len = 16;
3179 #if !defined(CONFIG_USER_ONLY)
3180 TCGLabel *l1;
3181 TCGv gpr1, gpr2;
3182 #endif
3183
3184 if (unlikely((rD(ctx->opcode) & 1))) {
3185 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3186 return;
3187 }
3188 gen_set_access_type(ctx, ACCESS_RES);
3189 EA = tcg_temp_local_new();
3190 gen_addr_reg_index(ctx, EA);
3191 if (len > 1) {
3192 gen_check_align(ctx, EA, (len) - 1);
3193 }
3194
3195 #if defined(CONFIG_USER_ONLY)
3196 gen_conditional_store(ctx, EA, reg, 16);
3197 #else
3198 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3199 l1 = gen_new_label();
3200 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
3201 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ);
3202
3203 if (unlikely(ctx->le_mode)) {
3204 gpr1 = cpu_gpr[reg + 1];
3205 gpr2 = cpu_gpr[reg];
3206 } else {
3207 gpr1 = cpu_gpr[reg];
3208 gpr2 = cpu_gpr[reg + 1];
3209 }
3210 tcg_gen_qemu_st_tl(gpr1, EA, ctx->mem_idx, DEF_MEMOP(MO_Q));
3211 gen_addr_add(ctx, EA, EA, 8);
3212 tcg_gen_qemu_st_tl(gpr2, EA, ctx->mem_idx, DEF_MEMOP(MO_Q));
3213
3214 gen_set_label(l1);
3215 tcg_gen_movi_tl(cpu_reserve, -1);
3216 #endif
3217 tcg_temp_free(EA);
3218 }
3219
3220 #endif /* defined(TARGET_PPC64) */
3221
3222 /* sync */
3223 static void gen_sync(DisasContext *ctx)
3224 {
3225 uint32_t l = (ctx->opcode >> 21) & 3;
3226
3227 /*
3228 * We may need to check for a pending TLB flush.
3229 *
3230 * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32.
3231 *
3232 * Additionally, this can only happen in kernel mode however so
3233 * check MSR_PR as well.
3234 */
3235 if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) {
3236 gen_check_tlb_flush(ctx, true);
3237 }
3238 }
3239
3240 /* wait */
3241 static void gen_wait(DisasContext *ctx)
3242 {
3243 TCGv_i32 t0 = tcg_const_i32(1);
3244 tcg_gen_st_i32(t0, cpu_env,
3245 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3246 tcg_temp_free_i32(t0);
3247 /* Stop translation, as the CPU is supposed to sleep from now */
3248 gen_exception_nip(ctx, EXCP_HLT, ctx->nip);
3249 }
3250
3251 #if defined(TARGET_PPC64)
3252 static void gen_doze(DisasContext *ctx)
3253 {
3254 #if defined(CONFIG_USER_ONLY)
3255 GEN_PRIV;
3256 #else
3257 TCGv_i32 t;
3258
3259 CHK_HV;
3260 t = tcg_const_i32(PPC_PM_DOZE);
3261 gen_helper_pminsn(cpu_env, t);
3262 tcg_temp_free_i32(t);
3263 gen_stop_exception(ctx);
3264 #endif /* defined(CONFIG_USER_ONLY) */
3265 }
3266
3267 static void gen_nap(DisasContext *ctx)
3268 {
3269 #if defined(CONFIG_USER_ONLY)
3270 GEN_PRIV;
3271 #else
3272 TCGv_i32 t;
3273
3274 CHK_HV;
3275 t = tcg_const_i32(PPC_PM_NAP);
3276 gen_helper_pminsn(cpu_env, t);
3277 tcg_temp_free_i32(t);
3278 gen_stop_exception(ctx);
3279 #endif /* defined(CONFIG_USER_ONLY) */
3280 }
3281
3282 static void gen_stop(DisasContext *ctx)
3283 {
3284 gen_nap(ctx);
3285 }
3286
3287 static void gen_sleep(DisasContext *ctx)
3288 {
3289 #if defined(CONFIG_USER_ONLY)
3290 GEN_PRIV;
3291 #else
3292 TCGv_i32 t;
3293
3294 CHK_HV;
3295 t = tcg_const_i32(PPC_PM_SLEEP);
3296 gen_helper_pminsn(cpu_env, t);
3297 tcg_temp_free_i32(t);
3298 gen_stop_exception(ctx);
3299 #endif /* defined(CONFIG_USER_ONLY) */
3300 }
3301
3302 static void gen_rvwinkle(DisasContext *ctx)
3303 {
3304 #if defined(CONFIG_USER_ONLY)
3305 GEN_PRIV;
3306 #else
3307 TCGv_i32 t;
3308
3309 CHK_HV;
3310 t = tcg_const_i32(PPC_PM_RVWINKLE);
3311 gen_helper_pminsn(cpu_env, t);
3312 tcg_temp_free_i32(t);
3313 gen_stop_exception(ctx);
3314 #endif /* defined(CONFIG_USER_ONLY) */
3315 }
3316 #endif /* #if defined(TARGET_PPC64) */
3317
3318 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3319 {
3320 #if defined(TARGET_PPC64)
3321 if (ctx->has_cfar)
3322 tcg_gen_movi_tl(cpu_cfar, nip);
3323 #endif
3324 }
3325
3326 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
3327 {
3328 if (unlikely(ctx->singlestep_enabled)) {
3329 return false;
3330 }
3331
3332 #ifndef CONFIG_USER_ONLY
3333 return (ctx->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
3334 #else
3335 return true;
3336 #endif
3337 }
3338
3339 /*** Branch ***/
3340 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3341 {
3342 if (NARROW_MODE(ctx)) {
3343 dest = (uint32_t) dest;
3344 }
3345 if (use_goto_tb(ctx, dest)) {
3346 tcg_gen_goto_tb(n);
3347 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3348 tcg_gen_exit_tb((uintptr_t)ctx->tb + n);
3349 } else {
3350 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3351 if (unlikely(ctx->singlestep_enabled)) {
3352 if ((ctx->singlestep_enabled &
3353 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3354 (ctx->exception == POWERPC_EXCP_BRANCH ||
3355 ctx->exception == POWERPC_EXCP_TRACE)) {
3356 gen_exception_nip(ctx, POWERPC_EXCP_TRACE, dest);
3357 }
3358 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3359 gen_debug_exception(ctx);
3360 }
3361 }
3362 tcg_gen_exit_tb(0);
3363 }
3364 }
3365
3366 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3367 {
3368 if (NARROW_MODE(ctx)) {
3369 nip = (uint32_t)nip;
3370 }
3371 tcg_gen_movi_tl(cpu_lr, nip);
3372 }
3373
3374 /* b ba bl bla */
3375 static void gen_b(DisasContext *ctx)
3376 {
3377 target_ulong li, target;
3378
3379 ctx->exception = POWERPC_EXCP_BRANCH;
3380 /* sign extend LI */
3381 li = LI(ctx->opcode);
3382 li = (li ^ 0x02000000) - 0x02000000;
3383 if (likely(AA(ctx->opcode) == 0)) {
3384 target = ctx->nip + li - 4;
3385 } else {
3386 target = li;
3387 }
3388 if (LK(ctx->opcode)) {
3389 gen_setlr(ctx, ctx->nip);
3390 }
3391 gen_update_cfar(ctx, ctx->nip - 4);
3392 gen_goto_tb(ctx, 0, target);
3393 }
3394
3395 #define BCOND_IM 0
3396 #define BCOND_LR 1
3397 #define BCOND_CTR 2
3398 #define BCOND_TAR 3
3399
3400 static inline void gen_bcond(DisasContext *ctx, int type)
3401 {
3402 uint32_t bo = BO(ctx->opcode);
3403 TCGLabel *l1;
3404 TCGv target;
3405
3406 ctx->exception = POWERPC_EXCP_BRANCH;
3407 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3408 target = tcg_temp_local_new();
3409 if (type == BCOND_CTR)
3410 tcg_gen_mov_tl(target, cpu_ctr);
3411 else if (type == BCOND_TAR)
3412 gen_load_spr(target, SPR_TAR);
3413 else
3414 tcg_gen_mov_tl(target, cpu_lr);
3415 } else {
3416 TCGV_UNUSED(target);
3417 }
3418 if (LK(ctx->opcode))
3419 gen_setlr(ctx, ctx->nip);
3420 l1 = gen_new_label();
3421 if ((bo & 0x4) == 0) {
3422 /* Decrement and test CTR */
3423 TCGv temp = tcg_temp_new();
3424 if (unlikely(type == BCOND_CTR)) {
3425 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3426 return;
3427 }
3428 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3429 if (NARROW_MODE(ctx)) {
3430 tcg_gen_ext32u_tl(temp, cpu_ctr);
3431 } else {
3432 tcg_gen_mov_tl(temp, cpu_ctr);
3433 }
3434 if (bo & 0x2) {
3435 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3436 } else {
3437 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3438 }
3439 tcg_temp_free(temp);
3440 }
3441 if ((bo & 0x10) == 0) {
3442 /* Test CR */
3443 uint32_t bi = BI(ctx->opcode);
3444 uint32_t mask = 0x08 >> (bi & 0x03);
3445 TCGv_i32 temp = tcg_temp_new_i32();
3446
3447 if (bo & 0x8) {
3448 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3449 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3450 } else {
3451 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3452 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3453 }
3454 tcg_temp_free_i32(temp);
3455 }
3456 gen_update_cfar(ctx, ctx->nip - 4);
3457 if (type == BCOND_IM) {
3458 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3459 if (likely(AA(ctx->opcode) == 0)) {
3460 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3461 } else {
3462 gen_goto_tb(ctx, 0, li);
3463 }
3464 if ((bo & 0x14) != 0x14) {
3465 gen_set_label(l1);
3466 gen_goto_tb(ctx, 1, ctx->nip);
3467 }
3468 } else {
3469 if (NARROW_MODE(ctx)) {
3470 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3471 } else {
3472 tcg_gen_andi_tl(cpu_nip, target, ~3);
3473 }
3474 tcg_gen_exit_tb(0);
3475 if ((bo & 0x14) != 0x14) {
3476 gen_set_label(l1);
3477 gen_update_nip(ctx, ctx->nip);
3478 tcg_gen_exit_tb(0);
3479 }
3480 }
3481 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3482 tcg_temp_free(target);
3483 }
3484 }
3485
3486 static void gen_bc(DisasContext *ctx)
3487 {
3488 gen_bcond(ctx, BCOND_IM);
3489 }
3490
3491 static void gen_bcctr(DisasContext *ctx)
3492 {
3493 gen_bcond(ctx, BCOND_CTR);
3494 }
3495
3496 static void gen_bclr(DisasContext *ctx)
3497 {
3498 gen_bcond(ctx, BCOND_LR);
3499 }
3500
3501 static void gen_bctar(DisasContext *ctx)
3502 {
3503 gen_bcond(ctx, BCOND_TAR);
3504 }
3505
3506 /*** Condition register logical ***/
3507 #define GEN_CRLOGIC(name, tcg_op, opc) \
3508 static void glue(gen_, name)(DisasContext *ctx) \
3509 { \
3510 uint8_t bitmask; \
3511 int sh; \
3512 TCGv_i32 t0, t1; \
3513 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3514 t0 = tcg_temp_new_i32(); \
3515 if (sh > 0) \
3516 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3517 else if (sh < 0) \
3518 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3519 else \
3520 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3521 t1 = tcg_temp_new_i32(); \
3522 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3523 if (sh > 0) \
3524 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3525 else if (sh < 0) \
3526 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3527 else \
3528 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3529 tcg_op(t0, t0, t1); \
3530 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \
3531 tcg_gen_andi_i32(t0, t0, bitmask); \
3532 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3533 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3534 tcg_temp_free_i32(t0); \
3535 tcg_temp_free_i32(t1); \
3536 }
3537
3538 /* crand */
3539 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3540 /* crandc */
3541 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3542 /* creqv */
3543 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3544 /* crnand */
3545 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3546 /* crnor */
3547 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3548 /* cror */
3549 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3550 /* crorc */
3551 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3552 /* crxor */
3553 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3554
3555 /* mcrf */
3556 static void gen_mcrf(DisasContext *ctx)
3557 {
3558 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3559 }
3560
3561 /*** System linkage ***/
3562
3563 /* rfi (supervisor only) */
3564 static void gen_rfi(DisasContext *ctx)
3565 {
3566 #if defined(CONFIG_USER_ONLY)
3567 GEN_PRIV;
3568 #else
3569 /* This instruction doesn't exist anymore on 64-bit server
3570 * processors compliant with arch 2.x
3571 */
3572 if (ctx->insns_flags & PPC_SEGMENT_64B) {
3573 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3574 return;
3575 }
3576 /* Restore CPU state */
3577 CHK_SV;
3578 gen_update_cfar(ctx, ctx->nip - 4);
3579 gen_helper_rfi(cpu_env);
3580 gen_sync_exception(ctx);
3581 #endif
3582 }
3583
3584 #if defined(TARGET_PPC64)
3585 static void gen_rfid(DisasContext *ctx)
3586 {
3587 #if defined(CONFIG_USER_ONLY)
3588 GEN_PRIV;
3589 #else
3590 /* Restore CPU state */
3591 CHK_SV;
3592 gen_update_cfar(ctx, ctx->nip - 4);
3593 gen_helper_rfid(cpu_env);
3594 gen_sync_exception(ctx);
3595 #endif
3596 }
3597
3598 static void gen_hrfid(DisasContext *ctx)
3599 {
3600 #if defined(CONFIG_USER_ONLY)
3601 GEN_PRIV;
3602 #else
3603 /* Restore CPU state */
3604 CHK_HV;
3605 gen_helper_hrfid(cpu_env);
3606 gen_sync_exception(ctx);
3607 #endif
3608 }
3609 #endif
3610
3611 /* sc */
3612 #if defined(CONFIG_USER_ONLY)
3613 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3614 #else
3615 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3616 #endif
3617 static void gen_sc(DisasContext *ctx)
3618 {
3619 uint32_t lev;
3620
3621 lev = (ctx->opcode >> 5) & 0x7F;
3622 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
3623 }
3624
3625 /*** Trap ***/
3626
3627 /* Check for unconditional traps (always or never) */
3628 static bool check_unconditional_trap(DisasContext *ctx)
3629 {
3630 /* Trap never */
3631 if (TO(ctx->opcode) == 0) {
3632 return true;
3633 }
3634 /* Trap always */
3635 if (TO(ctx->opcode) == 31) {
3636 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
3637 return true;
3638 }
3639 return false;
3640 }
3641
3642 /* tw */
3643 static void gen_tw(DisasContext *ctx)
3644 {
3645 TCGv_i32 t0;
3646
3647 if (check_unconditional_trap(ctx)) {
3648 return;
3649 }
3650 t0 = tcg_const_i32(TO(ctx->opcode));
3651 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3652 t0);
3653 tcg_temp_free_i32(t0);
3654 }
3655
3656 /* twi */
3657 static void gen_twi(DisasContext *ctx)
3658 {
3659 TCGv t0;
3660 TCGv_i32 t1;
3661
3662 if (check_unconditional_trap(ctx)) {
3663 return;
3664 }
3665 t0 = tcg_const_tl(SIMM(ctx->opcode));
3666 t1 = tcg_const_i32(TO(ctx->opcode));
3667 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3668 tcg_temp_free(t0);
3669 tcg_temp_free_i32(t1);
3670 }
3671
3672 #if defined(TARGET_PPC64)
3673 /* td */
3674 static void gen_td(DisasContext *ctx)
3675 {
3676 TCGv_i32 t0;
3677
3678 if (check_unconditional_trap(ctx)) {
3679 return;
3680 }
3681 t0 = tcg_const_i32(TO(ctx->opcode));
3682 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3683 t0);
3684 tcg_temp_free_i32(t0);
3685 }
3686
3687 /* tdi */
3688 static void gen_tdi(DisasContext *ctx)
3689 {
3690 TCGv t0;
3691 TCGv_i32 t1;
3692
3693 if (check_unconditional_trap(ctx)) {
3694 return;
3695 }
3696 t0 = tcg_const_tl(SIMM(ctx->opcode));
3697 t1 = tcg_const_i32(TO(ctx->opcode));
3698 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3699 tcg_temp_free(t0);
3700 tcg_temp_free_i32(t1);
3701 }
3702 #endif
3703
3704 /*** Processor control ***/
3705
3706 static void gen_read_xer(TCGv dst)
3707 {
3708 TCGv t0 = tcg_temp_new();
3709 TCGv t1 = tcg_temp_new();
3710 TCGv t2 = tcg_temp_new();
3711 tcg_gen_mov_tl(dst, cpu_xer);
3712 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
3713 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
3714 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
3715 tcg_gen_or_tl(t0, t0, t1);
3716 tcg_gen_or_tl(dst, dst, t2);
3717 tcg_gen_or_tl(dst, dst, t0);
3718 tcg_temp_free(t0);
3719 tcg_temp_free(t1);
3720 tcg_temp_free(t2);
3721 }
3722
3723 static void gen_write_xer(TCGv src)
3724 {
3725 tcg_gen_andi_tl(cpu_xer, src,
3726 ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
3727 tcg_gen_extract_tl(cpu_so, src, XER_SO, 1);
3728 tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1);
3729 tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1);
3730 }
3731
3732 /* mcrxr */
3733 static void gen_mcrxr(DisasContext *ctx)
3734 {
3735 TCGv_i32 t0 = tcg_temp_new_i32();
3736 TCGv_i32 t1 = tcg_temp_new_i32();
3737 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
3738
3739 tcg_gen_trunc_tl_i32(t0, cpu_so);
3740 tcg_gen_trunc_tl_i32(t1, cpu_ov);
3741 tcg_gen_trunc_tl_i32(dst, cpu_ca);
3742 tcg_gen_shli_i32(t0, t0, 3);
3743 tcg_gen_shli_i32(t1, t1, 2);
3744 tcg_gen_shli_i32(dst, dst, 1);
3745 tcg_gen_or_i32(dst, dst, t0);
3746 tcg_gen_or_i32(dst, dst, t1);
3747 tcg_temp_free_i32(t0);
3748 tcg_temp_free_i32(t1);
3749
3750 tcg_gen_movi_tl(cpu_so, 0);
3751 tcg_gen_movi_tl(cpu_ov, 0);
3752 tcg_gen_movi_tl(cpu_ca, 0);
3753 }
3754
3755 /* mfcr mfocrf */
3756 static void gen_mfcr(DisasContext *ctx)
3757 {
3758 uint32_t crm, crn;
3759
3760 if (likely(ctx->opcode & 0x00100000)) {
3761 crm = CRM(ctx->opcode);
3762 if (likely(crm && ((crm & (crm - 1)) == 0))) {
3763 crn = ctz32 (crm);
3764 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
3765 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
3766 cpu_gpr[rD(ctx->opcode)], crn * 4);
3767 }
3768 } else {
3769 TCGv_i32 t0 = tcg_temp_new_i32();
3770 tcg_gen_mov_i32(t0, cpu_crf[0]);
3771 tcg_gen_shli_i32(t0, t0, 4);
3772 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
3773 tcg_gen_shli_i32(t0, t0, 4);
3774 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
3775 tcg_gen_shli_i32(t0, t0, 4);
3776 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
3777 tcg_gen_shli_i32(t0, t0, 4);
3778 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
3779 tcg_gen_shli_i32(t0, t0, 4);
3780 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
3781 tcg_gen_shli_i32(t0, t0, 4);
3782 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
3783 tcg_gen_shli_i32(t0, t0, 4);
3784 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
3785 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
3786 tcg_temp_free_i32(t0);
3787 }
3788 }
3789
3790 /* mfmsr */
3791 static void gen_mfmsr(DisasContext *ctx)
3792 {
3793 CHK_SV;
3794 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
3795 }
3796
3797 static void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
3798 {
3799 #if 0
3800 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3801 printf("ERROR: try to access SPR %d !\n", sprn);
3802 #endif
3803 }
3804 #define SPR_NOACCESS (&spr_noaccess)
3805
3806 /* mfspr */
3807 static inline void gen_op_mfspr(DisasContext *ctx)
3808 {
3809 void (*read_cb)(DisasContext *ctx, int gprn, int sprn);
3810 uint32_t sprn = SPR(ctx->opcode);
3811
3812 #if defined(CONFIG_USER_ONLY)
3813 read_cb = ctx->spr_cb[sprn].uea_read;
3814 #else
3815 if (ctx->pr) {
3816 read_cb = ctx->spr_cb[sprn].uea_read;
3817 } else if (ctx->hv) {
3818 read_cb = ctx->spr_cb[sprn].hea_read;
3819 } else {
3820 read_cb = ctx->spr_cb[sprn].oea_read;
3821 }
3822 #endif
3823 if (likely(read_cb != NULL)) {
3824 if (likely(read_cb != SPR_NOACCESS)) {
3825 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3826 } else {
3827 /* Privilege exception */
3828 /* This is a hack to avoid warnings when running Linux:
3829 * this OS breaks the PowerPC virtualisation model,
3830 * allowing userland application to read the PVR
3831 */
3832 if (sprn != SPR_PVR) {
3833 fprintf(stderr, "Trying to read privileged spr %d (0x%03x) at "
3834 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3835 if (qemu_log_separate()) {
3836 qemu_log("Trying to read privileged spr %d (0x%03x) at "
3837 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3838 }
3839 }
3840 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
3841 }
3842 } else {
3843 /* ISA 2.07 defines these as no-ops */
3844 if ((ctx->insns_flags2 & PPC2_ISA207S) &&
3845 (sprn >= 808 && sprn <= 811)) {
3846 /* This is a nop */
3847 return;
3848 }
3849 /* Not defined */
3850 fprintf(stderr, "Trying to read invalid spr %d (0x%03x) at "
3851 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3852 if (qemu_log_separate()) {
3853 qemu_log("Trying to read invalid spr %d (0x%03x) at "
3854 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3855 }
3856
3857 /* The behaviour depends on MSR:PR and SPR# bit 0x10,
3858 * it can generate a priv, a hv emu or a no-op
3859 */
3860 if (sprn & 0x10) {
3861 if (ctx->pr) {
3862 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3863 }
3864 } else {
3865 if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) {
3866 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3867 }
3868 }
3869 }
3870 }
3871
3872 static void gen_mfspr(DisasContext *ctx)
3873 {
3874 gen_op_mfspr(ctx);
3875 }
3876
3877 /* mftb */
3878 static void gen_mftb(DisasContext *ctx)
3879 {
3880 gen_op_mfspr(ctx);
3881 }
3882
3883 /* mtcrf mtocrf*/
3884 static void gen_mtcrf(DisasContext *ctx)
3885 {
3886 uint32_t crm, crn;
3887
3888 crm = CRM(ctx->opcode);
3889 if (likely((ctx->opcode & 0x00100000))) {
3890 if (crm && ((crm & (crm - 1)) == 0)) {
3891 TCGv_i32 temp = tcg_temp_new_i32();
3892 crn = ctz32 (crm);
3893 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3894 tcg_gen_shri_i32(temp, temp, crn * 4);
3895 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
3896 tcg_temp_free_i32(temp);
3897 }
3898 } else {
3899 TCGv_i32 temp = tcg_temp_new_i32();
3900 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3901 for (crn = 0 ; crn < 8 ; crn++) {
3902 if (crm & (1 << crn)) {
3903 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
3904 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
3905 }
3906 }
3907 tcg_temp_free_i32(temp);
3908 }
3909 }
3910
3911 /* mtmsr */
3912 #if defined(TARGET_PPC64)
3913 static void gen_mtmsrd(DisasContext *ctx)
3914 {
3915 CHK_SV;
3916
3917 #if !defined(CONFIG_USER_ONLY)
3918 if (ctx->opcode & 0x00010000) {
3919 /* Special form that does not need any synchronisation */
3920 TCGv t0 = tcg_temp_new();
3921 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3922 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
3923 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3924 tcg_temp_free(t0);
3925 } else {
3926 /* XXX: we need to update nip before the store
3927 * if we enter power saving mode, we will exit the loop
3928 * directly from ppc_store_msr
3929 */
3930 gen_update_nip(ctx, ctx->nip);
3931 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
3932 /* Must stop the translation as machine state (may have) changed */
3933 /* Note that mtmsr is not always defined as context-synchronizing */
3934 gen_stop_exception(ctx);
3935 }
3936 #endif /* !defined(CONFIG_USER_ONLY) */
3937 }
3938 #endif /* defined(TARGET_PPC64) */
3939
3940 static void gen_mtmsr(DisasContext *ctx)
3941 {
3942 CHK_SV;
3943
3944 #if !defined(CONFIG_USER_ONLY)
3945 if (ctx->opcode & 0x00010000) {
3946 /* Special form that does not need any synchronisation */
3947 TCGv t0 = tcg_temp_new();
3948 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3949 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
3950 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3951 tcg_temp_free(t0);
3952 } else {
3953 TCGv msr = tcg_temp_new();
3954
3955 /* XXX: we need to update nip before the store
3956 * if we enter power saving mode, we will exit the loop
3957 * directly from ppc_store_msr
3958 */
3959 gen_update_nip(ctx, ctx->nip);
3960 #if defined(TARGET_PPC64)
3961 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
3962 #else
3963 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
3964 #endif
3965 gen_helper_store_msr(cpu_env, msr);
3966 tcg_temp_free(msr);
3967 /* Must stop the translation as machine state (may have) changed */
3968 /* Note that mtmsr is not always defined as context-synchronizing */
3969 gen_stop_exception(ctx);
3970 }
3971 #endif
3972 }
3973
3974 /* mtspr */
3975 static void gen_mtspr(DisasContext *ctx)
3976 {
3977 void (*write_cb)(DisasContext *ctx, int sprn, int gprn);
3978 uint32_t sprn = SPR(ctx->opcode);
3979
3980 #if defined(CONFIG_USER_ONLY)
3981 write_cb = ctx->spr_cb[sprn].uea_write;
3982 #else
3983 if (ctx->pr) {
3984 write_cb = ctx->spr_cb[sprn].uea_write;
3985 } else if (ctx->hv) {
3986 write_cb = ctx->spr_cb[sprn].hea_write;
3987 } else {
3988 write_cb = ctx->spr_cb[sprn].oea_write;
3989 }
3990 #endif
3991 if (likely(write_cb != NULL)) {
3992 if (likely(write_cb != SPR_NOACCESS)) {
3993 (*write_cb)(ctx, sprn, rS(ctx->opcode));
3994 } else {
3995 /* Privilege exception */
3996 fprintf(stderr, "Trying to write privileged spr %d (0x%03x) at "
3997 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3998 if (qemu_log_separate()) {
3999 qemu_log("Trying to write privileged spr %d (0x%03x) at "
4000 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4001 }
4002 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
4003 }
4004 } else {
4005 /* ISA 2.07 defines these as no-ops */
4006 if ((ctx->insns_flags2 & PPC2_ISA207S) &&
4007 (sprn >= 808 && sprn <= 811)) {
4008 /* This is a nop */
4009 return;
4010 }
4011
4012 /* Not defined */
4013 if (qemu_log_separate()) {
4014 qemu_log("Trying to write invalid spr %d (0x%03x) at "
4015 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4016 }
4017 fprintf(stderr, "Trying to write invalid spr %d (0x%03x) at "
4018 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4019
4020
4021 /* The behaviour depends on MSR:PR and SPR# bit 0x10,
4022 * it can generate a priv, a hv emu or a no-op
4023 */
4024 if (sprn & 0x10) {
4025 if (ctx->pr) {
4026 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4027 }
4028 } else {
4029 if (ctx->pr || sprn == 0) {
4030 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4031 }
4032 }
4033 }
4034 }
4035
4036 #if defined(TARGET_PPC64)
4037 /* setb */
4038 static void gen_setb(DisasContext *ctx)
4039 {
4040 TCGv_i32 t0 = tcg_temp_new_i32();
4041 TCGv_i32 t8 = tcg_temp_new_i32();
4042 TCGv_i32 tm1 = tcg_temp_new_i32();
4043 int crf = crfS(ctx->opcode);
4044
4045 tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4);
4046 tcg_gen_movi_i32(t8, 8);
4047 tcg_gen_movi_i32(tm1, -1);
4048 tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0);
4049 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4050
4051 tcg_temp_free_i32(t0);
4052 tcg_temp_free_i32(t8);
4053 tcg_temp_free_i32(tm1);
4054 }
4055 #endif
4056
4057 /*** Cache management ***/
4058
4059 /* dcbf */
4060 static void gen_dcbf(DisasContext *ctx)
4061 {
4062 /* XXX: specification says this is treated as a load by the MMU */
4063 TCGv t0;
4064 gen_set_access_type(ctx, ACCESS_CACHE);
4065 t0 = tcg_temp_new();
4066 gen_addr_reg_index(ctx, t0);
4067 gen_qemu_ld8u(ctx, t0, t0);
4068 tcg_temp_free(t0);
4069 }
4070
4071 /* dcbi (Supervisor only) */
4072 static void gen_dcbi(DisasContext *ctx)
4073 {
4074 #if defined(CONFIG_USER_ONLY)
4075 GEN_PRIV;
4076 #else
4077 TCGv EA, val;
4078
4079 CHK_SV;
4080 EA = tcg_temp_new();
4081 gen_set_access_type(ctx, ACCESS_CACHE);
4082 gen_addr_reg_index(ctx, EA);
4083 val = tcg_temp_new();
4084 /* XXX: specification says this should be treated as a store by the MMU */
4085 gen_qemu_ld8u(ctx, val, EA);
4086 gen_qemu_st8(ctx, val, EA);
4087 tcg_temp_free(val);
4088 tcg_temp_free(EA);
4089 #endif /* defined(CONFIG_USER_ONLY) */
4090 }
4091
4092 /* dcdst */
4093 static void gen_dcbst(DisasContext *ctx)
4094 {
4095 /* XXX: specification say this is treated as a load by the MMU */
4096 TCGv t0;
4097 gen_set_access_type(ctx, ACCESS_CACHE);
4098 t0 = tcg_temp_new();
4099 gen_addr_reg_index(ctx, t0);
4100 gen_qemu_ld8u(ctx, t0, t0);
4101 tcg_temp_free(t0);
4102 }
4103
4104 /* dcbt */
4105 static void gen_dcbt(DisasContext *ctx)
4106 {
4107 /* interpreted as no-op */
4108 /* XXX: specification say this is treated as a load by the MMU
4109 * but does not generate any exception
4110 */
4111 }
4112
4113 /* dcbtst */
4114 static void gen_dcbtst(DisasContext *ctx)
4115 {
4116 /* interpreted as no-op */
4117 /* XXX: specification say this is treated as a load by the MMU
4118 * but does not generate any exception
4119 */
4120 }
4121
4122 /* dcbtls */
4123 static void gen_dcbtls(DisasContext *ctx)
4124 {
4125 /* Always fails locking the cache */
4126 TCGv t0 = tcg_temp_new();
4127 gen_load_spr(t0, SPR_Exxx_L1CSR0);
4128 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL);
4129 gen_store_spr(SPR_Exxx_L1CSR0, t0);
4130 tcg_temp_free(t0);
4131 }
4132
4133 /* dcbz */
4134 static void gen_dcbz(DisasContext *ctx)
4135 {
4136 TCGv tcgv_addr;
4137 TCGv_i32 tcgv_op;
4138
4139 gen_set_access_type(ctx, ACCESS_CACHE);
4140 tcgv_addr = tcg_temp_new();
4141 tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000);
4142 gen_addr_reg_index(ctx, tcgv_addr);
4143 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op);
4144 tcg_temp_free(tcgv_addr);
4145 tcg_temp_free_i32(tcgv_op);
4146 }
4147
4148 /* dst / dstt */
4149 static void gen_dst(DisasContext *ctx)
4150 {
4151 if (rA(ctx->opcode) == 0) {
4152 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4153 } else {
4154 /* interpreted as no-op */
4155 }
4156 }
4157
4158 /* dstst /dststt */
4159 static void gen_dstst(DisasContext *ctx)
4160 {
4161 if (rA(ctx->opcode) == 0) {
4162 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4163 } else {
4164 /* interpreted as no-op */
4165 }
4166
4167 }
4168
4169 /* dss / dssall */
4170 static void gen_dss(DisasContext *ctx)
4171 {
4172 /* interpreted as no-op */
4173 }
4174
4175 /* icbi */
4176 static void gen_icbi(DisasContext *ctx)
4177 {
4178 TCGv t0;
4179 gen_set_access_type(ctx, ACCESS_CACHE);
4180 t0 = tcg_temp_new();
4181 gen_addr_reg_index(ctx, t0);
4182 gen_helper_icbi(cpu_env, t0);
4183 tcg_temp_free(t0);
4184 }
4185
4186 /* Optional: */
4187 /* dcba */
4188 static void gen_dcba(DisasContext *ctx)
4189 {
4190 /* interpreted as no-op */
4191 /* XXX: specification say this is treated as a store by the MMU
4192 * but does not generate any exception
4193 */
4194 }
4195
4196 /*** Segment register manipulation ***/
4197 /* Supervisor only: */
4198
4199 /* mfsr */
4200 static void gen_mfsr(DisasContext *ctx)
4201 {
4202 #if defined(CONFIG_USER_ONLY)
4203 GEN_PRIV;
4204 #else
4205 TCGv t0;
4206
4207 CHK_SV;
4208 t0 = tcg_const_tl(SR(ctx->opcode));
4209 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4210 tcg_temp_free(t0);
4211 #endif /* defined(CONFIG_USER_ONLY) */
4212 }
4213
4214 /* mfsrin */
4215 static void gen_mfsrin(DisasContext *ctx)
4216 {
4217 #if defined(CONFIG_USER_ONLY)
4218 GEN_PRIV;
4219 #else
4220 TCGv t0;
4221
4222 CHK_SV;
4223 t0 = tcg_temp_new();
4224 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4225 tcg_gen_andi_tl(t0, t0, 0xF);
4226 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4227 tcg_temp_free(t0);
4228 #endif /* defined(CONFIG_USER_ONLY) */
4229 }
4230
4231 /* mtsr */
4232 static void gen_mtsr(DisasContext *ctx)
4233 {
4234 #if defined(CONFIG_USER_ONLY)
4235 GEN_PRIV;
4236 #else
4237 TCGv t0;
4238
4239 CHK_SV;
4240 t0 = tcg_const_tl(SR(ctx->opcode));
4241 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4242 tcg_temp_free(t0);
4243 #endif /* defined(CONFIG_USER_ONLY) */
4244 }
4245
4246 /* mtsrin */
4247 static void gen_mtsrin(DisasContext *ctx)
4248 {
4249 #if defined(CONFIG_USER_ONLY)
4250 GEN_PRIV;
4251 #else
4252 TCGv t0;
4253 CHK_SV;
4254
4255 t0 = tcg_temp_new();
4256 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4257 tcg_gen_andi_tl(t0, t0, 0xF);
4258 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4259 tcg_temp_free(t0);
4260 #endif /* defined(CONFIG_USER_ONLY) */
4261 }
4262
4263 #if defined(TARGET_PPC64)
4264 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4265
4266 /* mfsr */
4267 static void gen_mfsr_64b(DisasContext *ctx)
4268 {
4269 #if defined(CONFIG_USER_ONLY)
4270 GEN_PRIV;
4271 #else
4272 TCGv t0;
4273
4274 CHK_SV;
4275 t0 = tcg_const_tl(SR(ctx->opcode));
4276 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4277 tcg_temp_free(t0);
4278 #endif /* defined(CONFIG_USER_ONLY) */
4279 }
4280
4281 /* mfsrin */
4282 static void gen_mfsrin_64b(DisasContext *ctx)
4283 {
4284 #if defined(CONFIG_USER_ONLY)
4285 GEN_PRIV;
4286 #else
4287 TCGv t0;
4288
4289 CHK_SV;
4290 t0 = tcg_temp_new();
4291 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4292 tcg_gen_andi_tl(t0, t0, 0xF);
4293 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4294 tcg_temp_free(t0);
4295 #endif /* defined(CONFIG_USER_ONLY) */
4296 }
4297
4298 /* mtsr */
4299 static void gen_mtsr_64b(DisasContext *ctx)
4300 {
4301 #if defined(CONFIG_USER_ONLY)
4302 GEN_PRIV;
4303 #else
4304 TCGv t0;
4305
4306 CHK_SV;
4307 t0 = tcg_const_tl(SR(ctx->opcode));
4308 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4309 tcg_temp_free(t0);
4310 #endif /* defined(CONFIG_USER_ONLY) */
4311 }
4312
4313 /* mtsrin */
4314 static void gen_mtsrin_64b(DisasContext *ctx)
4315 {
4316 #if defined(CONFIG_USER_ONLY)
4317 GEN_PRIV;
4318 #else
4319 TCGv t0;
4320
4321 CHK_SV;
4322 t0 = tcg_temp_new();
4323 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4324 tcg_gen_andi_tl(t0, t0, 0xF);
4325 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4326 tcg_temp_free(t0);
4327 #endif /* defined(CONFIG_USER_ONLY) */
4328 }
4329
4330 /* slbmte */
4331 static void gen_slbmte(DisasContext *ctx)
4332 {
4333 #if defined(CONFIG_USER_ONLY)
4334 GEN_PRIV;
4335 #else
4336 CHK_SV;
4337
4338 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4339 cpu_gpr[rS(ctx->opcode)]);
4340 #endif /* defined(CONFIG_USER_ONLY) */
4341 }
4342
4343 static void gen_slbmfee(DisasContext *ctx)
4344 {
4345 #if defined(CONFIG_USER_ONLY)
4346 GEN_PRIV;
4347 #else
4348 CHK_SV;
4349
4350 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4351 cpu_gpr[rB(ctx->opcode)]);
4352 #endif /* defined(CONFIG_USER_ONLY) */
4353 }
4354
4355 static void gen_slbmfev(DisasContext *ctx)
4356 {
4357 #if defined(CONFIG_USER_ONLY)
4358 GEN_PRIV;
4359 #else
4360 CHK_SV;
4361
4362 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4363 cpu_gpr[rB(ctx->opcode)]);
4364 #endif /* defined(CONFIG_USER_ONLY) */
4365 }
4366
4367 static void gen_slbfee_(DisasContext *ctx)
4368 {
4369 #if defined(CONFIG_USER_ONLY)
4370 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4371 #else
4372 TCGLabel *l1, *l2;
4373
4374 if (unlikely(ctx->pr)) {
4375 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4376 return;
4377 }
4378 gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4379 cpu_gpr[rB(ctx->opcode)]);
4380 l1 = gen_new_label();
4381 l2 = gen_new_label();
4382 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
4383 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1);
4384 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ);
4385 tcg_gen_br(l2);
4386 gen_set_label(l1);
4387 tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0);
4388 gen_set_label(l2);
4389 #endif
4390 }
4391 #endif /* defined(TARGET_PPC64) */
4392
4393 /*** Lookaside buffer management ***/
4394 /* Optional & supervisor only: */
4395
4396 /* tlbia */
4397 static void gen_tlbia(DisasContext *ctx)
4398 {
4399 #if defined(CONFIG_USER_ONLY)
4400 GEN_PRIV;
4401 #else
4402 CHK_HV;
4403
4404 gen_helper_tlbia(cpu_env);
4405 #endif /* defined(CONFIG_USER_ONLY) */
4406 }
4407
4408 /* tlbiel */
4409 static void gen_tlbiel(DisasContext *ctx)
4410 {
4411 #if defined(CONFIG_USER_ONLY)
4412 GEN_PRIV;
4413 #else
4414 CHK_SV;
4415
4416 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4417 #endif /* defined(CONFIG_USER_ONLY) */
4418 }
4419
4420 /* tlbie */
4421 static void gen_tlbie(DisasContext *ctx)
4422 {
4423 #if defined(CONFIG_USER_ONLY)
4424 GEN_PRIV;
4425 #else
4426 TCGv_i32 t1;
4427 CHK_HV;
4428
4429 if (NARROW_MODE(ctx)) {
4430 TCGv t0 = tcg_temp_new();
4431 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4432 gen_helper_tlbie(cpu_env, t0);
4433 tcg_temp_free(t0);
4434 } else {
4435 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4436 }
4437 t1 = tcg_temp_new_i32();
4438 tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
4439 tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH);
4440 tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
4441 tcg_temp_free_i32(t1);
4442 #endif /* defined(CONFIG_USER_ONLY) */
4443 }
4444
4445 /* tlbsync */
4446 static void gen_tlbsync(DisasContext *ctx)
4447 {
4448 #if defined(CONFIG_USER_ONLY)
4449 GEN_PRIV;
4450 #else
4451 CHK_HV;
4452
4453 /* BookS does both ptesync and tlbsync make tlbsync a nop for server */
4454 if (ctx->insns_flags & PPC_BOOKE) {
4455 gen_check_tlb_flush(ctx, true);
4456 }
4457 #endif /* defined(CONFIG_USER_ONLY) */
4458 }
4459
4460 #if defined(TARGET_PPC64)
4461 /* slbia */
4462 static void gen_slbia(DisasContext *ctx)
4463 {
4464 #if defined(CONFIG_USER_ONLY)
4465 GEN_PRIV;
4466 #else
4467 CHK_SV;
4468
4469 gen_helper_slbia(cpu_env);
4470 #endif /* defined(CONFIG_USER_ONLY) */
4471 }
4472
4473 /* slbie */
4474 static void gen_slbie(DisasContext *ctx)
4475 {
4476 #if defined(CONFIG_USER_ONLY)
4477 GEN_PRIV;
4478 #else
4479 CHK_SV;
4480
4481 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4482 #endif /* defined(CONFIG_USER_ONLY) */
4483 }
4484
4485 /* slbieg */
4486 static void gen_slbieg(DisasContext *ctx)
4487 {
4488 #if defined(CONFIG_USER_ONLY)
4489 GEN_PRIV;
4490 #else
4491 CHK_SV;
4492
4493 gen_helper_slbieg(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4494 #endif /* defined(CONFIG_USER_ONLY) */
4495 }
4496
4497 /* slbsync */
4498 static void gen_slbsync(DisasContext *ctx)
4499 {
4500 #if defined(CONFIG_USER_ONLY)
4501 GEN_PRIV;
4502 #else
4503 CHK_SV;
4504 gen_check_tlb_flush(ctx, true);
4505 #endif /* defined(CONFIG_USER_ONLY) */
4506 }
4507
4508 #endif /* defined(TARGET_PPC64) */
4509
4510 /*** External control ***/
4511 /* Optional: */
4512
4513 /* eciwx */
4514 static void gen_eciwx(DisasContext *ctx)
4515 {
4516 TCGv t0;
4517 /* Should check EAR[E] ! */
4518 gen_set_access_type(ctx, ACCESS_EXT);
4519 t0 = tcg_temp_new();
4520 gen_addr_reg_index(ctx, t0);
4521 gen_check_align(ctx, t0, 0x03);
4522 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4523 tcg_temp_free(t0);
4524 }
4525
4526 /* ecowx */
4527 static void gen_ecowx(DisasContext *ctx)
4528 {
4529 TCGv t0;
4530 /* Should check EAR[E] ! */
4531 gen_set_access_type(ctx, ACCESS_EXT);
4532 t0 = tcg_temp_new();
4533 gen_addr_reg_index(ctx, t0);
4534 gen_check_align(ctx, t0, 0x03);
4535 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4536 tcg_temp_free(t0);
4537 }
4538
4539 /* PowerPC 601 specific instructions */
4540
4541 /* abs - abs. */
4542 static void gen_abs(DisasContext *ctx)
4543 {
4544 TCGLabel *l1 = gen_new_label();
4545 TCGLabel *l2 = gen_new_label();
4546 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4547 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4548 tcg_gen_br(l2);
4549 gen_set_label(l1);
4550 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4551 gen_set_label(l2);
4552 if (unlikely(Rc(ctx->opcode) != 0))
4553 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4554 }
4555
4556 /* abso - abso. */
4557 static void gen_abso(DisasContext *ctx)
4558 {
4559 TCGLabel *l1 = gen_new_label();
4560 TCGLabel *l2 = gen_new_label();
4561 TCGLabel *l3 = gen_new_label();
4562 /* Start with XER OV disabled, the most likely case */
4563 tcg_gen_movi_tl(cpu_ov, 0);
4564 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4565 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4566 tcg_gen_movi_tl(cpu_ov, 1);
4567 tcg_gen_movi_tl(cpu_so, 1);
4568 tcg_gen_br(l2);
4569 gen_set_label(l1);
4570 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4571 tcg_gen_br(l3);
4572 gen_set_label(l2);
4573 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4574 gen_set_label(l3);
4575 if (unlikely(Rc(ctx->opcode) != 0))
4576 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4577 }
4578
4579 /* clcs */
4580 static void gen_clcs(DisasContext *ctx)
4581 {
4582 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4583 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4584 tcg_temp_free_i32(t0);
4585 /* Rc=1 sets CR0 to an undefined state */
4586 }
4587
4588 /* div - div. */
4589 static void gen_div(DisasContext *ctx)
4590 {
4591 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4592 cpu_gpr[rB(ctx->opcode)]);
4593 if (unlikely(Rc(ctx->opcode) != 0))
4594 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4595 }
4596
4597 /* divo - divo. */
4598 static void gen_divo(DisasContext *ctx)
4599 {
4600 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4601 cpu_gpr[rB(ctx->opcode)]);
4602 if (unlikely(Rc(ctx->opcode) != 0))
4603 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4604 }
4605
4606 /* divs - divs. */
4607 static void gen_divs(DisasContext *ctx)
4608 {
4609 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4610 cpu_gpr[rB(ctx->opcode)]);
4611 if (unlikely(Rc(ctx->opcode) != 0))
4612 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4613 }
4614
4615 /* divso - divso. */
4616 static void gen_divso(DisasContext *ctx)
4617 {
4618 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
4619 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4620 if (unlikely(Rc(ctx->opcode) != 0))
4621 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4622 }
4623
4624 /* doz - doz. */
4625 static void gen_doz(DisasContext *ctx)
4626 {
4627 TCGLabel *l1 = gen_new_label();
4628 TCGLabel *l2 = gen_new_label();
4629 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4630 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4631 tcg_gen_br(l2);
4632 gen_set_label(l1);
4633 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4634 gen_set_label(l2);
4635 if (unlikely(Rc(ctx->opcode) != 0))
4636 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4637 }
4638
4639 /* dozo - dozo. */
4640 static void gen_dozo(DisasContext *ctx)
4641 {
4642 TCGLabel *l1 = gen_new_label();
4643 TCGLabel *l2 = gen_new_label();
4644 TCGv t0 = tcg_temp_new();
4645 TCGv t1 = tcg_temp_new();
4646 TCGv t2 = tcg_temp_new();
4647 /* Start with XER OV disabled, the most likely case */
4648 tcg_gen_movi_tl(cpu_ov, 0);
4649 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4650 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4651 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4652 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4653 tcg_gen_andc_tl(t1, t1, t2);
4654 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4655 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4656 tcg_gen_movi_tl(cpu_ov, 1);
4657 tcg_gen_movi_tl(cpu_so, 1);
4658 tcg_gen_br(l2);
4659 gen_set_label(l1);
4660 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4661 gen_set_label(l2);
4662 tcg_temp_free(t0);
4663 tcg_temp_free(t1);
4664 tcg_temp_free(t2);
4665 if (unlikely(Rc(ctx->opcode) != 0))
4666 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4667 }
4668
4669 /* dozi */
4670 static void gen_dozi(DisasContext *ctx)
4671 {
4672 target_long simm = SIMM(ctx->opcode);
4673 TCGLabel *l1 = gen_new_label();
4674 TCGLabel *l2 = gen_new_label();
4675 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4676 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4677 tcg_gen_br(l2);
4678 gen_set_label(l1);
4679 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4680 gen_set_label(l2);
4681 if (unlikely(Rc(ctx->opcode) != 0))
4682 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4683 }
4684
4685 /* lscbx - lscbx. */
4686 static void gen_lscbx(DisasContext *ctx)
4687 {
4688 TCGv t0 = tcg_temp_new();
4689 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4690 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4691 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4692
4693 gen_addr_reg_index(ctx, t0);
4694 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
4695 tcg_temp_free_i32(t1);
4696 tcg_temp_free_i32(t2);
4697 tcg_temp_free_i32(t3);
4698 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4699 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
4700 if (unlikely(Rc(ctx->opcode) != 0))
4701 gen_set_Rc0(ctx, t0);
4702 tcg_temp_free(t0);
4703 }
4704
4705 /* maskg - maskg. */
4706 static void gen_maskg(DisasContext *ctx)
4707 {
4708 TCGLabel *l1 = gen_new_label();
4709 TCGv t0 = tcg_temp_new();
4710 TCGv t1 = tcg_temp_new();
4711 TCGv t2 = tcg_temp_new();
4712 TCGv t3 = tcg_temp_new();
4713 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4714 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4715 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4716 tcg_gen_addi_tl(t2, t0, 1);
4717 tcg_gen_shr_tl(t2, t3, t2);
4718 tcg_gen_shr_tl(t3, t3, t1);
4719 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4720 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4721 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4722 gen_set_label(l1);
4723 tcg_temp_free(t0);
4724 tcg_temp_free(t1);
4725 tcg_temp_free(t2);
4726 tcg_temp_free(t3);
4727 if (unlikely(Rc(ctx->opcode) != 0))
4728 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4729 }
4730
4731 /* maskir - maskir. */
4732 static void gen_maskir(DisasContext *ctx)
4733 {
4734 TCGv t0 = tcg_temp_new();
4735 TCGv t1 = tcg_temp_new();
4736 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4737 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4738 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4739 tcg_temp_free(t0);
4740 tcg_temp_free(t1);
4741 if (unlikely(Rc(ctx->opcode) != 0))
4742 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4743 }
4744
4745 /* mul - mul. */
4746 static void gen_mul(DisasContext *ctx)
4747 {
4748 TCGv_i64 t0 = tcg_temp_new_i64();
4749 TCGv_i64 t1 = tcg_temp_new_i64();
4750 TCGv t2 = tcg_temp_new();
4751 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4752 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4753 tcg_gen_mul_i64(t0, t0, t1);
4754 tcg_gen_trunc_i64_tl(t2, t0);
4755 gen_store_spr(SPR_MQ, t2);
4756 tcg_gen_shri_i64(t1, t0, 32);
4757 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4758 tcg_temp_free_i64(t0);
4759 tcg_temp_free_i64(t1);
4760 tcg_temp_free(t2);
4761 if (unlikely(Rc(ctx->opcode) != 0))
4762 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4763 }
4764
4765 /* mulo - mulo. */
4766 static void gen_mulo(DisasContext *ctx)
4767 {
4768 TCGLabel *l1 = gen_new_label();
4769 TCGv_i64 t0 = tcg_temp_new_i64();
4770 TCGv_i64 t1 = tcg_temp_new_i64();
4771 TCGv t2 = tcg_temp_new();
4772 /* Start with XER OV disabled, the most likely case */
4773 tcg_gen_movi_tl(cpu_ov, 0);
4774 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4775 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4776 tcg_gen_mul_i64(t0, t0, t1);
4777 tcg_gen_trunc_i64_tl(t2, t0);
4778 gen_store_spr(SPR_MQ, t2);
4779 tcg_gen_shri_i64(t1, t0, 32);
4780 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4781 tcg_gen_ext32s_i64(t1, t0);
4782 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4783 tcg_gen_movi_tl(cpu_ov, 1);
4784 tcg_gen_movi_tl(cpu_so, 1);
4785 gen_set_label(l1);
4786 tcg_temp_free_i64(t0);
4787 tcg_temp_free_i64(t1);
4788 tcg_temp_free(t2);
4789 if (unlikely(Rc(ctx->opcode) != 0))
4790 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4791 }
4792
4793 /* nabs - nabs. */
4794 static void gen_nabs(DisasContext *ctx)
4795 {
4796 TCGLabel *l1 = gen_new_label();
4797 TCGLabel *l2 = gen_new_label();
4798 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4799 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4800 tcg_gen_br(l2);
4801 gen_set_label(l1);
4802 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4803 gen_set_label(l2);
4804 if (unlikely(Rc(ctx->opcode) != 0))
4805 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4806 }
4807
4808 /* nabso - nabso. */
4809 static void gen_nabso(DisasContext *ctx)
4810 {
4811 TCGLabel *l1 = gen_new_label();
4812 TCGLabel *l2 = gen_new_label();
4813 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4814 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4815 tcg_gen_br(l2);
4816 gen_set_label(l1);
4817 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4818 gen_set_label(l2);
4819 /* nabs never overflows */
4820 tcg_gen_movi_tl(cpu_ov, 0);
4821 if (unlikely(Rc(ctx->opcode) != 0))
4822 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4823 }
4824
4825 /* rlmi - rlmi. */
4826 static void gen_rlmi(DisasContext *ctx)
4827 {
4828 uint32_t mb = MB(ctx->opcode);
4829 uint32_t me = ME(ctx->opcode);
4830 TCGv t0 = tcg_temp_new();
4831 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4832 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4833 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4834 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4835 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4836 tcg_temp_free(t0);
4837 if (unlikely(Rc(ctx->opcode) != 0))
4838 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4839 }
4840
4841 /* rrib - rrib. */
4842 static void gen_rrib(DisasContext *ctx)
4843 {
4844 TCGv t0 = tcg_temp_new();
4845 TCGv t1 = tcg_temp_new();
4846 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4847 tcg_gen_movi_tl(t1, 0x80000000);
4848 tcg_gen_shr_tl(t1, t1, t0);
4849 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4850 tcg_gen_and_tl(t0, t0, t1);
4851 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4852 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4853 tcg_temp_free(t0);
4854 tcg_temp_free(t1);
4855 if (unlikely(Rc(ctx->opcode) != 0))
4856 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4857 }
4858
4859 /* sle - sle. */
4860 static void gen_sle(DisasContext *ctx)
4861 {
4862 TCGv t0 = tcg_temp_new();
4863 TCGv t1 = tcg_temp_new();
4864 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4865 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4866 tcg_gen_subfi_tl(t1, 32, t1);
4867 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4868 tcg_gen_or_tl(t1, t0, t1);
4869 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4870 gen_store_spr(SPR_MQ, t1);
4871 tcg_temp_free(t0);
4872 tcg_temp_free(t1);
4873 if (unlikely(Rc(ctx->opcode) != 0))
4874 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4875 }
4876
4877 /* sleq - sleq. */
4878 static void gen_sleq(DisasContext *ctx)
4879 {
4880 TCGv t0 = tcg_temp_new();
4881 TCGv t1 = tcg_temp_new();
4882 TCGv t2 = tcg_temp_new();
4883 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4884 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
4885 tcg_gen_shl_tl(t2, t2, t0);
4886 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4887 gen_load_spr(t1, SPR_MQ);
4888 gen_store_spr(SPR_MQ, t0);
4889 tcg_gen_and_tl(t0, t0, t2);
4890 tcg_gen_andc_tl(t1, t1, t2);
4891 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4892 tcg_temp_free(t0);
4893 tcg_temp_free(t1);
4894 tcg_temp_free(t2);
4895 if (unlikely(Rc(ctx->opcode) != 0))
4896 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4897 }
4898
4899 /* sliq - sliq. */
4900 static void gen_sliq(DisasContext *ctx)
4901 {
4902 int sh = SH(ctx->opcode);
4903 TCGv t0 = tcg_temp_new();
4904 TCGv t1 = tcg_temp_new();
4905 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4906 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4907 tcg_gen_or_tl(t1, t0, t1);
4908 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4909 gen_store_spr(SPR_MQ, t1);
4910 tcg_temp_free(t0);
4911 tcg_temp_free(t1);
4912 if (unlikely(Rc(ctx->opcode) != 0))
4913 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4914 }
4915
4916 /* slliq - slliq. */
4917 static void gen_slliq(DisasContext *ctx)
4918 {
4919 int sh = SH(ctx->opcode);
4920 TCGv t0 = tcg_temp_new();
4921 TCGv t1 = tcg_temp_new();
4922 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4923 gen_load_spr(t1, SPR_MQ);
4924 gen_store_spr(SPR_MQ, t0);
4925 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
4926 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
4927 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4928 tcg_temp_free(t0);
4929 tcg_temp_free(t1);
4930 if (unlikely(Rc(ctx->opcode) != 0))
4931 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4932 }
4933
4934 /* sllq - sllq. */
4935 static void gen_sllq(DisasContext *ctx)
4936 {
4937 TCGLabel *l1 = gen_new_label();
4938 TCGLabel *l2 = gen_new_label();
4939 TCGv t0 = tcg_temp_local_new();
4940 TCGv t1 = tcg_temp_local_new();
4941 TCGv t2 = tcg_temp_local_new();
4942 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4943 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4944 tcg_gen_shl_tl(t1, t1, t2);
4945 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4946 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4947 gen_load_spr(t0, SPR_MQ);
4948 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4949 tcg_gen_br(l2);
4950 gen_set_label(l1);
4951 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4952 gen_load_spr(t2, SPR_MQ);
4953 tcg_gen_andc_tl(t1, t2, t1);
4954 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4955 gen_set_label(l2);
4956 tcg_temp_free(t0);
4957 tcg_temp_free(t1);
4958 tcg_temp_free(t2);
4959 if (unlikely(Rc(ctx->opcode) != 0))
4960 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4961 }
4962
4963 /* slq - slq. */
4964 static void gen_slq(DisasContext *ctx)
4965 {
4966 TCGLabel *l1 = gen_new_label();
4967 TCGv t0 = tcg_temp_new();
4968 TCGv t1 = tcg_temp_new();
4969 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4970 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4971 tcg_gen_subfi_tl(t1, 32, t1);
4972 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4973 tcg_gen_or_tl(t1, t0, t1);
4974 gen_store_spr(SPR_MQ, t1);
4975 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
4976 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4977 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4978 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
4979 gen_set_label(l1);
4980 tcg_temp_free(t0);
4981 tcg_temp_free(t1);
4982 if (unlikely(Rc(ctx->opcode) != 0))
4983 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4984 }
4985
4986 /* sraiq - sraiq. */
4987 static void gen_sraiq(DisasContext *ctx)
4988 {
4989 int sh = SH(ctx->opcode);
4990 TCGLabel *l1 = gen_new_label();
4991 TCGv t0 = tcg_temp_new();
4992 TCGv t1 = tcg_temp_new();
4993 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4994 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4995 tcg_gen_or_tl(t0, t0, t1);
4996 gen_store_spr(SPR_MQ, t0);
4997 tcg_gen_movi_tl(cpu_ca, 0);
4998 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4999 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
5000 tcg_gen_movi_tl(cpu_ca, 1);
5001 gen_set_label(l1);
5002 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
5003 tcg_temp_free(t0);
5004 tcg_temp_free(t1);
5005 if (unlikely(Rc(ctx->opcode) != 0))
5006 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5007 }
5008
5009 /* sraq - sraq. */
5010 static void gen_sraq(DisasContext *ctx)
5011 {
5012 TCGLabel *l1 = gen_new_label();
5013 TCGLabel *l2 = gen_new_label();
5014 TCGv t0 = tcg_temp_new();
5015 TCGv t1 = tcg_temp_local_new();
5016 TCGv t2 = tcg_temp_local_new();
5017 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5018 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5019 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
5020 tcg_gen_subfi_tl(t2, 32, t2);
5021 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
5022 tcg_gen_or_tl(t0, t0, t2);
5023 gen_store_spr(SPR_MQ, t0);
5024 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5025 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
5026 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
5027 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
5028 gen_set_label(l1);
5029 tcg_temp_free(t0);
5030 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
5031 tcg_gen_movi_tl(cpu_ca, 0);
5032 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5033 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
5034 tcg_gen_movi_tl(cpu_ca, 1);
5035 gen_set_label(l2);
5036 tcg_temp_free(t1);
5037 tcg_temp_free(t2);
5038 if (unlikely(Rc(ctx->opcode) != 0))
5039 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5040 }
5041
5042 /* sre - sre. */
5043 static void gen_sre(DisasContext *ctx)
5044 {
5045 TCGv t0 = tcg_temp_new();
5046 TCGv t1 = tcg_temp_new();
5047 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5048 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5049 tcg_gen_subfi_tl(t1, 32, t1);
5050 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5051 tcg_gen_or_tl(t1, t0, t1);
5052 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5053 gen_store_spr(SPR_MQ, t1);
5054 tcg_temp_free(t0);
5055 tcg_temp_free(t1);
5056 if (unlikely(Rc(ctx->opcode) != 0))
5057 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5058 }
5059
5060 /* srea - srea. */
5061 static void gen_srea(DisasContext *ctx)
5062 {
5063 TCGv t0 = tcg_temp_new();
5064 TCGv t1 = tcg_temp_new();
5065 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5066 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5067 gen_store_spr(SPR_MQ, t0);
5068 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5069 tcg_temp_free(t0);
5070 tcg_temp_free(t1);
5071 if (unlikely(Rc(ctx->opcode) != 0))
5072 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5073 }
5074
5075 /* sreq */
5076 static void gen_sreq(DisasContext *ctx)
5077 {
5078 TCGv t0 = tcg_temp_new();
5079 TCGv t1 = tcg_temp_new();
5080 TCGv t2 = tcg_temp_new();
5081 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5082 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5083 tcg_gen_shr_tl(t1, t1, t0);
5084 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5085 gen_load_spr(t2, SPR_MQ);
5086 gen_store_spr(SPR_MQ, t0);
5087 tcg_gen_and_tl(t0, t0, t1);
5088 tcg_gen_andc_tl(t2, t2, t1);
5089 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5090 tcg_temp_free(t0);
5091 tcg_temp_free(t1);
5092 tcg_temp_free(t2);
5093 if (unlikely(Rc(ctx->opcode) != 0))
5094 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5095 }
5096
5097 /* sriq */
5098 static void gen_sriq(DisasContext *ctx)
5099 {
5100 int sh = SH(ctx->opcode);
5101 TCGv t0 = tcg_temp_new();
5102 TCGv t1 = tcg_temp_new();
5103 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5104 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5105 tcg_gen_or_tl(t1, t0, t1);
5106 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5107 gen_store_spr(SPR_MQ, t1);
5108 tcg_temp_free(t0);
5109 tcg_temp_free(t1);
5110 if (unlikely(Rc(ctx->opcode) != 0))
5111 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5112 }
5113
5114 /* srliq */
5115 static void gen_srliq(DisasContext *ctx)
5116 {
5117 int sh = SH(ctx->opcode);
5118 TCGv t0 = tcg_temp_new();
5119 TCGv t1 = tcg_temp_new();
5120 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5121 gen_load_spr(t1, SPR_MQ);
5122 gen_store_spr(SPR_MQ, t0);
5123 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5124 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5125 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5126 tcg_temp_free(t0);
5127 tcg_temp_free(t1);
5128 if (unlikely(Rc(ctx->opcode) != 0))
5129 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5130 }
5131
5132 /* srlq */
5133 static void gen_srlq(DisasContext *ctx)
5134 {
5135 TCGLabel *l1 = gen_new_label();
5136 TCGLabel *l2 = gen_new_label();
5137 TCGv t0 = tcg_temp_local_new();
5138 TCGv t1 = tcg_temp_local_new();
5139 TCGv t2 = tcg_temp_local_new();
5140 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5141 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5142 tcg_gen_shr_tl(t2, t1, t2);
5143 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5144 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5145 gen_load_spr(t0, SPR_MQ);
5146 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5147 tcg_gen_br(l2);
5148 gen_set_label(l1);
5149 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5150 tcg_gen_and_tl(t0, t0, t2);
5151 gen_load_spr(t1, SPR_MQ);
5152 tcg_gen_andc_tl(t1, t1, t2);
5153 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5154 gen_set_label(l2);
5155 tcg_temp_free(t0);
5156 tcg_temp_free(t1);
5157 tcg_temp_free(t2);
5158 if (unlikely(Rc(ctx->opcode) != 0))
5159 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5160 }
5161
5162 /* srq */
5163 static void gen_srq(DisasContext *ctx)
5164 {
5165 TCGLabel *l1 = gen_new_label();
5166 TCGv t0 = tcg_temp_new();
5167 TCGv t1 = tcg_temp_new();
5168 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5169 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5170 tcg_gen_subfi_tl(t1, 32, t1);
5171 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5172 tcg_gen_or_tl(t1, t0, t1);
5173 gen_store_spr(SPR_MQ, t1);
5174 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5175 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5176 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5177 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5178 gen_set_label(l1);
5179 tcg_temp_free(t0);
5180 tcg_temp_free(t1);
5181 if (unlikely(Rc(ctx->opcode) != 0))
5182 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5183 }
5184
5185 /* PowerPC 602 specific instructions */
5186
5187 /* dsa */
5188 static void gen_dsa(DisasContext *ctx)
5189 {
5190 /* XXX: TODO */
5191 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5192 }
5193
5194 /* esa */
5195 static void gen_esa(DisasContext *ctx)
5196 {
5197 /* XXX: TODO */
5198 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5199 }
5200
5201 /* mfrom */
5202 static void gen_mfrom(DisasContext *ctx)
5203 {
5204 #if defined(CONFIG_USER_ONLY)
5205 GEN_PRIV;
5206 #else
5207 CHK_SV;
5208 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5209 #endif /* defined(CONFIG_USER_ONLY) */
5210 }
5211
5212 /* 602 - 603 - G2 TLB management */
5213
5214 /* tlbld */
5215 static void gen_tlbld_6xx(DisasContext *ctx)
5216 {
5217 #if defined(CONFIG_USER_ONLY)
5218 GEN_PRIV;
5219 #else
5220 CHK_SV;
5221 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5222 #endif /* defined(CONFIG_USER_ONLY) */
5223 }
5224
5225 /* tlbli */
5226 static void gen_tlbli_6xx(DisasContext *ctx)
5227 {
5228 #if defined(CONFIG_USER_ONLY)
5229 GEN_PRIV;
5230 #else
5231 CHK_SV;
5232 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5233 #endif /* defined(CONFIG_USER_ONLY) */
5234 }
5235
5236 /* 74xx TLB management */
5237
5238 /* tlbld */
5239 static void gen_tlbld_74xx(DisasContext *ctx)
5240 {
5241 #if defined(CONFIG_USER_ONLY)
5242 GEN_PRIV;
5243 #else
5244 CHK_SV;
5245 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5246 #endif /* defined(CONFIG_USER_ONLY) */
5247 }
5248
5249 /* tlbli */
5250 static void gen_tlbli_74xx(DisasContext *ctx)
5251 {
5252 #if defined(CONFIG_USER_ONLY)
5253 GEN_PRIV;
5254 #else
5255 CHK_SV;
5256 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5257 #endif /* defined(CONFIG_USER_ONLY) */
5258 }
5259
5260 /* POWER instructions not in PowerPC 601 */
5261
5262 /* clf */
5263 static void gen_clf(DisasContext *ctx)
5264 {
5265 /* Cache line flush: implemented as no-op */
5266 }
5267
5268 /* cli */
5269 static void gen_cli(DisasContext *ctx)
5270 {
5271 #if defined(CONFIG_USER_ONLY)
5272 GEN_PRIV;
5273 #else
5274 /* Cache line invalidate: privileged and treated as no-op */
5275 CHK_SV;
5276 #endif /* defined(CONFIG_USER_ONLY) */
5277 }
5278
5279 /* dclst */
5280 static void gen_dclst(DisasContext *ctx)
5281 {
5282 /* Data cache line store: treated as no-op */
5283 }
5284
5285 static void gen_mfsri(DisasContext *ctx)
5286 {
5287 #if defined(CONFIG_USER_ONLY)
5288 GEN_PRIV;
5289 #else
5290 int ra = rA(ctx->opcode);
5291 int rd = rD(ctx->opcode);
5292 TCGv t0;
5293
5294 CHK_SV;
5295 t0 = tcg_temp_new();
5296 gen_addr_reg_index(ctx, t0);
5297 tcg_gen_shri_tl(t0, t0, 28);
5298 tcg_gen_andi_tl(t0, t0, 0xF);
5299 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5300 tcg_temp_free(t0);
5301 if (ra != 0 && ra != rd)
5302 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5303 #endif /* defined(CONFIG_USER_ONLY) */
5304 }
5305
5306 static void gen_rac(DisasContext *ctx)
5307 {
5308 #if defined(CONFIG_USER_ONLY)
5309 GEN_PRIV;
5310 #else
5311 TCGv t0;
5312
5313 CHK_SV;
5314 t0 = tcg_temp_new();
5315 gen_addr_reg_index(ctx, t0);
5316 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5317 tcg_temp_free(t0);
5318 #endif /* defined(CONFIG_USER_ONLY) */
5319 }
5320
5321 static void gen_rfsvc(DisasContext *ctx)
5322 {
5323 #if defined(CONFIG_USER_ONLY)
5324 GEN_PRIV;
5325 #else
5326 CHK_SV;
5327
5328 gen_helper_rfsvc(cpu_env);
5329 gen_sync_exception(ctx);
5330 #endif /* defined(CONFIG_USER_ONLY) */
5331 }
5332
5333 /* svc is not implemented for now */
5334
5335 /* BookE specific instructions */
5336
5337 /* XXX: not implemented on 440 ? */
5338 static void gen_mfapidi(DisasContext *ctx)
5339 {
5340 /* XXX: TODO */
5341 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5342 }
5343
5344 /* XXX: not implemented on 440 ? */
5345 static void gen_tlbiva(DisasContext *ctx)
5346 {
5347 #if defined(CONFIG_USER_ONLY)
5348 GEN_PRIV;
5349 #else
5350 TCGv t0;
5351
5352 CHK_SV;
5353 t0 = tcg_temp_new();
5354 gen_addr_reg_index(ctx, t0);
5355 gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5356 tcg_temp_free(t0);
5357 #endif /* defined(CONFIG_USER_ONLY) */
5358 }
5359
5360 /* All 405 MAC instructions are translated here */
5361 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5362 int ra, int rb, int rt, int Rc)
5363 {
5364 TCGv t0, t1;
5365
5366 t0 = tcg_temp_local_new();
5367 t1 = tcg_temp_local_new();
5368
5369 switch (opc3 & 0x0D) {
5370 case 0x05:
5371 /* macchw - macchw. - macchwo - macchwo. */
5372 /* macchws - macchws. - macchwso - macchwso. */
5373 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5374 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5375 /* mulchw - mulchw. */
5376 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5377 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5378 tcg_gen_ext16s_tl(t1, t1);
5379 break;
5380 case 0x04:
5381 /* macchwu - macchwu. - macchwuo - macchwuo. */
5382 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5383 /* mulchwu - mulchwu. */
5384 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5385 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5386 tcg_gen_ext16u_tl(t1, t1);
5387 break;
5388 case 0x01:
5389 /* machhw - machhw. - machhwo - machhwo. */
5390 /* machhws - machhws. - machhwso - machhwso. */
5391 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5392 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5393 /* mulhhw - mulhhw. */
5394 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5395 tcg_gen_ext16s_tl(t0, t0);
5396 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5397 tcg_gen_ext16s_tl(t1, t1);
5398 break;
5399 case 0x00:
5400 /* machhwu - machhwu. - machhwuo - machhwuo. */
5401 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5402 /* mulhhwu - mulhhwu. */
5403 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5404 tcg_gen_ext16u_tl(t0, t0);
5405 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5406 tcg_gen_ext16u_tl(t1, t1);
5407 break;
5408 case 0x0D:
5409 /* maclhw - maclhw. - maclhwo - maclhwo. */
5410 /* maclhws - maclhws. - maclhwso - maclhwso. */
5411 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5412 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5413 /* mullhw - mullhw. */
5414 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5415 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5416 break;
5417 case 0x0C:
5418 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5419 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5420 /* mullhwu - mullhwu. */
5421 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5422 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5423 break;
5424 }
5425 if (opc2 & 0x04) {
5426 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5427 tcg_gen_mul_tl(t1, t0, t1);
5428 if (opc2 & 0x02) {
5429 /* nmultiply-and-accumulate (0x0E) */
5430 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5431 } else {
5432 /* multiply-and-accumulate (0x0C) */
5433 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5434 }
5435
5436 if (opc3 & 0x12) {
5437 /* Check overflow and/or saturate */
5438 TCGLabel *l1 = gen_new_label();
5439
5440 if (opc3 & 0x10) {
5441 /* Start with XER OV disabled, the most likely case */
5442 tcg_gen_movi_tl(cpu_ov, 0);
5443 }
5444 if (opc3 & 0x01) {
5445 /* Signed */
5446 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5447 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5448 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5449 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5450 if (opc3 & 0x02) {
5451 /* Saturate */
5452 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5453 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5454 }
5455 } else {
5456 /* Unsigned */
5457 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5458 if (opc3 & 0x02) {
5459 /* Saturate */
5460 tcg_gen_movi_tl(t0, UINT32_MAX);
5461 }
5462 }
5463 if (opc3 & 0x10) {
5464 /* Check overflow */
5465 tcg_gen_movi_tl(cpu_ov, 1);
5466 tcg_gen_movi_tl(cpu_so, 1);
5467 }
5468 gen_set_label(l1);
5469 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5470 }
5471 } else {
5472 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5473 }
5474 tcg_temp_free(t0);
5475 tcg_temp_free(t1);
5476 if (unlikely(Rc) != 0) {
5477 /* Update Rc0 */
5478 gen_set_Rc0(ctx, cpu_gpr[rt]);
5479 }
5480 }
5481
5482 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5483 static void glue(gen_, name)(DisasContext *ctx) \
5484 { \
5485 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5486 rD(ctx->opcode), Rc(ctx->opcode)); \
5487 }
5488
5489 /* macchw - macchw. */
5490 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5491 /* macchwo - macchwo. */
5492 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5493 /* macchws - macchws. */
5494 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5495 /* macchwso - macchwso. */
5496 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5497 /* macchwsu - macchwsu. */
5498 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5499 /* macchwsuo - macchwsuo. */
5500 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5501 /* macchwu - macchwu. */
5502 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5503 /* macchwuo - macchwuo. */
5504 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5505 /* machhw - machhw. */
5506 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5507 /* machhwo - machhwo. */
5508 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5509 /* machhws - machhws. */
5510 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5511 /* machhwso - machhwso. */
5512 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5513 /* machhwsu - machhwsu. */
5514 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5515 /* machhwsuo - machhwsuo. */
5516 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5517 /* machhwu - machhwu. */
5518 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5519 /* machhwuo - machhwuo. */
5520 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5521 /* maclhw - maclhw. */
5522 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5523 /* maclhwo - maclhwo. */
5524 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5525 /* maclhws - maclhws. */
5526 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5527 /* maclhwso - maclhwso. */
5528 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5529 /* maclhwu - maclhwu. */
5530 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5531 /* maclhwuo - maclhwuo. */
5532 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5533 /* maclhwsu - maclhwsu. */
5534 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5535 /* maclhwsuo - maclhwsuo. */
5536 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5537 /* nmacchw - nmacchw. */
5538 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5539 /* nmacchwo - nmacchwo. */
5540 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5541 /* nmacchws - nmacchws. */
5542 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5543 /* nmacchwso - nmacchwso. */
5544 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5545 /* nmachhw - nmachhw. */
5546 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5547 /* nmachhwo - nmachhwo. */
5548 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5549 /* nmachhws - nmachhws. */
5550 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5551 /* nmachhwso - nmachhwso. */
5552 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5553 /* nmaclhw - nmaclhw. */
5554 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5555 /* nmaclhwo - nmaclhwo. */
5556 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5557 /* nmaclhws - nmaclhws. */
5558 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5559 /* nmaclhwso - nmaclhwso. */
5560 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5561
5562 /* mulchw - mulchw. */
5563 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5564 /* mulchwu - mulchwu. */
5565 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5566 /* mulhhw - mulhhw. */
5567 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5568 /* mulhhwu - mulhhwu. */
5569 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5570 /* mullhw - mullhw. */
5571 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5572 /* mullhwu - mullhwu. */
5573 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5574
5575 /* mfdcr */
5576 static void gen_mfdcr(DisasContext *ctx)
5577 {
5578 #if defined(CONFIG_USER_ONLY)
5579 GEN_PRIV;
5580 #else
5581 TCGv dcrn;
5582
5583 CHK_SV;
5584 dcrn = tcg_const_tl(SPR(ctx->opcode));
5585 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
5586 tcg_temp_free(dcrn);
5587 #endif /* defined(CONFIG_USER_ONLY) */
5588 }
5589
5590 /* mtdcr */
5591 static void gen_mtdcr(DisasContext *ctx)
5592 {
5593 #if defined(CONFIG_USER_ONLY)
5594 GEN_PRIV;
5595 #else
5596 TCGv dcrn;
5597
5598 CHK_SV;
5599 dcrn = tcg_const_tl(SPR(ctx->opcode));
5600 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
5601 tcg_temp_free(dcrn);
5602 #endif /* defined(CONFIG_USER_ONLY) */
5603 }
5604
5605 /* mfdcrx */
5606 /* XXX: not implemented on 440 ? */
5607 static void gen_mfdcrx(DisasContext *ctx)
5608 {
5609 #if defined(CONFIG_USER_ONLY)
5610 GEN_PRIV;
5611 #else
5612 CHK_SV;
5613 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5614 cpu_gpr[rA(ctx->opcode)]);
5615 /* Note: Rc update flag set leads to undefined state of Rc0 */
5616 #endif /* defined(CONFIG_USER_ONLY) */
5617 }
5618
5619 /* mtdcrx */
5620 /* XXX: not implemented on 440 ? */
5621 static void gen_mtdcrx(DisasContext *ctx)
5622 {
5623 #if defined(CONFIG_USER_ONLY)
5624 GEN_PRIV;
5625 #else
5626 CHK_SV;
5627 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5628 cpu_gpr[rS(ctx->opcode)]);
5629 /* Note: Rc update flag set leads to undefined state of Rc0 */
5630 #endif /* defined(CONFIG_USER_ONLY) */
5631 }
5632
5633 /* mfdcrux (PPC 460) : user-mode access to DCR */
5634 static void gen_mfdcrux(DisasContext *ctx)
5635 {
5636 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5637 cpu_gpr[rA(ctx->opcode)]);
5638 /* Note: Rc update flag set leads to undefined state of Rc0 */
5639 }
5640
5641 /* mtdcrux (PPC 460) : user-mode access to DCR */
5642 static void gen_mtdcrux(DisasContext *ctx)
5643 {
5644 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5645 cpu_gpr[rS(ctx->opcode)]);
5646 /* Note: Rc update flag set leads to undefined state of Rc0 */
5647 }
5648
5649 /* dccci */
5650 static void gen_dccci(DisasContext *ctx)
5651 {
5652 CHK_SV;
5653 /* interpreted as no-op */
5654 }
5655
5656 /* dcread */
5657 static void gen_dcread(DisasContext *ctx)
5658 {
5659 #if defined(CONFIG_USER_ONLY)
5660 GEN_PRIV;
5661 #else
5662 TCGv EA, val;
5663
5664 CHK_SV;
5665 gen_set_access_type(ctx, ACCESS_CACHE);
5666 EA = tcg_temp_new();
5667 gen_addr_reg_index(ctx, EA);
5668 val = tcg_temp_new();
5669 gen_qemu_ld32u(ctx, val, EA);
5670 tcg_temp_free(val);
5671 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5672 tcg_temp_free(EA);
5673 #endif /* defined(CONFIG_USER_ONLY) */
5674 }
5675
5676 /* icbt */
5677 static void gen_icbt_40x(DisasContext *ctx)
5678 {
5679 /* interpreted as no-op */
5680 /* XXX: specification say this is treated as a load by the MMU
5681 * but does not generate any exception
5682 */
5683 }
5684
5685 /* iccci */
5686 static void gen_iccci(DisasContext *ctx)
5687 {
5688 CHK_SV;
5689 /* interpreted as no-op */
5690 }
5691
5692 /* icread */
5693 static void gen_icread(DisasContext *ctx)
5694 {
5695 CHK_SV;
5696 /* interpreted as no-op */
5697 }
5698
5699 /* rfci (supervisor only) */
5700 static void gen_rfci_40x(DisasContext *ctx)
5701 {
5702 #if defined(CONFIG_USER_ONLY)
5703 GEN_PRIV;
5704 #else
5705 CHK_SV;
5706 /* Restore CPU state */
5707 gen_helper_40x_rfci(cpu_env);
5708 gen_sync_exception(ctx);
5709 #endif /* defined(CONFIG_USER_ONLY) */
5710 }
5711
5712 static void gen_rfci(DisasContext *ctx)
5713 {
5714 #if defined(CONFIG_USER_ONLY)
5715 GEN_PRIV;
5716 #else
5717 CHK_SV;
5718 /* Restore CPU state */
5719 gen_helper_rfci(cpu_env);
5720 gen_sync_exception(ctx);
5721 #endif /* defined(CONFIG_USER_ONLY) */
5722 }
5723
5724 /* BookE specific */
5725
5726 /* XXX: not implemented on 440 ? */
5727 static void gen_rfdi(DisasContext *ctx)
5728 {
5729 #if defined(CONFIG_USER_ONLY)
5730 GEN_PRIV;
5731 #else
5732 CHK_SV;
5733 /* Restore CPU state */
5734 gen_helper_rfdi(cpu_env);
5735 gen_sync_exception(ctx);
5736 #endif /* defined(CONFIG_USER_ONLY) */
5737 }
5738
5739 /* XXX: not implemented on 440 ? */
5740 static void gen_rfmci(DisasContext *ctx)
5741 {
5742 #if defined(CONFIG_USER_ONLY)
5743 GEN_PRIV;
5744 #else
5745 CHK_SV;
5746 /* Restore CPU state */
5747 gen_helper_rfmci(cpu_env);
5748 gen_sync_exception(ctx);
5749 #endif /* defined(CONFIG_USER_ONLY) */
5750 }
5751
5752 /* TLB management - PowerPC 405 implementation */
5753
5754 /* tlbre */
5755 static void gen_tlbre_40x(DisasContext *ctx)
5756 {
5757 #if defined(CONFIG_USER_ONLY)
5758 GEN_PRIV;
5759 #else
5760 CHK_SV;
5761 switch (rB(ctx->opcode)) {
5762 case 0:
5763 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
5764 cpu_gpr[rA(ctx->opcode)]);
5765 break;
5766 case 1:
5767 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
5768 cpu_gpr[rA(ctx->opcode)]);
5769 break;
5770 default:
5771 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5772 break;
5773 }
5774 #endif /* defined(CONFIG_USER_ONLY) */
5775 }
5776
5777 /* tlbsx - tlbsx. */
5778 static void gen_tlbsx_40x(DisasContext *ctx)
5779 {
5780 #if defined(CONFIG_USER_ONLY)
5781 GEN_PRIV;
5782 #else
5783 TCGv t0;
5784
5785 CHK_SV;
5786 t0 = tcg_temp_new();
5787 gen_addr_reg_index(ctx, t0);
5788 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5789 tcg_temp_free(t0);
5790 if (Rc(ctx->opcode)) {
5791 TCGLabel *l1 = gen_new_label();
5792 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5793 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5794 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5795 gen_set_label(l1);
5796 }
5797 #endif /* defined(CONFIG_USER_ONLY) */
5798 }
5799
5800 /* tlbwe */
5801 static void gen_tlbwe_40x(DisasContext *ctx)
5802 {
5803 #if defined(CONFIG_USER_ONLY)
5804 GEN_PRIV;
5805 #else
5806 CHK_SV;
5807
5808 switch (rB(ctx->opcode)) {
5809 case 0:
5810 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
5811 cpu_gpr[rS(ctx->opcode)]);
5812 break;
5813 case 1:
5814 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
5815 cpu_gpr[rS(ctx->opcode)]);
5816 break;
5817 default:
5818 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5819 break;
5820 }
5821 #endif /* defined(CONFIG_USER_ONLY) */
5822 }
5823
5824 /* TLB management - PowerPC 440 implementation */
5825
5826 /* tlbre */
5827 static void gen_tlbre_440(DisasContext *ctx)
5828 {
5829 #if defined(CONFIG_USER_ONLY)
5830 GEN_PRIV;
5831 #else
5832 CHK_SV;
5833
5834 switch (rB(ctx->opcode)) {
5835 case 0:
5836 case 1:
5837 case 2:
5838 {
5839 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5840 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
5841 t0, cpu_gpr[rA(ctx->opcode)]);
5842 tcg_temp_free_i32(t0);
5843 }
5844 break;
5845 default:
5846 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5847 break;
5848 }
5849 #endif /* defined(CONFIG_USER_ONLY) */
5850 }
5851
5852 /* tlbsx - tlbsx. */
5853 static void gen_tlbsx_440(DisasContext *ctx)
5854 {
5855 #if defined(CONFIG_USER_ONLY)
5856 GEN_PRIV;
5857 #else
5858 TCGv t0;
5859
5860 CHK_SV;
5861 t0 = tcg_temp_new();
5862 gen_addr_reg_index(ctx, t0);
5863 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5864 tcg_temp_free(t0);
5865 if (Rc(ctx->opcode)) {
5866 TCGLabel *l1 = gen_new_label();
5867 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5868 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5869 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5870 gen_set_label(l1);
5871 }
5872 #endif /* defined(CONFIG_USER_ONLY) */
5873 }
5874
5875 /* tlbwe */
5876 static void gen_tlbwe_440(DisasContext *ctx)
5877 {
5878 #if defined(CONFIG_USER_ONLY)
5879 GEN_PRIV;
5880 #else
5881 CHK_SV;
5882 switch (rB(ctx->opcode)) {
5883 case 0:
5884 case 1:
5885 case 2:
5886 {
5887 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5888 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
5889 cpu_gpr[rS(ctx->opcode)]);
5890 tcg_temp_free_i32(t0);
5891 }
5892 break;
5893 default:
5894 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5895 break;
5896 }
5897 #endif /* defined(CONFIG_USER_ONLY) */
5898 }
5899
5900 /* TLB management - PowerPC BookE 2.06 implementation */
5901
5902 /* tlbre */
5903 static void gen_tlbre_booke206(DisasContext *ctx)
5904 {
5905 #if defined(CONFIG_USER_ONLY)
5906 GEN_PRIV;
5907 #else
5908 CHK_SV;
5909 gen_helper_booke206_tlbre(cpu_env);
5910 #endif /* defined(CONFIG_USER_ONLY) */
5911 }
5912
5913 /* tlbsx - tlbsx. */
5914 static void gen_tlbsx_booke206(DisasContext *ctx)
5915 {
5916 #if defined(CONFIG_USER_ONLY)
5917 GEN_PRIV;
5918 #else
5919 TCGv t0;
5920
5921 CHK_SV;
5922 if (rA(ctx->opcode)) {
5923 t0 = tcg_temp_new();
5924 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
5925 } else {
5926 t0 = tcg_const_tl(0);
5927 }
5928
5929 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
5930 gen_helper_booke206_tlbsx(cpu_env, t0);
5931 tcg_temp_free(t0);
5932 #endif /* defined(CONFIG_USER_ONLY) */
5933 }
5934
5935 /* tlbwe */
5936 static void gen_tlbwe_booke206(DisasContext *ctx)
5937 {
5938 #if defined(CONFIG_USER_ONLY)
5939 GEN_PRIV;
5940 #else
5941 CHK_SV;
5942 gen_helper_booke206_tlbwe(cpu_env);
5943 #endif /* defined(CONFIG_USER_ONLY) */
5944 }
5945
5946 static void gen_tlbivax_booke206(DisasContext *ctx)
5947 {
5948 #if defined(CONFIG_USER_ONLY)
5949 GEN_PRIV;
5950 #else
5951 TCGv t0;
5952
5953 CHK_SV;
5954 t0 = tcg_temp_new();
5955 gen_addr_reg_index(ctx, t0);
5956 gen_helper_booke206_tlbivax(cpu_env, t0);
5957 tcg_temp_free(t0);
5958 #endif /* defined(CONFIG_USER_ONLY) */
5959 }
5960
5961 static void gen_tlbilx_booke206(DisasContext *ctx)
5962 {
5963 #if defined(CONFIG_USER_ONLY)
5964 GEN_PRIV;
5965 #else
5966 TCGv t0;
5967
5968 CHK_SV;
5969 t0 = tcg_temp_new();
5970 gen_addr_reg_index(ctx, t0);
5971
5972 switch((ctx->opcode >> 21) & 0x3) {
5973 case 0:
5974 gen_helper_booke206_tlbilx0(cpu_env, t0);
5975 break;
5976 case 1:
5977 gen_helper_booke206_tlbilx1(cpu_env, t0);
5978 break;
5979 case 3:
5980 gen_helper_booke206_tlbilx3(cpu_env, t0);
5981 break;
5982 default:
5983 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5984 break;
5985 }
5986
5987 tcg_temp_free(t0);
5988 #endif /* defined(CONFIG_USER_ONLY) */
5989 }
5990
5991
5992 /* wrtee */
5993 static void gen_wrtee(DisasContext *ctx)
5994 {
5995 #if defined(CONFIG_USER_ONLY)
5996 GEN_PRIV;
5997 #else
5998 TCGv t0;
5999
6000 CHK_SV;
6001 t0 = tcg_temp_new();
6002 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6003 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6004 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6005 tcg_temp_free(t0);
6006 /* Stop translation to have a chance to raise an exception
6007 * if we just set msr_ee to 1
6008 */
6009 gen_stop_exception(ctx);
6010 #endif /* defined(CONFIG_USER_ONLY) */
6011 }
6012
6013 /* wrteei */
6014 static void gen_wrteei(DisasContext *ctx)
6015 {
6016 #if defined(CONFIG_USER_ONLY)
6017 GEN_PRIV;
6018 #else
6019 CHK_SV;
6020 if (ctx->opcode & 0x00008000) {
6021 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6022 /* Stop translation to have a chance to raise an exception */
6023 gen_stop_exception(ctx);
6024 } else {
6025 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6026 }
6027 #endif /* defined(CONFIG_USER_ONLY) */
6028 }
6029
6030 /* PowerPC 440 specific instructions */
6031
6032 /* dlmzb */
6033 static void gen_dlmzb(DisasContext *ctx)
6034 {
6035 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6036 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6037 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6038 tcg_temp_free_i32(t0);
6039 }
6040
6041 /* mbar replaces eieio on 440 */
6042 static void gen_mbar(DisasContext *ctx)
6043 {
6044 /* interpreted as no-op */
6045 }
6046
6047 /* msync replaces sync on 440 */
6048 static void gen_msync_4xx(DisasContext *ctx)
6049 {
6050 /* interpreted as no-op */
6051 }
6052
6053 /* icbt */
6054 static void gen_icbt_440(DisasContext *ctx)
6055 {
6056 /* interpreted as no-op */
6057 /* XXX: specification say this is treated as a load by the MMU
6058 * but does not generate any exception
6059 */
6060 }
6061
6062 /* Embedded.Processor Control */
6063
6064 static void gen_msgclr(DisasContext *ctx)
6065 {
6066 #if defined(CONFIG_USER_ONLY)
6067 GEN_PRIV;
6068 #else
6069 CHK_SV;
6070 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6071 #endif /* defined(CONFIG_USER_ONLY) */
6072 }
6073
6074 static void gen_msgsnd(DisasContext *ctx)
6075 {
6076 #if defined(CONFIG_USER_ONLY)
6077 GEN_PRIV;
6078 #else
6079 CHK_SV;
6080 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6081 #endif /* defined(CONFIG_USER_ONLY) */
6082 }
6083
6084
6085 #if defined(TARGET_PPC64)
6086 static void gen_maddld(DisasContext *ctx)
6087 {
6088 TCGv_i64 t1 = tcg_temp_new_i64();
6089
6090 tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6091 tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]);
6092 tcg_temp_free_i64(t1);
6093 }
6094
6095 /* maddhd maddhdu */
6096 static void gen_maddhd_maddhdu(DisasContext *ctx)
6097 {
6098 TCGv_i64 lo = tcg_temp_new_i64();
6099 TCGv_i64 hi = tcg_temp_new_i64();
6100 TCGv_i64 t1 = tcg_temp_new_i64();
6101
6102 if (Rc(ctx->opcode)) {
6103 tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
6104 cpu_gpr[rB(ctx->opcode)]);
6105 tcg_gen_movi_i64(t1, 0);
6106 } else {
6107 tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
6108 cpu_gpr[rB(ctx->opcode)]);
6109 tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63);
6110 }
6111 tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi,
6112 cpu_gpr[rC(ctx->opcode)], t1);
6113 tcg_temp_free_i64(lo);
6114 tcg_temp_free_i64(hi);
6115 tcg_temp_free_i64(t1);
6116 }
6117 #endif /* defined(TARGET_PPC64) */
6118
6119 static void gen_tbegin(DisasContext *ctx)
6120 {
6121 if (unlikely(!ctx->tm_enabled)) {
6122 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
6123 return;
6124 }
6125 gen_helper_tbegin(cpu_env);
6126 }
6127
6128 #define GEN_TM_NOOP(name) \
6129 static inline void gen_##name(DisasContext *ctx) \
6130 { \
6131 if (unlikely(!ctx->tm_enabled)) { \
6132 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
6133 return; \
6134 } \
6135 /* Because tbegin always fails in QEMU, these user \
6136 * space instructions all have a simple implementation: \
6137 * \
6138 * CR[0] = 0b0 || MSR[TS] || 0b0 \
6139 * = 0b0 || 0b00 || 0b0 \
6140 */ \
6141 tcg_gen_movi_i32(cpu_crf[0], 0); \
6142 }
6143
6144 GEN_TM_NOOP(tend);
6145 GEN_TM_NOOP(tabort);
6146 GEN_TM_NOOP(tabortwc);
6147 GEN_TM_NOOP(tabortwci);
6148 GEN_TM_NOOP(tabortdc);
6149 GEN_TM_NOOP(tabortdci);
6150 GEN_TM_NOOP(tsr);
6151 static inline void gen_cp_abort(DisasContext *ctx)
6152 {
6153 // Do Nothing
6154 }
6155
6156 #define GEN_CP_PASTE_NOOP(name) \
6157 static inline void gen_##name(DisasContext *ctx) \
6158 { \
6159 /* Generate invalid exception until \
6160 * we have an implementation of the copy \
6161 * paste facility \
6162 */ \
6163 gen_invalid(ctx); \
6164 }
6165
6166 GEN_CP_PASTE_NOOP(copy)
6167 GEN_CP_PASTE_NOOP(paste)
6168
6169 static void gen_tcheck(DisasContext *ctx)
6170 {
6171 if (unlikely(!ctx->tm_enabled)) {
6172 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
6173 return;
6174 }
6175 /* Because tbegin always fails, the tcheck implementation
6176 * is simple:
6177 *
6178 * CR[CRF] = TDOOMED || MSR[TS] || 0b0
6179 * = 0b1 || 0b00 || 0b0
6180 */
6181 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8);
6182 }
6183
6184 #if defined(CONFIG_USER_ONLY)
6185 #define GEN_TM_PRIV_NOOP(name) \
6186 static inline void gen_##name(DisasContext *ctx) \
6187 { \
6188 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
6189 }
6190
6191 #else
6192
6193 #define GEN_TM_PRIV_NOOP(name) \
6194 static inline void gen_##name(DisasContext *ctx) \
6195 { \
6196 CHK_SV; \
6197 if (unlikely(!ctx->tm_enabled)) { \
6198 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
6199 return; \
6200 } \
6201 /* Because tbegin always fails, the implementation is \
6202 * simple: \
6203 * \
6204 * CR[0] = 0b0 || MSR[TS] || 0b0 \
6205 * = 0b0 || 0b00 | 0b0 \
6206 */ \
6207 tcg_gen_movi_i32(cpu_crf[0], 0); \
6208 }
6209
6210 #endif
6211
6212 GEN_TM_PRIV_NOOP(treclaim);
6213 GEN_TM_PRIV_NOOP(trechkpt);
6214
6215 #include "translate/fp-impl.inc.c"
6216
6217 #include "translate/vmx-impl.inc.c"
6218
6219 #include "translate/vsx-impl.inc.c"
6220
6221 #include "translate/dfp-impl.inc.c"
6222
6223 #include "translate/spe-impl.inc.c"
6224
6225 /* Handles lfdp, lxsd, lxssp */
6226 static void gen_dform39(DisasContext *ctx)
6227 {
6228 switch (ctx->opcode & 0x3) {
6229 case 0: /* lfdp */
6230 if (ctx->insns_flags2 & PPC2_ISA205) {
6231 return gen_lfdp(ctx);
6232 }
6233 break;
6234 case 2: /* lxsd */
6235 if (ctx->insns_flags2 & PPC2_ISA300) {
6236 return gen_lxsd(ctx);
6237 }
6238 break;
6239 case 3: /* lxssp */
6240 if (ctx->insns_flags2 & PPC2_ISA300) {
6241 return gen_lxssp(ctx);
6242 }
6243 break;
6244 }
6245 return gen_invalid(ctx);
6246 }
6247
6248 /* handles stfdp, lxv, stxsd, stxssp lxvx */
6249 static void gen_dform3D(DisasContext *ctx)
6250 {
6251 if ((ctx->opcode & 3) == 1) { /* DQ-FORM */
6252 switch (ctx->opcode & 0x7) {
6253 case 1: /* lxv */
6254 if (ctx->insns_flags2 & PPC2_ISA300) {
6255 return gen_lxv(ctx);
6256 }
6257 break;
6258 case 5: /* stxv */
6259 if (ctx->insns_flags2 & PPC2_ISA300) {
6260 return gen_stxv(ctx);
6261 }
6262 break;
6263 }
6264 } else { /* DS-FORM */
6265 switch (ctx->opcode & 0x3) {
6266 case 0: /* stfdp */
6267 if (ctx->insns_flags2 & PPC2_ISA205) {
6268 return gen_stfdp(ctx);
6269 }
6270 break;
6271 case 2: /* stxsd */
6272 if (ctx->insns_flags2 & PPC2_ISA300) {
6273 return gen_stxsd(ctx);
6274 }
6275 break;
6276 case 3: /* stxssp */
6277 if (ctx->insns_flags2 & PPC2_ISA300) {
6278 return gen_stxssp(ctx);
6279 }
6280 break;
6281 }
6282 }
6283 return gen_invalid(ctx);
6284 }
6285
6286 static opcode_t opcodes[] = {
6287 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
6288 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
6289 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
6290 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400001, PPC_INTEGER),
6291 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
6292 #if defined(TARGET_PPC64)
6293 GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300),
6294 #endif
6295 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
6296 GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300),
6297 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
6298 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6299 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6300 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6301 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6302 GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
6303 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
6304 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
6305 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
6306 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
6307 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6308 #if defined(TARGET_PPC64)
6309 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
6310 #endif
6311 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
6312 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
6313 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6314 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6315 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6316 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
6317 GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300),
6318 GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300),
6319 GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300),
6320 GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300),
6321 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
6322 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
6323 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6324 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6325 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6326 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6327 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB),
6328 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
6329 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
6330 #if defined(TARGET_PPC64)
6331 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
6332 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
6333 GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300),
6334 GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300),
6335 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
6336 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
6337 #endif
6338 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6339 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6340 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6341 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
6342 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
6343 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
6344 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
6345 #if defined(TARGET_PPC64)
6346 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
6347 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
6348 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
6349 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
6350 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
6351 GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000,
6352 PPC_NONE, PPC2_ISA300),
6353 GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000,
6354 PPC_NONE, PPC2_ISA300),
6355 #endif
6356 #if defined(TARGET_PPC64)
6357 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
6358 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
6359 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
6360 #endif
6361 /* handles lfdp, lxsd, lxssp */
6362 GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
6363 /* handles stfdp, lxv, stxsd, stxssp, stxv */
6364 GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
6365 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6366 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6367 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
6368 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
6369 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
6370 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
6371 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
6372 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
6373 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6374 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6375 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
6376 GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300),
6377 GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300),
6378 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6379 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6380 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
6381 #if defined(TARGET_PPC64)
6382 GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300),
6383 GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300),
6384 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
6385 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
6386 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
6387 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
6388 #endif
6389 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
6390 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
6391 GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039FF801, PPC_NONE, PPC2_ISA300),
6392 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6393 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6394 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
6395 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
6396 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207),
6397 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
6398 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
6399 #if defined(TARGET_PPC64)
6400 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
6401 GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300),
6402 GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6403 GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6404 GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6405 GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6406 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
6407 #endif
6408 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
6409 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
6410 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6411 #if defined(TARGET_PPC64)
6412 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
6413 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
6414 #endif
6415 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
6416 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
6417 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
6418 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
6419 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
6420 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
6421 #if defined(TARGET_PPC64)
6422 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
6423 GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300),
6424 #endif
6425 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC),
6426 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC),
6427 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
6428 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
6429 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
6430 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
6431 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
6432 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
6433 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
6434 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
6435 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
6436 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
6437 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
6438 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
6439 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
6440 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
6441 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
6442 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
6443 #if defined(TARGET_PPC64)
6444 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
6445 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
6446 PPC_SEGMENT_64B),
6447 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
6448 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
6449 PPC_SEGMENT_64B),
6450 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
6451 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
6452 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
6453 GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B),
6454 #endif
6455 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
6456 /* XXX Those instructions will need to be handled differently for
6457 * different ISA versions */
6458 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE),
6459 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE),
6460 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
6461 #if defined(TARGET_PPC64)
6462 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI),
6463 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
6464 GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300),
6465 GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300),
6466 #endif
6467 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
6468 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
6469 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
6470 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
6471 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
6472 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
6473 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
6474 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
6475 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
6476 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
6477 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
6478 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
6479 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
6480 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
6481 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
6482 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
6483 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
6484 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
6485 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
6486 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
6487 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
6488 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
6489 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
6490 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
6491 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
6492 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
6493 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
6494 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
6495 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
6496 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
6497 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
6498 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
6499 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
6500 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
6501 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
6502 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
6503 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
6504 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
6505 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
6506 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
6507 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
6508 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
6509 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
6510 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
6511 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
6512 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
6513 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
6514 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
6515 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
6516 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6517 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6518 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
6519 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
6520 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6521 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6522 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
6523 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
6524 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
6525 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
6526 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
6527 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
6528 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
6529 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
6530 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
6531 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
6532 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
6533 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
6534 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
6535 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
6536 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
6537 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
6538 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
6539 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
6540 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
6541 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
6542 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
6543 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
6544 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
6545 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
6546 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
6547 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
6548 PPC_NONE, PPC2_BOOKE206),
6549 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
6550 PPC_NONE, PPC2_BOOKE206),
6551 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
6552 PPC_NONE, PPC2_BOOKE206),
6553 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
6554 PPC_NONE, PPC2_BOOKE206),
6555 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
6556 PPC_NONE, PPC2_BOOKE206),
6557 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
6558 PPC_NONE, PPC2_PRCNTL),
6559 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
6560 PPC_NONE, PPC2_PRCNTL),
6561 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
6562 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
6563 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
6564 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
6565 PPC_BOOKE, PPC2_BOOKE206),
6566 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
6567 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
6568 PPC_BOOKE, PPC2_BOOKE206),
6569 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
6570 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
6571 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
6572 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
6573 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
6574 #if defined(TARGET_PPC64)
6575 GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE,
6576 PPC2_ISA300),
6577 GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
6578 #endif
6579
6580 #undef GEN_INT_ARITH_ADD
6581 #undef GEN_INT_ARITH_ADD_CONST
6582 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
6583 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
6584 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
6585 add_ca, compute_ca, compute_ov) \
6586 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
6587 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
6588 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
6589 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
6590 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
6591 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
6592 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
6593 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
6594 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
6595 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
6596 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
6597
6598 #undef GEN_INT_ARITH_DIVW
6599 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
6600 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
6601 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
6602 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
6603 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
6604 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
6605 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6606 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6607 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6608 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6609 GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
6610 GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
6611
6612 #if defined(TARGET_PPC64)
6613 #undef GEN_INT_ARITH_DIVD
6614 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
6615 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
6616 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
6617 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
6618 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
6619 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
6620
6621 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6622 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6623 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6624 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6625 GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
6626 GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
6627
6628 #undef GEN_INT_ARITH_MUL_HELPER
6629 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
6630 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
6631 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
6632 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
6633 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
6634 #endif
6635
6636 #undef GEN_INT_ARITH_SUBF
6637 #undef GEN_INT_ARITH_SUBF_CONST
6638 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
6639 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
6640 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
6641 add_ca, compute_ca, compute_ov) \
6642 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
6643 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
6644 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
6645 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
6646 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
6647 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
6648 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
6649 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
6650 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
6651 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
6652 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
6653
6654 #undef GEN_LOGICAL1
6655 #undef GEN_LOGICAL2
6656 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
6657 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
6658 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
6659 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
6660 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
6661 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
6662 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
6663 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
6664 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
6665 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
6666 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
6667 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
6668 #if defined(TARGET_PPC64)
6669 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
6670 #endif
6671
6672 #if defined(TARGET_PPC64)
6673 #undef GEN_PPC64_R2
6674 #undef GEN_PPC64_R4
6675 #define GEN_PPC64_R2(name, opc1, opc2) \
6676 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
6677 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
6678 PPC_64B)
6679 #define GEN_PPC64_R4(name, opc1, opc2) \
6680 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
6681 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
6682 PPC_64B), \
6683 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
6684 PPC_64B), \
6685 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
6686 PPC_64B)
6687 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
6688 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
6689 GEN_PPC64_R4(rldic, 0x1E, 0x04),
6690 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
6691 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
6692 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
6693 #endif
6694
6695 #undef GEN_LD
6696 #undef GEN_LDU
6697 #undef GEN_LDUX
6698 #undef GEN_LDX_E
6699 #undef GEN_LDS
6700 #define GEN_LD(name, ldop, opc, type) \
6701 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
6702 #define GEN_LDU(name, ldop, opc, type) \
6703 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
6704 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
6705 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
6706 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
6707 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
6708 #define GEN_LDS(name, ldop, op, type) \
6709 GEN_LD(name, ldop, op | 0x20, type) \
6710 GEN_LDU(name, ldop, op | 0x21, type) \
6711 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
6712 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
6713
6714 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
6715 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
6716 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
6717 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
6718 #if defined(TARGET_PPC64)
6719 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
6720 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
6721 GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B)
6722 GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B)
6723 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE)
6724
6725 /* HV/P7 and later only */
6726 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST)
6727 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST)
6728 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
6729 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
6730 #endif
6731 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
6732 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
6733
6734 #undef GEN_ST
6735 #undef GEN_STU
6736 #undef GEN_STUX
6737 #undef GEN_STX_E
6738 #undef GEN_STS
6739 #define GEN_ST(name, stop, opc, type) \
6740 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
6741 #define GEN_STU(name, stop, opc, type) \
6742 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
6743 #define GEN_STUX(name, stop, opc2, opc3, type) \
6744 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
6745 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
6746 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
6747 #define GEN_STS(name, stop, op, type) \
6748 GEN_ST(name, stop, op | 0x20, type) \
6749 GEN_STU(name, stop, op | 0x21, type) \
6750 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
6751 GEN_STX(name, stop, 0x17, op | 0x00, type)
6752
6753 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
6754 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
6755 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
6756 #if defined(TARGET_PPC64)
6757 GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B)
6758 GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B)
6759 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE)
6760 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
6761 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
6762 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
6763 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
6764 #endif
6765 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
6766 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
6767
6768 #undef GEN_CRLOGIC
6769 #define GEN_CRLOGIC(name, tcg_op, opc) \
6770 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
6771 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
6772 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
6773 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
6774 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
6775 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
6776 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
6777 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
6778 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
6779
6780 #undef GEN_MAC_HANDLER
6781 #define GEN_MAC_HANDLER(name, opc2, opc3) \
6782 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
6783 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
6784 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
6785 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
6786 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
6787 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
6788 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
6789 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
6790 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
6791 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
6792 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
6793 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
6794 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
6795 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
6796 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
6797 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
6798 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
6799 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
6800 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
6801 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
6802 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
6803 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
6804 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
6805 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
6806 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
6807 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
6808 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
6809 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
6810 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
6811 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
6812 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
6813 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
6814 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
6815 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
6816 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
6817 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
6818 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
6819 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
6820 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
6821 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
6822 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
6823 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
6824 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
6825
6826 GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
6827 PPC_NONE, PPC2_TM),
6828 GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \
6829 PPC_NONE, PPC2_TM),
6830 GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
6831 PPC_NONE, PPC2_TM),
6832 GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
6833 PPC_NONE, PPC2_TM),
6834 GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
6835 PPC_NONE, PPC2_TM),
6836 GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
6837 PPC_NONE, PPC2_TM),
6838 GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
6839 PPC_NONE, PPC2_TM),
6840 GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
6841 PPC_NONE, PPC2_TM),
6842 GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
6843 PPC_NONE, PPC2_TM),
6844 GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
6845 PPC_NONE, PPC2_TM),
6846 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
6847 PPC_NONE, PPC2_TM),
6848
6849 #include "translate/fp-ops.inc.c"
6850
6851 #include "translate/vmx-ops.inc.c"
6852
6853 #include "translate/vsx-ops.inc.c"
6854
6855 #include "translate/dfp-ops.inc.c"
6856
6857 #include "translate/spe-ops.inc.c"
6858 };
6859
6860 #include "helper_regs.h"
6861 #include "translate_init.c"
6862
6863 /*****************************************************************************/
6864 /* Misc PowerPC helpers */
6865 void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
6866 int flags)
6867 {
6868 #define RGPL 4
6869 #define RFPL 4
6870
6871 PowerPCCPU *cpu = POWERPC_CPU(cs);
6872 CPUPPCState *env = &cpu->env;
6873 int i;
6874
6875 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
6876 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
6877 env->nip, env->lr, env->ctr, cpu_read_xer(env),
6878 cs->cpu_index);
6879 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
6880 TARGET_FMT_lx " iidx %d didx %d\n",
6881 env->msr, env->spr[SPR_HID0],
6882 env->hflags, env->immu_idx, env->dmmu_idx);
6883 #if !defined(NO_TIMER_DUMP)
6884 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
6885 #if !defined(CONFIG_USER_ONLY)
6886 " DECR %08" PRIu32
6887 #endif
6888 "\n",
6889 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
6890 #if !defined(CONFIG_USER_ONLY)
6891 , cpu_ppc_load_decr(env)
6892 #endif
6893 );
6894 #endif
6895 for (i = 0; i < 32; i++) {
6896 if ((i & (RGPL - 1)) == 0)
6897 cpu_fprintf(f, "GPR%02d", i);
6898 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
6899 if ((i & (RGPL - 1)) == (RGPL - 1))
6900 cpu_fprintf(f, "\n");
6901 }
6902 cpu_fprintf(f, "CR ");
6903 for (i = 0; i < 8; i++)
6904 cpu_fprintf(f, "%01x", env->crf[i]);
6905 cpu_fprintf(f, " [");
6906 for (i = 0; i < 8; i++) {
6907 char a = '-';
6908 if (env->crf[i] & 0x08)
6909 a = 'L';
6910 else if (env->crf[i] & 0x04)
6911 a = 'G';
6912 else if (env->crf[i] & 0x02)
6913 a = 'E';
6914 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
6915 }
6916 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
6917 env->reserve_addr);
6918 for (i = 0; i < 32; i++) {
6919 if ((i & (RFPL - 1)) == 0)
6920 cpu_fprintf(f, "FPR%02d", i);
6921 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
6922 if ((i & (RFPL - 1)) == (RFPL - 1))
6923 cpu_fprintf(f, "\n");
6924 }
6925 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
6926 #if !defined(CONFIG_USER_ONLY)
6927 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
6928 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
6929 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
6930 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
6931
6932 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
6933 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
6934 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
6935 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
6936
6937 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
6938 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
6939 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
6940 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
6941
6942 #if defined(TARGET_PPC64)
6943 if (env->excp_model == POWERPC_EXCP_POWER7 ||
6944 env->excp_model == POWERPC_EXCP_POWER8) {
6945 cpu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n",
6946 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
6947 }
6948 #endif
6949 if (env->excp_model == POWERPC_EXCP_BOOKE) {
6950 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
6951 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
6952 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
6953 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
6954
6955 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
6956 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
6957 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
6958 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
6959
6960 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
6961 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
6962 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
6963 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
6964
6965 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
6966 " EPR " TARGET_FMT_lx "\n",
6967 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
6968 env->spr[SPR_BOOKE_EPR]);
6969
6970 /* FSL-specific */
6971 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
6972 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
6973 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
6974 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
6975
6976 /*
6977 * IVORs are left out as they are large and do not change often --
6978 * they can be read with "p $ivor0", "p $ivor1", etc.
6979 */
6980 }
6981
6982 #if defined(TARGET_PPC64)
6983 if (env->flags & POWERPC_FLAG_CFAR) {
6984 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
6985 }
6986 #endif
6987
6988 if (env->spr_cb[SPR_LPCR].name)
6989 cpu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]);
6990
6991 switch (env->mmu_model) {
6992 case POWERPC_MMU_32B:
6993 case POWERPC_MMU_601:
6994 case POWERPC_MMU_SOFT_6xx:
6995 case POWERPC_MMU_SOFT_74xx:
6996 #if defined(TARGET_PPC64)
6997 case POWERPC_MMU_64B:
6998 case POWERPC_MMU_2_03:
6999 case POWERPC_MMU_2_06:
7000 case POWERPC_MMU_2_06a:
7001 case POWERPC_MMU_2_07:
7002 case POWERPC_MMU_2_07a:
7003 #endif
7004 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " DAR " TARGET_FMT_lx
7005 " DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1],
7006 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
7007 break;
7008 case POWERPC_MMU_BOOKE206:
7009 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
7010 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
7011 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
7012 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
7013
7014 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
7015 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
7016 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
7017 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
7018
7019 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
7020 " TLB1CFG " TARGET_FMT_lx "\n",
7021 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
7022 env->spr[SPR_BOOKE_TLB1CFG]);
7023 break;
7024 default:
7025 break;
7026 }
7027 #endif
7028
7029 #undef RGPL
7030 #undef RFPL
7031 }
7032
7033 void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
7034 fprintf_function cpu_fprintf, int flags)
7035 {
7036 #if defined(DO_PPC_STATISTICS)
7037 PowerPCCPU *cpu = POWERPC_CPU(cs);
7038 opc_handler_t **t1, **t2, **t3, *handler;
7039 int op1, op2, op3;
7040
7041 t1 = cpu->env.opcodes;
7042 for (op1 = 0; op1 < 64; op1++) {
7043 handler = t1[op1];
7044 if (is_indirect_opcode(handler)) {
7045 t2 = ind_table(handler);
7046 for (op2 = 0; op2 < 32; op2++) {
7047 handler = t2[op2];
7048 if (is_indirect_opcode(handler)) {
7049 t3 = ind_table(handler);
7050 for (op3 = 0; op3 < 32; op3++) {
7051 handler = t3[op3];
7052 if (handler->count == 0)
7053 continue;
7054 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
7055 "%016" PRIx64 " %" PRId64 "\n",
7056 op1, op2, op3, op1, (op3 << 5) | op2,
7057 handler->oname,
7058 handler->count, handler->count);
7059 }
7060 } else {
7061 if (handler->count == 0)
7062 continue;
7063 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
7064 "%016" PRIx64 " %" PRId64 "\n",
7065 op1, op2, op1, op2, handler->oname,
7066 handler->count, handler->count);
7067 }
7068 }
7069 } else {
7070 if (handler->count == 0)
7071 continue;
7072 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
7073 " %" PRId64 "\n",
7074 op1, op1, handler->oname,
7075 handler->count, handler->count);
7076 }
7077 }
7078 #endif
7079 }
7080
7081 /*****************************************************************************/
7082 void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb)
7083 {
7084 PowerPCCPU *cpu = ppc_env_get_cpu(env);
7085 CPUState *cs = CPU(cpu);
7086 DisasContext ctx, *ctxp = &ctx;
7087 opc_handler_t **table, *handler;
7088 target_ulong pc_start;
7089 int num_insns;
7090 int max_insns;
7091
7092 pc_start = tb->pc;
7093 ctx.nip = pc_start;
7094 ctx.tb = tb;
7095 ctx.exception = POWERPC_EXCP_NONE;
7096 ctx.spr_cb = env->spr_cb;
7097 ctx.pr = msr_pr;
7098 ctx.mem_idx = env->dmmu_idx;
7099 ctx.dr = msr_dr;
7100 #if !defined(CONFIG_USER_ONLY)
7101 ctx.hv = msr_hv || !env->has_hv_mode;
7102 #endif
7103 ctx.insns_flags = env->insns_flags;
7104 ctx.insns_flags2 = env->insns_flags2;
7105 ctx.access_type = -1;
7106 ctx.need_access_type = !(env->mmu_model & POWERPC_MMU_64B);
7107 ctx.le_mode = !!(env->hflags & (1 << MSR_LE));
7108 ctx.default_tcg_memop_mask = ctx.le_mode ? MO_LE : MO_BE;
7109 #if defined(TARGET_PPC64)
7110 ctx.sf_mode = msr_is_64bit(env, env->msr);
7111 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
7112 #endif
7113 if (env->mmu_model == POWERPC_MMU_32B ||
7114 env->mmu_model == POWERPC_MMU_601 ||
7115 (env->mmu_model & POWERPC_MMU_64B))
7116 ctx.lazy_tlb_flush = true;
7117
7118 ctx.fpu_enabled = !!msr_fp;
7119 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
7120 ctx.spe_enabled = !!msr_spe;
7121 else
7122 ctx.spe_enabled = false;
7123 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
7124 ctx.altivec_enabled = !!msr_vr;
7125 else
7126 ctx.altivec_enabled = false;
7127 if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
7128 ctx.vsx_enabled = !!msr_vsx;
7129 } else {
7130 ctx.vsx_enabled = false;
7131 }
7132 #if defined(TARGET_PPC64)
7133 if ((env->flags & POWERPC_FLAG_TM) && msr_tm) {
7134 ctx.tm_enabled = !!msr_tm;
7135 } else {
7136 ctx.tm_enabled = false;
7137 }
7138 #endif
7139 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
7140 ctx.singlestep_enabled = CPU_SINGLE_STEP;
7141 else
7142 ctx.singlestep_enabled = 0;
7143 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
7144 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
7145 if (unlikely(cs->singlestep_enabled)) {
7146 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
7147 }
7148 #if defined (DO_SINGLE_STEP) && 0
7149 /* Single step trace mode */
7150 msr_se = 1;
7151 #endif
7152 num_insns = 0;
7153 max_insns = tb->cflags & CF_COUNT_MASK;
7154 if (max_insns == 0) {
7155 max_insns = CF_COUNT_MASK;
7156 }
7157 if (max_insns > TCG_MAX_INSNS) {
7158 max_insns = TCG_MAX_INSNS;
7159 }
7160
7161 gen_tb_start(tb);
7162 tcg_clear_temp_count();
7163 /* Set env in case of segfault during code fetch */
7164 while (ctx.exception == POWERPC_EXCP_NONE && !tcg_op_buf_full()) {
7165 tcg_gen_insn_start(ctx.nip);
7166 num_insns++;
7167
7168 if (unlikely(cpu_breakpoint_test(cs, ctx.nip, BP_ANY))) {
7169 gen_debug_exception(ctxp);
7170 /* The address covered by the breakpoint must be included in
7171 [tb->pc, tb->pc + tb->size) in order to for it to be
7172 properly cleared -- thus we increment the PC here so that
7173 the logic setting tb->size below does the right thing. */
7174 ctx.nip += 4;
7175 break;
7176 }
7177
7178 LOG_DISAS("----------------\n");
7179 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
7180 ctx.nip, ctx.mem_idx, (int)msr_ir);
7181 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO))
7182 gen_io_start();
7183 if (unlikely(need_byteswap(&ctx))) {
7184 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
7185 } else {
7186 ctx.opcode = cpu_ldl_code(env, ctx.nip);
7187 }
7188 LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n",
7189 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
7190 opc3(ctx.opcode), opc4(ctx.opcode),
7191 ctx.le_mode ? "little" : "big");
7192 ctx.nip += 4;
7193 table = env->opcodes;
7194 handler = table[opc1(ctx.opcode)];
7195 if (is_indirect_opcode(handler)) {
7196 table = ind_table(handler);
7197 handler = table[opc2(ctx.opcode)];
7198 if (is_indirect_opcode(handler)) {
7199 table = ind_table(handler);
7200 handler = table[opc3(ctx.opcode)];
7201 if (is_indirect_opcode(handler)) {
7202 table = ind_table(handler);
7203 handler = table[opc4(ctx.opcode)];
7204 }
7205 }
7206 }
7207 /* Is opcode *REALLY* valid ? */
7208 if (unlikely(handler->handler == &gen_invalid)) {
7209 qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: "
7210 "%02x - %02x - %02x - %02x (%08x) "
7211 TARGET_FMT_lx " %d\n",
7212 opc1(ctx.opcode), opc2(ctx.opcode),
7213 opc3(ctx.opcode), opc4(ctx.opcode),
7214 ctx.opcode, ctx.nip - 4, (int)msr_ir);
7215 } else {
7216 uint32_t inval;
7217
7218 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
7219 inval = handler->inval2;
7220 } else {
7221 inval = handler->inval1;
7222 }
7223
7224 if (unlikely((ctx.opcode & inval) != 0)) {
7225 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: "
7226 "%02x - %02x - %02x - %02x (%08x) "
7227 TARGET_FMT_lx "\n", ctx.opcode & inval,
7228 opc1(ctx.opcode), opc2(ctx.opcode),
7229 opc3(ctx.opcode), opc4(ctx.opcode),
7230 ctx.opcode, ctx.nip - 4);
7231 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
7232 break;
7233 }
7234 }
7235 (*(handler->handler))(&ctx);
7236 #if defined(DO_PPC_STATISTICS)
7237 handler->count++;
7238 #endif
7239 /* Check trace mode exceptions */
7240 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
7241 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
7242 ctx.exception != POWERPC_SYSCALL &&
7243 ctx.exception != POWERPC_EXCP_TRAP &&
7244 ctx.exception != POWERPC_EXCP_BRANCH)) {
7245 gen_exception_nip(ctxp, POWERPC_EXCP_TRACE, ctx.nip);
7246 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
7247 (cs->singlestep_enabled) ||
7248 singlestep ||
7249 num_insns >= max_insns)) {
7250 /* if we reach a page boundary or are single stepping, stop
7251 * generation
7252 */
7253 break;
7254 }
7255 if (tcg_check_temp_count()) {
7256 fprintf(stderr, "Opcode %02x %02x %02x %02x (%08x) leaked "
7257 "temporaries\n", opc1(ctx.opcode), opc2(ctx.opcode),
7258 opc3(ctx.opcode), opc4(ctx.opcode), ctx.opcode);
7259 exit(1);
7260 }
7261 }
7262 if (tb->cflags & CF_LAST_IO)
7263 gen_io_end();
7264 if (ctx.exception == POWERPC_EXCP_NONE) {
7265 gen_goto_tb(&ctx, 0, ctx.nip);
7266 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
7267 if (unlikely(cs->singlestep_enabled)) {
7268 gen_debug_exception(ctxp);
7269 }
7270 /* Generate the return instruction */
7271 tcg_gen_exit_tb(0);
7272 }
7273 gen_tb_end(tb, num_insns);
7274
7275 tb->size = ctx.nip - pc_start;
7276 tb->icount = num_insns;
7277
7278 #if defined(DEBUG_DISAS)
7279 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
7280 && qemu_log_in_addr_range(pc_start)) {
7281 int flags;
7282 flags = env->bfd_mach;
7283 flags |= ctx.le_mode << 16;
7284 qemu_log_lock();
7285 qemu_log("IN: %s\n", lookup_symbol(pc_start));
7286 log_target_disas(cs, pc_start, ctx.nip - pc_start, flags);
7287 qemu_log("\n");
7288 qemu_log_unlock();
7289 }
7290 #endif
7291 }
7292
7293 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb,
7294 target_ulong *data)
7295 {
7296 env->nip = data[0];
7297 }
QEmu