target/rx/cpu.c

   1 /*
   2  * QEMU RX CPU
   3  *
   4  * Copyright (c) 2019 Yoshinori Sato
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2 or later, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include "qemu/osdep.h"
  20 #include "qemu/qemu-print.h"
  21 #include "qapi/error.h"
  22 #include "cpu.h"
  23 #include "qemu-common.h"
  24 #include "migration/vmstate.h"
  25 #include "exec/exec-all.h"
  26 #include "hw/loader.h"
  27 #include "fpu/softfloat.h"
  28
  29 static void rx_cpu_set_pc(CPUState *cs, vaddr value)
  30 {
  31     RXCPU *cpu = RX_CPU(cs);
  32
  33     cpu->env.pc = value;
  34 }
  35
  36 static void rx_cpu_synchronize_from_tb(CPUState *cs,
  37                                        const TranslationBlock *tb)
  38 {
  39     RXCPU *cpu = RX_CPU(cs);
  40
  41     cpu->env.pc = tb->pc;
  42 }
  43
  44 static bool rx_cpu_has_work(CPUState *cs)
  45 {
  46     return cs->interrupt_request &
  47         (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIR);
  48 }
  49
  50 static void rx_cpu_reset(DeviceState *dev)
  51 {
  52     RXCPU *cpu = RX_CPU(dev);
  53     RXCPUClass *rcc = RX_CPU_GET_CLASS(cpu);
  54     CPURXState *env = &cpu->env;
  55     uint32_t *resetvec;
  56
  57     rcc->parent_reset(dev);
  58
  59     memset(env, 0, offsetof(CPURXState, end_reset_fields));
  60
  61     resetvec = rom_ptr(0xfffffffc, 4);
  62     if (resetvec) {
  63         /* In the case of kernel, it is ignored because it is not set. */
  64         env->pc = ldl_p(resetvec);
  65     }
  66     rx_cpu_unpack_psw(env, 0, 1);
  67     env->regs[0] = env->isp = env->usp = 0;
  68     env->fpsw = 0;
  69     set_flush_to_zero(1, &env->fp_status);
  70     set_flush_inputs_to_zero(1, &env->fp_status);
  71 }
  72
  73 static void rx_cpu_list_entry(gpointer data, gpointer user_data)
  74 {
  75     ObjectClass *oc = data;
  76
  77     qemu_printf("  %s\n", object_class_get_name(oc));
  78 }
  79
  80 void rx_cpu_list(void)
  81 {
  82     GSList *list;
  83     list = object_class_get_list_sorted(TYPE_RX_CPU, false);
  84     qemu_printf("Available CPUs:\n");
  85     g_slist_foreach(list, rx_cpu_list_entry, NULL);
  86     g_slist_free(list);
  87 }
  88
  89 static ObjectClass *rx_cpu_class_by_name(const char *cpu_model)
  90 {
  91     ObjectClass *oc;
  92     char *typename;
  93
  94     oc = object_class_by_name(cpu_model);
  95     if (oc != NULL && object_class_dynamic_cast(oc, TYPE_RX_CPU) != NULL &&
  96         !object_class_is_abstract(oc)) {
  97         return oc;
  98     }
  99     typename = g_strdup_printf(RX_CPU_TYPE_NAME("%s"), cpu_model);
 100     oc = object_class_by_name(typename);
 101     g_free(typename);
 102     if (oc != NULL && object_class_is_abstract(oc)) {
 103         oc = NULL;
 104     }
 105
 106     return oc;
 107 }
 108
 109 static void rx_cpu_realize(DeviceState *dev, Error **errp)
 110 {
 111     CPUState *cs = CPU(dev);
 112     RXCPUClass *rcc = RX_CPU_GET_CLASS(dev);
 113     Error *local_err = NULL;
 114
 115     cpu_exec_realizefn(cs, &local_err);
 116     if (local_err != NULL) {
 117         error_propagate(errp, local_err);
 118         return;
 119     }
 120
 121     qemu_init_vcpu(cs);
 122     cpu_reset(cs);
 123
 124     rcc->parent_realize(dev, errp);
 125 }
 126
 127 static void rx_cpu_set_irq(void *opaque, int no, int request)
 128 {
 129     RXCPU *cpu = opaque;
 130     CPUState *cs = CPU(cpu);
 131     int irq = request & 0xff;
 132
 133     static const int mask[] = {
 134         [RX_CPU_IRQ] = CPU_INTERRUPT_HARD,
 135         [RX_CPU_FIR] = CPU_INTERRUPT_FIR,
 136     };
 137     if (irq) {
 138         cpu->env.req_irq = irq;
 139         cpu->env.req_ipl = (request >> 8) & 0x0f;
 140         cpu_interrupt(cs, mask[no]);
 141     } else {
 142         cpu_reset_interrupt(cs, mask[no]);
 143     }
 144 }
 145
 146 static void rx_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
 147 {
 148     info->mach = bfd_mach_rx;
 149     info->print_insn = print_insn_rx;
 150 }
 151
 152 static bool rx_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,
 153                             MMUAccessType access_type, int mmu_idx,
 154                             bool probe, uintptr_t retaddr)
 155 {
 156     uint32_t address, physical, prot;
 157
 158     /* Linear mapping */
 159     address = physical = addr & TARGET_PAGE_MASK;
 160     prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 161     tlb_set_page(cs, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE);
 162     return true;
 163 }
 164
 165 static void rx_cpu_init(Object *obj)
 166 {
 167     CPUState *cs = CPU(obj);
 168     RXCPU *cpu = RX_CPU(obj);
 169     CPURXState *env = &cpu->env;
 170
 171     cpu_set_cpustate_pointers(cpu);
 172     cs->env_ptr = env;
 173     qdev_init_gpio_in(DEVICE(cpu), rx_cpu_set_irq, 2);
 174 }
 175
 176 #include "hw/core/tcg-cpu-ops.h"
 177
 178 static struct TCGCPUOps rx_tcg_ops = {
 179     .initialize = rx_translate_init,
 180     .synchronize_from_tb = rx_cpu_synchronize_from_tb,
 181     .cpu_exec_interrupt = rx_cpu_exec_interrupt,
 182     .tlb_fill = rx_cpu_tlb_fill,
 183
 184 #ifndef CONFIG_USER_ONLY
 185     .do_interrupt = rx_cpu_do_interrupt,
 186 #endif /* !CONFIG_USER_ONLY */
 187 };
 188
 189 static void rx_cpu_class_init(ObjectClass *klass, void *data)
 190 {
 191     DeviceClass *dc = DEVICE_CLASS(klass);
 192     CPUClass *cc = CPU_CLASS(klass);
 193     RXCPUClass *rcc = RX_CPU_CLASS(klass);
 194
 195     device_class_set_parent_realize(dc, rx_cpu_realize,
 196                                     &rcc->parent_realize);
 197     device_class_set_parent_reset(dc, rx_cpu_reset,
 198                                   &rcc->parent_reset);
 199
 200     cc->class_by_name = rx_cpu_class_by_name;
 201     cc->has_work = rx_cpu_has_work;
 202     cc->dump_state = rx_cpu_dump_state;
 203     cc->set_pc = rx_cpu_set_pc;
 204
 205     cc->gdb_read_register = rx_cpu_gdb_read_register;
 206     cc->gdb_write_register = rx_cpu_gdb_write_register;
 207     cc->get_phys_page_debug = rx_cpu_get_phys_page_debug;
 208     cc->disas_set_info = rx_cpu_disas_set_info;
 209
 210     cc->gdb_num_core_regs = 26;
 211     cc->gdb_core_xml_file = "rx-core.xml";
 212     cc->tcg_ops = &rx_tcg_ops;
 213 }
 214
 215 static const TypeInfo rx_cpu_info = {
 216     .name = TYPE_RX_CPU,
 217     .parent = TYPE_CPU,
 218     .instance_size = sizeof(RXCPU),
 219     .instance_init = rx_cpu_init,
 220     .abstract = true,
 221     .class_size = sizeof(RXCPUClass),
 222     .class_init = rx_cpu_class_init,
 223 };
 224
 225 static const TypeInfo rx62n_rx_cpu_info = {
 226     .name = TYPE_RX62N_CPU,
 227     .parent = TYPE_RX_CPU,
 228 };
 229
 230 static void rx_cpu_register_types(void)
 231 {
 232     type_register_static(&rx_cpu_info);
 233     type_register_static(&rx62n_rx_cpu_info);
 234 }
 235
 236 type_init(rx_cpu_register_types)