hw/sh_pci.c

   1 /*
   2  * SuperH on-chip PCIC emulation.
   3  *
   4  * Copyright (c) 2008 Takashi YOSHII
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "sh.h"
  26 #include "pci.h"
  27 #include "pci_host.h"
  28 #include "sh_pci.h"
  29 #include "bswap.h"
  30
  31 typedef struct {
  32     PCIBus *bus;
  33     PCIDevice *dev;
  34     uint32_t par;
  35     uint32_t mbr;
  36     uint32_t iobr;
  37 } SHPCIC;
  38
  39 static void sh_pci_reg_write (void *p, target_phys_addr_t addr, uint32_t val)
  40 {
  41     SHPCIC *pcic = p;
  42     switch(addr) {
  43     case 0 ... 0xfc:
  44         cpu_to_le32w((uint32_t*)(pcic->dev->config + addr), val);
  45         break;
  46     case 0x1c0:
  47         pcic->par = val;
  48         break;
  49     case 0x1c4:
  50         pcic->mbr = val & 0xff000001;
  51         break;
  52     case 0x1c8:
  53         if ((val & 0xfffc0000) != (pcic->iobr & 0xfffc0000)) {
  54             cpu_register_physical_memory(pcic->iobr & 0xfffc0000, 0x40000,
  55                                          IO_MEM_UNASSIGNED);
  56             pcic->iobr = val & 0xfffc0001;
  57             isa_mmio_init(pcic->iobr & 0xfffc0000, 0x40000);
  58         }
  59         break;
  60     case 0x220:
  61         pci_data_write(pcic->bus, pcic->par, val, 4);
  62         break;
  63     }
  64 }
  65
  66 static uint32_t sh_pci_reg_read (void *p, target_phys_addr_t addr)
  67 {
  68     SHPCIC *pcic = p;
  69     switch(addr) {
  70     case 0 ... 0xfc:
  71         return le32_to_cpup((uint32_t*)(pcic->dev->config + addr));
  72     case 0x1c0:
  73         return pcic->par;
  74     case 0x1c4:
  75         return pcic->mbr;
  76     case 0x1c8:
  77         return pcic->iobr;
  78     case 0x220:
  79         return pci_data_read(pcic->bus, pcic->par, 4);
  80     }
  81     return 0;
  82 }
  83
  84 typedef struct {
  85     CPUReadMemoryFunc * const r[3];
  86     CPUWriteMemoryFunc * const w[3];
  87 } MemOp;
  88
  89 static MemOp sh_pci_reg = {
  90     { NULL, NULL, sh_pci_reg_read },
  91     { NULL, NULL, sh_pci_reg_write },
  92 };
  93
  94 PCIBus *sh_pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
  95                             void *opaque, int devfn_min, int nirq)
  96 {
  97     SHPCIC *p;
  98     int reg;
  99
 100     p = qemu_mallocz(sizeof(SHPCIC));
 101     p->bus = pci_register_bus(NULL, "pci",
 102                               set_irq, map_irq, opaque, devfn_min, nirq);
 103
 104     p->dev = pci_register_device(p->bus, "SH PCIC", sizeof(PCIDevice),
 105                                  -1, NULL, NULL);
 106     reg = cpu_register_io_memory(sh_pci_reg.r, sh_pci_reg.w, p,
 107                                  DEVICE_NATIVE_ENDIAN);
 108     cpu_register_physical_memory(0x1e200000, 0x224, reg);
 109     cpu_register_physical_memory(0xfe200000, 0x224, reg);
 110
 111     p->iobr = 0xfe240000;
 112     isa_mmio_init(p->iobr, 0x40000);
 113
 114     pci_config_set_vendor_id(p->dev->config, PCI_VENDOR_ID_HITACHI);
 115     pci_config_set_device_id(p->dev->config, PCI_DEVICE_ID_HITACHI_SH7751R);
 116     p->dev->config[0x04] = 0x80;
 117     p->dev->config[0x05] = 0x00;
 118     p->dev->config[0x06] = 0x90;
 119     p->dev->config[0x07] = 0x02;
 120
 121     return p->bus;
 122 }