hw/r2d.c

   1 /*
   2  * Renesas SH7751R R2D-PLUS emulation
   3  *
   4  * Copyright (c) 2007 Magnus Damm
   5  * Copyright (c) 2008 Paul Mundt
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 #include "hw.h"
  27 #include "sh.h"
  28 #include "devices.h"
  29 #include "sysemu.h"
  30 #include "boards.h"
  31 #include "pci.h"
  32 #include "sh_pci.h"
  33 #include "net.h"
  34 #include "sh7750_regs.h"
  35 #include "ide.h"
  36 #include "loader.h"
  37 #include "usb.h"
  38 #include "flash.h"
  39 #include "blockdev.h"
  40
  41 #define FLASH_BASE 0x00000000
  42 #define FLASH_SIZE 0x02000000
  43
  44 #define SDRAM_BASE 0x0c000000 /* Physical location of SDRAM: Area 3 */
  45 #define SDRAM_SIZE 0x04000000
  46
  47 #define SM501_VRAM_SIZE 0x800000
  48
  49 #define BOOT_PARAMS_OFFSET 0x0010000
  50 /* CONFIG_BOOT_LINK_OFFSET of Linux kernel */
  51 #define LINUX_LOAD_OFFSET  0x0800000
  52 #define INITRD_LOAD_OFFSET 0x1800000
  53
  54 #define PA_IRLMSK       0x00
  55 #define PA_POWOFF       0x30
  56 #define PA_VERREG       0x32
  57 #define PA_OUTPORT      0x36
  58
  59 typedef struct {
  60     uint16_t bcr;
  61     uint16_t irlmsk;
  62     uint16_t irlmon;
  63     uint16_t cfctl;
  64     uint16_t cfpow;
  65     uint16_t dispctl;
  66     uint16_t sdmpow;
  67     uint16_t rtcce;
  68     uint16_t pcicd;
  69     uint16_t voyagerrts;
  70     uint16_t cfrst;
  71     uint16_t admrts;
  72     uint16_t extrst;
  73     uint16_t cfcdintclr;
  74     uint16_t keyctlclr;
  75     uint16_t pad0;
  76     uint16_t pad1;
  77     uint16_t verreg;
  78     uint16_t inport;
  79     uint16_t outport;
  80     uint16_t bverreg;
  81
  82 /* output pin */
  83     qemu_irq irl;
  84 } r2d_fpga_t;
  85
  86 enum r2d_fpga_irq {
  87     PCI_INTD, CF_IDE, CF_CD, PCI_INTC, SM501, KEY, RTC_A, RTC_T,
  88     SDCARD, PCI_INTA, PCI_INTB, EXT, TP,
  89     NR_IRQS
  90 };
  91
  92 static const struct { short irl; uint16_t msk; } irqtab[NR_IRQS] = {
  93     [CF_IDE]    = {  1, 1<<9 },
  94     [CF_CD]     = {  2, 1<<8 },
  95     [PCI_INTA]  = {  9, 1<<14 },
  96     [PCI_INTB]  = { 10, 1<<13 },
  97     [PCI_INTC]  = {  3, 1<<12 },
  98     [PCI_INTD]  = {  0, 1<<11 },
  99     [SM501]     = {  4, 1<<10 },
 100     [KEY]       = {  5, 1<<6 },
 101     [RTC_A]     = {  6, 1<<5 },
 102     [RTC_T]     = {  7, 1<<4 },
 103     [SDCARD]    = {  8, 1<<7 },
 104     [EXT]       = { 11, 1<<0 },
 105     [TP]        = { 12, 1<<15 },
 106 };
 107
 108 static void update_irl(r2d_fpga_t *fpga)
 109 {
 110     int i, irl = 15;
 111     for (i = 0; i < NR_IRQS; i++)
 112         if (fpga->irlmon & fpga->irlmsk & irqtab[i].msk)
 113             if (irqtab[i].irl < irl)
 114                 irl = irqtab[i].irl;
 115     qemu_set_irq(fpga->irl, irl ^ 15);
 116 }
 117
 118 static void r2d_fpga_irq_set(void *opaque, int n, int level)
 119 {
 120     r2d_fpga_t *fpga = opaque;
 121     if (level)
 122         fpga->irlmon |= irqtab[n].msk;
 123     else
 124         fpga->irlmon &= ~irqtab[n].msk;
 125     update_irl(fpga);
 126 }
 127
 128 static uint32_t r2d_fpga_read(void *opaque, target_phys_addr_t addr)
 129 {
 130     r2d_fpga_t *s = opaque;
 131
 132     switch (addr) {
 133     case PA_IRLMSK:
 134         return s->irlmsk;
 135     case PA_OUTPORT:
 136         return s->outport;
 137     case PA_POWOFF:
 138         return 0x00;
 139     case PA_VERREG:
 140         return 0x10;
 141     }
 142
 143     return 0;
 144 }
 145
 146 static void
 147 r2d_fpga_write(void *opaque, target_phys_addr_t addr, uint32_t value)
 148 {
 149     r2d_fpga_t *s = opaque;
 150
 151     switch (addr) {
 152     case PA_IRLMSK:
 153         s->irlmsk = value;
 154         update_irl(s);
 155         break;
 156     case PA_OUTPORT:
 157         s->outport = value;
 158         break;
 159     case PA_POWOFF:
 160         if (value & 1) {
 161             qemu_system_shutdown_request();
 162         }
 163         break;
 164     case PA_VERREG:
 165         /* Discard writes */
 166         break;
 167     }
 168 }
 169
 170 static CPUReadMemoryFunc * const r2d_fpga_readfn[] = {
 171     r2d_fpga_read,
 172     r2d_fpga_read,
 173     NULL,
 174 };
 175
 176 static CPUWriteMemoryFunc * const r2d_fpga_writefn[] = {
 177     r2d_fpga_write,
 178     r2d_fpga_write,
 179     NULL,
 180 };
 181
 182 static qemu_irq *r2d_fpga_init(target_phys_addr_t base, qemu_irq irl)
 183 {
 184     int iomemtype;
 185     r2d_fpga_t *s;
 186
 187     s = qemu_mallocz(sizeof(r2d_fpga_t));
 188
 189     s->irl = irl;
 190
 191     iomemtype = cpu_register_io_memory(r2d_fpga_readfn,
 192                                        r2d_fpga_writefn, s,
 193                                        DEVICE_NATIVE_ENDIAN);
 194     cpu_register_physical_memory(base, 0x40, iomemtype);
 195     return qemu_allocate_irqs(r2d_fpga_irq_set, s, NR_IRQS);
 196 }
 197
 198 static void r2d_pci_set_irq(void *opaque, int n, int l)
 199 {
 200     qemu_irq *p = opaque;
 201
 202     qemu_set_irq(p[n], l);
 203 }
 204
 205 static int r2d_pci_map_irq(PCIDevice *d, int irq_num)
 206 {
 207     const int intx[] = { PCI_INTA, PCI_INTB, PCI_INTC, PCI_INTD };
 208     return intx[d->devfn >> 3];
 209 }
 210
 211 typedef struct ResetData {
 212     CPUState *env;
 213     uint32_t vector;
 214 } ResetData;
 215
 216 static void main_cpu_reset(void *opaque)
 217 {
 218     ResetData *s = (ResetData *)opaque;
 219     CPUState *env = s->env;
 220
 221     cpu_reset(env);
 222     env->pc = s->vector;
 223 }
 224
 225 static struct __attribute__((__packed__))
 226 {
 227     int mount_root_rdonly;
 228     int ramdisk_flags;
 229     int orig_root_dev;
 230     int loader_type;
 231     int initrd_start;
 232     int initrd_size;
 233
 234     char pad[232];
 235
 236     char kernel_cmdline[256];
 237 } boot_params;
 238
 239 static void r2d_init(ram_addr_t ram_size,
 240               const char *boot_device,
 241               const char *kernel_filename, const char *kernel_cmdline,
 242               const char *initrd_filename, const char *cpu_model)
 243 {
 244     CPUState *env;
 245     ResetData *reset_info;
 246     struct SH7750State *s;
 247     ram_addr_t sdram_addr;
 248     qemu_irq *irq;
 249     DriveInfo *dinfo;
 250     int i;
 251
 252     if (!cpu_model)
 253         cpu_model = "SH7751R";
 254
 255     env = cpu_init(cpu_model);
 256     if (!env) {
 257         fprintf(stderr, "Unable to find CPU definition\n");
 258         exit(1);
 259     }
 260     reset_info = qemu_mallocz(sizeof(ResetData));
 261     reset_info->env = env;
 262     reset_info->vector = env->pc;
 263     qemu_register_reset(main_cpu_reset, reset_info);
 264
 265     /* Allocate memory space */
 266     sdram_addr = qemu_ram_alloc(NULL, "r2d.sdram", SDRAM_SIZE);
 267     cpu_register_physical_memory(SDRAM_BASE, SDRAM_SIZE, sdram_addr);
 268     /* Register peripherals */
 269     s = sh7750_init(env);
 270     irq = r2d_fpga_init(0x04000000, sh7750_irl(s));
 271     sh_pci_register_bus(r2d_pci_set_irq, r2d_pci_map_irq, irq, 0, 4);
 272
 273     sm501_init(0x10000000, SM501_VRAM_SIZE, irq[SM501], serial_hds[2]);
 274
 275     /* onboard CF (True IDE mode, Master only). */
 276     dinfo = drive_get(IF_IDE, 0, 0);
 277     mmio_ide_init(0x14001000, 0x1400080c, irq[CF_IDE], 1,
 278                   dinfo, NULL);
 279
 280     /* onboard flash memory */
 281     dinfo = drive_get(IF_PFLASH, 0, 0);
 282     pflash_cfi02_register(0x0, qemu_ram_alloc(NULL, "r2d.flash", FLASH_SIZE),
 283                           dinfo ? dinfo->bdrv : NULL, (16 * 1024),
 284                           FLASH_SIZE >> 16,
 285                           1, 4, 0x0000, 0x0000, 0x0000, 0x0000,
 286                           0x555, 0x2aa, 0);
 287
 288     /* NIC: rtl8139 on-board, and 2 slots. */
 289     for (i = 0; i < nb_nics; i++)
 290         pci_nic_init_nofail(&nd_table[i], "rtl8139", i==0 ? "2" : NULL);
 291
 292     /* USB keyboard */
 293     usbdevice_create("keyboard");
 294
 295     /* Todo: register on board registers */
 296     memset(&boot_params, 0, sizeof(boot_params));
 297
 298     if (kernel_filename) {
 299         int kernel_size;
 300
 301         kernel_size = load_image_targphys(kernel_filename,
 302                                           SDRAM_BASE + LINUX_LOAD_OFFSET,
 303                                           INITRD_LOAD_OFFSET - LINUX_LOAD_OFFSET);
 304         if (kernel_size < 0) {
 305           fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename);
 306           exit(1);
 307         }
 308
 309         /* initialization which should be done by firmware */
 310         stl_phys(SH7750_BCR1, 1<<3); /* cs3 SDRAM */
 311         stw_phys(SH7750_BCR2, 3<<(3*2)); /* cs3 32bit */
 312         reset_info->vector = (SDRAM_BASE + LINUX_LOAD_OFFSET) | 0xa0000000; /* Start from P2 area */
 313     }
 314
 315     if (initrd_filename) {
 316         int initrd_size;
 317
 318         initrd_size = load_image_targphys(initrd_filename,
 319                                           SDRAM_BASE + INITRD_LOAD_OFFSET,
 320                                           SDRAM_SIZE - INITRD_LOAD_OFFSET);
 321
 322         if (initrd_size < 0) {
 323           fprintf(stderr, "qemu: could not load initrd '%s'\n", initrd_filename);
 324           exit(1);
 325         }
 326
 327         /* initialization which should be done by firmware */
 328         boot_params.loader_type = 1;
 329         boot_params.initrd_start = INITRD_LOAD_OFFSET;
 330         boot_params.initrd_size = initrd_size;
 331     }
 332
 333     if (kernel_cmdline) {
 334         strncpy(boot_params.kernel_cmdline, kernel_cmdline,
 335                 sizeof(boot_params.kernel_cmdline));
 336     }
 337
 338     rom_add_blob_fixed("boot_params", &boot_params, sizeof(boot_params),
 339                        SDRAM_BASE + BOOT_PARAMS_OFFSET);
 340 }
 341
 342 static QEMUMachine r2d_machine = {
 343     .name = "r2d",
 344     .desc = "r2d-plus board",
 345     .init = r2d_init,
 346 };
 347
 348 static void r2d_machine_init(void)
 349 {
 350     qemu_register_machine(&r2d_machine);
 351 }
 352
 353 machine_init(r2d_machine_init);