hw/ppc405_boards.c

   1 /*
   2  * QEMU PowerPC 405 evaluation boards emulation
   3  *
   4  * Copyright (c) 2007 Jocelyn Mayer
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "ppc.h"
  26 #include "ppc405.h"
  27 #include "nvram.h"
  28 #include "flash.h"
  29 #include "sysemu.h"
  30 #include "block.h"
  31 #include "boards.h"
  32 #include "qemu-log.h"
  33 #include "loader.h"
  34 #include "blockdev.h"
  35
  36 #define BIOS_FILENAME "ppc405_rom.bin"
  37 #define BIOS_SIZE (2048 * 1024)
  38
  39 #define KERNEL_LOAD_ADDR 0x00000000
  40 #define INITRD_LOAD_ADDR 0x01800000
  41
  42 #define USE_FLASH_BIOS
  43
  44 #define DEBUG_BOARD_INIT
  45
  46 /*****************************************************************************/
  47 /* PPC405EP reference board (IBM) */
  48 /* Standalone board with:
  49  * - PowerPC 405EP CPU
  50  * - SDRAM (0x00000000)
  51  * - Flash (0xFFF80000)
  52  * - SRAM  (0xFFF00000)
  53  * - NVRAM (0xF0000000)
  54  * - FPGA  (0xF0300000)
  55  */
  56 typedef struct ref405ep_fpga_t ref405ep_fpga_t;
  57 struct ref405ep_fpga_t {
  58     uint8_t reg0;
  59     uint8_t reg1;
  60 };
  61
  62 static uint32_t ref405ep_fpga_readb (void *opaque, target_phys_addr_t addr)
  63 {
  64     ref405ep_fpga_t *fpga;
  65     uint32_t ret;
  66
  67     fpga = opaque;
  68     switch (addr) {
  69     case 0x0:
  70         ret = fpga->reg0;
  71         break;
  72     case 0x1:
  73         ret = fpga->reg1;
  74         break;
  75     default:
  76         ret = 0;
  77         break;
  78     }
  79
  80     return ret;
  81 }
  82
  83 static void ref405ep_fpga_writeb (void *opaque,
  84                                   target_phys_addr_t addr, uint32_t value)
  85 {
  86     ref405ep_fpga_t *fpga;
  87
  88     fpga = opaque;
  89     switch (addr) {
  90     case 0x0:
  91         /* Read only */
  92         break;
  93     case 0x1:
  94         fpga->reg1 = value;
  95         break;
  96     default:
  97         break;
  98     }
  99 }
 100
 101 static uint32_t ref405ep_fpga_readw (void *opaque, target_phys_addr_t addr)
 102 {
 103     uint32_t ret;
 104
 105     ret = ref405ep_fpga_readb(opaque, addr) << 8;
 106     ret |= ref405ep_fpga_readb(opaque, addr + 1);
 107
 108     return ret;
 109 }
 110
 111 static void ref405ep_fpga_writew (void *opaque,
 112                                   target_phys_addr_t addr, uint32_t value)
 113 {
 114     ref405ep_fpga_writeb(opaque, addr, (value >> 8) & 0xFF);
 115     ref405ep_fpga_writeb(opaque, addr + 1, value & 0xFF);
 116 }
 117
 118 static uint32_t ref405ep_fpga_readl (void *opaque, target_phys_addr_t addr)
 119 {
 120     uint32_t ret;
 121
 122     ret = ref405ep_fpga_readb(opaque, addr) << 24;
 123     ret |= ref405ep_fpga_readb(opaque, addr + 1) << 16;
 124     ret |= ref405ep_fpga_readb(opaque, addr + 2) << 8;
 125     ret |= ref405ep_fpga_readb(opaque, addr + 3);
 126
 127     return ret;
 128 }
 129
 130 static void ref405ep_fpga_writel (void *opaque,
 131                                   target_phys_addr_t addr, uint32_t value)
 132 {
 133     ref405ep_fpga_writeb(opaque, addr, (value >> 24) & 0xFF);
 134     ref405ep_fpga_writeb(opaque, addr + 1, (value >> 16) & 0xFF);
 135     ref405ep_fpga_writeb(opaque, addr + 2, (value >> 8) & 0xFF);
 136     ref405ep_fpga_writeb(opaque, addr + 3, value & 0xFF);
 137 }
 138
 139 static CPUReadMemoryFunc * const ref405ep_fpga_read[] = {
 140     &ref405ep_fpga_readb,
 141     &ref405ep_fpga_readw,
 142     &ref405ep_fpga_readl,
 143 };
 144
 145 static CPUWriteMemoryFunc * const ref405ep_fpga_write[] = {
 146     &ref405ep_fpga_writeb,
 147     &ref405ep_fpga_writew,
 148     &ref405ep_fpga_writel,
 149 };
 150
 151 static void ref405ep_fpga_reset (void *opaque)
 152 {
 153     ref405ep_fpga_t *fpga;
 154
 155     fpga = opaque;
 156     fpga->reg0 = 0x00;
 157     fpga->reg1 = 0x0F;
 158 }
 159
 160 static void ref405ep_fpga_init (uint32_t base)
 161 {
 162     ref405ep_fpga_t *fpga;
 163     int fpga_memory;
 164
 165     fpga = qemu_mallocz(sizeof(ref405ep_fpga_t));
 166     fpga_memory = cpu_register_io_memory(ref405ep_fpga_read,
 167                                          ref405ep_fpga_write, fpga);
 168     cpu_register_physical_memory(base, 0x00000100, fpga_memory);
 169     qemu_register_reset(&ref405ep_fpga_reset, fpga);
 170 }
 171
 172 static void ref405ep_init (ram_addr_t ram_size,
 173                            const char *boot_device,
 174                            const char *kernel_filename,
 175                            const char *kernel_cmdline,
 176                            const char *initrd_filename,
 177                            const char *cpu_model)
 178 {
 179     char *filename;
 180     ppc4xx_bd_info_t bd;
 181     CPUPPCState *env;
 182     qemu_irq *pic;
 183     ram_addr_t sram_offset, bios_offset, bdloc;
 184     target_phys_addr_t ram_bases[2], ram_sizes[2];
 185     target_ulong sram_size;
 186     long bios_size;
 187     //int phy_addr = 0;
 188     //static int phy_addr = 1;
 189     target_ulong kernel_base, initrd_base;
 190     long kernel_size, initrd_size;
 191     int linux_boot;
 192     int fl_idx, fl_sectors, len;
 193     DriveInfo *dinfo;
 194
 195     /* XXX: fix this */
 196     ram_bases[0] = qemu_ram_alloc(NULL, "ef405ep.ram", 0x08000000);
 197     ram_sizes[0] = 0x08000000;
 198     ram_bases[1] = 0x00000000;
 199     ram_sizes[1] = 0x00000000;
 200     ram_size = 128 * 1024 * 1024;
 201 #ifdef DEBUG_BOARD_INIT
 202     printf("%s: register cpu\n", __func__);
 203 #endif
 204     env = ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic,
 205                         kernel_filename == NULL ? 0 : 1);
 206     /* allocate SRAM */
 207     sram_size = 512 * 1024;
 208     sram_offset = qemu_ram_alloc(NULL, "ef405ep.sram", sram_size);
 209 #ifdef DEBUG_BOARD_INIT
 210     printf("%s: register SRAM at offset %08lx\n", __func__, sram_offset);
 211 #endif
 212     cpu_register_physical_memory(0xFFF00000, sram_size,
 213                                  sram_offset | IO_MEM_RAM);
 214     /* allocate and load BIOS */
 215 #ifdef DEBUG_BOARD_INIT
 216     printf("%s: register BIOS\n", __func__);
 217 #endif
 218     fl_idx = 0;
 219 #ifdef USE_FLASH_BIOS
 220     dinfo = drive_get(IF_PFLASH, 0, fl_idx);
 221     if (dinfo) {
 222         bios_size = bdrv_getlength(dinfo->bdrv);
 223         bios_offset = qemu_ram_alloc(NULL, "ef405ep.bios", bios_size);
 224         fl_sectors = (bios_size + 65535) >> 16;
 225 #ifdef DEBUG_BOARD_INIT
 226         printf("Register parallel flash %d size %lx"
 227                " at offset %08lx addr %lx '%s' %d\n",
 228                fl_idx, bios_size, bios_offset, -bios_size,
 229                bdrv_get_device_name(dinfo->bdrv), fl_sectors);
 230 #endif
 231         pflash_cfi02_register((uint32_t)(-bios_size), bios_offset,
 232                               dinfo->bdrv, 65536, fl_sectors, 1,
 233                               2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
 234                               1);
 235         fl_idx++;
 236     } else
 237 #endif
 238     {
 239 #ifdef DEBUG_BOARD_INIT
 240         printf("Load BIOS from file\n");
 241 #endif
 242         bios_offset = qemu_ram_alloc(NULL, "ef405ep.bios", BIOS_SIZE);
 243         if (bios_name == NULL)
 244             bios_name = BIOS_FILENAME;
 245         filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 246         if (filename) {
 247             bios_size = load_image(filename, qemu_get_ram_ptr(bios_offset));
 248             qemu_free(filename);
 249         } else {
 250             bios_size = -1;
 251         }
 252         if (bios_size < 0 || bios_size > BIOS_SIZE) {
 253             fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n",
 254                     bios_name);
 255             exit(1);
 256         }
 257         bios_size = (bios_size + 0xfff) & ~0xfff;
 258         cpu_register_physical_memory((uint32_t)(-bios_size),
 259                                      bios_size, bios_offset | IO_MEM_ROM);
 260     }
 261     /* Register FPGA */
 262 #ifdef DEBUG_BOARD_INIT
 263     printf("%s: register FPGA\n", __func__);
 264 #endif
 265     ref405ep_fpga_init(0xF0300000);
 266     /* Register NVRAM */
 267 #ifdef DEBUG_BOARD_INIT
 268     printf("%s: register NVRAM\n", __func__);
 269 #endif
 270     m48t59_init(NULL, 0xF0000000, 0, 8192, 8);
 271     /* Load kernel */
 272     linux_boot = (kernel_filename != NULL);
 273     if (linux_boot) {
 274 #ifdef DEBUG_BOARD_INIT
 275         printf("%s: load kernel\n", __func__);
 276 #endif
 277         memset(&bd, 0, sizeof(bd));
 278         bd.bi_memstart = 0x00000000;
 279         bd.bi_memsize = ram_size;
 280         bd.bi_flashstart = -bios_size;
 281         bd.bi_flashsize = -bios_size;
 282         bd.bi_flashoffset = 0;
 283         bd.bi_sramstart = 0xFFF00000;
 284         bd.bi_sramsize = sram_size;
 285         bd.bi_bootflags = 0;
 286         bd.bi_intfreq = 133333333;
 287         bd.bi_busfreq = 33333333;
 288         bd.bi_baudrate = 115200;
 289         bd.bi_s_version[0] = 'Q';
 290         bd.bi_s_version[1] = 'M';
 291         bd.bi_s_version[2] = 'U';
 292         bd.bi_s_version[3] = '\0';
 293         bd.bi_r_version[0] = 'Q';
 294         bd.bi_r_version[1] = 'E';
 295         bd.bi_r_version[2] = 'M';
 296         bd.bi_r_version[3] = 'U';
 297         bd.bi_r_version[4] = '\0';
 298         bd.bi_procfreq = 133333333;
 299         bd.bi_plb_busfreq = 33333333;
 300         bd.bi_pci_busfreq = 33333333;
 301         bd.bi_opbfreq = 33333333;
 302         bdloc = ppc405_set_bootinfo(env, &bd, 0x00000001);
 303         env->gpr[3] = bdloc;
 304         kernel_base = KERNEL_LOAD_ADDR;
 305         /* now we can load the kernel */
 306         kernel_size = load_image_targphys(kernel_filename, kernel_base,
 307                                           ram_size - kernel_base);
 308         if (kernel_size < 0) {
 309             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 310                     kernel_filename);
 311             exit(1);
 312         }
 313         printf("Load kernel size %ld at " TARGET_FMT_lx,
 314                kernel_size, kernel_base);
 315         /* load initrd */
 316         if (initrd_filename) {
 317             initrd_base = INITRD_LOAD_ADDR;
 318             initrd_size = load_image_targphys(initrd_filename, initrd_base,
 319                                               ram_size - initrd_base);
 320             if (initrd_size < 0) {
 321                 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 322                         initrd_filename);
 323                 exit(1);
 324             }
 325         } else {
 326             initrd_base = 0;
 327             initrd_size = 0;
 328         }
 329         env->gpr[4] = initrd_base;
 330         env->gpr[5] = initrd_size;
 331         if (kernel_cmdline != NULL) {
 332             len = strlen(kernel_cmdline);
 333             bdloc -= ((len + 255) & ~255);
 334             cpu_physical_memory_write(bdloc, (void *)kernel_cmdline, len + 1);
 335             env->gpr[6] = bdloc;
 336             env->gpr[7] = bdloc + len;
 337         } else {
 338             env->gpr[6] = 0;
 339             env->gpr[7] = 0;
 340         }
 341         env->nip = KERNEL_LOAD_ADDR;
 342     } else {
 343         kernel_base = 0;
 344         kernel_size = 0;
 345         initrd_base = 0;
 346         initrd_size = 0;
 347         bdloc = 0;
 348     }
 349 #ifdef DEBUG_BOARD_INIT
 350     printf("%s: Done\n", __func__);
 351 #endif
 352     printf("bdloc %016lx\n", (unsigned long)bdloc);
 353 }
 354
 355 static QEMUMachine ref405ep_machine = {
 356     .name = "ref405ep",
 357     .desc = "ref405ep",
 358     .init = ref405ep_init,
 359 };
 360
 361 /*****************************************************************************/
 362 /* AMCC Taihu evaluation board */
 363 /* - PowerPC 405EP processor
 364  * - SDRAM               128 MB at 0x00000000
 365  * - Boot flash          2 MB   at 0xFFE00000
 366  * - Application flash   32 MB  at 0xFC000000
 367  * - 2 serial ports
 368  * - 2 ethernet PHY
 369  * - 1 USB 1.1 device    0x50000000
 370  * - 1 LCD display       0x50100000
 371  * - 1 CPLD              0x50100000
 372  * - 1 I2C EEPROM
 373  * - 1 I2C thermal sensor
 374  * - a set of LEDs
 375  * - bit-bang SPI port using GPIOs
 376  * - 1 EBC interface connector 0 0x50200000
 377  * - 1 cardbus controller + expansion slot.
 378  * - 1 PCI expansion slot.
 379  */
 380 typedef struct taihu_cpld_t taihu_cpld_t;
 381 struct taihu_cpld_t {
 382     uint8_t reg0;
 383     uint8_t reg1;
 384 };
 385
 386 static uint32_t taihu_cpld_readb (void *opaque, target_phys_addr_t addr)
 387 {
 388     taihu_cpld_t *cpld;
 389     uint32_t ret;
 390
 391     cpld = opaque;
 392     switch (addr) {
 393     case 0x0:
 394         ret = cpld->reg0;
 395         break;
 396     case 0x1:
 397         ret = cpld->reg1;
 398         break;
 399     default:
 400         ret = 0;
 401         break;
 402     }
 403
 404     return ret;
 405 }
 406
 407 static void taihu_cpld_writeb (void *opaque,
 408                                target_phys_addr_t addr, uint32_t value)
 409 {
 410     taihu_cpld_t *cpld;
 411
 412     cpld = opaque;
 413     switch (addr) {
 414     case 0x0:
 415         /* Read only */
 416         break;
 417     case 0x1:
 418         cpld->reg1 = value;
 419         break;
 420     default:
 421         break;
 422     }
 423 }
 424
 425 static uint32_t taihu_cpld_readw (void *opaque, target_phys_addr_t addr)
 426 {
 427     uint32_t ret;
 428
 429     ret = taihu_cpld_readb(opaque, addr) << 8;
 430     ret |= taihu_cpld_readb(opaque, addr + 1);
 431
 432     return ret;
 433 }
 434
 435 static void taihu_cpld_writew (void *opaque,
 436                                target_phys_addr_t addr, uint32_t value)
 437 {
 438     taihu_cpld_writeb(opaque, addr, (value >> 8) & 0xFF);
 439     taihu_cpld_writeb(opaque, addr + 1, value & 0xFF);
 440 }
 441
 442 static uint32_t taihu_cpld_readl (void *opaque, target_phys_addr_t addr)
 443 {
 444     uint32_t ret;
 445
 446     ret = taihu_cpld_readb(opaque, addr) << 24;
 447     ret |= taihu_cpld_readb(opaque, addr + 1) << 16;
 448     ret |= taihu_cpld_readb(opaque, addr + 2) << 8;
 449     ret |= taihu_cpld_readb(opaque, addr + 3);
 450
 451     return ret;
 452 }
 453
 454 static void taihu_cpld_writel (void *opaque,
 455                                target_phys_addr_t addr, uint32_t value)
 456 {
 457     taihu_cpld_writel(opaque, addr, (value >> 24) & 0xFF);
 458     taihu_cpld_writel(opaque, addr + 1, (value >> 16) & 0xFF);
 459     taihu_cpld_writel(opaque, addr + 2, (value >> 8) & 0xFF);
 460     taihu_cpld_writeb(opaque, addr + 3, value & 0xFF);
 461 }
 462
 463 static CPUReadMemoryFunc * const taihu_cpld_read[] = {
 464     &taihu_cpld_readb,
 465     &taihu_cpld_readw,
 466     &taihu_cpld_readl,
 467 };
 468
 469 static CPUWriteMemoryFunc * const taihu_cpld_write[] = {
 470     &taihu_cpld_writeb,
 471     &taihu_cpld_writew,
 472     &taihu_cpld_writel,
 473 };
 474
 475 static void taihu_cpld_reset (void *opaque)
 476 {
 477     taihu_cpld_t *cpld;
 478
 479     cpld = opaque;
 480     cpld->reg0 = 0x01;
 481     cpld->reg1 = 0x80;
 482 }
 483
 484 static void taihu_cpld_init (uint32_t base)
 485 {
 486     taihu_cpld_t *cpld;
 487     int cpld_memory;
 488
 489     cpld = qemu_mallocz(sizeof(taihu_cpld_t));
 490     cpld_memory = cpu_register_io_memory(taihu_cpld_read,
 491                                          taihu_cpld_write, cpld);
 492     cpu_register_physical_memory(base, 0x00000100, cpld_memory);
 493     qemu_register_reset(&taihu_cpld_reset, cpld);
 494 }
 495
 496 static void taihu_405ep_init(ram_addr_t ram_size,
 497                              const char *boot_device,
 498                              const char *kernel_filename,
 499                              const char *kernel_cmdline,
 500                              const char *initrd_filename,
 501                              const char *cpu_model)
 502 {
 503     char *filename;
 504     qemu_irq *pic;
 505     ram_addr_t bios_offset;
 506     target_phys_addr_t ram_bases[2], ram_sizes[2];
 507     long bios_size;
 508     target_ulong kernel_base, initrd_base;
 509     long kernel_size, initrd_size;
 510     int linux_boot;
 511     int fl_idx, fl_sectors;
 512     DriveInfo *dinfo;
 513
 514     /* RAM is soldered to the board so the size cannot be changed */
 515     ram_bases[0] = qemu_ram_alloc(NULL, "taihu_405ep.ram-0", 0x04000000);
 516     ram_sizes[0] = 0x04000000;
 517     ram_bases[1] = qemu_ram_alloc(NULL, "taihu_405ep.ram-1", 0x04000000);
 518     ram_sizes[1] = 0x04000000;
 519     ram_size = 0x08000000;
 520 #ifdef DEBUG_BOARD_INIT
 521     printf("%s: register cpu\n", __func__);
 522 #endif
 523     ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic,
 524                   kernel_filename == NULL ? 0 : 1);
 525     /* allocate and load BIOS */
 526 #ifdef DEBUG_BOARD_INIT
 527     printf("%s: register BIOS\n", __func__);
 528 #endif
 529     fl_idx = 0;
 530 #if defined(USE_FLASH_BIOS)
 531     dinfo = drive_get(IF_PFLASH, 0, fl_idx);
 532     if (dinfo) {
 533         bios_size = bdrv_getlength(dinfo->bdrv);
 534         /* XXX: should check that size is 2MB */
 535         //        bios_size = 2 * 1024 * 1024;
 536         fl_sectors = (bios_size + 65535) >> 16;
 537         bios_offset = qemu_ram_alloc(NULL, "taihu_405ep.bios", bios_size);
 538 #ifdef DEBUG_BOARD_INIT
 539         printf("Register parallel flash %d size %lx"
 540                " at offset %08lx addr %lx '%s' %d\n",
 541                fl_idx, bios_size, bios_offset, -bios_size,
 542                bdrv_get_device_name(dinfo->bdrv), fl_sectors);
 543 #endif
 544         pflash_cfi02_register((uint32_t)(-bios_size), bios_offset,
 545                               dinfo->bdrv, 65536, fl_sectors, 1,
 546                               4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
 547                               1);
 548         fl_idx++;
 549     } else
 550 #endif
 551     {
 552 #ifdef DEBUG_BOARD_INIT
 553         printf("Load BIOS from file\n");
 554 #endif
 555         if (bios_name == NULL)
 556             bios_name = BIOS_FILENAME;
 557         bios_offset = qemu_ram_alloc(NULL, "taihu_405ep.bios", BIOS_SIZE);
 558         filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 559         if (filename) {
 560             bios_size = load_image(filename, qemu_get_ram_ptr(bios_offset));
 561         } else {
 562             bios_size = -1;
 563         }
 564         if (bios_size < 0 || bios_size > BIOS_SIZE) {
 565             fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n",
 566                     bios_name);
 567             exit(1);
 568         }
 569         bios_size = (bios_size + 0xfff) & ~0xfff;
 570         cpu_register_physical_memory((uint32_t)(-bios_size),
 571                                      bios_size, bios_offset | IO_MEM_ROM);
 572     }
 573     /* Register Linux flash */
 574     dinfo = drive_get(IF_PFLASH, 0, fl_idx);
 575     if (dinfo) {
 576         bios_size = bdrv_getlength(dinfo->bdrv);
 577         /* XXX: should check that size is 32MB */
 578         bios_size = 32 * 1024 * 1024;
 579         fl_sectors = (bios_size + 65535) >> 16;
 580 #ifdef DEBUG_BOARD_INIT
 581         printf("Register parallel flash %d size %lx"
 582                " at offset %08lx  addr " TARGET_FMT_lx " '%s'\n",
 583                fl_idx, bios_size, bios_offset, (target_ulong)0xfc000000,
 584                bdrv_get_device_name(dinfo->bdrv));
 585 #endif
 586         bios_offset = qemu_ram_alloc(NULL, "taihu_405ep.flash", bios_size);
 587         pflash_cfi02_register(0xfc000000, bios_offset,
 588                               dinfo->bdrv, 65536, fl_sectors, 1,
 589                               4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
 590                               1);
 591         fl_idx++;
 592     }
 593     /* Register CLPD & LCD display */
 594 #ifdef DEBUG_BOARD_INIT
 595     printf("%s: register CPLD\n", __func__);
 596 #endif
 597     taihu_cpld_init(0x50100000);
 598     /* Load kernel */
 599     linux_boot = (kernel_filename != NULL);
 600     if (linux_boot) {
 601 #ifdef DEBUG_BOARD_INIT
 602         printf("%s: load kernel\n", __func__);
 603 #endif
 604         kernel_base = KERNEL_LOAD_ADDR;
 605         /* now we can load the kernel */
 606         kernel_size = load_image_targphys(kernel_filename, kernel_base,
 607                                           ram_size - kernel_base);
 608         if (kernel_size < 0) {
 609             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 610                     kernel_filename);
 611             exit(1);
 612         }
 613         /* load initrd */
 614         if (initrd_filename) {
 615             initrd_base = INITRD_LOAD_ADDR;
 616             initrd_size = load_image_targphys(initrd_filename, initrd_base,
 617                                               ram_size - initrd_base);
 618             if (initrd_size < 0) {
 619                 fprintf(stderr,
 620                         "qemu: could not load initial ram disk '%s'\n",
 621                         initrd_filename);
 622                 exit(1);
 623             }
 624         } else {
 625             initrd_base = 0;
 626             initrd_size = 0;
 627         }
 628     } else {
 629         kernel_base = 0;
 630         kernel_size = 0;
 631         initrd_base = 0;
 632         initrd_size = 0;
 633     }
 634 #ifdef DEBUG_BOARD_INIT
 635     printf("%s: Done\n", __func__);
 636 #endif
 637 }
 638
 639 static QEMUMachine taihu_machine = {
 640     .name = "taihu",
 641     .desc = "taihu",
 642     .init = taihu_405ep_init,
 643 };
 644
 645 static void ppc405_machine_init(void)
 646 {
 647     qemu_register_machine(&ref405ep_machine);
 648     qemu_register_machine(&taihu_machine);
 649 }
 650
 651 machine_init(ppc405_machine_init);