tests: add top-level make dependency for docker builds
[qemu.git] / hw / acpi / pcihp.c
blob80d42e12ff740893340041b2bc5aad55d1eabf46
1 /*
2 * QEMU<->ACPI BIOS PCI hotplug interface
4 * QEMU supports PCI hotplug via ACPI. This module
5 * implements the interface between QEMU and the ACPI BIOS.
6 * Interface specification - see docs/specs/acpi_pci_hotplug.txt
8 * Copyright (c) 2013, Red Hat Inc, Michael S. Tsirkin (mst@redhat.com)
9 * Copyright (c) 2006 Fabrice Bellard
11 * This library is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU Lesser General Public
13 * License version 2 as published by the Free Software Foundation.
15 * This library is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * Lesser General Public License for more details.
20 * You should have received a copy of the GNU Lesser General Public
21 * License along with this library; if not, see <http://www.gnu.org/licenses/>
23 * Contributions after 2012-01-13 are licensed under the terms of the
24 * GNU GPL, version 2 or (at your option) any later version.
27 #include "qemu/osdep.h"
28 #include "hw/acpi/pcihp.h"
30 #include "hw/hw.h"
31 #include "hw/i386/pc.h"
32 #include "hw/pci/pci.h"
33 #include "hw/acpi/acpi.h"
34 #include "sysemu/sysemu.h"
35 #include "exec/address-spaces.h"
36 #include "hw/pci/pci_bus.h"
37 #include "qapi/error.h"
38 #include "qom/qom-qobject.h"
40 //#define DEBUG
42 #ifdef DEBUG
43 # define ACPI_PCIHP_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
44 #else
45 # define ACPI_PCIHP_DPRINTF(format, ...) do { } while (0)
46 #endif
48 #define ACPI_PCIHP_ADDR 0xae00
49 #define ACPI_PCIHP_SIZE 0x0014
50 #define PCI_UP_BASE 0x0000
51 #define PCI_DOWN_BASE 0x0004
52 #define PCI_EJ_BASE 0x0008
53 #define PCI_RMV_BASE 0x000c
54 #define PCI_SEL_BASE 0x0010
56 typedef struct AcpiPciHpFind {
57 int bsel;
58 PCIBus *bus;
59 } AcpiPciHpFind;
61 static int acpi_pcihp_get_bsel(PCIBus *bus)
63 Error *local_err = NULL;
64 uint64_t bsel = object_property_get_uint(OBJECT(bus), ACPI_PCIHP_PROP_BSEL,
65 &local_err);
67 if (local_err || bsel >= ACPI_PCIHP_MAX_HOTPLUG_BUS) {
68 if (local_err) {
69 error_free(local_err);
71 return -1;
72 } else {
73 return bsel;
77 /* Assign BSEL property to all buses. In the future, this can be changed
78 * to only assign to buses that support hotplug.
80 static void *acpi_set_bsel(PCIBus *bus, void *opaque)
82 unsigned *bsel_alloc = opaque;
83 unsigned *bus_bsel;
85 if (qbus_is_hotpluggable(BUS(bus))) {
86 bus_bsel = g_malloc(sizeof *bus_bsel);
88 *bus_bsel = (*bsel_alloc)++;
89 object_property_add_uint32_ptr(OBJECT(bus), ACPI_PCIHP_PROP_BSEL,
90 bus_bsel, &error_abort);
93 return bsel_alloc;
96 static void acpi_set_pci_info(void)
98 static bool bsel_is_set;
99 PCIBus *bus;
100 unsigned bsel_alloc = ACPI_PCIHP_BSEL_DEFAULT;
102 if (bsel_is_set) {
103 return;
105 bsel_is_set = true;
107 bus = find_i440fx(); /* TODO: Q35 support */
108 if (bus) {
109 /* Scan all PCI buses. Set property to enable acpi based hotplug. */
110 pci_for_each_bus_depth_first(bus, acpi_set_bsel, NULL, &bsel_alloc);
114 static void acpi_pcihp_test_hotplug_bus(PCIBus *bus, void *opaque)
116 AcpiPciHpFind *find = opaque;
117 if (find->bsel == acpi_pcihp_get_bsel(bus)) {
118 find->bus = bus;
122 static PCIBus *acpi_pcihp_find_hotplug_bus(AcpiPciHpState *s, int bsel)
124 AcpiPciHpFind find = { .bsel = bsel, .bus = NULL };
126 if (bsel < 0) {
127 return NULL;
130 pci_for_each_bus(s->root, acpi_pcihp_test_hotplug_bus, &find);
132 /* Make bsel 0 eject root bus if bsel property is not set,
133 * for compatibility with non acpi setups.
134 * TODO: really needed?
136 if (!bsel && !find.bus) {
137 find.bus = s->root;
139 return find.bus;
142 static bool acpi_pcihp_pc_no_hotplug(AcpiPciHpState *s, PCIDevice *dev)
144 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
145 DeviceClass *dc = DEVICE_GET_CLASS(dev);
147 * ACPI doesn't allow hotplug of bridge devices. Don't allow
148 * hot-unplug of bridge devices unless they were added by hotplug
149 * (and so, not described by acpi).
151 return (pc->is_bridge && !dev->qdev.hotplugged) || !dc->hotpluggable;
154 static void acpi_pcihp_eject_slot(AcpiPciHpState *s, unsigned bsel, unsigned slots)
156 BusChild *kid, *next;
157 int slot = ctz32(slots);
158 PCIBus *bus = acpi_pcihp_find_hotplug_bus(s, bsel);
160 if (!bus) {
161 return;
164 /* Mark request as complete */
165 s->acpi_pcihp_pci_status[bsel].down &= ~(1U << slot);
166 s->acpi_pcihp_pci_status[bsel].up &= ~(1U << slot);
168 QTAILQ_FOREACH_SAFE(kid, &bus->qbus.children, sibling, next) {
169 DeviceState *qdev = kid->child;
170 PCIDevice *dev = PCI_DEVICE(qdev);
171 if (PCI_SLOT(dev->devfn) == slot) {
172 if (!acpi_pcihp_pc_no_hotplug(s, dev)) {
173 object_unparent(OBJECT(qdev));
179 static void acpi_pcihp_update_hotplug_bus(AcpiPciHpState *s, int bsel)
181 BusChild *kid, *next;
182 PCIBus *bus = acpi_pcihp_find_hotplug_bus(s, bsel);
184 /* Execute any pending removes during reset */
185 while (s->acpi_pcihp_pci_status[bsel].down) {
186 acpi_pcihp_eject_slot(s, bsel, s->acpi_pcihp_pci_status[bsel].down);
189 s->acpi_pcihp_pci_status[bsel].hotplug_enable = ~0;
191 if (!bus) {
192 return;
194 QTAILQ_FOREACH_SAFE(kid, &bus->qbus.children, sibling, next) {
195 DeviceState *qdev = kid->child;
196 PCIDevice *pdev = PCI_DEVICE(qdev);
197 int slot = PCI_SLOT(pdev->devfn);
199 if (acpi_pcihp_pc_no_hotplug(s, pdev)) {
200 s->acpi_pcihp_pci_status[bsel].hotplug_enable &= ~(1U << slot);
205 static void acpi_pcihp_update(AcpiPciHpState *s)
207 int i;
209 for (i = 0; i < ACPI_PCIHP_MAX_HOTPLUG_BUS; ++i) {
210 acpi_pcihp_update_hotplug_bus(s, i);
214 void acpi_pcihp_reset(AcpiPciHpState *s)
216 acpi_set_pci_info();
217 acpi_pcihp_update(s);
220 void acpi_pcihp_device_plug_cb(HotplugHandler *hotplug_dev, AcpiPciHpState *s,
221 DeviceState *dev, Error **errp)
223 PCIDevice *pdev = PCI_DEVICE(dev);
224 int slot = PCI_SLOT(pdev->devfn);
225 int bsel = acpi_pcihp_get_bsel(pci_get_bus(pdev));
226 if (bsel < 0) {
227 error_setg(errp, "Unsupported bus. Bus doesn't have property '"
228 ACPI_PCIHP_PROP_BSEL "' set");
229 return;
232 /* Don't send event when device is enabled during qemu machine creation:
233 * it is present on boot, no hotplug event is necessary. We do send an
234 * event when the device is disabled later. */
235 if (!dev->hotplugged) {
236 return;
239 s->acpi_pcihp_pci_status[bsel].up |= (1U << slot);
240 acpi_send_event(DEVICE(hotplug_dev), ACPI_PCI_HOTPLUG_STATUS);
243 void acpi_pcihp_device_unplug_cb(HotplugHandler *hotplug_dev, AcpiPciHpState *s,
244 DeviceState *dev, Error **errp)
246 PCIDevice *pdev = PCI_DEVICE(dev);
247 int slot = PCI_SLOT(pdev->devfn);
248 int bsel = acpi_pcihp_get_bsel(pci_get_bus(pdev));
249 if (bsel < 0) {
250 error_setg(errp, "Unsupported bus. Bus doesn't have property '"
251 ACPI_PCIHP_PROP_BSEL "' set");
252 return;
255 s->acpi_pcihp_pci_status[bsel].down |= (1U << slot);
256 acpi_send_event(DEVICE(hotplug_dev), ACPI_PCI_HOTPLUG_STATUS);
259 static uint64_t pci_read(void *opaque, hwaddr addr, unsigned int size)
261 AcpiPciHpState *s = opaque;
262 uint32_t val = 0;
263 int bsel = s->hotplug_select;
265 if (bsel < 0 || bsel >= ACPI_PCIHP_MAX_HOTPLUG_BUS) {
266 return 0;
269 switch (addr) {
270 case PCI_UP_BASE:
271 val = s->acpi_pcihp_pci_status[bsel].up;
272 if (!s->legacy_piix) {
273 s->acpi_pcihp_pci_status[bsel].up = 0;
275 ACPI_PCIHP_DPRINTF("pci_up_read %" PRIu32 "\n", val);
276 break;
277 case PCI_DOWN_BASE:
278 val = s->acpi_pcihp_pci_status[bsel].down;
279 ACPI_PCIHP_DPRINTF("pci_down_read %" PRIu32 "\n", val);
280 break;
281 case PCI_EJ_BASE:
282 /* No feature defined yet */
283 ACPI_PCIHP_DPRINTF("pci_features_read %" PRIu32 "\n", val);
284 break;
285 case PCI_RMV_BASE:
286 val = s->acpi_pcihp_pci_status[bsel].hotplug_enable;
287 ACPI_PCIHP_DPRINTF("pci_rmv_read %" PRIu32 "\n", val);
288 break;
289 case PCI_SEL_BASE:
290 val = s->hotplug_select;
291 ACPI_PCIHP_DPRINTF("pci_sel_read %" PRIu32 "\n", val);
292 default:
293 break;
296 return val;
299 static void pci_write(void *opaque, hwaddr addr, uint64_t data,
300 unsigned int size)
302 AcpiPciHpState *s = opaque;
303 switch (addr) {
304 case PCI_EJ_BASE:
305 if (s->hotplug_select >= ACPI_PCIHP_MAX_HOTPLUG_BUS) {
306 break;
308 acpi_pcihp_eject_slot(s, s->hotplug_select, data);
309 ACPI_PCIHP_DPRINTF("pciej write %" HWADDR_PRIx " <== %" PRIu64 "\n",
310 addr, data);
311 break;
312 case PCI_SEL_BASE:
313 s->hotplug_select = s->legacy_piix ? ACPI_PCIHP_BSEL_DEFAULT : data;
314 ACPI_PCIHP_DPRINTF("pcisel write %" HWADDR_PRIx " <== %" PRIu64 "\n",
315 addr, data);
316 default:
317 break;
321 static const MemoryRegionOps acpi_pcihp_io_ops = {
322 .read = pci_read,
323 .write = pci_write,
324 .endianness = DEVICE_LITTLE_ENDIAN,
325 .valid = {
326 .min_access_size = 4,
327 .max_access_size = 4,
331 void acpi_pcihp_init(Object *owner, AcpiPciHpState *s, PCIBus *root_bus,
332 MemoryRegion *address_space_io, bool bridges_enabled)
334 s->io_len = ACPI_PCIHP_SIZE;
335 s->io_base = ACPI_PCIHP_ADDR;
337 s->root= root_bus;
338 s->legacy_piix = !bridges_enabled;
340 memory_region_init_io(&s->io, owner, &acpi_pcihp_io_ops, s,
341 "acpi-pci-hotplug", s->io_len);
342 memory_region_add_subregion(address_space_io, s->io_base, &s->io);
344 object_property_add_uint16_ptr(owner, ACPI_PCIHP_IO_BASE_PROP, &s->io_base,
345 &error_abort);
346 object_property_add_uint16_ptr(owner, ACPI_PCIHP_IO_LEN_PROP, &s->io_len,
347 &error_abort);
350 const VMStateDescription vmstate_acpi_pcihp_pci_status = {
351 .name = "acpi_pcihp_pci_status",
352 .version_id = 1,
353 .minimum_version_id = 1,
354 .fields = (VMStateField[]) {
355 VMSTATE_UINT32(up, AcpiPciHpPciStatus),
356 VMSTATE_UINT32(down, AcpiPciHpPciStatus),
357 VMSTATE_END_OF_LIST()