target-ppc/misc_helper.c

   1 /*
   2  * Miscellaneous PowerPC emulation helpers for QEMU.
   3  *
   4  *  Copyright (c) 2003-2007 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include "cpu.h"
  20 #include "helper.h"
  21
  22 #include "helper_regs.h"
  23
  24 /*****************************************************************************/
  25 /* SPR accesses */
  26 void helper_load_dump_spr(CPUPPCState *env, uint32_t sprn)
  27 {
  28     qemu_log("Read SPR %d %03x => " TARGET_FMT_lx "\n", sprn, sprn,
  29              env->spr[sprn]);
  30 }
  31
  32 void helper_store_dump_spr(CPUPPCState *env, uint32_t sprn)
  33 {
  34     qemu_log("Write SPR %d %03x <= " TARGET_FMT_lx "\n", sprn, sprn,
  35              env->spr[sprn]);
  36 }
  37 #if !defined(CONFIG_USER_ONLY)
  38
  39 void helper_store_sdr1(CPUPPCState *env, target_ulong val)
  40 {
  41     if (!env->external_htab) {
  42         ppc_store_sdr1(env, val);
  43     }
  44 }
  45
  46 void helper_store_hid0_601(CPUPPCState *env, target_ulong val)
  47 {
  48     target_ulong hid0;
  49
  50     hid0 = env->spr[SPR_HID0];
  51     if ((val ^ hid0) & 0x00000008) {
  52         /* Change current endianness */
  53         env->hflags &= ~(1 << MSR_LE);
  54         env->hflags_nmsr &= ~(1 << MSR_LE);
  55         env->hflags_nmsr |= (1 << MSR_LE) & (((val >> 3) & 1) << MSR_LE);
  56         env->hflags |= env->hflags_nmsr;
  57         qemu_log("%s: set endianness to %c => " TARGET_FMT_lx "\n", __func__,
  58                  val & 0x8 ? 'l' : 'b', env->hflags);
  59     }
  60     env->spr[SPR_HID0] = (uint32_t)val;
  61 }
  62
  63 void helper_store_403_pbr(CPUPPCState *env, uint32_t num, target_ulong value)
  64 {
  65     if (likely(env->pb[num] != value)) {
  66         env->pb[num] = value;
  67         /* Should be optimized */
  68         tlb_flush(env, 1);
  69     }
  70 }
  71
  72 void helper_store_40x_dbcr0(CPUPPCState *env, target_ulong val)
  73 {
  74     store_40x_dbcr0(env, val);
  75 }
  76
  77 void helper_store_40x_sler(CPUPPCState *env, target_ulong val)
  78 {
  79     store_40x_sler(env, val);
  80 }
  81 #endif
  82 /*****************************************************************************/
  83 /* PowerPC 601 specific instructions (POWER bridge) */
  84
  85 target_ulong helper_clcs(CPUPPCState *env, uint32_t arg)
  86 {
  87     switch (arg) {
  88     case 0x0CUL:
  89         /* Instruction cache line size */
  90         return env->icache_line_size;
  91         break;
  92     case 0x0DUL:
  93         /* Data cache line size */
  94         return env->dcache_line_size;
  95         break;
  96     case 0x0EUL:
  97         /* Minimum cache line size */
  98         return (env->icache_line_size < env->dcache_line_size) ?
  99             env->icache_line_size : env->dcache_line_size;
 100         break;
 101     case 0x0FUL:
 102         /* Maximum cache line size */
 103         return (env->icache_line_size > env->dcache_line_size) ?
 104             env->icache_line_size : env->dcache_line_size;
 105         break;
 106     default:
 107         /* Undefined */
 108         return 0;
 109         break;
 110     }
 111 }
 112
 113 /*****************************************************************************/
 114 /* Special registers manipulation */
 115
 116 /* GDBstub can read and write MSR... */
 117 void ppc_store_msr(CPUPPCState *env, target_ulong value)
 118 {
 119     hreg_store_msr(env, value, 0);
 120 }