target-i386/kvm.c

   1 /*
   2  * QEMU KVM support
   3  *
   4  * Copyright (C) 2006-2008 Qumranet Technologies
   5  * Copyright IBM, Corp. 2008
   6  *
   7  * Authors:
   8  *  Anthony Liguori   <aliguori@us.ibm.com>
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  11  * See the COPYING file in the top-level directory.
  12  *
  13  */
  14
  15 #include <sys/types.h>
  16 #include <sys/ioctl.h>
  17 #include <sys/mman.h>
  18 #include <sys/utsname.h>
  19
  20 #include <linux/kvm.h>
  21
  22 #include "qemu-common.h"
  23 #include "sysemu.h"
  24 #include "kvm.h"
  25 #include "cpu.h"
  26 #include "gdbstub.h"
  27 #include "host-utils.h"
  28 #include "hw/pc.h"
  29 #include "hw/apic.h"
  30 #include "ioport.h"
  31 #include "kvm_x86.h"
  32
  33 #ifdef CONFIG_KVM_PARA
  34 #include <linux/kvm_para.h>
  35 #endif
  36 //
  37 //#define DEBUG_KVM
  38
  39 #ifdef DEBUG_KVM
  40 #define DPRINTF(fmt, ...) \
  41     do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
  42 #else
  43 #define DPRINTF(fmt, ...) \
  44     do { } while (0)
  45 #endif
  46
  47 #define MSR_KVM_WALL_CLOCK  0x11
  48 #define MSR_KVM_SYSTEM_TIME 0x12
  49
  50 #ifndef BUS_MCEERR_AR
  51 #define BUS_MCEERR_AR 4
  52 #endif
  53 #ifndef BUS_MCEERR_AO
  54 #define BUS_MCEERR_AO 5
  55 #endif
  56
  57 static int lm_capable_kernel;
  58
  59 #ifdef KVM_CAP_EXT_CPUID
  60
  61 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
  62 {
  63     struct kvm_cpuid2 *cpuid;
  64     int r, size;
  65
  66     size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
  67     cpuid = (struct kvm_cpuid2 *)qemu_mallocz(size);
  68     cpuid->nent = max;
  69     r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
  70     if (r == 0 && cpuid->nent >= max) {
  71         r = -E2BIG;
  72     }
  73     if (r < 0) {
  74         if (r == -E2BIG) {
  75             qemu_free(cpuid);
  76             return NULL;
  77         } else {
  78             fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
  79                     strerror(-r));
  80             exit(1);
  81         }
  82     }
  83     return cpuid;
  84 }
  85
  86 uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function,
  87                                       uint32_t index, int reg)
  88 {
  89     struct kvm_cpuid2 *cpuid;
  90     int i, max;
  91     uint32_t ret = 0;
  92     uint32_t cpuid_1_edx;
  93
  94     if (!kvm_check_extension(env->kvm_state, KVM_CAP_EXT_CPUID)) {
  95         return -1U;
  96     }
  97
  98     max = 1;
  99     while ((cpuid = try_get_cpuid(env->kvm_state, max)) == NULL) {
 100         max *= 2;
 101     }
 102
 103     for (i = 0; i < cpuid->nent; ++i) {
 104         if (cpuid->entries[i].function == function &&
 105             cpuid->entries[i].index == index) {
 106             switch (reg) {
 107             case R_EAX:
 108                 ret = cpuid->entries[i].eax;
 109                 break;
 110             case R_EBX:
 111                 ret = cpuid->entries[i].ebx;
 112                 break;
 113             case R_ECX:
 114                 ret = cpuid->entries[i].ecx;
 115                 break;
 116             case R_EDX:
 117                 ret = cpuid->entries[i].edx;
 118                 switch (function) {
 119                 case 1:
 120                     /* KVM before 2.6.30 misreports the following features */
 121                     ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
 122                     break;
 123                 case 0x80000001:
 124                     /* On Intel, kvm returns cpuid according to the Intel spec,
 125                      * so add missing bits according to the AMD spec:
 126                      */
 127                     cpuid_1_edx = kvm_arch_get_supported_cpuid(env, 1, 0, R_EDX);
 128                     ret |= cpuid_1_edx & 0x183f7ff;
 129                     break;
 130                 }
 131                 break;
 132             }
 133         }
 134     }
 135
 136     qemu_free(cpuid);
 137
 138     return ret;
 139 }
 140
 141 #else
 142
 143 uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function,
 144                                       uint32_t index, int reg)
 145 {
 146     return -1U;
 147 }
 148
 149 #endif
 150
 151 #ifdef CONFIG_KVM_PARA
 152 struct kvm_para_features {
 153     int cap;
 154     int feature;
 155 } para_features[] = {
 156 #ifdef KVM_CAP_CLOCKSOURCE
 157     { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
 158 #endif
 159 #ifdef KVM_CAP_NOP_IO_DELAY
 160     { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
 161 #endif
 162 #ifdef KVM_CAP_PV_MMU
 163     { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
 164 #endif
 165 #ifdef KVM_CAP_ASYNC_PF
 166     { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
 167 #endif
 168     { -1, -1 }
 169 };
 170
 171 static int get_para_features(CPUState *env)
 172 {
 173     int i, features = 0;
 174
 175     for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) {
 176         if (kvm_check_extension(env->kvm_state, para_features[i].cap)) {
 177             features |= (1 << para_features[i].feature);
 178         }
 179     }
 180     return features;
 181 }
 182 #endif
 183
 184 #ifdef KVM_CAP_MCE
 185 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
 186                                      int *max_banks)
 187 {
 188     int r;
 189
 190     r = kvm_check_extension(s, KVM_CAP_MCE);
 191     if (r > 0) {
 192         *max_banks = r;
 193         return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
 194     }
 195     return -ENOSYS;
 196 }
 197
 198 static int kvm_setup_mce(CPUState *env, uint64_t *mcg_cap)
 199 {
 200     return kvm_vcpu_ioctl(env, KVM_X86_SETUP_MCE, mcg_cap);
 201 }
 202
 203 static int kvm_set_mce(CPUState *env, struct kvm_x86_mce *m)
 204 {
 205     return kvm_vcpu_ioctl(env, KVM_X86_SET_MCE, m);
 206 }
 207
 208 static int kvm_get_msr(CPUState *env, struct kvm_msr_entry *msrs, int n)
 209 {
 210     struct kvm_msrs *kmsrs = qemu_malloc(sizeof *kmsrs + n * sizeof *msrs);
 211     int r;
 212
 213     kmsrs->nmsrs = n;
 214     memcpy(kmsrs->entries, msrs, n * sizeof *msrs);
 215     r = kvm_vcpu_ioctl(env, KVM_GET_MSRS, kmsrs);
 216     memcpy(msrs, kmsrs->entries, n * sizeof *msrs);
 217     free(kmsrs);
 218     return r;
 219 }
 220
 221 /* FIXME: kill this and kvm_get_msr, use env->mcg_status instead */
 222 static int kvm_mce_in_progress(CPUState *env)
 223 {
 224     struct kvm_msr_entry msr_mcg_status = {
 225         .index = MSR_MCG_STATUS,
 226     };
 227     int r;
 228
 229     r = kvm_get_msr(env, &msr_mcg_status, 1);
 230     if (r == -1 || r == 0) {
 231         fprintf(stderr, "Failed to get MCE status\n");
 232         return 0;
 233     }
 234     return !!(msr_mcg_status.data & MCG_STATUS_MCIP);
 235 }
 236
 237 struct kvm_x86_mce_data
 238 {
 239     CPUState *env;
 240     struct kvm_x86_mce *mce;
 241     int abort_on_error;
 242 };
 243
 244 static void kvm_do_inject_x86_mce(void *_data)
 245 {
 246     struct kvm_x86_mce_data *data = _data;
 247     int r;
 248
 249     /* If there is an MCE exception being processed, ignore this SRAO MCE */
 250     if ((data->env->mcg_cap & MCG_SER_P) &&
 251         !(data->mce->status & MCI_STATUS_AR)) {
 252         if (kvm_mce_in_progress(data->env)) {
 253             return;
 254         }
 255     }
 256
 257     r = kvm_set_mce(data->env, data->mce);
 258     if (r < 0) {
 259         perror("kvm_set_mce FAILED");
 260         if (data->abort_on_error) {
 261             abort();
 262         }
 263     }
 264 }
 265
 266 static void kvm_inject_x86_mce_on(CPUState *env, struct kvm_x86_mce *mce,
 267                                   int flag)
 268 {
 269     struct kvm_x86_mce_data data = {
 270         .env = env,
 271         .mce = mce,
 272         .abort_on_error = (flag & ABORT_ON_ERROR),
 273     };
 274
 275     if (!env->mcg_cap) {
 276         fprintf(stderr, "MCE support is not enabled!\n");
 277         return;
 278     }
 279
 280     run_on_cpu(env, kvm_do_inject_x86_mce, &data);
 281 }
 282
 283 static void kvm_mce_broadcast_rest(CPUState *env);
 284 #endif
 285
 286 void kvm_inject_x86_mce(CPUState *cenv, int bank, uint64_t status,
 287                         uint64_t mcg_status, uint64_t addr, uint64_t misc,
 288                         int flag)
 289 {
 290 #ifdef KVM_CAP_MCE
 291     struct kvm_x86_mce mce = {
 292         .bank = bank,
 293         .status = status,
 294         .mcg_status = mcg_status,
 295         .addr = addr,
 296         .misc = misc,
 297     };
 298
 299     if (flag & MCE_BROADCAST) {
 300         kvm_mce_broadcast_rest(cenv);
 301     }
 302
 303     kvm_inject_x86_mce_on(cenv, &mce, flag);
 304 #else
 305     if (flag & ABORT_ON_ERROR) {
 306         abort();
 307     }
 308 #endif
 309 }
 310
 311 int kvm_arch_init_vcpu(CPUState *env)
 312 {
 313     struct {
 314         struct kvm_cpuid2 cpuid;
 315         struct kvm_cpuid_entry2 entries[100];
 316     } __attribute__((packed)) cpuid_data;
 317     uint32_t limit, i, j, cpuid_i;
 318     uint32_t unused;
 319     struct kvm_cpuid_entry2 *c;
 320 #ifdef KVM_CPUID_SIGNATURE
 321     uint32_t signature[3];
 322 #endif
 323
 324     env->cpuid_features &= kvm_arch_get_supported_cpuid(env, 1, 0, R_EDX);
 325
 326     i = env->cpuid_ext_features & CPUID_EXT_HYPERVISOR;
 327     env->cpuid_ext_features &= kvm_arch_get_supported_cpuid(env, 1, 0, R_ECX);
 328     env->cpuid_ext_features |= i;
 329
 330     env->cpuid_ext2_features &= kvm_arch_get_supported_cpuid(env, 0x80000001,
 331                                                              0, R_EDX);
 332     env->cpuid_ext3_features &= kvm_arch_get_supported_cpuid(env, 0x80000001,
 333                                                              0, R_ECX);
 334     env->cpuid_svm_features  &= kvm_arch_get_supported_cpuid(env, 0x8000000A,
 335                                                              0, R_EDX);
 336
 337
 338     cpuid_i = 0;
 339
 340 #ifdef CONFIG_KVM_PARA
 341     /* Paravirtualization CPUIDs */
 342     memcpy(signature, "KVMKVMKVM\0\0\0", 12);
 343     c = &cpuid_data.entries[cpuid_i++];
 344     memset(c, 0, sizeof(*c));
 345     c->function = KVM_CPUID_SIGNATURE;
 346     c->eax = 0;
 347     c->ebx = signature[0];
 348     c->ecx = signature[1];
 349     c->edx = signature[2];
 350
 351     c = &cpuid_data.entries[cpuid_i++];
 352     memset(c, 0, sizeof(*c));
 353     c->function = KVM_CPUID_FEATURES;
 354     c->eax = env->cpuid_kvm_features & get_para_features(env);
 355 #endif
 356
 357     cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
 358
 359     for (i = 0; i <= limit; i++) {
 360         c = &cpuid_data.entries[cpuid_i++];
 361
 362         switch (i) {
 363         case 2: {
 364             /* Keep reading function 2 till all the input is received */
 365             int times;
 366
 367             c->function = i;
 368             c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
 369                        KVM_CPUID_FLAG_STATE_READ_NEXT;
 370             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 371             times = c->eax & 0xff;
 372
 373             for (j = 1; j < times; ++j) {
 374                 c = &cpuid_data.entries[cpuid_i++];
 375                 c->function = i;
 376                 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
 377                 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 378             }
 379             break;
 380         }
 381         case 4:
 382         case 0xb:
 383         case 0xd:
 384             for (j = 0; ; j++) {
 385                 c->function = i;
 386                 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
 387                 c->index = j;
 388                 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
 389
 390                 if (i == 4 && c->eax == 0) {
 391                     break;
 392                 }
 393                 if (i == 0xb && !(c->ecx & 0xff00)) {
 394                     break;
 395                 }
 396                 if (i == 0xd && c->eax == 0) {
 397                     break;
 398                 }
 399                 c = &cpuid_data.entries[cpuid_i++];
 400             }
 401             break;
 402         default:
 403             c->function = i;
 404             c->flags = 0;
 405             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 406             break;
 407         }
 408     }
 409     cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
 410
 411     for (i = 0x80000000; i <= limit; i++) {
 412         c = &cpuid_data.entries[cpuid_i++];
 413
 414         c->function = i;
 415         c->flags = 0;
 416         cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 417     }
 418
 419     cpuid_data.cpuid.nent = cpuid_i;
 420
 421 #ifdef KVM_CAP_MCE
 422     if (((env->cpuid_version >> 8)&0xF) >= 6
 423         && (env->cpuid_features&(CPUID_MCE|CPUID_MCA)) == (CPUID_MCE|CPUID_MCA)
 424         && kvm_check_extension(env->kvm_state, KVM_CAP_MCE) > 0) {
 425         uint64_t mcg_cap;
 426         int banks;
 427
 428         if (kvm_get_mce_cap_supported(env->kvm_state, &mcg_cap, &banks)) {
 429             perror("kvm_get_mce_cap_supported FAILED");
 430         } else {
 431             if (banks > MCE_BANKS_DEF)
 432                 banks = MCE_BANKS_DEF;
 433             mcg_cap &= MCE_CAP_DEF;
 434             mcg_cap |= banks;
 435             if (kvm_setup_mce(env, &mcg_cap)) {
 436                 perror("kvm_setup_mce FAILED");
 437             } else {
 438                 env->mcg_cap = mcg_cap;
 439             }
 440         }
 441     }
 442 #endif
 443
 444     return kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data);
 445 }
 446
 447 void kvm_arch_reset_vcpu(CPUState *env)
 448 {
 449     env->exception_injected = -1;
 450     env->interrupt_injected = -1;
 451     env->nmi_injected = 0;
 452     env->nmi_pending = 0;
 453     env->xcr0 = 1;
 454     if (kvm_irqchip_in_kernel()) {
 455         env->mp_state = cpu_is_bsp(env) ? KVM_MP_STATE_RUNNABLE :
 456                                           KVM_MP_STATE_UNINITIALIZED;
 457     } else {
 458         env->mp_state = KVM_MP_STATE_RUNNABLE;
 459     }
 460 }
 461
 462 int has_msr_star;
 463 int has_msr_hsave_pa;
 464
 465 static void kvm_supported_msrs(CPUState *env)
 466 {
 467     static int kvm_supported_msrs;
 468     int ret;
 469
 470     /* first time */
 471     if (kvm_supported_msrs == 0) {
 472         struct kvm_msr_list msr_list, *kvm_msr_list;
 473
 474         kvm_supported_msrs = -1;
 475
 476         /* Obtain MSR list from KVM.  These are the MSRs that we must
 477          * save/restore */
 478         msr_list.nmsrs = 0;
 479         ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, &msr_list);
 480         if (ret < 0 && ret != -E2BIG) {
 481             return;
 482         }
 483         /* Old kernel modules had a bug and could write beyond the provided
 484            memory. Allocate at least a safe amount of 1K. */
 485         kvm_msr_list = qemu_mallocz(MAX(1024, sizeof(msr_list) +
 486                                               msr_list.nmsrs *
 487                                               sizeof(msr_list.indices[0])));
 488
 489         kvm_msr_list->nmsrs = msr_list.nmsrs;
 490         ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
 491         if (ret >= 0) {
 492             int i;
 493
 494             for (i = 0; i < kvm_msr_list->nmsrs; i++) {
 495                 if (kvm_msr_list->indices[i] == MSR_STAR) {
 496                     has_msr_star = 1;
 497                     continue;
 498                 }
 499                 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
 500                     has_msr_hsave_pa = 1;
 501                     continue;
 502                 }
 503             }
 504         }
 505
 506         free(kvm_msr_list);
 507     }
 508
 509     return;
 510 }
 511
 512 static int kvm_has_msr_hsave_pa(CPUState *env)
 513 {
 514     kvm_supported_msrs(env);
 515     return has_msr_hsave_pa;
 516 }
 517
 518 static int kvm_has_msr_star(CPUState *env)
 519 {
 520     kvm_supported_msrs(env);
 521     return has_msr_star;
 522 }
 523
 524 static int kvm_init_identity_map_page(KVMState *s)
 525 {
 526 #ifdef KVM_CAP_SET_IDENTITY_MAP_ADDR
 527     int ret;
 528     uint64_t addr = 0xfffbc000;
 529
 530     if (!kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
 531         return 0;
 532     }
 533
 534     ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &addr);
 535     if (ret < 0) {
 536         fprintf(stderr, "kvm_set_identity_map_addr: %s\n", strerror(ret));
 537         return ret;
 538     }
 539 #endif
 540     return 0;
 541 }
 542
 543 int kvm_arch_init(KVMState *s, int smp_cpus)
 544 {
 545     int ret;
 546
 547     struct utsname utsname;
 548
 549     uname(&utsname);
 550     lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
 551
 552     /* create vm86 tss.  KVM uses vm86 mode to emulate 16-bit code
 553      * directly.  In order to use vm86 mode, a TSS is needed.  Since this
 554      * must be part of guest physical memory, we need to allocate it.  Older
 555      * versions of KVM just assumed that it would be at the end of physical
 556      * memory but that doesn't work with more than 4GB of memory.  We simply
 557      * refuse to work with those older versions of KVM. */
 558     ret = kvm_check_extension(s, KVM_CAP_SET_TSS_ADDR);
 559     if (ret <= 0) {
 560         fprintf(stderr, "kvm does not support KVM_CAP_SET_TSS_ADDR\n");
 561         return ret;
 562     }
 563
 564     /* this address is 3 pages before the bios, and the bios should present
 565      * as unavaible memory.  FIXME, need to ensure the e820 map deals with
 566      * this?
 567      */
 568     /*
 569      * Tell fw_cfg to notify the BIOS to reserve the range.
 570      */
 571     if (e820_add_entry(0xfffbc000, 0x4000, E820_RESERVED) < 0) {
 572         perror("e820_add_entry() table is full");
 573         exit(1);
 574     }
 575     ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, 0xfffbd000);
 576     if (ret < 0) {
 577         return ret;
 578     }
 579
 580     return kvm_init_identity_map_page(s);
 581 }
 582
 583 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 584 {
 585     lhs->selector = rhs->selector;
 586     lhs->base = rhs->base;
 587     lhs->limit = rhs->limit;
 588     lhs->type = 3;
 589     lhs->present = 1;
 590     lhs->dpl = 3;
 591     lhs->db = 0;
 592     lhs->s = 1;
 593     lhs->l = 0;
 594     lhs->g = 0;
 595     lhs->avl = 0;
 596     lhs->unusable = 0;
 597 }
 598
 599 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 600 {
 601     unsigned flags = rhs->flags;
 602     lhs->selector = rhs->selector;
 603     lhs->base = rhs->base;
 604     lhs->limit = rhs->limit;
 605     lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
 606     lhs->present = (flags & DESC_P_MASK) != 0;
 607     lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
 608     lhs->db = (flags >> DESC_B_SHIFT) & 1;
 609     lhs->s = (flags & DESC_S_MASK) != 0;
 610     lhs->l = (flags >> DESC_L_SHIFT) & 1;
 611     lhs->g = (flags & DESC_G_MASK) != 0;
 612     lhs->avl = (flags & DESC_AVL_MASK) != 0;
 613     lhs->unusable = 0;
 614 }
 615
 616 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
 617 {
 618     lhs->selector = rhs->selector;
 619     lhs->base = rhs->base;
 620     lhs->limit = rhs->limit;
 621     lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
 622                  (rhs->present * DESC_P_MASK) |
 623                  (rhs->dpl << DESC_DPL_SHIFT) |
 624                  (rhs->db << DESC_B_SHIFT) |
 625                  (rhs->s * DESC_S_MASK) |
 626                  (rhs->l << DESC_L_SHIFT) |
 627                  (rhs->g * DESC_G_MASK) |
 628                  (rhs->avl * DESC_AVL_MASK);
 629 }
 630
 631 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
 632 {
 633     if (set) {
 634         *kvm_reg = *qemu_reg;
 635     } else {
 636         *qemu_reg = *kvm_reg;
 637     }
 638 }
 639
 640 static int kvm_getput_regs(CPUState *env, int set)
 641 {
 642     struct kvm_regs regs;
 643     int ret = 0;
 644
 645     if (!set) {
 646         ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
 647         if (ret < 0) {
 648             return ret;
 649         }
 650     }
 651
 652     kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
 653     kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
 654     kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
 655     kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
 656     kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
 657     kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
 658     kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
 659     kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
 660 #ifdef TARGET_X86_64
 661     kvm_getput_reg(&regs.r8, &env->regs[8], set);
 662     kvm_getput_reg(&regs.r9, &env->regs[9], set);
 663     kvm_getput_reg(&regs.r10, &env->regs[10], set);
 664     kvm_getput_reg(&regs.r11, &env->regs[11], set);
 665     kvm_getput_reg(&regs.r12, &env->regs[12], set);
 666     kvm_getput_reg(&regs.r13, &env->regs[13], set);
 667     kvm_getput_reg(&regs.r14, &env->regs[14], set);
 668     kvm_getput_reg(&regs.r15, &env->regs[15], set);
 669 #endif
 670
 671     kvm_getput_reg(&regs.rflags, &env->eflags, set);
 672     kvm_getput_reg(&regs.rip, &env->eip, set);
 673
 674     if (set) {
 675         ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);
 676     }
 677
 678     return ret;
 679 }
 680
 681 static int kvm_put_fpu(CPUState *env)
 682 {
 683     struct kvm_fpu fpu;
 684     int i;
 685
 686     memset(&fpu, 0, sizeof fpu);
 687     fpu.fsw = env->fpus & ~(7 << 11);
 688     fpu.fsw |= (env->fpstt & 7) << 11;
 689     fpu.fcw = env->fpuc;
 690     for (i = 0; i < 8; ++i) {
 691         fpu.ftwx |= (!env->fptags[i]) << i;
 692     }
 693     memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
 694     memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
 695     fpu.mxcsr = env->mxcsr;
 696
 697     return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu);
 698 }
 699
 700 #ifdef KVM_CAP_XSAVE
 701 #define XSAVE_CWD_RIP     2
 702 #define XSAVE_CWD_RDP     4
 703 #define XSAVE_MXCSR       6
 704 #define XSAVE_ST_SPACE    8
 705 #define XSAVE_XMM_SPACE   40
 706 #define XSAVE_XSTATE_BV   128
 707 #define XSAVE_YMMH_SPACE  144
 708 #endif
 709
 710 static int kvm_put_xsave(CPUState *env)
 711 {
 712 #ifdef KVM_CAP_XSAVE
 713     int i, r;
 714     struct kvm_xsave* xsave;
 715     uint16_t cwd, swd, twd, fop;
 716
 717     if (!kvm_has_xsave()) {
 718         return kvm_put_fpu(env);
 719     }
 720
 721     xsave = qemu_memalign(4096, sizeof(struct kvm_xsave));
 722     memset(xsave, 0, sizeof(struct kvm_xsave));
 723     cwd = swd = twd = fop = 0;
 724     swd = env->fpus & ~(7 << 11);
 725     swd |= (env->fpstt & 7) << 11;
 726     cwd = env->fpuc;
 727     for (i = 0; i < 8; ++i) {
 728         twd |= (!env->fptags[i]) << i;
 729     }
 730     xsave->region[0] = (uint32_t)(swd << 16) + cwd;
 731     xsave->region[1] = (uint32_t)(fop << 16) + twd;
 732     memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs,
 733             sizeof env->fpregs);
 734     memcpy(&xsave->region[XSAVE_XMM_SPACE], env->xmm_regs,
 735             sizeof env->xmm_regs);
 736     xsave->region[XSAVE_MXCSR] = env->mxcsr;
 737     *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
 738     memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs,
 739             sizeof env->ymmh_regs);
 740     r = kvm_vcpu_ioctl(env, KVM_SET_XSAVE, xsave);
 741     qemu_free(xsave);
 742     return r;
 743 #else
 744     return kvm_put_fpu(env);
 745 #endif
 746 }
 747
 748 static int kvm_put_xcrs(CPUState *env)
 749 {
 750 #ifdef KVM_CAP_XCRS
 751     struct kvm_xcrs xcrs;
 752
 753     if (!kvm_has_xcrs()) {
 754         return 0;
 755     }
 756
 757     xcrs.nr_xcrs = 1;
 758     xcrs.flags = 0;
 759     xcrs.xcrs[0].xcr = 0;
 760     xcrs.xcrs[0].value = env->xcr0;
 761     return kvm_vcpu_ioctl(env, KVM_SET_XCRS, &xcrs);
 762 #else
 763     return 0;
 764 #endif
 765 }
 766
 767 static int kvm_put_sregs(CPUState *env)
 768 {
 769     struct kvm_sregs sregs;
 770
 771     memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
 772     if (env->interrupt_injected >= 0) {
 773         sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
 774                 (uint64_t)1 << (env->interrupt_injected % 64);
 775     }
 776
 777     if ((env->eflags & VM_MASK)) {
 778         set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
 779         set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
 780         set_v8086_seg(&sregs.es, &env->segs[R_ES]);
 781         set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
 782         set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
 783         set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
 784     } else {
 785         set_seg(&sregs.cs, &env->segs[R_CS]);
 786         set_seg(&sregs.ds, &env->segs[R_DS]);
 787         set_seg(&sregs.es, &env->segs[R_ES]);
 788         set_seg(&sregs.fs, &env->segs[R_FS]);
 789         set_seg(&sregs.gs, &env->segs[R_GS]);
 790         set_seg(&sregs.ss, &env->segs[R_SS]);
 791     }
 792
 793     set_seg(&sregs.tr, &env->tr);
 794     set_seg(&sregs.ldt, &env->ldt);
 795
 796     sregs.idt.limit = env->idt.limit;
 797     sregs.idt.base = env->idt.base;
 798     sregs.gdt.limit = env->gdt.limit;
 799     sregs.gdt.base = env->gdt.base;
 800
 801     sregs.cr0 = env->cr[0];
 802     sregs.cr2 = env->cr[2];
 803     sregs.cr3 = env->cr[3];
 804     sregs.cr4 = env->cr[4];
 805
 806     sregs.cr8 = cpu_get_apic_tpr(env->apic_state);
 807     sregs.apic_base = cpu_get_apic_base(env->apic_state);
 808
 809     sregs.efer = env->efer;
 810
 811     return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
 812 }
 813
 814 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
 815                               uint32_t index, uint64_t value)
 816 {
 817     entry->index = index;
 818     entry->data = value;
 819 }
 820
 821 static int kvm_put_msrs(CPUState *env, int level)
 822 {
 823     struct {
 824         struct kvm_msrs info;
 825         struct kvm_msr_entry entries[100];
 826     } msr_data;
 827     struct kvm_msr_entry *msrs = msr_data.entries;
 828     int n = 0;
 829
 830     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
 831     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
 832     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
 833     if (kvm_has_msr_star(env)) {
 834         kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
 835     }
 836     if (kvm_has_msr_hsave_pa(env)) {
 837         kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
 838     }
 839 #ifdef TARGET_X86_64
 840     if (lm_capable_kernel) {
 841         kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
 842         kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
 843         kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
 844         kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
 845     }
 846 #endif
 847     if (level == KVM_PUT_FULL_STATE) {
 848         /*
 849          * KVM is yet unable to synchronize TSC values of multiple VCPUs on
 850          * writeback. Until this is fixed, we only write the offset to SMP
 851          * guests after migration, desynchronizing the VCPUs, but avoiding
 852          * huge jump-backs that would occur without any writeback at all.
 853          */
 854         if (smp_cpus == 1 || env->tsc != 0) {
 855             kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
 856         }
 857         kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
 858                           env->system_time_msr);
 859         kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
 860 #ifdef KVM_CAP_ASYNC_PF
 861         kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
 862 #endif
 863     }
 864 #ifdef KVM_CAP_MCE
 865     if (env->mcg_cap) {
 866         int i;
 867
 868         if (level == KVM_PUT_RESET_STATE) {
 869             kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
 870         } else if (level == KVM_PUT_FULL_STATE) {
 871             kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
 872             kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl);
 873             for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
 874                 kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]);
 875             }
 876         }
 877     }
 878 #endif
 879
 880     msr_data.info.nmsrs = n;
 881
 882     return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
 883
 884 }
 885
 886
 887 static int kvm_get_fpu(CPUState *env)
 888 {
 889     struct kvm_fpu fpu;
 890     int i, ret;
 891
 892     ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu);
 893     if (ret < 0) {
 894         return ret;
 895     }
 896
 897     env->fpstt = (fpu.fsw >> 11) & 7;
 898     env->fpus = fpu.fsw;
 899     env->fpuc = fpu.fcw;
 900     for (i = 0; i < 8; ++i) {
 901         env->fptags[i] = !((fpu.ftwx >> i) & 1);
 902     }
 903     memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
 904     memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
 905     env->mxcsr = fpu.mxcsr;
 906
 907     return 0;
 908 }
 909
 910 static int kvm_get_xsave(CPUState *env)
 911 {
 912 #ifdef KVM_CAP_XSAVE
 913     struct kvm_xsave* xsave;
 914     int ret, i;
 915     uint16_t cwd, swd, twd, fop;
 916
 917     if (!kvm_has_xsave()) {
 918         return kvm_get_fpu(env);
 919     }
 920
 921     xsave = qemu_memalign(4096, sizeof(struct kvm_xsave));
 922     ret = kvm_vcpu_ioctl(env, KVM_GET_XSAVE, xsave);
 923     if (ret < 0) {
 924         qemu_free(xsave);
 925         return ret;
 926     }
 927
 928     cwd = (uint16_t)xsave->region[0];
 929     swd = (uint16_t)(xsave->region[0] >> 16);
 930     twd = (uint16_t)xsave->region[1];
 931     fop = (uint16_t)(xsave->region[1] >> 16);
 932     env->fpstt = (swd >> 11) & 7;
 933     env->fpus = swd;
 934     env->fpuc = cwd;
 935     for (i = 0; i < 8; ++i) {
 936         env->fptags[i] = !((twd >> i) & 1);
 937     }
 938     env->mxcsr = xsave->region[XSAVE_MXCSR];
 939     memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE],
 940             sizeof env->fpregs);
 941     memcpy(env->xmm_regs, &xsave->region[XSAVE_XMM_SPACE],
 942             sizeof env->xmm_regs);
 943     env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
 944     memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE],
 945             sizeof env->ymmh_regs);
 946     qemu_free(xsave);
 947     return 0;
 948 #else
 949     return kvm_get_fpu(env);
 950 #endif
 951 }
 952
 953 static int kvm_get_xcrs(CPUState *env)
 954 {
 955 #ifdef KVM_CAP_XCRS
 956     int i, ret;
 957     struct kvm_xcrs xcrs;
 958
 959     if (!kvm_has_xcrs()) {
 960         return 0;
 961     }
 962
 963     ret = kvm_vcpu_ioctl(env, KVM_GET_XCRS, &xcrs);
 964     if (ret < 0) {
 965         return ret;
 966     }
 967
 968     for (i = 0; i < xcrs.nr_xcrs; i++) {
 969         /* Only support xcr0 now */
 970         if (xcrs.xcrs[0].xcr == 0) {
 971             env->xcr0 = xcrs.xcrs[0].value;
 972             break;
 973         }
 974     }
 975     return 0;
 976 #else
 977     return 0;
 978 #endif
 979 }
 980
 981 static int kvm_get_sregs(CPUState *env)
 982 {
 983     struct kvm_sregs sregs;
 984     uint32_t hflags;
 985     int bit, i, ret;
 986
 987     ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
 988     if (ret < 0) {
 989         return ret;
 990     }
 991
 992     /* There can only be one pending IRQ set in the bitmap at a time, so try
 993        to find it and save its number instead (-1 for none). */
 994     env->interrupt_injected = -1;
 995     for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
 996         if (sregs.interrupt_bitmap[i]) {
 997             bit = ctz64(sregs.interrupt_bitmap[i]);
 998             env->interrupt_injected = i * 64 + bit;
 999             break;
1000         }
1001     }
1002
1003     get_seg(&env->segs[R_CS], &sregs.cs);
1004     get_seg(&env->segs[R_DS], &sregs.ds);
1005     get_seg(&env->segs[R_ES], &sregs.es);
1006     get_seg(&env->segs[R_FS], &sregs.fs);
1007     get_seg(&env->segs[R_GS], &sregs.gs);
1008     get_seg(&env->segs[R_SS], &sregs.ss);
1009
1010     get_seg(&env->tr, &sregs.tr);
1011     get_seg(&env->ldt, &sregs.ldt);
1012
1013     env->idt.limit = sregs.idt.limit;
1014     env->idt.base = sregs.idt.base;
1015     env->gdt.limit = sregs.gdt.limit;
1016     env->gdt.base = sregs.gdt.base;
1017
1018     env->cr[0] = sregs.cr0;
1019     env->cr[2] = sregs.cr2;
1020     env->cr[3] = sregs.cr3;
1021     env->cr[4] = sregs.cr4;
1022
1023     cpu_set_apic_base(env->apic_state, sregs.apic_base);
1024
1025     env->efer = sregs.efer;
1026     //cpu_set_apic_tpr(env->apic_state, sregs.cr8);
1027
1028 #define HFLAG_COPY_MASK \
1029     ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1030        HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1031        HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1032        HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1033
1034     hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1035     hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1036     hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1037                 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1038     hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1039     hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
1040                 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
1041
1042     if (env->efer & MSR_EFER_LMA) {
1043         hflags |= HF_LMA_MASK;
1044     }
1045
1046     if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1047         hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1048     } else {
1049         hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1050                     (DESC_B_SHIFT - HF_CS32_SHIFT);
1051         hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1052                     (DESC_B_SHIFT - HF_SS32_SHIFT);
1053         if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1054             !(hflags & HF_CS32_MASK)) {
1055             hflags |= HF_ADDSEG_MASK;
1056         } else {
1057             hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1058                         env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1059         }
1060     }
1061     env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
1062
1063     return 0;
1064 }
1065
1066 static int kvm_get_msrs(CPUState *env)
1067 {
1068     struct {
1069         struct kvm_msrs info;
1070         struct kvm_msr_entry entries[100];
1071     } msr_data;
1072     struct kvm_msr_entry *msrs = msr_data.entries;
1073     int ret, i, n;
1074
1075     n = 0;
1076     msrs[n++].index = MSR_IA32_SYSENTER_CS;
1077     msrs[n++].index = MSR_IA32_SYSENTER_ESP;
1078     msrs[n++].index = MSR_IA32_SYSENTER_EIP;
1079     if (kvm_has_msr_star(env)) {
1080         msrs[n++].index = MSR_STAR;
1081     }
1082     if (kvm_has_msr_hsave_pa(env)) {
1083         msrs[n++].index = MSR_VM_HSAVE_PA;
1084     }
1085     msrs[n++].index = MSR_IA32_TSC;
1086 #ifdef TARGET_X86_64
1087     if (lm_capable_kernel) {
1088         msrs[n++].index = MSR_CSTAR;
1089         msrs[n++].index = MSR_KERNELGSBASE;
1090         msrs[n++].index = MSR_FMASK;
1091         msrs[n++].index = MSR_LSTAR;
1092     }
1093 #endif
1094     msrs[n++].index = MSR_KVM_SYSTEM_TIME;
1095     msrs[n++].index = MSR_KVM_WALL_CLOCK;
1096 #ifdef KVM_CAP_ASYNC_PF
1097     msrs[n++].index = MSR_KVM_ASYNC_PF_EN;
1098 #endif
1099
1100 #ifdef KVM_CAP_MCE
1101     if (env->mcg_cap) {
1102         msrs[n++].index = MSR_MCG_STATUS;
1103         msrs[n++].index = MSR_MCG_CTL;
1104         for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1105             msrs[n++].index = MSR_MC0_CTL + i;
1106         }
1107     }
1108 #endif
1109
1110     msr_data.info.nmsrs = n;
1111     ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);
1112     if (ret < 0) {
1113         return ret;
1114     }
1115
1116     for (i = 0; i < ret; i++) {
1117         switch (msrs[i].index) {
1118         case MSR_IA32_SYSENTER_CS:
1119             env->sysenter_cs = msrs[i].data;
1120             break;
1121         case MSR_IA32_SYSENTER_ESP:
1122             env->sysenter_esp = msrs[i].data;
1123             break;
1124         case MSR_IA32_SYSENTER_EIP:
1125             env->sysenter_eip = msrs[i].data;
1126             break;
1127         case MSR_STAR:
1128             env->star = msrs[i].data;
1129             break;
1130 #ifdef TARGET_X86_64
1131         case MSR_CSTAR:
1132             env->cstar = msrs[i].data;
1133             break;
1134         case MSR_KERNELGSBASE:
1135             env->kernelgsbase = msrs[i].data;
1136             break;
1137         case MSR_FMASK:
1138             env->fmask = msrs[i].data;
1139             break;
1140         case MSR_LSTAR:
1141             env->lstar = msrs[i].data;
1142             break;
1143 #endif
1144         case MSR_IA32_TSC:
1145             env->tsc = msrs[i].data;
1146             break;
1147         case MSR_VM_HSAVE_PA:
1148             env->vm_hsave = msrs[i].data;
1149             break;
1150         case MSR_KVM_SYSTEM_TIME:
1151             env->system_time_msr = msrs[i].data;
1152             break;
1153         case MSR_KVM_WALL_CLOCK:
1154             env->wall_clock_msr = msrs[i].data;
1155             break;
1156 #ifdef KVM_CAP_MCE
1157         case MSR_MCG_STATUS:
1158             env->mcg_status = msrs[i].data;
1159             break;
1160         case MSR_MCG_CTL:
1161             env->mcg_ctl = msrs[i].data;
1162             break;
1163 #endif
1164         default:
1165 #ifdef KVM_CAP_MCE
1166             if (msrs[i].index >= MSR_MC0_CTL &&
1167                 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
1168                 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
1169             }
1170 #endif
1171             break;
1172 #ifdef KVM_CAP_ASYNC_PF
1173         case MSR_KVM_ASYNC_PF_EN:
1174             env->async_pf_en_msr = msrs[i].data;
1175             break;
1176 #endif
1177         }
1178     }
1179
1180     return 0;
1181 }
1182
1183 static int kvm_put_mp_state(CPUState *env)
1184 {
1185     struct kvm_mp_state mp_state = { .mp_state = env->mp_state };
1186
1187     return kvm_vcpu_ioctl(env, KVM_SET_MP_STATE, &mp_state);
1188 }
1189
1190 static int kvm_get_mp_state(CPUState *env)
1191 {
1192     struct kvm_mp_state mp_state;
1193     int ret;
1194
1195     ret = kvm_vcpu_ioctl(env, KVM_GET_MP_STATE, &mp_state);
1196     if (ret < 0) {
1197         return ret;
1198     }
1199     env->mp_state = mp_state.mp_state;
1200     if (kvm_irqchip_in_kernel()) {
1201         env->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
1202     }
1203     return 0;
1204 }
1205
1206 static int kvm_put_vcpu_events(CPUState *env, int level)
1207 {
1208 #ifdef KVM_CAP_VCPU_EVENTS
1209     struct kvm_vcpu_events events;
1210
1211     if (!kvm_has_vcpu_events()) {
1212         return 0;
1213     }
1214
1215     events.exception.injected = (env->exception_injected >= 0);
1216     events.exception.nr = env->exception_injected;
1217     events.exception.has_error_code = env->has_error_code;
1218     events.exception.error_code = env->error_code;
1219
1220     events.interrupt.injected = (env->interrupt_injected >= 0);
1221     events.interrupt.nr = env->interrupt_injected;
1222     events.interrupt.soft = env->soft_interrupt;
1223
1224     events.nmi.injected = env->nmi_injected;
1225     events.nmi.pending = env->nmi_pending;
1226     events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
1227
1228     events.sipi_vector = env->sipi_vector;
1229
1230     events.flags = 0;
1231     if (level >= KVM_PUT_RESET_STATE) {
1232         events.flags |=
1233             KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
1234     }
1235
1236     return kvm_vcpu_ioctl(env, KVM_SET_VCPU_EVENTS, &events);
1237 #else
1238     return 0;
1239 #endif
1240 }
1241
1242 static int kvm_get_vcpu_events(CPUState *env)
1243 {
1244 #ifdef KVM_CAP_VCPU_EVENTS
1245     struct kvm_vcpu_events events;
1246     int ret;
1247
1248     if (!kvm_has_vcpu_events()) {
1249         return 0;
1250     }
1251
1252     ret = kvm_vcpu_ioctl(env, KVM_GET_VCPU_EVENTS, &events);
1253     if (ret < 0) {
1254        return ret;
1255     }
1256     env->exception_injected =
1257        events.exception.injected ? events.exception.nr : -1;
1258     env->has_error_code = events.exception.has_error_code;
1259     env->error_code = events.exception.error_code;
1260
1261     env->interrupt_injected =
1262         events.interrupt.injected ? events.interrupt.nr : -1;
1263     env->soft_interrupt = events.interrupt.soft;
1264
1265     env->nmi_injected = events.nmi.injected;
1266     env->nmi_pending = events.nmi.pending;
1267     if (events.nmi.masked) {
1268         env->hflags2 |= HF2_NMI_MASK;
1269     } else {
1270         env->hflags2 &= ~HF2_NMI_MASK;
1271     }
1272
1273     env->sipi_vector = events.sipi_vector;
1274 #endif
1275
1276     return 0;
1277 }
1278
1279 static int kvm_guest_debug_workarounds(CPUState *env)
1280 {
1281     int ret = 0;
1282 #ifdef KVM_CAP_SET_GUEST_DEBUG
1283     unsigned long reinject_trap = 0;
1284
1285     if (!kvm_has_vcpu_events()) {
1286         if (env->exception_injected == 1) {
1287             reinject_trap = KVM_GUESTDBG_INJECT_DB;
1288         } else if (env->exception_injected == 3) {
1289             reinject_trap = KVM_GUESTDBG_INJECT_BP;
1290         }
1291         env->exception_injected = -1;
1292     }
1293
1294     /*
1295      * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
1296      * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
1297      * by updating the debug state once again if single-stepping is on.
1298      * Another reason to call kvm_update_guest_debug here is a pending debug
1299      * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
1300      * reinject them via SET_GUEST_DEBUG.
1301      */
1302     if (reinject_trap ||
1303         (!kvm_has_robust_singlestep() && env->singlestep_enabled)) {
1304         ret = kvm_update_guest_debug(env, reinject_trap);
1305     }
1306 #endif /* KVM_CAP_SET_GUEST_DEBUG */
1307     return ret;
1308 }
1309
1310 static int kvm_put_debugregs(CPUState *env)
1311 {
1312 #ifdef KVM_CAP_DEBUGREGS
1313     struct kvm_debugregs dbgregs;
1314     int i;
1315
1316     if (!kvm_has_debugregs()) {
1317         return 0;
1318     }
1319
1320     for (i = 0; i < 4; i++) {
1321         dbgregs.db[i] = env->dr[i];
1322     }
1323     dbgregs.dr6 = env->dr[6];
1324     dbgregs.dr7 = env->dr[7];
1325     dbgregs.flags = 0;
1326
1327     return kvm_vcpu_ioctl(env, KVM_SET_DEBUGREGS, &dbgregs);
1328 #else
1329     return 0;
1330 #endif
1331 }
1332
1333 static int kvm_get_debugregs(CPUState *env)
1334 {
1335 #ifdef KVM_CAP_DEBUGREGS
1336     struct kvm_debugregs dbgregs;
1337     int i, ret;
1338
1339     if (!kvm_has_debugregs()) {
1340         return 0;
1341     }
1342
1343     ret = kvm_vcpu_ioctl(env, KVM_GET_DEBUGREGS, &dbgregs);
1344     if (ret < 0) {
1345         return ret;
1346     }
1347     for (i = 0; i < 4; i++) {
1348         env->dr[i] = dbgregs.db[i];
1349     }
1350     env->dr[4] = env->dr[6] = dbgregs.dr6;
1351     env->dr[5] = env->dr[7] = dbgregs.dr7;
1352 #endif
1353
1354     return 0;
1355 }
1356
1357 int kvm_arch_put_registers(CPUState *env, int level)
1358 {
1359     int ret;
1360
1361     assert(cpu_is_stopped(env) || qemu_cpu_self(env));
1362
1363     ret = kvm_getput_regs(env, 1);
1364     if (ret < 0) {
1365         return ret;
1366     }
1367     ret = kvm_put_xsave(env);
1368     if (ret < 0) {
1369         return ret;
1370     }
1371     ret = kvm_put_xcrs(env);
1372     if (ret < 0) {
1373         return ret;
1374     }
1375     ret = kvm_put_sregs(env);
1376     if (ret < 0) {
1377         return ret;
1378     }
1379     ret = kvm_put_msrs(env, level);
1380     if (ret < 0) {
1381         return ret;
1382     }
1383     if (level >= KVM_PUT_RESET_STATE) {
1384         ret = kvm_put_mp_state(env);
1385         if (ret < 0) {
1386             return ret;
1387         }
1388     }
1389     ret = kvm_put_vcpu_events(env, level);
1390     if (ret < 0) {
1391         return ret;
1392     }
1393     ret = kvm_put_debugregs(env);
1394     if (ret < 0) {
1395         return ret;
1396     }
1397     /* must be last */
1398     ret = kvm_guest_debug_workarounds(env);
1399     if (ret < 0) {
1400         return ret;
1401     }
1402     return 0;
1403 }
1404
1405 int kvm_arch_get_registers(CPUState *env)
1406 {
1407     int ret;
1408
1409     assert(cpu_is_stopped(env) || qemu_cpu_self(env));
1410
1411     ret = kvm_getput_regs(env, 0);
1412     if (ret < 0) {
1413         return ret;
1414     }
1415     ret = kvm_get_xsave(env);
1416     if (ret < 0) {
1417         return ret;
1418     }
1419     ret = kvm_get_xcrs(env);
1420     if (ret < 0) {
1421         return ret;
1422     }
1423     ret = kvm_get_sregs(env);
1424     if (ret < 0) {
1425         return ret;
1426     }
1427     ret = kvm_get_msrs(env);
1428     if (ret < 0) {
1429         return ret;
1430     }
1431     ret = kvm_get_mp_state(env);
1432     if (ret < 0) {
1433         return ret;
1434     }
1435     ret = kvm_get_vcpu_events(env);
1436     if (ret < 0) {
1437         return ret;
1438     }
1439     ret = kvm_get_debugregs(env);
1440     if (ret < 0) {
1441         return ret;
1442     }
1443     return 0;
1444 }
1445
1446 int kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
1447 {
1448     /* Inject NMI */
1449     if (env->interrupt_request & CPU_INTERRUPT_NMI) {
1450         env->interrupt_request &= ~CPU_INTERRUPT_NMI;
1451         DPRINTF("injected NMI\n");
1452         kvm_vcpu_ioctl(env, KVM_NMI);
1453     }
1454
1455     /* Try to inject an interrupt if the guest can accept it */
1456     if (run->ready_for_interrupt_injection &&
1457         (env->interrupt_request & CPU_INTERRUPT_HARD) &&
1458         (env->eflags & IF_MASK)) {
1459         int irq;
1460
1461         env->interrupt_request &= ~CPU_INTERRUPT_HARD;
1462         irq = cpu_get_pic_interrupt(env);
1463         if (irq >= 0) {
1464             struct kvm_interrupt intr;
1465             intr.irq = irq;
1466             /* FIXME: errors */
1467             DPRINTF("injected interrupt %d\n", irq);
1468             kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr);
1469         }
1470     }
1471
1472     /* If we have an interrupt but the guest is not ready to receive an
1473      * interrupt, request an interrupt window exit.  This will
1474      * cause a return to userspace as soon as the guest is ready to
1475      * receive interrupts. */
1476     if ((env->interrupt_request & CPU_INTERRUPT_HARD)) {
1477         run->request_interrupt_window = 1;
1478     } else {
1479         run->request_interrupt_window = 0;
1480     }
1481
1482     DPRINTF("setting tpr\n");
1483     run->cr8 = cpu_get_apic_tpr(env->apic_state);
1484
1485     return 0;
1486 }
1487
1488 int kvm_arch_post_run(CPUState *env, struct kvm_run *run)
1489 {
1490     if (run->if_flag) {
1491         env->eflags |= IF_MASK;
1492     } else {
1493         env->eflags &= ~IF_MASK;
1494     }
1495     cpu_set_apic_tpr(env->apic_state, run->cr8);
1496     cpu_set_apic_base(env->apic_state, run->apic_base);
1497
1498     return 0;
1499 }
1500
1501 int kvm_arch_process_irqchip_events(CPUState *env)
1502 {
1503     if (env->interrupt_request & CPU_INTERRUPT_INIT) {
1504         kvm_cpu_synchronize_state(env);
1505         do_cpu_init(env);
1506         env->exception_index = EXCP_HALTED;
1507     }
1508
1509     if (env->interrupt_request & CPU_INTERRUPT_SIPI) {
1510         kvm_cpu_synchronize_state(env);
1511         do_cpu_sipi(env);
1512     }
1513
1514     return env->halted;
1515 }
1516
1517 static int kvm_handle_halt(CPUState *env)
1518 {
1519     if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1520           (env->eflags & IF_MASK)) &&
1521         !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
1522         env->halted = 1;
1523         env->exception_index = EXCP_HLT;
1524         return 0;
1525     }
1526
1527     return 1;
1528 }
1529
1530 static bool host_supports_vmx(void)
1531 {
1532     uint32_t ecx, unused;
1533
1534     host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
1535     return ecx & CPUID_EXT_VMX;
1536 }
1537
1538 #define VMX_INVALID_GUEST_STATE 0x80000021
1539
1540 int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run)
1541 {
1542     uint64_t code;
1543     int ret = 0;
1544
1545     switch (run->exit_reason) {
1546     case KVM_EXIT_HLT:
1547         DPRINTF("handle_hlt\n");
1548         ret = kvm_handle_halt(env);
1549         break;
1550     case KVM_EXIT_SET_TPR:
1551         ret = 1;
1552         break;
1553     case KVM_EXIT_FAIL_ENTRY:
1554         code = run->fail_entry.hardware_entry_failure_reason;
1555         fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
1556                 code);
1557         if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
1558             fprintf(stderr,
1559                     "\nIf you're runnning a guest on an Intel machine without "
1560                         "unrestricted mode\n"
1561                     "support, the failure can be most likely due to the guest "
1562                         "entering an invalid\n"
1563                     "state for Intel VT. For example, the guest maybe running "
1564                         "in big real mode\n"
1565                     "which is not supported on less recent Intel processors."
1566                         "\n\n");
1567         }
1568         ret = -1;
1569         break;
1570     case KVM_EXIT_EXCEPTION:
1571         fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
1572                 run->ex.exception, run->ex.error_code);
1573         ret = -1;
1574         break;
1575     default:
1576         fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
1577         ret = -1;
1578         break;
1579     }
1580
1581     return ret;
1582 }
1583
1584 #ifdef KVM_CAP_SET_GUEST_DEBUG
1585 int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1586 {
1587     static const uint8_t int3 = 0xcc;
1588
1589     if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
1590         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1)) {
1591         return -EINVAL;
1592     }
1593     return 0;
1594 }
1595
1596 int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1597 {
1598     uint8_t int3;
1599
1600     if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
1601         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
1602         return -EINVAL;
1603     }
1604     return 0;
1605 }
1606
1607 static struct {
1608     target_ulong addr;
1609     int len;
1610     int type;
1611 } hw_breakpoint[4];
1612
1613 static int nb_hw_breakpoint;
1614
1615 static int find_hw_breakpoint(target_ulong addr, int len, int type)
1616 {
1617     int n;
1618
1619     for (n = 0; n < nb_hw_breakpoint; n++) {
1620         if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
1621             (hw_breakpoint[n].len == len || len == -1)) {
1622             return n;
1623         }
1624     }
1625     return -1;
1626 }
1627
1628 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
1629                                   target_ulong len, int type)
1630 {
1631     switch (type) {
1632     case GDB_BREAKPOINT_HW:
1633         len = 1;
1634         break;
1635     case GDB_WATCHPOINT_WRITE:
1636     case GDB_WATCHPOINT_ACCESS:
1637         switch (len) {
1638         case 1:
1639             break;
1640         case 2:
1641         case 4:
1642         case 8:
1643             if (addr & (len - 1)) {
1644                 return -EINVAL;
1645             }
1646             break;
1647         default:
1648             return -EINVAL;
1649         }
1650         break;
1651     default:
1652         return -ENOSYS;
1653     }
1654
1655     if (nb_hw_breakpoint == 4) {
1656         return -ENOBUFS;
1657     }
1658     if (find_hw_breakpoint(addr, len, type) >= 0) {
1659         return -EEXIST;
1660     }
1661     hw_breakpoint[nb_hw_breakpoint].addr = addr;
1662     hw_breakpoint[nb_hw_breakpoint].len = len;
1663     hw_breakpoint[nb_hw_breakpoint].type = type;
1664     nb_hw_breakpoint++;
1665
1666     return 0;
1667 }
1668
1669 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
1670                                   target_ulong len, int type)
1671 {
1672     int n;
1673
1674     n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
1675     if (n < 0) {
1676         return -ENOENT;
1677     }
1678     nb_hw_breakpoint--;
1679     hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
1680
1681     return 0;
1682 }
1683
1684 void kvm_arch_remove_all_hw_breakpoints(void)
1685 {
1686     nb_hw_breakpoint = 0;
1687 }
1688
1689 static CPUWatchpoint hw_watchpoint;
1690
1691 int kvm_arch_debug(struct kvm_debug_exit_arch *arch_info)
1692 {
1693     int handle = 0;
1694     int n;
1695
1696     if (arch_info->exception == 1) {
1697         if (arch_info->dr6 & (1 << 14)) {
1698             if (cpu_single_env->singlestep_enabled) {
1699                 handle = 1;
1700             }
1701         } else {
1702             for (n = 0; n < 4; n++) {
1703                 if (arch_info->dr6 & (1 << n)) {
1704                     switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
1705                     case 0x0:
1706                         handle = 1;
1707                         break;
1708                     case 0x1:
1709                         handle = 1;
1710                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
1711                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1712                         hw_watchpoint.flags = BP_MEM_WRITE;
1713                         break;
1714                     case 0x3:
1715                         handle = 1;
1716                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
1717                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1718                         hw_watchpoint.flags = BP_MEM_ACCESS;
1719                         break;
1720                     }
1721                 }
1722             }
1723         }
1724     } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc)) {
1725         handle = 1;
1726     }
1727     if (!handle) {
1728         cpu_synchronize_state(cpu_single_env);
1729         assert(cpu_single_env->exception_injected == -1);
1730
1731         cpu_single_env->exception_injected = arch_info->exception;
1732         cpu_single_env->has_error_code = 0;
1733     }
1734
1735     return handle;
1736 }
1737
1738 void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg)
1739 {
1740     const uint8_t type_code[] = {
1741         [GDB_BREAKPOINT_HW] = 0x0,
1742         [GDB_WATCHPOINT_WRITE] = 0x1,
1743         [GDB_WATCHPOINT_ACCESS] = 0x3
1744     };
1745     const uint8_t len_code[] = {
1746         [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
1747     };
1748     int n;
1749
1750     if (kvm_sw_breakpoints_active(env)) {
1751         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
1752     }
1753     if (nb_hw_breakpoint > 0) {
1754         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
1755         dbg->arch.debugreg[7] = 0x0600;
1756         for (n = 0; n < nb_hw_breakpoint; n++) {
1757             dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
1758             dbg->arch.debugreg[7] |= (2 << (n * 2)) |
1759                 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
1760                 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
1761         }
1762     }
1763 }
1764 #endif /* KVM_CAP_SET_GUEST_DEBUG */
1765
1766 bool kvm_arch_stop_on_emulation_error(CPUState *env)
1767 {
1768     return !(env->cr[0] & CR0_PE_MASK) ||
1769            ((env->segs[R_CS].selector  & 3) != 3);
1770 }
1771
1772 static void hardware_memory_error(void)
1773 {
1774     fprintf(stderr, "Hardware memory error!\n");
1775     exit(1);
1776 }
1777
1778 #ifdef KVM_CAP_MCE
1779 static void kvm_mce_broadcast_rest(CPUState *env)
1780 {
1781     struct kvm_x86_mce mce = {
1782         .bank = 1,
1783         .status = MCI_STATUS_VAL | MCI_STATUS_UC,
1784         .mcg_status = MCG_STATUS_MCIP | MCG_STATUS_RIPV,
1785         .addr = 0,
1786         .misc = 0,
1787     };
1788     CPUState *cenv;
1789
1790     /* Broadcast MCA signal for processor version 06H_EH and above */
1791     if (cpu_x86_support_mca_broadcast(env)) {
1792         for (cenv = first_cpu; cenv != NULL; cenv = cenv->next_cpu) {
1793             if (cenv == env) {
1794                 continue;
1795             }
1796             kvm_inject_x86_mce_on(cenv, &mce, ABORT_ON_ERROR);
1797         }
1798     }
1799 }
1800
1801 static void kvm_mce_inj_srar_dataload(CPUState *env, target_phys_addr_t paddr)
1802 {
1803     struct kvm_x86_mce mce = {
1804         .bank = 9,
1805         .status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN
1806                   | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S
1807                   | MCI_STATUS_AR | 0x134,
1808         .mcg_status = MCG_STATUS_MCIP | MCG_STATUS_EIPV,
1809         .addr = paddr,
1810         .misc = (MCM_ADDR_PHYS << 6) | 0xc,
1811     };
1812     int r;
1813
1814     r = kvm_set_mce(env, &mce);
1815     if (r < 0) {
1816         fprintf(stderr, "kvm_set_mce: %s\n", strerror(errno));
1817         abort();
1818     }
1819     kvm_mce_broadcast_rest(env);
1820 }
1821
1822 static void kvm_mce_inj_srao_memscrub(CPUState *env, target_phys_addr_t paddr)
1823 {
1824     struct kvm_x86_mce mce = {
1825         .bank = 9,
1826         .status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN
1827                   | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S
1828                   | 0xc0,
1829         .mcg_status = MCG_STATUS_MCIP | MCG_STATUS_RIPV,
1830         .addr = paddr,
1831         .misc = (MCM_ADDR_PHYS << 6) | 0xc,
1832     };
1833     int r;
1834
1835     r = kvm_set_mce(env, &mce);
1836     if (r < 0) {
1837         fprintf(stderr, "kvm_set_mce: %s\n", strerror(errno));
1838         abort();
1839     }
1840     kvm_mce_broadcast_rest(env);
1841 }
1842
1843 static void kvm_mce_inj_srao_memscrub2(CPUState *env, target_phys_addr_t paddr)
1844 {
1845     struct kvm_x86_mce mce = {
1846         .bank = 9,
1847         .status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN
1848                   | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S
1849                   | 0xc0,
1850         .mcg_status = MCG_STATUS_MCIP | MCG_STATUS_RIPV,
1851         .addr = paddr,
1852         .misc = (MCM_ADDR_PHYS << 6) | 0xc,
1853     };
1854
1855     kvm_inject_x86_mce_on(env, &mce, ABORT_ON_ERROR);
1856     kvm_mce_broadcast_rest(env);
1857 }
1858
1859 #endif
1860
1861 int kvm_on_sigbus_vcpu(CPUState *env, int code, void *addr)
1862 {
1863 #if defined(KVM_CAP_MCE)
1864     void *vaddr;
1865     ram_addr_t ram_addr;
1866     target_phys_addr_t paddr;
1867
1868     if ((env->mcg_cap & MCG_SER_P) && addr
1869         && (code == BUS_MCEERR_AR
1870             || code == BUS_MCEERR_AO)) {
1871         vaddr = (void *)addr;
1872         if (qemu_ram_addr_from_host(vaddr, &ram_addr) ||
1873             !kvm_physical_memory_addr_from_ram(env->kvm_state, ram_addr, &paddr)) {
1874             fprintf(stderr, "Hardware memory error for memory used by "
1875                     "QEMU itself instead of guest system!\n");
1876             /* Hope we are lucky for AO MCE */
1877             if (code == BUS_MCEERR_AO) {
1878                 return 0;
1879             } else {
1880                 hardware_memory_error();
1881             }
1882         }
1883
1884         if (code == BUS_MCEERR_AR) {
1885             /* Fake an Intel architectural Data Load SRAR UCR */
1886             kvm_mce_inj_srar_dataload(env, paddr);
1887         } else {
1888             /*
1889              * If there is an MCE excpetion being processed, ignore
1890              * this SRAO MCE
1891              */
1892             if (!kvm_mce_in_progress(env)) {
1893                 /* Fake an Intel architectural Memory scrubbing UCR */
1894                 kvm_mce_inj_srao_memscrub(env, paddr);
1895             }
1896         }
1897     } else
1898 #endif
1899     {
1900         if (code == BUS_MCEERR_AO) {
1901             return 0;
1902         } else if (code == BUS_MCEERR_AR) {
1903             hardware_memory_error();
1904         } else {
1905             return 1;
1906         }
1907     }
1908     return 0;
1909 }
1910
1911 int kvm_on_sigbus(int code, void *addr)
1912 {
1913 #if defined(KVM_CAP_MCE)
1914     if ((first_cpu->mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
1915         void *vaddr;
1916         ram_addr_t ram_addr;
1917         target_phys_addr_t paddr;
1918
1919         /* Hope we are lucky for AO MCE */
1920         vaddr = addr;
1921         if (qemu_ram_addr_from_host(vaddr, &ram_addr) ||
1922             !kvm_physical_memory_addr_from_ram(first_cpu->kvm_state, ram_addr, &paddr)) {
1923             fprintf(stderr, "Hardware memory error for memory used by "
1924                     "QEMU itself instead of guest system!: %p\n", addr);
1925             return 0;
1926         }
1927         kvm_mce_inj_srao_memscrub2(first_cpu, paddr);
1928     } else
1929 #endif
1930     {
1931         if (code == BUS_MCEERR_AO) {
1932             return 0;
1933         } else if (code == BUS_MCEERR_AR) {
1934             hardware_memory_error();
1935         } else {
1936             return 1;
1937         }
1938     }
1939     return 0;
1940 }