target-s390x/cpu.h

   1 /*
   2  * S/390 virtual CPU header
   3  *
   4  *  Copyright (c) 2009 Ulrich Hecht
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * Contributions after 2012-10-29 are licensed under the terms of the
  17  * GNU GPL, version 2 or (at your option) any later version.
  18  *
  19  * You should have received a copy of the GNU (Lesser) General Public
  20  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  21  */
  22 #ifndef CPU_S390X_H
  23 #define CPU_S390X_H
  24
  25 #include "config.h"
  26 #include "qemu-common.h"
  27
  28 #define TARGET_LONG_BITS 64
  29
  30 #define ELF_MACHINE     EM_S390
  31 #define ELF_MACHINE_UNAME "S390X"
  32
  33 #define CPUArchState struct CPUS390XState
  34
  35 #include "exec/cpu-defs.h"
  36 #define TARGET_PAGE_BITS 12
  37
  38 #define TARGET_PHYS_ADDR_SPACE_BITS 64
  39 #define TARGET_VIRT_ADDR_SPACE_BITS 64
  40
  41 #include "exec/cpu-all.h"
  42
  43 #include "fpu/softfloat.h"
  44
  45 #define NB_MMU_MODES 3
  46
  47 #define MMU_MODE0_SUFFIX _primary
  48 #define MMU_MODE1_SUFFIX _secondary
  49 #define MMU_MODE2_SUFFIX _home
  50
  51 #define MMU_USER_IDX 1
  52
  53 #define MAX_EXT_QUEUE 16
  54 #define MAX_IO_QUEUE 16
  55 #define MAX_MCHK_QUEUE 16
  56
  57 #define PSW_MCHK_MASK 0x0004000000000000
  58 #define PSW_IO_MASK 0x0200000000000000
  59
  60 typedef struct PSW {
  61     uint64_t mask;
  62     uint64_t addr;
  63 } PSW;
  64
  65 typedef struct ExtQueue {
  66     uint32_t code;
  67     uint32_t param;
  68     uint32_t param64;
  69 } ExtQueue;
  70
  71 typedef struct IOIntQueue {
  72     uint16_t id;
  73     uint16_t nr;
  74     uint32_t parm;
  75     uint32_t word;
  76 } IOIntQueue;
  77
  78 typedef struct MchkQueue {
  79     uint16_t type;
  80 } MchkQueue;
  81
  82 typedef struct CPUS390XState {
  83     uint64_t regs[16];     /* GP registers */
  84     CPU_DoubleU fregs[16]; /* FP registers */
  85     uint32_t aregs[16];    /* access registers */
  86
  87     uint32_t fpc;          /* floating-point control register */
  88     uint32_t cc_op;
  89
  90     float_status fpu_status; /* passed to softfloat lib */
  91
  92     /* The low part of a 128-bit return, or remainder of a divide.  */
  93     uint64_t retxl;
  94
  95     PSW psw;
  96
  97     uint64_t cc_src;
  98     uint64_t cc_dst;
  99     uint64_t cc_vr;
 100
 101     uint64_t __excp_addr;
 102     uint64_t psa;
 103
 104     uint32_t int_pgm_code;
 105     uint32_t int_pgm_ilen;
 106
 107     uint32_t int_svc_code;
 108     uint32_t int_svc_ilen;
 109
 110     uint64_t cregs[16]; /* control registers */
 111
 112     ExtQueue ext_queue[MAX_EXT_QUEUE];
 113     IOIntQueue io_queue[MAX_IO_QUEUE][8];
 114     MchkQueue mchk_queue[MAX_MCHK_QUEUE];
 115
 116     int pending_int;
 117     int ext_index;
 118     int io_index[8];
 119     int mchk_index;
 120
 121     uint64_t ckc;
 122     uint64_t cputm;
 123     uint32_t todpr;
 124
 125     uint64_t pfault_token;
 126     uint64_t pfault_compare;
 127     uint64_t pfault_select;
 128
 129     uint64_t gbea;
 130     uint64_t pp;
 131
 132     CPU_COMMON
 133
 134     /* reset does memset(0) up to here */
 135
 136     uint32_t cpu_num;
 137     uint32_t machine_type;
 138
 139     uint8_t *storage_keys;
 140
 141     uint64_t tod_offset;
 142     uint64_t tod_basetime;
 143     QEMUTimer *tod_timer;
 144
 145     QEMUTimer *cpu_timer;
 146
 147     /*
 148      * The cpu state represents the logical state of a cpu. In contrast to other
 149      * architectures, there is a difference between a halt and a stop on s390.
 150      * If all cpus are either stopped (including check stop) or in the disabled
 151      * wait state, the vm can be shut down.
 152      */
 153 #define CPU_STATE_UNINITIALIZED        0x00
 154 #define CPU_STATE_STOPPED              0x01
 155 #define CPU_STATE_CHECK_STOP           0x02
 156 #define CPU_STATE_OPERATING            0x03
 157 #define CPU_STATE_LOAD                 0x04
 158     uint8_t cpu_state;
 159
 160     /* currently processed sigp order */
 161     uint8_t sigp_order;
 162
 163 } CPUS390XState;
 164
 165 #include "cpu-qom.h"
 166 #include <sysemu/kvm.h>
 167
 168 /* distinguish between 24 bit and 31 bit addressing */
 169 #define HIGH_ORDER_BIT 0x80000000
 170
 171 /* Interrupt Codes */
 172 /* Program Interrupts */
 173 #define PGM_OPERATION                   0x0001
 174 #define PGM_PRIVILEGED                  0x0002
 175 #define PGM_EXECUTE                     0x0003
 176 #define PGM_PROTECTION                  0x0004
 177 #define PGM_ADDRESSING                  0x0005
 178 #define PGM_SPECIFICATION               0x0006
 179 #define PGM_DATA                        0x0007
 180 #define PGM_FIXPT_OVERFLOW              0x0008
 181 #define PGM_FIXPT_DIVIDE                0x0009
 182 #define PGM_DEC_OVERFLOW                0x000a
 183 #define PGM_DEC_DIVIDE                  0x000b
 184 #define PGM_HFP_EXP_OVERFLOW            0x000c
 185 #define PGM_HFP_EXP_UNDERFLOW           0x000d
 186 #define PGM_HFP_SIGNIFICANCE            0x000e
 187 #define PGM_HFP_DIVIDE                  0x000f
 188 #define PGM_SEGMENT_TRANS               0x0010
 189 #define PGM_PAGE_TRANS                  0x0011
 190 #define PGM_TRANS_SPEC                  0x0012
 191 #define PGM_SPECIAL_OP                  0x0013
 192 #define PGM_OPERAND                     0x0015
 193 #define PGM_TRACE_TABLE                 0x0016
 194 #define PGM_SPACE_SWITCH                0x001c
 195 #define PGM_HFP_SQRT                    0x001d
 196 #define PGM_PC_TRANS_SPEC               0x001f
 197 #define PGM_AFX_TRANS                   0x0020
 198 #define PGM_ASX_TRANS                   0x0021
 199 #define PGM_LX_TRANS                    0x0022
 200 #define PGM_EX_TRANS                    0x0023
 201 #define PGM_PRIM_AUTH                   0x0024
 202 #define PGM_SEC_AUTH                    0x0025
 203 #define PGM_ALET_SPEC                   0x0028
 204 #define PGM_ALEN_SPEC                   0x0029
 205 #define PGM_ALE_SEQ                     0x002a
 206 #define PGM_ASTE_VALID                  0x002b
 207 #define PGM_ASTE_SEQ                    0x002c
 208 #define PGM_EXT_AUTH                    0x002d
 209 #define PGM_STACK_FULL                  0x0030
 210 #define PGM_STACK_EMPTY                 0x0031
 211 #define PGM_STACK_SPEC                  0x0032
 212 #define PGM_STACK_TYPE                  0x0033
 213 #define PGM_STACK_OP                    0x0034
 214 #define PGM_ASCE_TYPE                   0x0038
 215 #define PGM_REG_FIRST_TRANS             0x0039
 216 #define PGM_REG_SEC_TRANS               0x003a
 217 #define PGM_REG_THIRD_TRANS             0x003b
 218 #define PGM_MONITOR                     0x0040
 219 #define PGM_PER                         0x0080
 220 #define PGM_CRYPTO                      0x0119
 221
 222 /* External Interrupts */
 223 #define EXT_INTERRUPT_KEY               0x0040
 224 #define EXT_CLOCK_COMP                  0x1004
 225 #define EXT_CPU_TIMER                   0x1005
 226 #define EXT_MALFUNCTION                 0x1200
 227 #define EXT_EMERGENCY                   0x1201
 228 #define EXT_EXTERNAL_CALL               0x1202
 229 #define EXT_ETR                         0x1406
 230 #define EXT_SERVICE                     0x2401
 231 #define EXT_VIRTIO                      0x2603
 232
 233 /* PSW defines */
 234 #undef PSW_MASK_PER
 235 #undef PSW_MASK_DAT
 236 #undef PSW_MASK_IO
 237 #undef PSW_MASK_EXT
 238 #undef PSW_MASK_KEY
 239 #undef PSW_SHIFT_KEY
 240 #undef PSW_MASK_MCHECK
 241 #undef PSW_MASK_WAIT
 242 #undef PSW_MASK_PSTATE
 243 #undef PSW_MASK_ASC
 244 #undef PSW_MASK_CC
 245 #undef PSW_MASK_PM
 246 #undef PSW_MASK_64
 247 #undef PSW_MASK_32
 248 #undef PSW_MASK_ESA_ADDR
 249
 250 #define PSW_MASK_PER            0x4000000000000000ULL
 251 #define PSW_MASK_DAT            0x0400000000000000ULL
 252 #define PSW_MASK_IO             0x0200000000000000ULL
 253 #define PSW_MASK_EXT            0x0100000000000000ULL
 254 #define PSW_MASK_KEY            0x00F0000000000000ULL
 255 #define PSW_SHIFT_KEY           56
 256 #define PSW_MASK_MCHECK         0x0004000000000000ULL
 257 #define PSW_MASK_WAIT           0x0002000000000000ULL
 258 #define PSW_MASK_PSTATE         0x0001000000000000ULL
 259 #define PSW_MASK_ASC            0x0000C00000000000ULL
 260 #define PSW_MASK_CC             0x0000300000000000ULL
 261 #define PSW_MASK_PM             0x00000F0000000000ULL
 262 #define PSW_MASK_64             0x0000000100000000ULL
 263 #define PSW_MASK_32             0x0000000080000000ULL
 264 #define PSW_MASK_ESA_ADDR       0x000000007fffffffULL
 265
 266 #undef PSW_ASC_PRIMARY
 267 #undef PSW_ASC_ACCREG
 268 #undef PSW_ASC_SECONDARY
 269 #undef PSW_ASC_HOME
 270
 271 #define PSW_ASC_PRIMARY         0x0000000000000000ULL
 272 #define PSW_ASC_ACCREG          0x0000400000000000ULL
 273 #define PSW_ASC_SECONDARY       0x0000800000000000ULL
 274 #define PSW_ASC_HOME            0x0000C00000000000ULL
 275
 276 /* tb flags */
 277
 278 #define FLAG_MASK_PER           (PSW_MASK_PER    >> 32)
 279 #define FLAG_MASK_DAT           (PSW_MASK_DAT    >> 32)
 280 #define FLAG_MASK_IO            (PSW_MASK_IO     >> 32)
 281 #define FLAG_MASK_EXT           (PSW_MASK_EXT    >> 32)
 282 #define FLAG_MASK_KEY           (PSW_MASK_KEY    >> 32)
 283 #define FLAG_MASK_MCHECK        (PSW_MASK_MCHECK >> 32)
 284 #define FLAG_MASK_WAIT          (PSW_MASK_WAIT   >> 32)
 285 #define FLAG_MASK_PSTATE        (PSW_MASK_PSTATE >> 32)
 286 #define FLAG_MASK_ASC           (PSW_MASK_ASC    >> 32)
 287 #define FLAG_MASK_CC            (PSW_MASK_CC     >> 32)
 288 #define FLAG_MASK_PM            (PSW_MASK_PM     >> 32)
 289 #define FLAG_MASK_64            (PSW_MASK_64     >> 32)
 290 #define FLAG_MASK_32            0x00001000
 291
 292 /* Control register 0 bits */
 293 #define CR0_LOWPROT             0x0000000010000000ULL
 294 #define CR0_EDAT                0x0000000000800000ULL
 295
 296 static inline int cpu_mmu_index (CPUS390XState *env)
 297 {
 298     if (env->psw.mask & PSW_MASK_PSTATE) {
 299         return 1;
 300     }
 301
 302     return 0;
 303 }
 304
 305 static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
 306                                         target_ulong *cs_base, int *flags)
 307 {
 308     *pc = env->psw.addr;
 309     *cs_base = 0;
 310     *flags = ((env->psw.mask >> 32) & ~FLAG_MASK_CC) |
 311              ((env->psw.mask & PSW_MASK_32) ? FLAG_MASK_32 : 0);
 312 }
 313
 314 /* While the PoO talks about ILC (a number between 1-3) what is actually
 315    stored in LowCore is shifted left one bit (an even between 2-6).  As
 316    this is the actual length of the insn and therefore more useful, that
 317    is what we want to pass around and manipulate.  To make sure that we
 318    have applied this distinction universally, rename the "ILC" to "ILEN".  */
 319 static inline int get_ilen(uint8_t opc)
 320 {
 321     switch (opc >> 6) {
 322     case 0:
 323         return 2;
 324     case 1:
 325     case 2:
 326         return 4;
 327     default:
 328         return 6;
 329     }
 330 }
 331
 332 #ifndef CONFIG_USER_ONLY
 333 /* In several cases of runtime exceptions, we havn't recorded the true
 334    instruction length.  Use these codes when raising exceptions in order
 335    to re-compute the length by examining the insn in memory.  */
 336 #define ILEN_LATER       0x20
 337 #define ILEN_LATER_INC   0x21
 338 void trigger_pgm_exception(CPUS390XState *env, uint32_t code, uint32_t ilen);
 339 #endif
 340
 341 S390CPU *cpu_s390x_init(const char *cpu_model);
 342 void s390x_translate_init(void);
 343 int cpu_s390x_exec(CPUS390XState *s);
 344
 345 /* you can call this signal handler from your SIGBUS and SIGSEGV
 346    signal handlers to inform the virtual CPU of exceptions. non zero
 347    is returned if the signal was handled by the virtual CPU.  */
 348 int cpu_s390x_signal_handler(int host_signum, void *pinfo,
 349                            void *puc);
 350 int s390_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
 351                               int mmu_idx);
 352
 353 #include "ioinst.h"
 354
 355
 356 #ifndef CONFIG_USER_ONLY
 357 void do_restart_interrupt(CPUS390XState *env);
 358
 359 static inline hwaddr decode_basedisp_s(CPUS390XState *env, uint32_t ipb,
 360                                        uint8_t *ar)
 361 {
 362     hwaddr addr = 0;
 363     uint8_t reg;
 364
 365     reg = ipb >> 28;
 366     if (reg > 0) {
 367         addr = env->regs[reg];
 368     }
 369     addr += (ipb >> 16) & 0xfff;
 370     if (ar) {
 371         *ar = reg;
 372     }
 373
 374     return addr;
 375 }
 376
 377 /* Base/displacement are at the same locations. */
 378 #define decode_basedisp_rs decode_basedisp_s
 379
 380 /* helper functions for run_on_cpu() */
 381 static inline void s390_do_cpu_reset(void *arg)
 382 {
 383     CPUState *cs = arg;
 384     S390CPUClass *scc = S390_CPU_GET_CLASS(cs);
 385
 386     scc->cpu_reset(cs);
 387 }
 388 static inline void s390_do_cpu_full_reset(void *arg)
 389 {
 390     CPUState *cs = arg;
 391
 392     cpu_reset(cs);
 393 }
 394
 395 void s390x_tod_timer(void *opaque);
 396 void s390x_cpu_timer(void *opaque);
 397
 398 int s390_virtio_hypercall(CPUS390XState *env);
 399 void s390_virtio_irq(int config_change, uint64_t token);
 400
 401 #ifdef CONFIG_KVM
 402 void kvm_s390_virtio_irq(int config_change, uint64_t token);
 403 void kvm_s390_service_interrupt(uint32_t parm);
 404 void kvm_s390_vcpu_interrupt(S390CPU *cpu, struct kvm_s390_irq *irq);
 405 void kvm_s390_floating_interrupt(struct kvm_s390_irq *irq);
 406 int kvm_s390_inject_flic(struct kvm_s390_irq *irq);
 407 void kvm_s390_access_exception(S390CPU *cpu, uint16_t code, uint64_t te_code);
 408 int kvm_s390_mem_op(S390CPU *cpu, vaddr addr, uint8_t ar, void *hostbuf,
 409                     int len, bool is_write);
 410 int kvm_s390_get_clock(uint8_t *tod_high, uint64_t *tod_clock);
 411 int kvm_s390_set_clock(uint8_t *tod_high, uint64_t *tod_clock);
 412 #else
 413 static inline void kvm_s390_virtio_irq(int config_change, uint64_t token)
 414 {
 415 }
 416 static inline void kvm_s390_service_interrupt(uint32_t parm)
 417 {
 418 }
 419 static inline int kvm_s390_get_clock(uint8_t *tod_high, uint64_t *tod_low)
 420 {
 421     return -ENOSYS;
 422 }
 423 static inline int kvm_s390_set_clock(uint8_t *tod_high, uint64_t *tod_low)
 424 {
 425     return -ENOSYS;
 426 }
 427 static inline int kvm_s390_mem_op(S390CPU *cpu, vaddr addr, uint8_t ar,
 428                                   void *hostbuf, int len, bool is_write)
 429 {
 430     return -ENOSYS;
 431 }
 432 static inline void kvm_s390_access_exception(S390CPU *cpu, uint16_t code,
 433                                              uint64_t te_code)
 434 {
 435 }
 436 #endif
 437
 438 static inline int s390_get_clock(uint8_t *tod_high, uint64_t *tod_low)
 439 {
 440     if (kvm_enabled()) {
 441         return kvm_s390_get_clock(tod_high, tod_low);
 442     }
 443     /* Fixme TCG */
 444     *tod_high = 0;
 445     *tod_low = 0;
 446     return 0;
 447 }
 448
 449 static inline int s390_set_clock(uint8_t *tod_high, uint64_t *tod_low)
 450 {
 451     if (kvm_enabled()) {
 452         return kvm_s390_set_clock(tod_high, tod_low);
 453     }
 454     /* Fixme TCG */
 455     return 0;
 456 }
 457
 458 S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
 459 unsigned int s390_cpu_halt(S390CPU *cpu);
 460 void s390_cpu_unhalt(S390CPU *cpu);
 461 unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu);
 462 static inline uint8_t s390_cpu_get_state(S390CPU *cpu)
 463 {
 464     return cpu->env.cpu_state;
 465 }
 466
 467 void gtod_save(QEMUFile *f, void *opaque);
 468 int gtod_load(QEMUFile *f, void *opaque, int version_id);
 469
 470 /* service interrupts are floating therefore we must not pass an cpustate */
 471 void s390_sclp_extint(uint32_t parm);
 472
 473 /* from s390-virtio-bus */
 474 extern const hwaddr virtio_size;
 475
 476 #else
 477 static inline unsigned int s390_cpu_halt(S390CPU *cpu)
 478 {
 479     return 0;
 480 }
 481
 482 static inline void s390_cpu_unhalt(S390CPU *cpu)
 483 {
 484 }
 485
 486 static inline unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu)
 487 {
 488     return 0;
 489 }
 490 #endif
 491 void cpu_lock(void);
 492 void cpu_unlock(void);
 493
 494 typedef struct SubchDev SubchDev;
 495
 496 #ifndef CONFIG_USER_ONLY
 497 extern void io_subsystem_reset(void);
 498 SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid,
 499                          uint16_t schid);
 500 bool css_subch_visible(SubchDev *sch);
 501 void css_conditional_io_interrupt(SubchDev *sch);
 502 int css_do_stsch(SubchDev *sch, SCHIB *schib);
 503 bool css_schid_final(int m, uint8_t cssid, uint8_t ssid, uint16_t schid);
 504 int css_do_msch(SubchDev *sch, const SCHIB *schib);
 505 int css_do_xsch(SubchDev *sch);
 506 int css_do_csch(SubchDev *sch);
 507 int css_do_hsch(SubchDev *sch);
 508 int css_do_ssch(SubchDev *sch, ORB *orb);
 509 int css_do_tsch_get_irb(SubchDev *sch, IRB *irb, int *irb_len);
 510 void css_do_tsch_update_subch(SubchDev *sch);
 511 int css_do_stcrw(CRW *crw);
 512 void css_undo_stcrw(CRW *crw);
 513 int css_do_tpi(IOIntCode *int_code, int lowcore);
 514 int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid, uint8_t l_chpid,
 515                          int rfmt, void *buf);
 516 void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo);
 517 int css_enable_mcsse(void);
 518 int css_enable_mss(void);
 519 int css_do_rsch(SubchDev *sch);
 520 int css_do_rchp(uint8_t cssid, uint8_t chpid);
 521 bool css_present(uint8_t cssid);
 522 #endif
 523
 524 #define cpu_init(model) CPU(cpu_s390x_init(model))
 525 #define cpu_exec cpu_s390x_exec
 526 #define cpu_gen_code cpu_s390x_gen_code
 527 #define cpu_signal_handler cpu_s390x_signal_handler
 528
 529 void s390_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 530 #define cpu_list s390_cpu_list
 531
 532 #include "exec/exec-all.h"
 533
 534 #define EXCP_EXT 1 /* external interrupt */
 535 #define EXCP_SVC 2 /* supervisor call (syscall) */
 536 #define EXCP_PGM 3 /* program interruption */
 537 #define EXCP_IO  7 /* I/O interrupt */
 538 #define EXCP_MCHK 8 /* machine check */
 539
 540 #define INTERRUPT_EXT        (1 << 0)
 541 #define INTERRUPT_TOD        (1 << 1)
 542 #define INTERRUPT_CPUTIMER   (1 << 2)
 543 #define INTERRUPT_IO         (1 << 3)
 544 #define INTERRUPT_MCHK       (1 << 4)
 545
 546 /* Program Status Word.  */
 547 #define S390_PSWM_REGNUM 0
 548 #define S390_PSWA_REGNUM 1
 549 /* General Purpose Registers.  */
 550 #define S390_R0_REGNUM 2
 551 #define S390_R1_REGNUM 3
 552 #define S390_R2_REGNUM 4
 553 #define S390_R3_REGNUM 5
 554 #define S390_R4_REGNUM 6
 555 #define S390_R5_REGNUM 7
 556 #define S390_R6_REGNUM 8
 557 #define S390_R7_REGNUM 9
 558 #define S390_R8_REGNUM 10
 559 #define S390_R9_REGNUM 11
 560 #define S390_R10_REGNUM 12
 561 #define S390_R11_REGNUM 13
 562 #define S390_R12_REGNUM 14
 563 #define S390_R13_REGNUM 15
 564 #define S390_R14_REGNUM 16
 565 #define S390_R15_REGNUM 17
 566 /* Total Core Registers. */
 567 #define S390_NUM_CORE_REGS 18
 568
 569 /* CC optimization */
 570
 571 enum cc_op {
 572     CC_OP_CONST0 = 0,           /* CC is 0 */
 573     CC_OP_CONST1,               /* CC is 1 */
 574     CC_OP_CONST2,               /* CC is 2 */
 575     CC_OP_CONST3,               /* CC is 3 */
 576
 577     CC_OP_DYNAMIC,              /* CC calculation defined by env->cc_op */
 578     CC_OP_STATIC,               /* CC value is env->cc_op */
 579
 580     CC_OP_NZ,                   /* env->cc_dst != 0 */
 581     CC_OP_LTGT_32,              /* signed less/greater than (32bit) */
 582     CC_OP_LTGT_64,              /* signed less/greater than (64bit) */
 583     CC_OP_LTUGTU_32,            /* unsigned less/greater than (32bit) */
 584     CC_OP_LTUGTU_64,            /* unsigned less/greater than (64bit) */
 585     CC_OP_LTGT0_32,             /* signed less/greater than 0 (32bit) */
 586     CC_OP_LTGT0_64,             /* signed less/greater than 0 (64bit) */
 587
 588     CC_OP_ADD_64,               /* overflow on add (64bit) */
 589     CC_OP_ADDU_64,              /* overflow on unsigned add (64bit) */
 590     CC_OP_ADDC_64,              /* overflow on unsigned add-carry (64bit) */
 591     CC_OP_SUB_64,               /* overflow on subtraction (64bit) */
 592     CC_OP_SUBU_64,              /* overflow on unsigned subtraction (64bit) */
 593     CC_OP_SUBB_64,              /* overflow on unsigned sub-borrow (64bit) */
 594     CC_OP_ABS_64,               /* sign eval on abs (64bit) */
 595     CC_OP_NABS_64,              /* sign eval on nabs (64bit) */
 596
 597     CC_OP_ADD_32,               /* overflow on add (32bit) */
 598     CC_OP_ADDU_32,              /* overflow on unsigned add (32bit) */
 599     CC_OP_ADDC_32,              /* overflow on unsigned add-carry (32bit) */
 600     CC_OP_SUB_32,               /* overflow on subtraction (32bit) */
 601     CC_OP_SUBU_32,              /* overflow on unsigned subtraction (32bit) */
 602     CC_OP_SUBB_32,              /* overflow on unsigned sub-borrow (32bit) */
 603     CC_OP_ABS_32,               /* sign eval on abs (64bit) */
 604     CC_OP_NABS_32,              /* sign eval on nabs (64bit) */
 605
 606     CC_OP_COMP_32,              /* complement */
 607     CC_OP_COMP_64,              /* complement */
 608
 609     CC_OP_TM_32,                /* test under mask (32bit) */
 610     CC_OP_TM_64,                /* test under mask (64bit) */
 611
 612     CC_OP_NZ_F32,               /* FP dst != 0 (32bit) */
 613     CC_OP_NZ_F64,               /* FP dst != 0 (64bit) */
 614     CC_OP_NZ_F128,              /* FP dst != 0 (128bit) */
 615
 616     CC_OP_ICM,                  /* insert characters under mask */
 617     CC_OP_SLA_32,               /* Calculate shift left signed (32bit) */
 618     CC_OP_SLA_64,               /* Calculate shift left signed (64bit) */
 619     CC_OP_FLOGR,                /* find leftmost one */
 620     CC_OP_MAX
 621 };
 622
 623 static const char *cc_names[] = {
 624     [CC_OP_CONST0]    = "CC_OP_CONST0",
 625     [CC_OP_CONST1]    = "CC_OP_CONST1",
 626     [CC_OP_CONST2]    = "CC_OP_CONST2",
 627     [CC_OP_CONST3]    = "CC_OP_CONST3",
 628     [CC_OP_DYNAMIC]   = "CC_OP_DYNAMIC",
 629     [CC_OP_STATIC]    = "CC_OP_STATIC",
 630     [CC_OP_NZ]        = "CC_OP_NZ",
 631     [CC_OP_LTGT_32]   = "CC_OP_LTGT_32",
 632     [CC_OP_LTGT_64]   = "CC_OP_LTGT_64",
 633     [CC_OP_LTUGTU_32] = "CC_OP_LTUGTU_32",
 634     [CC_OP_LTUGTU_64] = "CC_OP_LTUGTU_64",
 635     [CC_OP_LTGT0_32]  = "CC_OP_LTGT0_32",
 636     [CC_OP_LTGT0_64]  = "CC_OP_LTGT0_64",
 637     [CC_OP_ADD_64]    = "CC_OP_ADD_64",
 638     [CC_OP_ADDU_64]   = "CC_OP_ADDU_64",
 639     [CC_OP_ADDC_64]   = "CC_OP_ADDC_64",
 640     [CC_OP_SUB_64]    = "CC_OP_SUB_64",
 641     [CC_OP_SUBU_64]   = "CC_OP_SUBU_64",
 642     [CC_OP_SUBB_64]   = "CC_OP_SUBB_64",
 643     [CC_OP_ABS_64]    = "CC_OP_ABS_64",
 644     [CC_OP_NABS_64]   = "CC_OP_NABS_64",
 645     [CC_OP_ADD_32]    = "CC_OP_ADD_32",
 646     [CC_OP_ADDU_32]   = "CC_OP_ADDU_32",
 647     [CC_OP_ADDC_32]   = "CC_OP_ADDC_32",
 648     [CC_OP_SUB_32]    = "CC_OP_SUB_32",
 649     [CC_OP_SUBU_32]   = "CC_OP_SUBU_32",
 650     [CC_OP_SUBB_32]   = "CC_OP_SUBB_32",
 651     [CC_OP_ABS_32]    = "CC_OP_ABS_32",
 652     [CC_OP_NABS_32]   = "CC_OP_NABS_32",
 653     [CC_OP_COMP_32]   = "CC_OP_COMP_32",
 654     [CC_OP_COMP_64]   = "CC_OP_COMP_64",
 655     [CC_OP_TM_32]     = "CC_OP_TM_32",
 656     [CC_OP_TM_64]     = "CC_OP_TM_64",
 657     [CC_OP_NZ_F32]    = "CC_OP_NZ_F32",
 658     [CC_OP_NZ_F64]    = "CC_OP_NZ_F64",
 659     [CC_OP_NZ_F128]   = "CC_OP_NZ_F128",
 660     [CC_OP_ICM]       = "CC_OP_ICM",
 661     [CC_OP_SLA_32]    = "CC_OP_SLA_32",
 662     [CC_OP_SLA_64]    = "CC_OP_SLA_64",
 663     [CC_OP_FLOGR]     = "CC_OP_FLOGR",
 664 };
 665
 666 static inline const char *cc_name(int cc_op)
 667 {
 668     return cc_names[cc_op];
 669 }
 670
 671 static inline void setcc(S390CPU *cpu, uint64_t cc)
 672 {
 673     CPUS390XState *env = &cpu->env;
 674
 675     env->psw.mask &= ~(3ull << 44);
 676     env->psw.mask |= (cc & 3) << 44;
 677 }
 678
 679 typedef struct LowCore
 680 {
 681     /* prefix area: defined by architecture */
 682     uint32_t        ccw1[2];                  /* 0x000 */
 683     uint32_t        ccw2[4];                  /* 0x008 */
 684     uint8_t         pad1[0x80-0x18];          /* 0x018 */
 685     uint32_t        ext_params;               /* 0x080 */
 686     uint16_t        cpu_addr;                 /* 0x084 */
 687     uint16_t        ext_int_code;             /* 0x086 */
 688     uint16_t        svc_ilen;                 /* 0x088 */
 689     uint16_t        svc_code;                 /* 0x08a */
 690     uint16_t        pgm_ilen;                 /* 0x08c */
 691     uint16_t        pgm_code;                 /* 0x08e */
 692     uint32_t        data_exc_code;            /* 0x090 */
 693     uint16_t        mon_class_num;            /* 0x094 */
 694     uint16_t        per_perc_atmid;           /* 0x096 */
 695     uint64_t        per_address;              /* 0x098 */
 696     uint8_t         exc_access_id;            /* 0x0a0 */
 697     uint8_t         per_access_id;            /* 0x0a1 */
 698     uint8_t         op_access_id;             /* 0x0a2 */
 699     uint8_t         ar_access_id;             /* 0x0a3 */
 700     uint8_t         pad2[0xA8-0xA4];          /* 0x0a4 */
 701     uint64_t        trans_exc_code;           /* 0x0a8 */
 702     uint64_t        monitor_code;             /* 0x0b0 */
 703     uint16_t        subchannel_id;            /* 0x0b8 */
 704     uint16_t        subchannel_nr;            /* 0x0ba */
 705     uint32_t        io_int_parm;              /* 0x0bc */
 706     uint32_t        io_int_word;              /* 0x0c0 */
 707     uint8_t         pad3[0xc8-0xc4];          /* 0x0c4 */
 708     uint32_t        stfl_fac_list;            /* 0x0c8 */
 709     uint8_t         pad4[0xe8-0xcc];          /* 0x0cc */
 710     uint32_t        mcck_interruption_code[2]; /* 0x0e8 */
 711     uint8_t         pad5[0xf4-0xf0];          /* 0x0f0 */
 712     uint32_t        external_damage_code;     /* 0x0f4 */
 713     uint64_t        failing_storage_address;  /* 0x0f8 */
 714     uint8_t         pad6[0x120-0x100];        /* 0x100 */
 715     PSW             restart_old_psw;          /* 0x120 */
 716     PSW             external_old_psw;         /* 0x130 */
 717     PSW             svc_old_psw;              /* 0x140 */
 718     PSW             program_old_psw;          /* 0x150 */
 719     PSW             mcck_old_psw;             /* 0x160 */
 720     PSW             io_old_psw;               /* 0x170 */
 721     uint8_t         pad7[0x1a0-0x180];        /* 0x180 */
 722     PSW             restart_new_psw;          /* 0x1a0 */
 723     PSW             external_new_psw;         /* 0x1b0 */
 724     PSW             svc_new_psw;              /* 0x1c0 */
 725     PSW             program_new_psw;          /* 0x1d0 */
 726     PSW             mcck_new_psw;             /* 0x1e0 */
 727     PSW             io_new_psw;               /* 0x1f0 */
 728     PSW             return_psw;               /* 0x200 */
 729     uint8_t         irb[64];                  /* 0x210 */
 730     uint64_t        sync_enter_timer;         /* 0x250 */
 731     uint64_t        async_enter_timer;        /* 0x258 */
 732     uint64_t        exit_timer;               /* 0x260 */
 733     uint64_t        last_update_timer;        /* 0x268 */
 734     uint64_t        user_timer;               /* 0x270 */
 735     uint64_t        system_timer;             /* 0x278 */
 736     uint64_t        last_update_clock;        /* 0x280 */
 737     uint64_t        steal_clock;              /* 0x288 */
 738     PSW             return_mcck_psw;          /* 0x290 */
 739     uint8_t         pad8[0xc00-0x2a0];        /* 0x2a0 */
 740     /* System info area */
 741     uint64_t        save_area[16];            /* 0xc00 */
 742     uint8_t         pad9[0xd40-0xc80];        /* 0xc80 */
 743     uint64_t        kernel_stack;             /* 0xd40 */
 744     uint64_t        thread_info;              /* 0xd48 */
 745     uint64_t        async_stack;              /* 0xd50 */
 746     uint64_t        kernel_asce;              /* 0xd58 */
 747     uint64_t        user_asce;                /* 0xd60 */
 748     uint64_t        panic_stack;              /* 0xd68 */
 749     uint64_t        user_exec_asce;           /* 0xd70 */
 750     uint8_t         pad10[0xdc0-0xd78];       /* 0xd78 */
 751
 752     /* SMP info area: defined by DJB */
 753     uint64_t        clock_comparator;         /* 0xdc0 */
 754     uint64_t        ext_call_fast;            /* 0xdc8 */
 755     uint64_t        percpu_offset;            /* 0xdd0 */
 756     uint64_t        current_task;             /* 0xdd8 */
 757     uint32_t        softirq_pending;          /* 0xde0 */
 758     uint32_t        pad_0x0de4;               /* 0xde4 */
 759     uint64_t        int_clock;                /* 0xde8 */
 760     uint8_t         pad12[0xe00-0xdf0];       /* 0xdf0 */
 761
 762     /* 0xe00 is used as indicator for dump tools */
 763     /* whether the kernel died with panic() or not */
 764     uint32_t        panic_magic;              /* 0xe00 */
 765
 766     uint8_t         pad13[0x11b8-0xe04];      /* 0xe04 */
 767
 768     /* 64 bit extparam used for pfault, diag 250 etc  */
 769     uint64_t        ext_params2;               /* 0x11B8 */
 770
 771     uint8_t         pad14[0x1200-0x11C0];      /* 0x11C0 */
 772
 773     /* System info area */
 774
 775     uint64_t        floating_pt_save_area[16]; /* 0x1200 */
 776     uint64_t        gpregs_save_area[16];      /* 0x1280 */
 777     uint32_t        st_status_fixed_logout[4]; /* 0x1300 */
 778     uint8_t         pad15[0x1318-0x1310];      /* 0x1310 */
 779     uint32_t        prefixreg_save_area;       /* 0x1318 */
 780     uint32_t        fpt_creg_save_area;        /* 0x131c */
 781     uint8_t         pad16[0x1324-0x1320];      /* 0x1320 */
 782     uint32_t        tod_progreg_save_area;     /* 0x1324 */
 783     uint32_t        cpu_timer_save_area[2];    /* 0x1328 */
 784     uint32_t        clock_comp_save_area[2];   /* 0x1330 */
 785     uint8_t         pad17[0x1340-0x1338];      /* 0x1338 */
 786     uint32_t        access_regs_save_area[16]; /* 0x1340 */
 787     uint64_t        cregs_save_area[16];       /* 0x1380 */
 788
 789     /* align to the top of the prefix area */
 790
 791     uint8_t         pad18[0x2000-0x1400];      /* 0x1400 */
 792 } QEMU_PACKED LowCore;
 793
 794 /* STSI */
 795 #define STSI_LEVEL_MASK         0x00000000f0000000ULL
 796 #define STSI_LEVEL_CURRENT      0x0000000000000000ULL
 797 #define STSI_LEVEL_1            0x0000000010000000ULL
 798 #define STSI_LEVEL_2            0x0000000020000000ULL
 799 #define STSI_LEVEL_3            0x0000000030000000ULL
 800 #define STSI_R0_RESERVED_MASK   0x000000000fffff00ULL
 801 #define STSI_R0_SEL1_MASK       0x00000000000000ffULL
 802 #define STSI_R1_RESERVED_MASK   0x00000000ffff0000ULL
 803 #define STSI_R1_SEL2_MASK       0x000000000000ffffULL
 804
 805 /* Basic Machine Configuration */
 806 struct sysib_111 {
 807     uint32_t res1[8];
 808     uint8_t  manuf[16];
 809     uint8_t  type[4];
 810     uint8_t  res2[12];
 811     uint8_t  model[16];
 812     uint8_t  sequence[16];
 813     uint8_t  plant[4];
 814     uint8_t  res3[156];
 815 };
 816
 817 /* Basic Machine CPU */
 818 struct sysib_121 {
 819     uint32_t res1[80];
 820     uint8_t  sequence[16];
 821     uint8_t  plant[4];
 822     uint8_t  res2[2];
 823     uint16_t cpu_addr;
 824     uint8_t  res3[152];
 825 };
 826
 827 /* Basic Machine CPUs */
 828 struct sysib_122 {
 829     uint8_t res1[32];
 830     uint32_t capability;
 831     uint16_t total_cpus;
 832     uint16_t active_cpus;
 833     uint16_t standby_cpus;
 834     uint16_t reserved_cpus;
 835     uint16_t adjustments[2026];
 836 };
 837
 838 /* LPAR CPU */
 839 struct sysib_221 {
 840     uint32_t res1[80];
 841     uint8_t  sequence[16];
 842     uint8_t  plant[4];
 843     uint16_t cpu_id;
 844     uint16_t cpu_addr;
 845     uint8_t  res3[152];
 846 };
 847
 848 /* LPAR CPUs */
 849 struct sysib_222 {
 850     uint32_t res1[32];
 851     uint16_t lpar_num;
 852     uint8_t  res2;
 853     uint8_t  lcpuc;
 854     uint16_t total_cpus;
 855     uint16_t conf_cpus;
 856     uint16_t standby_cpus;
 857     uint16_t reserved_cpus;
 858     uint8_t  name[8];
 859     uint32_t caf;
 860     uint8_t  res3[16];
 861     uint16_t dedicated_cpus;
 862     uint16_t shared_cpus;
 863     uint8_t  res4[180];
 864 };
 865
 866 /* VM CPUs */
 867 struct sysib_322 {
 868     uint8_t  res1[31];
 869     uint8_t  count;
 870     struct {
 871         uint8_t  res2[4];
 872         uint16_t total_cpus;
 873         uint16_t conf_cpus;
 874         uint16_t standby_cpus;
 875         uint16_t reserved_cpus;
 876         uint8_t  name[8];
 877         uint32_t caf;
 878         uint8_t  cpi[16];
 879         uint8_t res5[3];
 880         uint8_t ext_name_encoding;
 881         uint32_t res3;
 882         uint8_t uuid[16];
 883     } vm[8];
 884     uint8_t res4[1504];
 885     uint8_t ext_names[8][256];
 886 };
 887
 888 /* MMU defines */
 889 #define _ASCE_ORIGIN            ~0xfffULL /* segment table origin             */
 890 #define _ASCE_SUBSPACE          0x200     /* subspace group control           */
 891 #define _ASCE_PRIVATE_SPACE     0x100     /* private space control            */
 892 #define _ASCE_ALT_EVENT         0x80      /* storage alteration event control */
 893 #define _ASCE_SPACE_SWITCH      0x40      /* space switch event               */
 894 #define _ASCE_REAL_SPACE        0x20      /* real space control               */
 895 #define _ASCE_TYPE_MASK         0x0c      /* asce table type mask             */
 896 #define _ASCE_TYPE_REGION1      0x0c      /* region first table type          */
 897 #define _ASCE_TYPE_REGION2      0x08      /* region second table type         */
 898 #define _ASCE_TYPE_REGION3      0x04      /* region third table type          */
 899 #define _ASCE_TYPE_SEGMENT      0x00      /* segment table type               */
 900 #define _ASCE_TABLE_LENGTH      0x03      /* region table length              */
 901
 902 #define _REGION_ENTRY_ORIGIN    ~0xfffULL /* region/segment table origin      */
 903 #define _REGION_ENTRY_RO        0x200     /* region/segment protection bit    */
 904 #define _REGION_ENTRY_TF        0xc0      /* region/segment table offset      */
 905 #define _REGION_ENTRY_INV       0x20      /* invalid region table entry       */
 906 #define _REGION_ENTRY_TYPE_MASK 0x0c      /* region/segment table type mask   */
 907 #define _REGION_ENTRY_TYPE_R1   0x0c      /* region first table type          */
 908 #define _REGION_ENTRY_TYPE_R2   0x08      /* region second table type         */
 909 #define _REGION_ENTRY_TYPE_R3   0x04      /* region third table type          */
 910 #define _REGION_ENTRY_LENGTH    0x03      /* region third length              */
 911
 912 #define _SEGMENT_ENTRY_ORIGIN   ~0x7ffULL /* segment table origin             */
 913 #define _SEGMENT_ENTRY_FC       0x400     /* format control                   */
 914 #define _SEGMENT_ENTRY_RO       0x200     /* page protection bit              */
 915 #define _SEGMENT_ENTRY_INV      0x20      /* invalid segment table entry      */
 916
 917 #define _PAGE_RO        0x200            /* HW read-only bit  */
 918 #define _PAGE_INVALID   0x400            /* HW invalid bit    */
 919 #define _PAGE_RES0      0x800            /* bit must be zero  */
 920
 921 #define SK_C                    (0x1 << 1)
 922 #define SK_R                    (0x1 << 2)
 923 #define SK_F                    (0x1 << 3)
 924 #define SK_ACC_MASK             (0xf << 4)
 925
 926 /* SIGP order codes */
 927 #define SIGP_SENSE             0x01
 928 #define SIGP_EXTERNAL_CALL     0x02
 929 #define SIGP_EMERGENCY         0x03
 930 #define SIGP_START             0x04
 931 #define SIGP_STOP              0x05
 932 #define SIGP_RESTART           0x06
 933 #define SIGP_STOP_STORE_STATUS 0x09
 934 #define SIGP_INITIAL_CPU_RESET 0x0b
 935 #define SIGP_CPU_RESET         0x0c
 936 #define SIGP_SET_PREFIX        0x0d
 937 #define SIGP_STORE_STATUS_ADDR 0x0e
 938 #define SIGP_SET_ARCH          0x12
 939
 940 /* SIGP condition codes */
 941 #define SIGP_CC_ORDER_CODE_ACCEPTED 0
 942 #define SIGP_CC_STATUS_STORED       1
 943 #define SIGP_CC_BUSY                2
 944 #define SIGP_CC_NOT_OPERATIONAL     3
 945
 946 /* SIGP status bits */
 947 #define SIGP_STAT_EQUIPMENT_CHECK   0x80000000UL
 948 #define SIGP_STAT_INCORRECT_STATE   0x00000200UL
 949 #define SIGP_STAT_INVALID_PARAMETER 0x00000100UL
 950 #define SIGP_STAT_EXT_CALL_PENDING  0x00000080UL
 951 #define SIGP_STAT_STOPPED           0x00000040UL
 952 #define SIGP_STAT_OPERATOR_INTERV   0x00000020UL
 953 #define SIGP_STAT_CHECK_STOP        0x00000010UL
 954 #define SIGP_STAT_INOPERATIVE       0x00000004UL
 955 #define SIGP_STAT_INVALID_ORDER     0x00000002UL
 956 #define SIGP_STAT_RECEIVER_CHECK    0x00000001UL
 957
 958 /* SIGP SET ARCHITECTURE modes */
 959 #define SIGP_MODE_ESA_S390 0
 960 #define SIGP_MODE_Z_ARCH_TRANS_ALL_PSW 1
 961 #define SIGP_MODE_Z_ARCH_TRANS_CUR_PSW 2
 962
 963 void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr);
 964 int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
 965                   target_ulong *raddr, int *flags, bool exc);
 966 int sclp_service_call(CPUS390XState *env, uint64_t sccb, uint32_t code);
 967 uint32_t calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t src, uint64_t dst,
 968                  uint64_t vr);
 969
 970 int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, uint8_t ar, void *hostbuf,
 971                          int len, bool is_write);
 972
 973 #define s390_cpu_virt_mem_read(cpu, laddr, ar, dest, len)    \
 974         s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, false)
 975 #define s390_cpu_virt_mem_write(cpu, laddr, ar, dest, len)       \
 976         s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, true)
 977 #define s390_cpu_virt_mem_check_write(cpu, laddr, ar, len)   \
 978         s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, true)
 979
 980 /* The value of the TOD clock for 1.1.1970. */
 981 #define TOD_UNIX_EPOCH 0x7d91048bca000000ULL
 982
 983 /* Converts ns to s390's clock format */
 984 static inline uint64_t time2tod(uint64_t ns) {
 985     return (ns << 9) / 125;
 986 }
 987
 988 static inline void cpu_inject_ext(S390CPU *cpu, uint32_t code, uint32_t param,
 989                                   uint64_t param64)
 990 {
 991     CPUS390XState *env = &cpu->env;
 992
 993     if (env->ext_index == MAX_EXT_QUEUE - 1) {
 994         /* ugh - can't queue anymore. Let's drop. */
 995         return;
 996     }
 997
 998     env->ext_index++;
 999     assert(env->ext_index < MAX_EXT_QUEUE);
1000
1001     env->ext_queue[env->ext_index].code = code;
1002     env->ext_queue[env->ext_index].param = param;
1003     env->ext_queue[env->ext_index].param64 = param64;
1004
1005     env->pending_int |= INTERRUPT_EXT;
1006     cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
1007 }
1008
1009 static inline void cpu_inject_io(S390CPU *cpu, uint16_t subchannel_id,
1010                                  uint16_t subchannel_number,
1011                                  uint32_t io_int_parm, uint32_t io_int_word)
1012 {
1013     CPUS390XState *env = &cpu->env;
1014     int isc = IO_INT_WORD_ISC(io_int_word);
1015
1016     if (env->io_index[isc] == MAX_IO_QUEUE - 1) {
1017         /* ugh - can't queue anymore. Let's drop. */
1018         return;
1019     }
1020
1021     env->io_index[isc]++;
1022     assert(env->io_index[isc] < MAX_IO_QUEUE);
1023
1024     env->io_queue[env->io_index[isc]][isc].id = subchannel_id;
1025     env->io_queue[env->io_index[isc]][isc].nr = subchannel_number;
1026     env->io_queue[env->io_index[isc]][isc].parm = io_int_parm;
1027     env->io_queue[env->io_index[isc]][isc].word = io_int_word;
1028
1029     env->pending_int |= INTERRUPT_IO;
1030     cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
1031 }
1032
1033 static inline void cpu_inject_crw_mchk(S390CPU *cpu)
1034 {
1035     CPUS390XState *env = &cpu->env;
1036
1037     if (env->mchk_index == MAX_MCHK_QUEUE - 1) {
1038         /* ugh - can't queue anymore. Let's drop. */
1039         return;
1040     }
1041
1042     env->mchk_index++;
1043     assert(env->mchk_index < MAX_MCHK_QUEUE);
1044
1045     env->mchk_queue[env->mchk_index].type = 1;
1046
1047     env->pending_int |= INTERRUPT_MCHK;
1048     cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
1049 }
1050
1051 /* from s390-virtio-ccw */
1052 #define MEM_SECTION_SIZE             0x10000000UL
1053 #define MAX_AVAIL_SLOTS              32
1054
1055 /* fpu_helper.c */
1056 uint32_t set_cc_nz_f32(float32 v);
1057 uint32_t set_cc_nz_f64(float64 v);
1058 uint32_t set_cc_nz_f128(float128 v);
1059
1060 /* misc_helper.c */
1061 #ifndef CONFIG_USER_ONLY
1062 void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3);
1063 #endif
1064 void program_interrupt(CPUS390XState *env, uint32_t code, int ilen);
1065 void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp,
1066                                      uintptr_t retaddr);
1067
1068 #ifdef CONFIG_KVM
1069 void kvm_s390_io_interrupt(uint16_t subchannel_id,
1070                            uint16_t subchannel_nr, uint32_t io_int_parm,
1071                            uint32_t io_int_word);
1072 void kvm_s390_crw_mchk(void);
1073 void kvm_s390_enable_css_support(S390CPU *cpu);
1074 int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch,
1075                                     int vq, bool assign);
1076 int kvm_s390_cpu_restart(S390CPU *cpu);
1077 int kvm_s390_get_memslot_count(KVMState *s);
1078 void kvm_s390_clear_cmma_callback(void *opaque);
1079 int kvm_s390_set_cpu_state(S390CPU *cpu, uint8_t cpu_state);
1080 void kvm_s390_reset_vcpu(S390CPU *cpu);
1081 int kvm_s390_set_mem_limit(KVMState *s, uint64_t new_limit, uint64_t *hw_limit);
1082 void kvm_s390_vcpu_interrupt_pre_save(S390CPU *cpu);
1083 int kvm_s390_vcpu_interrupt_post_load(S390CPU *cpu);
1084 #else
1085 static inline void kvm_s390_io_interrupt(uint16_t subchannel_id,
1086                                         uint16_t subchannel_nr,
1087                                         uint32_t io_int_parm,
1088                                         uint32_t io_int_word)
1089 {
1090 }
1091 static inline void kvm_s390_crw_mchk(void)
1092 {
1093 }
1094 static inline void kvm_s390_enable_css_support(S390CPU *cpu)
1095 {
1096 }
1097 static inline int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier,
1098                                                   uint32_t sch, int vq,
1099                                                   bool assign)
1100 {
1101     return -ENOSYS;
1102 }
1103 static inline int kvm_s390_cpu_restart(S390CPU *cpu)
1104 {
1105     return -ENOSYS;
1106 }
1107 static inline void kvm_s390_clear_cmma_callback(void *opaque)
1108 {
1109 }
1110 static inline int kvm_s390_get_memslot_count(KVMState *s)
1111 {
1112   return MAX_AVAIL_SLOTS;
1113 }
1114 static inline int kvm_s390_set_cpu_state(S390CPU *cpu, uint8_t cpu_state)
1115 {
1116     return -ENOSYS;
1117 }
1118 static inline void kvm_s390_reset_vcpu(S390CPU *cpu)
1119 {
1120 }
1121 static inline int kvm_s390_set_mem_limit(KVMState *s, uint64_t new_limit,
1122                                          uint64_t *hw_limit)
1123 {
1124     return 0;
1125 }
1126 static inline void kvm_s390_vcpu_interrupt_pre_save(S390CPU *cpu)
1127 {
1128 }
1129 static inline int kvm_s390_vcpu_interrupt_post_load(S390CPU *cpu)
1130 {
1131     return 0;
1132 }
1133 #endif
1134
1135 static inline int s390_set_memory_limit(uint64_t new_limit, uint64_t *hw_limit)
1136 {
1137     if (kvm_enabled()) {
1138         return kvm_s390_set_mem_limit(kvm_state, new_limit, hw_limit);
1139     }
1140     return 0;
1141 }
1142
1143 static inline void cmma_reset(S390CPU *cpu)
1144 {
1145     if (kvm_enabled()) {
1146         CPUState *cs = CPU(cpu);
1147         kvm_s390_clear_cmma_callback(cs->kvm_state);
1148     }
1149 }
1150
1151 static inline int s390_cpu_restart(S390CPU *cpu)
1152 {
1153     if (kvm_enabled()) {
1154         return kvm_s390_cpu_restart(cpu);
1155     }
1156     return -ENOSYS;
1157 }
1158
1159 static inline int s390_get_memslot_count(KVMState *s)
1160 {
1161     if (kvm_enabled()) {
1162         return kvm_s390_get_memslot_count(s);
1163     } else {
1164         return MAX_AVAIL_SLOTS;
1165     }
1166 }
1167
1168 void s390_io_interrupt(uint16_t subchannel_id, uint16_t subchannel_nr,
1169                        uint32_t io_int_parm, uint32_t io_int_word);
1170 void s390_crw_mchk(void);
1171
1172 static inline int s390_assign_subch_ioeventfd(EventNotifier *notifier,
1173                                               uint32_t sch_id, int vq,
1174                                               bool assign)
1175 {
1176     if (kvm_enabled()) {
1177         return kvm_s390_assign_subch_ioeventfd(notifier, sch_id, vq, assign);
1178     } else {
1179         return -ENOSYS;
1180     }
1181 }
1182
1183 #endif