4 * Copyright (c) 2004-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>
19 #include "qemu/thread.h"
20 #include "hw/i386/apic_internal.h"
21 #include "hw/i386/apic.h"
22 #include "hw/i386/ioapic.h"
23 #include "hw/pci/msi.h"
24 #include "qemu/host-utils.h"
26 #include "hw/i386/pc.h"
27 #include "hw/i386/apic-msidef.h"
29 #define MAX_APIC_WORDS 8
31 #define SYNC_FROM_VAPIC 0x1
32 #define SYNC_TO_VAPIC 0x2
33 #define SYNC_ISR_IRR_TO_VAPIC 0x4
35 static APICCommonState
*local_apics
[MAX_APICS
+ 1];
37 static void apic_set_irq(APICCommonState
*s
, int vector_num
, int trigger_mode
);
38 static void apic_update_irq(APICCommonState
*s
);
39 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask
,
40 uint8_t dest
, uint8_t dest_mode
);
42 /* Find first bit starting from msb */
43 static int apic_fls_bit(uint32_t value
)
45 return 31 - clz32(value
);
48 /* Find first bit starting from lsb */
49 static int apic_ffs_bit(uint32_t value
)
54 static inline void apic_reset_bit(uint32_t *tab
, int index
)
58 mask
= 1 << (index
& 0x1f);
62 /* return -1 if no bit is set */
63 static int get_highest_priority_int(uint32_t *tab
)
66 for (i
= 7; i
>= 0; i
--) {
68 return i
* 32 + apic_fls_bit(tab
[i
]);
74 static void apic_sync_vapic(APICCommonState
*s
, int sync_type
)
76 VAPICState vapic_state
;
81 if (!s
->vapic_paddr
) {
84 if (sync_type
& SYNC_FROM_VAPIC
) {
85 cpu_physical_memory_read(s
->vapic_paddr
, &vapic_state
,
87 s
->tpr
= vapic_state
.tpr
;
89 if (sync_type
& (SYNC_TO_VAPIC
| SYNC_ISR_IRR_TO_VAPIC
)) {
90 start
= offsetof(VAPICState
, isr
);
91 length
= offsetof(VAPICState
, enabled
) - offsetof(VAPICState
, isr
);
93 if (sync_type
& SYNC_TO_VAPIC
) {
94 assert(qemu_cpu_is_self(CPU(s
->cpu
)));
96 vapic_state
.tpr
= s
->tpr
;
97 vapic_state
.enabled
= 1;
99 length
= sizeof(VAPICState
);
102 vector
= get_highest_priority_int(s
->isr
);
106 vapic_state
.isr
= vector
& 0xf0;
108 vapic_state
.zero
= 0;
110 vector
= get_highest_priority_int(s
->irr
);
114 vapic_state
.irr
= vector
& 0xff;
116 cpu_physical_memory_write_rom(&address_space_memory
,
117 s
->vapic_paddr
+ start
,
118 ((void *)&vapic_state
) + start
, length
);
122 static void apic_vapic_base_update(APICCommonState
*s
)
124 apic_sync_vapic(s
, SYNC_TO_VAPIC
);
127 static void apic_local_deliver(APICCommonState
*s
, int vector
)
129 uint32_t lvt
= s
->lvt
[vector
];
132 trace_apic_local_deliver(vector
, (lvt
>> 8) & 7);
134 if (lvt
& APIC_LVT_MASKED
)
137 switch ((lvt
>> 8) & 7) {
139 cpu_interrupt(CPU(s
->cpu
), CPU_INTERRUPT_SMI
);
143 cpu_interrupt(CPU(s
->cpu
), CPU_INTERRUPT_NMI
);
147 cpu_interrupt(CPU(s
->cpu
), CPU_INTERRUPT_HARD
);
151 trigger_mode
= APIC_TRIGGER_EDGE
;
152 if ((vector
== APIC_LVT_LINT0
|| vector
== APIC_LVT_LINT1
) &&
153 (lvt
& APIC_LVT_LEVEL_TRIGGER
))
154 trigger_mode
= APIC_TRIGGER_LEVEL
;
155 apic_set_irq(s
, lvt
& 0xff, trigger_mode
);
159 void apic_deliver_pic_intr(DeviceState
*dev
, int level
)
161 APICCommonState
*s
= APIC_COMMON(dev
);
164 apic_local_deliver(s
, APIC_LVT_LINT0
);
166 uint32_t lvt
= s
->lvt
[APIC_LVT_LINT0
];
168 switch ((lvt
>> 8) & 7) {
170 if (!(lvt
& APIC_LVT_LEVEL_TRIGGER
))
172 apic_reset_bit(s
->irr
, lvt
& 0xff);
181 static void apic_external_nmi(APICCommonState
*s
)
183 apic_local_deliver(s
, APIC_LVT_LINT1
);
186 #define foreach_apic(apic, deliver_bitmask, code) \
189 for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\
190 uint32_t __mask = deliver_bitmask[__i];\
192 for(__j = 0; __j < 32; __j++) {\
193 if (__mask & (1U << __j)) {\
194 apic = local_apics[__i * 32 + __j];\
204 static void apic_bus_deliver(const uint32_t *deliver_bitmask
,
205 uint8_t delivery_mode
, uint8_t vector_num
,
206 uint8_t trigger_mode
)
208 APICCommonState
*apic_iter
;
210 switch (delivery_mode
) {
212 /* XXX: search for focus processor, arbitration */
216 for(i
= 0; i
< MAX_APIC_WORDS
; i
++) {
217 if (deliver_bitmask
[i
]) {
218 d
= i
* 32 + apic_ffs_bit(deliver_bitmask
[i
]);
223 apic_iter
= local_apics
[d
];
225 apic_set_irq(apic_iter
, vector_num
, trigger_mode
);
235 foreach_apic(apic_iter
, deliver_bitmask
,
236 cpu_interrupt(CPU(apic_iter
->cpu
), CPU_INTERRUPT_SMI
)
241 foreach_apic(apic_iter
, deliver_bitmask
,
242 cpu_interrupt(CPU(apic_iter
->cpu
), CPU_INTERRUPT_NMI
)
247 /* normal INIT IPI sent to processors */
248 foreach_apic(apic_iter
, deliver_bitmask
,
249 cpu_interrupt(CPU(apic_iter
->cpu
),
255 /* handled in I/O APIC code */
262 foreach_apic(apic_iter
, deliver_bitmask
,
263 apic_set_irq(apic_iter
, vector_num
, trigger_mode
) );
266 void apic_deliver_irq(uint8_t dest
, uint8_t dest_mode
, uint8_t delivery_mode
,
267 uint8_t vector_num
, uint8_t trigger_mode
)
269 uint32_t deliver_bitmask
[MAX_APIC_WORDS
];
271 trace_apic_deliver_irq(dest
, dest_mode
, delivery_mode
, vector_num
,
274 apic_get_delivery_bitmask(deliver_bitmask
, dest
, dest_mode
);
275 apic_bus_deliver(deliver_bitmask
, delivery_mode
, vector_num
, trigger_mode
);
278 static void apic_set_base(APICCommonState
*s
, uint64_t val
)
280 s
->apicbase
= (val
& 0xfffff000) |
281 (s
->apicbase
& (MSR_IA32_APICBASE_BSP
| MSR_IA32_APICBASE_ENABLE
));
282 /* if disabled, cannot be enabled again */
283 if (!(val
& MSR_IA32_APICBASE_ENABLE
)) {
284 s
->apicbase
&= ~MSR_IA32_APICBASE_ENABLE
;
285 cpu_clear_apic_feature(&s
->cpu
->env
);
286 s
->spurious_vec
&= ~APIC_SV_ENABLE
;
290 static void apic_set_tpr(APICCommonState
*s
, uint8_t val
)
292 /* Updates from cr8 are ignored while the VAPIC is active */
293 if (!s
->vapic_paddr
) {
299 static uint8_t apic_get_tpr(APICCommonState
*s
)
301 apic_sync_vapic(s
, SYNC_FROM_VAPIC
);
305 int apic_get_ppr(APICCommonState
*s
)
310 isrv
= get_highest_priority_int(s
->isr
);
321 static int apic_get_arb_pri(APICCommonState
*s
)
323 /* XXX: arbitration */
329 * <0 - low prio interrupt,
331 * >0 - interrupt number
333 static int apic_irq_pending(APICCommonState
*s
)
337 if (!(s
->spurious_vec
& APIC_SV_ENABLE
)) {
341 irrv
= get_highest_priority_int(s
->irr
);
345 ppr
= apic_get_ppr(s
);
346 if (ppr
&& (irrv
& 0xf0) <= (ppr
& 0xf0)) {
353 /* signal the CPU if an irq is pending */
354 static void apic_update_irq(APICCommonState
*s
)
357 DeviceState
*dev
= (DeviceState
*)s
;
360 if (!qemu_cpu_is_self(cpu
)) {
361 cpu_interrupt(cpu
, CPU_INTERRUPT_POLL
);
362 } else if (apic_irq_pending(s
) > 0) {
363 cpu_interrupt(cpu
, CPU_INTERRUPT_HARD
);
364 } else if (!apic_accept_pic_intr(dev
) || !pic_get_output(isa_pic
)) {
365 cpu_reset_interrupt(cpu
, CPU_INTERRUPT_HARD
);
369 void apic_poll_irq(DeviceState
*dev
)
371 APICCommonState
*s
= APIC_COMMON(dev
);
373 apic_sync_vapic(s
, SYNC_FROM_VAPIC
);
377 static void apic_set_irq(APICCommonState
*s
, int vector_num
, int trigger_mode
)
379 apic_report_irq_delivered(!apic_get_bit(s
->irr
, vector_num
));
381 apic_set_bit(s
->irr
, vector_num
);
383 apic_set_bit(s
->tmr
, vector_num
);
385 apic_reset_bit(s
->tmr
, vector_num
);
386 if (s
->vapic_paddr
) {
387 apic_sync_vapic(s
, SYNC_ISR_IRR_TO_VAPIC
);
389 * The vcpu thread needs to see the new IRR before we pull its current
390 * TPR value. That way, if we miss a lowering of the TRP, the guest
391 * has the chance to notice the new IRR and poll for IRQs on its own.
394 apic_sync_vapic(s
, SYNC_FROM_VAPIC
);
399 static void apic_eoi(APICCommonState
*s
)
402 isrv
= get_highest_priority_int(s
->isr
);
405 apic_reset_bit(s
->isr
, isrv
);
406 if (!(s
->spurious_vec
& APIC_SV_DIRECTED_IO
) && apic_get_bit(s
->tmr
, isrv
)) {
407 ioapic_eoi_broadcast(isrv
);
409 apic_sync_vapic(s
, SYNC_FROM_VAPIC
| SYNC_TO_VAPIC
);
413 static int apic_find_dest(uint8_t dest
)
415 APICCommonState
*apic
= local_apics
[dest
];
418 if (apic
&& apic
->id
== dest
)
419 return dest
; /* shortcut in case apic->id == apic->idx */
421 for (i
= 0; i
< MAX_APICS
; i
++) {
422 apic
= local_apics
[i
];
423 if (apic
&& apic
->id
== dest
)
432 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask
,
433 uint8_t dest
, uint8_t dest_mode
)
435 APICCommonState
*apic_iter
;
438 if (dest_mode
== 0) {
440 memset(deliver_bitmask
, 0xff, MAX_APIC_WORDS
* sizeof(uint32_t));
442 int idx
= apic_find_dest(dest
);
443 memset(deliver_bitmask
, 0x00, MAX_APIC_WORDS
* sizeof(uint32_t));
445 apic_set_bit(deliver_bitmask
, idx
);
448 /* XXX: cluster mode */
449 memset(deliver_bitmask
, 0x00, MAX_APIC_WORDS
* sizeof(uint32_t));
450 for(i
= 0; i
< MAX_APICS
; i
++) {
451 apic_iter
= local_apics
[i
];
453 if (apic_iter
->dest_mode
== 0xf) {
454 if (dest
& apic_iter
->log_dest
)
455 apic_set_bit(deliver_bitmask
, i
);
456 } else if (apic_iter
->dest_mode
== 0x0) {
457 if ((dest
& 0xf0) == (apic_iter
->log_dest
& 0xf0) &&
458 (dest
& apic_iter
->log_dest
& 0x0f)) {
459 apic_set_bit(deliver_bitmask
, i
);
469 static void apic_startup(APICCommonState
*s
, int vector_num
)
471 s
->sipi_vector
= vector_num
;
472 cpu_interrupt(CPU(s
->cpu
), CPU_INTERRUPT_SIPI
);
475 void apic_sipi(DeviceState
*dev
)
477 APICCommonState
*s
= APIC_COMMON(dev
);
479 cpu_reset_interrupt(CPU(s
->cpu
), CPU_INTERRUPT_SIPI
);
481 if (!s
->wait_for_sipi
)
483 cpu_x86_load_seg_cache_sipi(s
->cpu
, s
->sipi_vector
);
484 s
->wait_for_sipi
= 0;
487 static void apic_deliver(DeviceState
*dev
, uint8_t dest
, uint8_t dest_mode
,
488 uint8_t delivery_mode
, uint8_t vector_num
,
489 uint8_t trigger_mode
)
491 APICCommonState
*s
= APIC_COMMON(dev
);
492 uint32_t deliver_bitmask
[MAX_APIC_WORDS
];
493 int dest_shorthand
= (s
->icr
[0] >> 18) & 3;
494 APICCommonState
*apic_iter
;
496 switch (dest_shorthand
) {
498 apic_get_delivery_bitmask(deliver_bitmask
, dest
, dest_mode
);
501 memset(deliver_bitmask
, 0x00, sizeof(deliver_bitmask
));
502 apic_set_bit(deliver_bitmask
, s
->idx
);
505 memset(deliver_bitmask
, 0xff, sizeof(deliver_bitmask
));
508 memset(deliver_bitmask
, 0xff, sizeof(deliver_bitmask
));
509 apic_reset_bit(deliver_bitmask
, s
->idx
);
513 switch (delivery_mode
) {
516 int trig_mode
= (s
->icr
[0] >> 15) & 1;
517 int level
= (s
->icr
[0] >> 14) & 1;
518 if (level
== 0 && trig_mode
== 1) {
519 foreach_apic(apic_iter
, deliver_bitmask
,
520 apic_iter
->arb_id
= apic_iter
->id
);
527 foreach_apic(apic_iter
, deliver_bitmask
,
528 apic_startup(apic_iter
, vector_num
) );
532 apic_bus_deliver(deliver_bitmask
, delivery_mode
, vector_num
, trigger_mode
);
535 static bool apic_check_pic(APICCommonState
*s
)
537 DeviceState
*dev
= (DeviceState
*)s
;
539 if (!apic_accept_pic_intr(dev
) || !pic_get_output(isa_pic
)) {
542 apic_deliver_pic_intr(dev
, 1);
546 int apic_get_interrupt(DeviceState
*dev
)
548 APICCommonState
*s
= APIC_COMMON(dev
);
551 /* if the APIC is installed or enabled, we let the 8259 handle the
555 if (!(s
->spurious_vec
& APIC_SV_ENABLE
))
558 apic_sync_vapic(s
, SYNC_FROM_VAPIC
);
559 intno
= apic_irq_pending(s
);
561 /* if there is an interrupt from the 8259, let the caller handle
562 * that first since ExtINT interrupts ignore the priority.
564 if (intno
== 0 || apic_check_pic(s
)) {
565 apic_sync_vapic(s
, SYNC_TO_VAPIC
);
567 } else if (intno
< 0) {
568 apic_sync_vapic(s
, SYNC_TO_VAPIC
);
569 return s
->spurious_vec
& 0xff;
571 apic_reset_bit(s
->irr
, intno
);
572 apic_set_bit(s
->isr
, intno
);
573 apic_sync_vapic(s
, SYNC_TO_VAPIC
);
580 int apic_accept_pic_intr(DeviceState
*dev
)
582 APICCommonState
*s
= APIC_COMMON(dev
);
588 lvt0
= s
->lvt
[APIC_LVT_LINT0
];
590 if ((s
->apicbase
& MSR_IA32_APICBASE_ENABLE
) == 0 ||
591 (lvt0
& APIC_LVT_MASKED
) == 0)
597 static uint32_t apic_get_current_count(APICCommonState
*s
)
601 d
= (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) - s
->initial_count_load_time
) >>
603 if (s
->lvt
[APIC_LVT_TIMER
] & APIC_LVT_TIMER_PERIODIC
) {
605 val
= s
->initial_count
- (d
% ((uint64_t)s
->initial_count
+ 1));
607 if (d
>= s
->initial_count
)
610 val
= s
->initial_count
- d
;
615 static void apic_timer_update(APICCommonState
*s
, int64_t current_time
)
617 if (apic_next_timer(s
, current_time
)) {
618 timer_mod(s
->timer
, s
->next_time
);
624 static void apic_timer(void *opaque
)
626 APICCommonState
*s
= opaque
;
628 apic_local_deliver(s
, APIC_LVT_TIMER
);
629 apic_timer_update(s
, s
->next_time
);
632 static uint32_t apic_mem_readb(void *opaque
, hwaddr addr
)
637 static uint32_t apic_mem_readw(void *opaque
, hwaddr addr
)
642 static void apic_mem_writeb(void *opaque
, hwaddr addr
, uint32_t val
)
646 static void apic_mem_writew(void *opaque
, hwaddr addr
, uint32_t val
)
650 static uint32_t apic_mem_readl(void *opaque
, hwaddr addr
)
657 dev
= cpu_get_current_apic();
661 s
= APIC_COMMON(dev
);
663 index
= (addr
>> 4) & 0xff;
668 case 0x03: /* version */
669 val
= s
->version
| ((APIC_LVT_NB
- 1) << 16);
672 apic_sync_vapic(s
, SYNC_FROM_VAPIC
);
673 if (apic_report_tpr_access
) {
674 cpu_report_tpr_access(&s
->cpu
->env
, TPR_ACCESS_READ
);
679 val
= apic_get_arb_pri(s
);
683 val
= apic_get_ppr(s
);
689 val
= s
->log_dest
<< 24;
692 val
= (s
->dest_mode
<< 28) | 0xfffffff;
695 val
= s
->spurious_vec
;
698 val
= s
->isr
[index
& 7];
701 val
= s
->tmr
[index
& 7];
704 val
= s
->irr
[index
& 7];
711 val
= s
->icr
[index
& 1];
714 val
= s
->lvt
[index
- 0x32];
717 val
= s
->initial_count
;
720 val
= apic_get_current_count(s
);
723 val
= s
->divide_conf
;
726 s
->esr
|= APIC_ESR_ILLEGAL_ADDRESS
;
730 trace_apic_mem_readl(addr
, val
);
734 static void apic_send_msi(hwaddr addr
, uint32_t data
)
736 uint8_t dest
= (addr
& MSI_ADDR_DEST_ID_MASK
) >> MSI_ADDR_DEST_ID_SHIFT
;
737 uint8_t vector
= (data
& MSI_DATA_VECTOR_MASK
) >> MSI_DATA_VECTOR_SHIFT
;
738 uint8_t dest_mode
= (addr
>> MSI_ADDR_DEST_MODE_SHIFT
) & 0x1;
739 uint8_t trigger_mode
= (data
>> MSI_DATA_TRIGGER_SHIFT
) & 0x1;
740 uint8_t delivery
= (data
>> MSI_DATA_DELIVERY_MODE_SHIFT
) & 0x7;
741 /* XXX: Ignore redirection hint. */
742 apic_deliver_irq(dest
, dest_mode
, delivery
, vector
, trigger_mode
);
745 static void apic_mem_writel(void *opaque
, hwaddr addr
, uint32_t val
)
749 int index
= (addr
>> 4) & 0xff;
750 if (addr
> 0xfff || !index
) {
751 /* MSI and MMIO APIC are at the same memory location,
752 * but actually not on the global bus: MSI is on PCI bus
753 * APIC is connected directly to the CPU.
754 * Mapping them on the global bus happens to work because
755 * MSI registers are reserved in APIC MMIO and vice versa. */
756 apic_send_msi(addr
, val
);
760 dev
= cpu_get_current_apic();
764 s
= APIC_COMMON(dev
);
766 trace_apic_mem_writel(addr
, val
);
775 if (apic_report_tpr_access
) {
776 cpu_report_tpr_access(&s
->cpu
->env
, TPR_ACCESS_WRITE
);
779 apic_sync_vapic(s
, SYNC_TO_VAPIC
);
789 s
->log_dest
= val
>> 24;
792 s
->dest_mode
= val
>> 28;
795 s
->spurious_vec
= val
& 0x1ff;
805 apic_deliver(dev
, (s
->icr
[1] >> 24) & 0xff, (s
->icr
[0] >> 11) & 1,
806 (s
->icr
[0] >> 8) & 7, (s
->icr
[0] & 0xff),
807 (s
->icr
[0] >> 15) & 1);
814 int n
= index
- 0x32;
816 if (n
== APIC_LVT_TIMER
) {
817 apic_timer_update(s
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
));
818 } else if (n
== APIC_LVT_LINT0
&& apic_check_pic(s
)) {
824 s
->initial_count
= val
;
825 s
->initial_count_load_time
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
826 apic_timer_update(s
, s
->initial_count_load_time
);
833 s
->divide_conf
= val
& 0xb;
834 v
= (s
->divide_conf
& 3) | ((s
->divide_conf
>> 1) & 4);
835 s
->count_shift
= (v
+ 1) & 7;
839 s
->esr
|= APIC_ESR_ILLEGAL_ADDRESS
;
844 static void apic_pre_save(APICCommonState
*s
)
846 apic_sync_vapic(s
, SYNC_FROM_VAPIC
);
849 static void apic_post_load(APICCommonState
*s
)
851 if (s
->timer_expiry
!= -1) {
852 timer_mod(s
->timer
, s
->timer_expiry
);
858 static const MemoryRegionOps apic_io_ops
= {
860 .read
= { apic_mem_readb
, apic_mem_readw
, apic_mem_readl
, },
861 .write
= { apic_mem_writeb
, apic_mem_writew
, apic_mem_writel
, },
863 .endianness
= DEVICE_NATIVE_ENDIAN
,
866 static void apic_realize(DeviceState
*dev
, Error
**errp
)
868 APICCommonState
*s
= APIC_COMMON(dev
);
870 memory_region_init_io(&s
->io_memory
, OBJECT(s
), &apic_io_ops
, s
, "apic-msi",
873 s
->timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, apic_timer
, s
);
874 local_apics
[s
->idx
] = s
;
876 msi_supported
= true;
879 static void apic_class_init(ObjectClass
*klass
, void *data
)
881 APICCommonClass
*k
= APIC_COMMON_CLASS(klass
);
883 k
->realize
= apic_realize
;
884 k
->set_base
= apic_set_base
;
885 k
->set_tpr
= apic_set_tpr
;
886 k
->get_tpr
= apic_get_tpr
;
887 k
->vapic_base_update
= apic_vapic_base_update
;
888 k
->external_nmi
= apic_external_nmi
;
889 k
->pre_save
= apic_pre_save
;
890 k
->post_load
= apic_post_load
;
893 static const TypeInfo apic_info
= {
895 .instance_size
= sizeof(APICCommonState
),
896 .parent
= TYPE_APIC_COMMON
,
897 .class_init
= apic_class_init
,
900 static void apic_register_types(void)
902 type_register_static(&apic_info
);
905 type_init(apic_register_types
)