target/nios2/helper.c

   1 /*
   2  * Altera Nios II helper routines.
   3  *
   4  * Copyright (c) 2012 Chris Wulff <crwulff@gmail.com>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see
  18  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  19  */
  20
  21 #include "qemu/osdep.h"
  22
  23 #include "cpu.h"
  24 #include "qemu/host-utils.h"
  25 #include "exec/exec-all.h"
  26 #include "exec/cpu_ldst.h"
  27 #include "exec/log.h"
  28 #include "exec/helper-proto.h"
  29 #include "semihosting/semihost.h"
  30
  31
  32 void nios2_cpu_do_interrupt(CPUState *cs)
  33 {
  34     Nios2CPU *cpu = NIOS2_CPU(cs);
  35     CPUNios2State *env = &cpu->env;
  36
  37     switch (cs->exception_index) {
  38     case EXCP_IRQ:
  39         assert(env->regs[CR_STATUS] & CR_STATUS_PIE);
  40
  41         qemu_log_mask(CPU_LOG_INT, "interrupt at pc=%x\n", env->pc);
  42
  43         env->regs[CR_ESTATUS] = env->regs[CR_STATUS];
  44         env->regs[CR_STATUS] |= CR_STATUS_IH;
  45         env->regs[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U);
  46
  47         env->regs[CR_EXCEPTION] &= ~(0x1F << 2);
  48         env->regs[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2;
  49
  50         env->regs[R_EA] = env->pc + 4;
  51         env->pc = cpu->exception_addr;
  52         break;
  53
  54     case EXCP_TLBD:
  55         if ((env->regs[CR_STATUS] & CR_STATUS_EH) == 0) {
  56             qemu_log_mask(CPU_LOG_INT, "TLB MISS (fast) at pc=%x\n", env->pc);
  57
  58             /* Fast TLB miss */
  59             /* Variation from the spec. Table 3-35 of the cpu reference shows
  60              * estatus not being changed for TLB miss but this appears to
  61              * be incorrect. */
  62             env->regs[CR_ESTATUS] = env->regs[CR_STATUS];
  63             env->regs[CR_STATUS] |= CR_STATUS_EH;
  64             env->regs[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U);
  65
  66             env->regs[CR_EXCEPTION] &= ~(0x1F << 2);
  67             env->regs[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2;
  68
  69             env->regs[CR_TLBMISC] &= ~CR_TLBMISC_DBL;
  70             env->regs[CR_TLBMISC] |= CR_TLBMISC_WR;
  71
  72             env->regs[R_EA] = env->pc + 4;
  73             env->pc = cpu->fast_tlb_miss_addr;
  74         } else {
  75             qemu_log_mask(CPU_LOG_INT, "TLB MISS (double) at pc=%x\n", env->pc);
  76
  77             /* Double TLB miss */
  78             env->regs[CR_STATUS] |= CR_STATUS_EH;
  79             env->regs[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U);
  80
  81             env->regs[CR_EXCEPTION] &= ~(0x1F << 2);
  82             env->regs[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2;
  83
  84             env->regs[CR_TLBMISC] |= CR_TLBMISC_DBL;
  85
  86             env->pc = cpu->exception_addr;
  87         }
  88         break;
  89
  90     case EXCP_TLBR:
  91     case EXCP_TLBW:
  92     case EXCP_TLBX:
  93         qemu_log_mask(CPU_LOG_INT, "TLB PERM at pc=%x\n", env->pc);
  94
  95         env->regs[CR_ESTATUS] = env->regs[CR_STATUS];
  96         env->regs[CR_STATUS] |= CR_STATUS_EH;
  97         env->regs[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U);
  98
  99         env->regs[CR_EXCEPTION] &= ~(0x1F << 2);
 100         env->regs[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2;
 101
 102         if ((env->regs[CR_STATUS] & CR_STATUS_EH) == 0) {
 103             env->regs[CR_TLBMISC] |= CR_TLBMISC_WR;
 104         }
 105
 106         env->regs[R_EA] = env->pc + 4;
 107         env->pc = cpu->exception_addr;
 108         break;
 109
 110     case EXCP_SUPERA:
 111     case EXCP_SUPERI:
 112     case EXCP_SUPERD:
 113         qemu_log_mask(CPU_LOG_INT, "SUPERVISOR exception at pc=%x\n", env->pc);
 114
 115         if ((env->regs[CR_STATUS] & CR_STATUS_EH) == 0) {
 116             env->regs[CR_ESTATUS] = env->regs[CR_STATUS];
 117             env->regs[R_EA] = env->pc + 4;
 118         }
 119
 120         env->regs[CR_STATUS] |= CR_STATUS_EH;
 121         env->regs[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U);
 122
 123         env->regs[CR_EXCEPTION] &= ~(0x1F << 2);
 124         env->regs[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2;
 125
 126         env->pc = cpu->exception_addr;
 127         break;
 128
 129     case EXCP_ILLEGAL:
 130     case EXCP_TRAP:
 131         qemu_log_mask(CPU_LOG_INT, "TRAP exception at pc=%x\n", env->pc);
 132
 133         if ((env->regs[CR_STATUS] & CR_STATUS_EH) == 0) {
 134             env->regs[CR_ESTATUS] = env->regs[CR_STATUS];
 135             env->regs[R_EA] = env->pc + 4;
 136         }
 137
 138         env->regs[CR_STATUS] |= CR_STATUS_EH;
 139         env->regs[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U);
 140
 141         env->regs[CR_EXCEPTION] &= ~(0x1F << 2);
 142         env->regs[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2;
 143
 144         env->pc = cpu->exception_addr;
 145         break;
 146
 147     case EXCP_BREAK:
 148         qemu_log_mask(CPU_LOG_INT, "BREAK exception at pc=%x\n", env->pc);
 149         /* The semihosting instruction is "break 1".  */
 150         if (semihosting_enabled() &&
 151             cpu_ldl_code(env, env->pc) == 0x003da07a)  {
 152             qemu_log_mask(CPU_LOG_INT, "Entering semihosting\n");
 153             env->pc += 4;
 154             do_nios2_semihosting(env);
 155             break;
 156         }
 157
 158         if ((env->regs[CR_STATUS] & CR_STATUS_EH) == 0) {
 159             env->regs[CR_BSTATUS] = env->regs[CR_STATUS];
 160             env->regs[R_BA] = env->pc + 4;
 161         }
 162
 163         env->regs[CR_STATUS] |= CR_STATUS_EH;
 164         env->regs[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U);
 165
 166         env->regs[CR_EXCEPTION] &= ~(0x1F << 2);
 167         env->regs[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2;
 168
 169         env->pc = cpu->exception_addr;
 170         break;
 171
 172     default:
 173         cpu_abort(cs, "unhandled exception type=%d\n",
 174                   cs->exception_index);
 175         break;
 176     }
 177 }
 178
 179 hwaddr nios2_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
 180 {
 181     Nios2CPU *cpu = NIOS2_CPU(cs);
 182     CPUNios2State *env = &cpu->env;
 183     target_ulong vaddr, paddr = 0;
 184     Nios2MMULookup lu;
 185     unsigned int hit;
 186
 187     if (cpu->mmu_present && (addr < 0xC0000000)) {
 188         hit = mmu_translate(env, &lu, addr, 0, 0);
 189         if (hit) {
 190             vaddr = addr & TARGET_PAGE_MASK;
 191             paddr = lu.paddr + vaddr - lu.vaddr;
 192         } else {
 193             paddr = -1;
 194             qemu_log("cpu_get_phys_page debug MISS: %#" PRIx64 "\n", addr);
 195         }
 196     } else {
 197         paddr = addr & TARGET_PAGE_MASK;
 198     }
 199
 200     return paddr;
 201 }
 202
 203 void nios2_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
 204                                    MMUAccessType access_type,
 205                                    int mmu_idx, uintptr_t retaddr)
 206 {
 207     Nios2CPU *cpu = NIOS2_CPU(cs);
 208     CPUNios2State *env = &cpu->env;
 209
 210     env->regs[CR_BADADDR] = addr;
 211     env->regs[CR_EXCEPTION] = EXCP_UNALIGN << 2;
 212     helper_raise_exception(env, EXCP_UNALIGN);
 213 }
 214
 215 bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 216                         MMUAccessType access_type, int mmu_idx,
 217                         bool probe, uintptr_t retaddr)
 218 {
 219     Nios2CPU *cpu = NIOS2_CPU(cs);
 220     CPUNios2State *env = &cpu->env;
 221     unsigned int excp = EXCP_TLBD;
 222     target_ulong vaddr, paddr;
 223     Nios2MMULookup lu;
 224     unsigned int hit;
 225
 226     if (!cpu->mmu_present) {
 227         /* No MMU */
 228         address &= TARGET_PAGE_MASK;
 229         tlb_set_page(cs, address, address, PAGE_BITS,
 230                      mmu_idx, TARGET_PAGE_SIZE);
 231         return true;
 232     }
 233
 234     if (MMU_SUPERVISOR_IDX == mmu_idx) {
 235         if (address >= 0xC0000000) {
 236             /* Kernel physical page - TLB bypassed */
 237             address &= TARGET_PAGE_MASK;
 238             tlb_set_page(cs, address, address, PAGE_BITS,
 239                          mmu_idx, TARGET_PAGE_SIZE);
 240             return true;
 241         }
 242     } else {
 243         if (address >= 0x80000000) {
 244             /* Illegal access from user mode */
 245             if (probe) {
 246                 return false;
 247             }
 248             cs->exception_index = EXCP_SUPERA;
 249             env->regs[CR_BADADDR] = address;
 250             cpu_loop_exit_restore(cs, retaddr);
 251         }
 252     }
 253
 254     /* Virtual page.  */
 255     hit = mmu_translate(env, &lu, address, access_type, mmu_idx);
 256     if (hit) {
 257         vaddr = address & TARGET_PAGE_MASK;
 258         paddr = lu.paddr + vaddr - lu.vaddr;
 259
 260         if (((access_type == MMU_DATA_LOAD) && (lu.prot & PAGE_READ)) ||
 261             ((access_type == MMU_DATA_STORE) && (lu.prot & PAGE_WRITE)) ||
 262             ((access_type == MMU_INST_FETCH) && (lu.prot & PAGE_EXEC))) {
 263             tlb_set_page(cs, vaddr, paddr, lu.prot,
 264                          mmu_idx, TARGET_PAGE_SIZE);
 265             return true;
 266         }
 267
 268         /* Permission violation */
 269         excp = (access_type == MMU_DATA_LOAD ? EXCP_TLBR :
 270                 access_type == MMU_DATA_STORE ? EXCP_TLBW : EXCP_TLBX);
 271     }
 272
 273     if (probe) {
 274         return false;
 275     }
 276
 277     if (access_type == MMU_INST_FETCH) {
 278         env->regs[CR_TLBMISC] &= ~CR_TLBMISC_D;
 279     } else {
 280         env->regs[CR_TLBMISC] |= CR_TLBMISC_D;
 281     }
 282     env->regs[CR_PTEADDR] &= CR_PTEADDR_PTBASE_MASK;
 283     env->regs[CR_PTEADDR] |= (address >> 10) & CR_PTEADDR_VPN_MASK;
 284     env->mmu.pteaddr_wr = env->regs[CR_PTEADDR];
 285
 286     cs->exception_index = excp;
 287     env->regs[CR_BADADDR] = address;
 288     cpu_loop_exit_restore(cs, retaddr);
 289 }