mirror: clarify mirror_do_read return code
[qemu.git] / target-sh4 / cpu.c
blobf589532e18ebd745d1a2ce6e916de43f762f8176
1 /*
2 * QEMU SuperH CPU
4 * Copyright (c) 2005 Samuel Tardieu
5 * Copyright (c) 2012 SUSE LINUX Products GmbH
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see
19 * <http://www.gnu.org/licenses/lgpl-2.1.html>
22 #include "qemu/osdep.h"
23 #include "qapi/error.h"
24 #include "cpu.h"
25 #include "qemu-common.h"
26 #include "migration/vmstate.h"
27 #include "exec/exec-all.h"
30 static void superh_cpu_set_pc(CPUState *cs, vaddr value)
32 SuperHCPU *cpu = SUPERH_CPU(cs);
34 cpu->env.pc = value;
37 static void superh_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
39 SuperHCPU *cpu = SUPERH_CPU(cs);
41 cpu->env.pc = tb->pc;
42 cpu->env.flags = tb->flags;
45 static bool superh_cpu_has_work(CPUState *cs)
47 return cs->interrupt_request & CPU_INTERRUPT_HARD;
50 /* CPUClass::reset() */
51 static void superh_cpu_reset(CPUState *s)
53 SuperHCPU *cpu = SUPERH_CPU(s);
54 SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(cpu);
55 CPUSH4State *env = &cpu->env;
57 scc->parent_reset(s);
59 memset(env, 0, offsetof(CPUSH4State, id));
60 tlb_flush(s, 1);
62 env->pc = 0xA0000000;
63 #if defined(CONFIG_USER_ONLY)
64 env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */
65 set_float_rounding_mode(float_round_nearest_even, &env->fp_status); /* ?! */
66 #else
67 env->sr = (1u << SR_MD) | (1u << SR_RB) | (1u << SR_BL) |
68 (1u << SR_I3) | (1u << SR_I2) | (1u << SR_I1) | (1u << SR_I0);
69 env->fpscr = FPSCR_DN | FPSCR_RM_ZERO; /* CPU reset value according to SH4 manual */
70 set_float_rounding_mode(float_round_to_zero, &env->fp_status);
71 set_flush_to_zero(1, &env->fp_status);
72 #endif
73 set_default_nan_mode(1, &env->fp_status);
74 set_snan_bit_is_one(1, &env->fp_status);
77 static void superh_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
79 info->mach = bfd_mach_sh4;
80 info->print_insn = print_insn_sh;
83 typedef struct SuperHCPUListState {
84 fprintf_function cpu_fprintf;
85 FILE *file;
86 } SuperHCPUListState;
88 /* Sort alphabetically by type name. */
89 static gint superh_cpu_list_compare(gconstpointer a, gconstpointer b)
91 ObjectClass *class_a = (ObjectClass *)a;
92 ObjectClass *class_b = (ObjectClass *)b;
93 const char *name_a, *name_b;
95 name_a = object_class_get_name(class_a);
96 name_b = object_class_get_name(class_b);
97 return strcmp(name_a, name_b);
100 static void superh_cpu_list_entry(gpointer data, gpointer user_data)
102 ObjectClass *oc = data;
103 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
104 SuperHCPUListState *s = user_data;
106 (*s->cpu_fprintf)(s->file, "%s\n",
107 scc->name);
110 void sh4_cpu_list(FILE *f, fprintf_function cpu_fprintf)
112 SuperHCPUListState s = {
113 .cpu_fprintf = cpu_fprintf,
114 .file = f,
116 GSList *list;
118 list = object_class_get_list(TYPE_SUPERH_CPU, false);
119 list = g_slist_sort(list, superh_cpu_list_compare);
120 g_slist_foreach(list, superh_cpu_list_entry, &s);
121 g_slist_free(list);
124 static gint superh_cpu_name_compare(gconstpointer a, gconstpointer b)
126 const SuperHCPUClass *scc = SUPERH_CPU_CLASS(a);
127 const char *name = b;
129 return strcasecmp(scc->name, name);
132 static ObjectClass *superh_cpu_class_by_name(const char *cpu_model)
134 ObjectClass *oc;
135 GSList *list, *item;
137 if (cpu_model == NULL) {
138 return NULL;
140 if (strcasecmp(cpu_model, "any") == 0) {
141 return object_class_by_name(TYPE_SH7750R_CPU);
144 oc = object_class_by_name(cpu_model);
145 if (oc != NULL && object_class_dynamic_cast(oc, TYPE_SUPERH_CPU) != NULL
146 && !object_class_is_abstract(oc)) {
147 return oc;
150 oc = NULL;
151 list = object_class_get_list(TYPE_SUPERH_CPU, false);
152 item = g_slist_find_custom(list, cpu_model, superh_cpu_name_compare);
153 if (item != NULL) {
154 oc = item->data;
156 g_slist_free(list);
157 return oc;
160 SuperHCPU *cpu_sh4_init(const char *cpu_model)
162 return SUPERH_CPU(cpu_generic_init(TYPE_SUPERH_CPU, cpu_model));
165 static void sh7750r_cpu_initfn(Object *obj)
167 SuperHCPU *cpu = SUPERH_CPU(obj);
168 CPUSH4State *env = &cpu->env;
170 env->id = SH_CPU_SH7750R;
171 env->features = SH_FEATURE_BCR3_AND_BCR4;
174 static void sh7750r_class_init(ObjectClass *oc, void *data)
176 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
178 scc->name = "SH7750R";
179 scc->pvr = 0x00050000;
180 scc->prr = 0x00000100;
181 scc->cvr = 0x00110000;
184 static const TypeInfo sh7750r_type_info = {
185 .name = TYPE_SH7750R_CPU,
186 .parent = TYPE_SUPERH_CPU,
187 .class_init = sh7750r_class_init,
188 .instance_init = sh7750r_cpu_initfn,
191 static void sh7751r_cpu_initfn(Object *obj)
193 SuperHCPU *cpu = SUPERH_CPU(obj);
194 CPUSH4State *env = &cpu->env;
196 env->id = SH_CPU_SH7751R;
197 env->features = SH_FEATURE_BCR3_AND_BCR4;
200 static void sh7751r_class_init(ObjectClass *oc, void *data)
202 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
204 scc->name = "SH7751R";
205 scc->pvr = 0x04050005;
206 scc->prr = 0x00000113;
207 scc->cvr = 0x00110000; /* Neutered caches, should be 0x20480000 */
210 static const TypeInfo sh7751r_type_info = {
211 .name = TYPE_SH7751R_CPU,
212 .parent = TYPE_SUPERH_CPU,
213 .class_init = sh7751r_class_init,
214 .instance_init = sh7751r_cpu_initfn,
217 static void sh7785_cpu_initfn(Object *obj)
219 SuperHCPU *cpu = SUPERH_CPU(obj);
220 CPUSH4State *env = &cpu->env;
222 env->id = SH_CPU_SH7785;
223 env->features = SH_FEATURE_SH4A;
226 static void sh7785_class_init(ObjectClass *oc, void *data)
228 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
230 scc->name = "SH7785";
231 scc->pvr = 0x10300700;
232 scc->prr = 0x00000200;
233 scc->cvr = 0x71440211;
236 static const TypeInfo sh7785_type_info = {
237 .name = TYPE_SH7785_CPU,
238 .parent = TYPE_SUPERH_CPU,
239 .class_init = sh7785_class_init,
240 .instance_init = sh7785_cpu_initfn,
243 static void superh_cpu_realizefn(DeviceState *dev, Error **errp)
245 CPUState *cs = CPU(dev);
246 SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(dev);
248 cpu_reset(cs);
249 qemu_init_vcpu(cs);
251 scc->parent_realize(dev, errp);
254 static void superh_cpu_initfn(Object *obj)
256 CPUState *cs = CPU(obj);
257 SuperHCPU *cpu = SUPERH_CPU(obj);
258 CPUSH4State *env = &cpu->env;
260 cs->env_ptr = env;
261 cpu_exec_init(cs, &error_abort);
263 env->movcal_backup_tail = &(env->movcal_backup);
265 if (tcg_enabled()) {
266 sh4_translate_init();
270 static const VMStateDescription vmstate_sh_cpu = {
271 .name = "cpu",
272 .unmigratable = 1,
275 static void superh_cpu_class_init(ObjectClass *oc, void *data)
277 DeviceClass *dc = DEVICE_CLASS(oc);
278 CPUClass *cc = CPU_CLASS(oc);
279 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
281 scc->parent_realize = dc->realize;
282 dc->realize = superh_cpu_realizefn;
284 scc->parent_reset = cc->reset;
285 cc->reset = superh_cpu_reset;
287 cc->class_by_name = superh_cpu_class_by_name;
288 cc->has_work = superh_cpu_has_work;
289 cc->do_interrupt = superh_cpu_do_interrupt;
290 cc->cpu_exec_interrupt = superh_cpu_exec_interrupt;
291 cc->dump_state = superh_cpu_dump_state;
292 cc->set_pc = superh_cpu_set_pc;
293 cc->synchronize_from_tb = superh_cpu_synchronize_from_tb;
294 cc->gdb_read_register = superh_cpu_gdb_read_register;
295 cc->gdb_write_register = superh_cpu_gdb_write_register;
296 #ifdef CONFIG_USER_ONLY
297 cc->handle_mmu_fault = superh_cpu_handle_mmu_fault;
298 #else
299 cc->get_phys_page_debug = superh_cpu_get_phys_page_debug;
300 #endif
301 cc->disas_set_info = superh_cpu_disas_set_info;
303 cc->gdb_num_core_regs = 59;
305 dc->vmsd = &vmstate_sh_cpu;
308 * Reason: superh_cpu_initfn() calls cpu_exec_init(), which saves
309 * the object in cpus -> dangling pointer after final
310 * object_unref().
312 dc->cannot_destroy_with_object_finalize_yet = true;
315 static const TypeInfo superh_cpu_type_info = {
316 .name = TYPE_SUPERH_CPU,
317 .parent = TYPE_CPU,
318 .instance_size = sizeof(SuperHCPU),
319 .instance_init = superh_cpu_initfn,
320 .abstract = true,
321 .class_size = sizeof(SuperHCPUClass),
322 .class_init = superh_cpu_class_init,
325 static void superh_cpu_register_types(void)
327 type_register_static(&superh_cpu_type_info);
328 type_register_static(&sh7750r_type_info);
329 type_register_static(&sh7751r_type_info);
330 type_register_static(&sh7785_type_info);
333 type_init(superh_cpu_register_types)