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eepro100: Use PCI DMA stub functions
[qemu.git] / hw / pxa2xx.c
blobbfc28a999b147bb8ad4e762ef075687488efa37a
1 /*
2 * Intel XScale PXA255/270 processor support.
3 *
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Written by Andrzej Zaborowski <balrog@zabor.org>
6 *
7 * This code is licensed under the GPL.
8 */
9
10 #include "sysbus.h"
11 #include "pxa.h"
12 #include "sysemu.h"
13 #include "pc.h"
14 #include "i2c.h"
15 #include "ssi.h"
16 #include "qemu-char.h"
17 #include "blockdev.h"
18
19 static struct {
20 target_phys_addr_t io_base;
21 int irqn;
22 } pxa255_serial[] = {
23 { 0x40100000, PXA2XX_PIC_FFUART },
24 { 0x40200000, PXA2XX_PIC_BTUART },
25 { 0x40700000, PXA2XX_PIC_STUART },
26 { 0x41600000, PXA25X_PIC_HWUART },
27 { 0, 0 }
28 }, pxa270_serial[] = {
29 { 0x40100000, PXA2XX_PIC_FFUART },
30 { 0x40200000, PXA2XX_PIC_BTUART },
31 { 0x40700000, PXA2XX_PIC_STUART },
32 { 0, 0 }
33 };
34
35 typedef struct PXASSPDef {
36 target_phys_addr_t io_base;
37 int irqn;
38 } PXASSPDef;
39
40 #if 0
41 static PXASSPDef pxa250_ssp[] = {
42 { 0x41000000, PXA2XX_PIC_SSP },
43 { 0, 0 }
44 };
45 #endif
46
47 static PXASSPDef pxa255_ssp[] = {
48 { 0x41000000, PXA2XX_PIC_SSP },
49 { 0x41400000, PXA25X_PIC_NSSP },
50 { 0, 0 }
51 };
52
53 #if 0
54 static PXASSPDef pxa26x_ssp[] = {
55 { 0x41000000, PXA2XX_PIC_SSP },
56 { 0x41400000, PXA25X_PIC_NSSP },
57 { 0x41500000, PXA26X_PIC_ASSP },
58 { 0, 0 }
59 };
60 #endif
61
62 static PXASSPDef pxa27x_ssp[] = {
63 { 0x41000000, PXA2XX_PIC_SSP },
64 { 0x41700000, PXA27X_PIC_SSP2 },
65 { 0x41900000, PXA2XX_PIC_SSP3 },
66 { 0, 0 }
67 };
68
69 #define PMCR 0x00 /* Power Manager Control register */
70 #define PSSR 0x04 /* Power Manager Sleep Status register */
71 #define PSPR 0x08 /* Power Manager Scratch-Pad register */
72 #define PWER 0x0c /* Power Manager Wake-Up Enable register */
73 #define PRER 0x10 /* Power Manager Rising-Edge Detect Enable register */
74 #define PFER 0x14 /* Power Manager Falling-Edge Detect Enable register */
75 #define PEDR 0x18 /* Power Manager Edge-Detect Status register */
76 #define PCFR 0x1c /* Power Manager General Configuration register */
77 #define PGSR0 0x20 /* Power Manager GPIO Sleep-State register 0 */
78 #define PGSR1 0x24 /* Power Manager GPIO Sleep-State register 1 */
79 #define PGSR2 0x28 /* Power Manager GPIO Sleep-State register 2 */
80 #define PGSR3 0x2c /* Power Manager GPIO Sleep-State register 3 */
81 #define RCSR 0x30 /* Reset Controller Status register */
82 #define PSLR 0x34 /* Power Manager Sleep Configuration register */
83 #define PTSR 0x38 /* Power Manager Standby Configuration register */
84 #define PVCR 0x40 /* Power Manager Voltage Change Control register */
85 #define PUCR 0x4c /* Power Manager USIM Card Control/Status register */
86 #define PKWR 0x50 /* Power Manager Keyboard Wake-Up Enable register */
87 #define PKSR 0x54 /* Power Manager Keyboard Level-Detect Status */
88 #define PCMD0 0x80 /* Power Manager I2C Command register File 0 */
89 #define PCMD31 0xfc /* Power Manager I2C Command register File 31 */
90
91 static uint64_t pxa2xx_pm_read(void *opaque, target_phys_addr_t addr,
92 unsigned size)
93 {
94 PXA2xxState *s = (PXA2xxState *) opaque;
95
96 switch (addr) {
97 case PMCR ... PCMD31:
98 if (addr & 3)
99 goto fail;
100
101 return s->pm_regs[addr >> 2];
102 default:
103 fail:
104 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
105 break;
106 }
107 return 0;
108 }
109
110 static void pxa2xx_pm_write(void *opaque, target_phys_addr_t addr,
111 uint64_t value, unsigned size)
112 {
113 PXA2xxState *s = (PXA2xxState *) opaque;
114
115 switch (addr) {
116 case PMCR:
117 s->pm_regs[addr >> 2] &= 0x15 & ~(value & 0x2a);
118 s->pm_regs[addr >> 2] |= value & 0x15;
119 break;
120
121 case PSSR: /* Read-clean registers */
122 case RCSR:
123 case PKSR:
124 s->pm_regs[addr >> 2] &= ~value;
125 break;
126
127 default: /* Read-write registers */
128 if (!(addr & 3)) {
129 s->pm_regs[addr >> 2] = value;
130 break;
131 }
132
133 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
134 break;
135 }
136 }
137
138 static const MemoryRegionOps pxa2xx_pm_ops = {
139 .read = pxa2xx_pm_read,
140 .write = pxa2xx_pm_write,
141 .endianness = DEVICE_NATIVE_ENDIAN,
142 };
143
144 static const VMStateDescription vmstate_pxa2xx_pm = {
145 .name = "pxa2xx_pm",
146 .version_id = 0,
147 .minimum_version_id = 0,
148 .minimum_version_id_old = 0,
149 .fields = (VMStateField[]) {
150 VMSTATE_UINT32_ARRAY(pm_regs, PXA2xxState, 0x40),
151 VMSTATE_END_OF_LIST()
152 }
153 };
154
155 #define CCCR 0x00 /* Core Clock Configuration register */
156 #define CKEN 0x04 /* Clock Enable register */
157 #define OSCC 0x08 /* Oscillator Configuration register */
158 #define CCSR 0x0c /* Core Clock Status register */
159
160 static uint64_t pxa2xx_cm_read(void *opaque, target_phys_addr_t addr,
161 unsigned size)
162 {
163 PXA2xxState *s = (PXA2xxState *) opaque;
164
165 switch (addr) {
166 case CCCR:
167 case CKEN:
168 case OSCC:
169 return s->cm_regs[addr >> 2];
170
171 case CCSR:
172 return s->cm_regs[CCCR >> 2] | (3 << 28);
173
174 default:
175 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
176 break;
177 }
178 return 0;
179 }
180
181 static void pxa2xx_cm_write(void *opaque, target_phys_addr_t addr,
182 uint64_t value, unsigned size)
183 {
184 PXA2xxState *s = (PXA2xxState *) opaque;
185
186 switch (addr) {
187 case CCCR:
188 case CKEN:
189 s->cm_regs[addr >> 2] = value;
190 break;
191
192 case OSCC:
193 s->cm_regs[addr >> 2] &= ~0x6c;
194 s->cm_regs[addr >> 2] |= value & 0x6e;
195 if ((value >> 1) & 1) /* OON */
196 s->cm_regs[addr >> 2] |= 1 << 0; /* Oscillator is now stable */
197 break;
198
199 default:
200 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
201 break;
202 }
203 }
204
205 static const MemoryRegionOps pxa2xx_cm_ops = {
206 .read = pxa2xx_cm_read,
207 .write = pxa2xx_cm_write,
208 .endianness = DEVICE_NATIVE_ENDIAN,
209 };
210
211 static const VMStateDescription vmstate_pxa2xx_cm = {
212 .name = "pxa2xx_cm",
213 .version_id = 0,
214 .minimum_version_id = 0,
215 .minimum_version_id_old = 0,
216 .fields = (VMStateField[]) {
217 VMSTATE_UINT32_ARRAY(cm_regs, PXA2xxState, 4),
218 VMSTATE_UINT32(clkcfg, PXA2xxState),
219 VMSTATE_UINT32(pmnc, PXA2xxState),
220 VMSTATE_END_OF_LIST()
221 }
222 };
223
224 static uint32_t pxa2xx_clkpwr_read(void *opaque, int op2, int reg, int crm)
225 {
226 PXA2xxState *s = (PXA2xxState *) opaque;
227
228 switch (reg) {
229 case 6: /* Clock Configuration register */
230 return s->clkcfg;
231
232 case 7: /* Power Mode register */
233 return 0;
234
235 default:
236 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
237 break;
238 }
239 return 0;
240 }
241
242 static void pxa2xx_clkpwr_write(void *opaque, int op2, int reg, int crm,
243 uint32_t value)
244 {
245 PXA2xxState *s = (PXA2xxState *) opaque;
246 static const char *pwrmode[8] = {
247 "Normal", "Idle", "Deep-idle", "Standby",
248 "Sleep", "reserved (!)", "reserved (!)", "Deep-sleep",
249 };
250
251 switch (reg) {
252 case 6: /* Clock Configuration register */
253 s->clkcfg = value & 0xf;
254 if (value & 2)
255 printf("%s: CPU frequency change attempt\n", __FUNCTION__);
256 break;
257
258 case 7: /* Power Mode register */
259 if (value & 8)
260 printf("%s: CPU voltage change attempt\n", __FUNCTION__);
261 switch (value & 7) {
262 case 0:
263 /* Do nothing */
264 break;
265
266 case 1:
267 /* Idle */
268 if (!(s->cm_regs[CCCR >> 2] & (1 << 31))) { /* CPDIS */
269 cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
270 break;
271 }
272 /* Fall through. */
273
274 case 2:
275 /* Deep-Idle */
276 cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
277 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
278 goto message;
279
280 case 3:
281 s->env->uncached_cpsr =
282 ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
283 s->env->cp15.c1_sys = 0;
284 s->env->cp15.c1_coproc = 0;
285 s->env->cp15.c2_base0 = 0;
286 s->env->cp15.c3 = 0;
287 s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */
288 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
289
290 /*
291 * The scratch-pad register is almost universally used
292 * for storing the return address on suspend. For the
293 * lack of a resuming bootloader, perform a jump
294 * directly to that address.
295 */
296 memset(s->env->regs, 0, 4 * 15);
297 s->env->regs[15] = s->pm_regs[PSPR >> 2];
298
299 #if 0
300 buffer = 0xe59ff000; /* ldr pc, [pc, #0] */
301 cpu_physical_memory_write(0, &buffer, 4);
302 buffer = s->pm_regs[PSPR >> 2];
303 cpu_physical_memory_write(8, &buffer, 4);
304 #endif
305
306 /* Suspend */
307 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
308
309 goto message;
310
311 default:
312 message:
313 printf("%s: machine entered %s mode\n", __FUNCTION__,
314 pwrmode[value & 7]);
315 }
316 break;
317
318 default:
319 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
320 break;
321 }
322 }
323
324 /* Performace Monitoring Registers */
325 #define CPPMNC 0 /* Performance Monitor Control register */
326 #define CPCCNT 1 /* Clock Counter register */
327 #define CPINTEN 4 /* Interrupt Enable register */
328 #define CPFLAG 5 /* Overflow Flag register */
329 #define CPEVTSEL 8 /* Event Selection register */
330
331 #define CPPMN0 0 /* Performance Count register 0 */
332 #define CPPMN1 1 /* Performance Count register 1 */
333 #define CPPMN2 2 /* Performance Count register 2 */
334 #define CPPMN3 3 /* Performance Count register 3 */
335
336 static uint32_t pxa2xx_perf_read(void *opaque, int op2, int reg, int crm)
337 {
338 PXA2xxState *s = (PXA2xxState *) opaque;
339
340 switch (reg) {
341 case CPPMNC:
342 return s->pmnc;
343 case CPCCNT:
344 if (s->pmnc & 1)
345 return qemu_get_clock_ns(vm_clock);
346 else
347 return 0;
348 case CPINTEN:
349 case CPFLAG:
350 case CPEVTSEL:
351 return 0;
352
353 default:
354 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
355 break;
356 }
357 return 0;
358 }
359
360 static void pxa2xx_perf_write(void *opaque, int op2, int reg, int crm,
361 uint32_t value)
362 {
363 PXA2xxState *s = (PXA2xxState *) opaque;
364
365 switch (reg) {
366 case CPPMNC:
367 s->pmnc = value;
368 break;
369
370 case CPCCNT:
371 case CPINTEN:
372 case CPFLAG:
373 case CPEVTSEL:
374 break;
375
376 default:
377 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
378 break;
379 }
380 }
381
382 static uint32_t pxa2xx_cp14_read(void *opaque, int op2, int reg, int crm)
383 {
384 switch (crm) {
385 case 0:
386 return pxa2xx_clkpwr_read(opaque, op2, reg, crm);
387 case 1:
388 return pxa2xx_perf_read(opaque, op2, reg, crm);
389 case 2:
390 switch (reg) {
391 case CPPMN0:
392 case CPPMN1:
393 case CPPMN2:
394 case CPPMN3:
395 return 0;
396 }
397 /* Fall through */
398 default:
399 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
400 break;
401 }
402 return 0;
403 }
404
405 static void pxa2xx_cp14_write(void *opaque, int op2, int reg, int crm,
406 uint32_t value)
407 {
408 switch (crm) {
409 case 0:
410 pxa2xx_clkpwr_write(opaque, op2, reg, crm, value);
411 break;
412 case 1:
413 pxa2xx_perf_write(opaque, op2, reg, crm, value);
414 break;
415 case 2:
416 switch (reg) {
417 case CPPMN0:
418 case CPPMN1:
419 case CPPMN2:
420 case CPPMN3:
421 return;
422 }
423 /* Fall through */
424 default:
425 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
426 break;
427 }
428 }
429
430 #define MDCNFG 0x00 /* SDRAM Configuration register */
431 #define MDREFR 0x04 /* SDRAM Refresh Control register */
432 #define MSC0 0x08 /* Static Memory Control register 0 */
433 #define MSC1 0x0c /* Static Memory Control register 1 */
434 #define MSC2 0x10 /* Static Memory Control register 2 */
435 #define MECR 0x14 /* Expansion Memory Bus Config register */
436 #define SXCNFG 0x1c /* Synchronous Static Memory Config register */
437 #define MCMEM0 0x28 /* PC Card Memory Socket 0 Timing register */
438 #define MCMEM1 0x2c /* PC Card Memory Socket 1 Timing register */
439 #define MCATT0 0x30 /* PC Card Attribute Socket 0 register */
440 #define MCATT1 0x34 /* PC Card Attribute Socket 1 register */
441 #define MCIO0 0x38 /* PC Card I/O Socket 0 Timing register */
442 #define MCIO1 0x3c /* PC Card I/O Socket 1 Timing register */
443 #define MDMRS 0x40 /* SDRAM Mode Register Set Config register */
444 #define BOOT_DEF 0x44 /* Boot-time Default Configuration register */
445 #define ARB_CNTL 0x48 /* Arbiter Control register */
446 #define BSCNTR0 0x4c /* Memory Buffer Strength Control register 0 */
447 #define BSCNTR1 0x50 /* Memory Buffer Strength Control register 1 */
448 #define LCDBSCNTR 0x54 /* LCD Buffer Strength Control register */
449 #define MDMRSLP 0x58 /* Low Power SDRAM Mode Set Config register */
450 #define BSCNTR2 0x5c /* Memory Buffer Strength Control register 2 */
451 #define BSCNTR3 0x60 /* Memory Buffer Strength Control register 3 */
452 #define SA1110 0x64 /* SA-1110 Memory Compatibility register */
453
454 static uint64_t pxa2xx_mm_read(void *opaque, target_phys_addr_t addr,
455 unsigned size)
456 {
457 PXA2xxState *s = (PXA2xxState *) opaque;
458
459 switch (addr) {
460 case MDCNFG ... SA1110:
461 if ((addr & 3) == 0)
462 return s->mm_regs[addr >> 2];
463
464 default:
465 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
466 break;
467 }
468 return 0;
469 }
470
471 static void pxa2xx_mm_write(void *opaque, target_phys_addr_t addr,
472 uint64_t value, unsigned size)
473 {
474 PXA2xxState *s = (PXA2xxState *) opaque;
475
476 switch (addr) {
477 case MDCNFG ... SA1110:
478 if ((addr & 3) == 0) {
479 s->mm_regs[addr >> 2] = value;
480 break;
481 }
482
483 default:
484 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
485 break;
486 }
487 }
488
489 static const MemoryRegionOps pxa2xx_mm_ops = {
490 .read = pxa2xx_mm_read,
491 .write = pxa2xx_mm_write,
492 .endianness = DEVICE_NATIVE_ENDIAN,
493 };
494
495 static const VMStateDescription vmstate_pxa2xx_mm = {
496 .name = "pxa2xx_mm",
497 .version_id = 0,
498 .minimum_version_id = 0,
499 .minimum_version_id_old = 0,
500 .fields = (VMStateField[]) {
501 VMSTATE_UINT32_ARRAY(mm_regs, PXA2xxState, 0x1a),
502 VMSTATE_END_OF_LIST()
503 }
504 };
505
506 /* Synchronous Serial Ports */
507 typedef struct {
508 SysBusDevice busdev;
509 MemoryRegion iomem;
510 qemu_irq irq;
511 int enable;
512 SSIBus *bus;
513
514 uint32_t sscr[2];
515 uint32_t sspsp;
516 uint32_t ssto;
517 uint32_t ssitr;
518 uint32_t sssr;
519 uint8_t sstsa;
520 uint8_t ssrsa;
521 uint8_t ssacd;
522
523 uint32_t rx_fifo[16];
524 int rx_level;
525 int rx_start;
526 } PXA2xxSSPState;
527
528 #define SSCR0 0x00 /* SSP Control register 0 */
529 #define SSCR1 0x04 /* SSP Control register 1 */
530 #define SSSR 0x08 /* SSP Status register */
531 #define SSITR 0x0c /* SSP Interrupt Test register */
532 #define SSDR 0x10 /* SSP Data register */
533 #define SSTO 0x28 /* SSP Time-Out register */
534 #define SSPSP 0x2c /* SSP Programmable Serial Protocol register */
535 #define SSTSA 0x30 /* SSP TX Time Slot Active register */
536 #define SSRSA 0x34 /* SSP RX Time Slot Active register */
537 #define SSTSS 0x38 /* SSP Time Slot Status register */
538 #define SSACD 0x3c /* SSP Audio Clock Divider register */
539
540 /* Bitfields for above registers */
541 #define SSCR0_SPI(x) (((x) & 0x30) == 0x00)
542 #define SSCR0_SSP(x) (((x) & 0x30) == 0x10)
543 #define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20)
544 #define SSCR0_PSP(x) (((x) & 0x30) == 0x30)
545 #define SSCR0_SSE (1 << 7)
546 #define SSCR0_RIM (1 << 22)
547 #define SSCR0_TIM (1 << 23)
548 #define SSCR0_MOD (1 << 31)
549 #define SSCR0_DSS(x) (((((x) >> 16) & 0x10) | ((x) & 0xf)) + 1)
550 #define SSCR1_RIE (1 << 0)
551 #define SSCR1_TIE (1 << 1)
552 #define SSCR1_LBM (1 << 2)
553 #define SSCR1_MWDS (1 << 5)
554 #define SSCR1_TFT(x) ((((x) >> 6) & 0xf) + 1)
555 #define SSCR1_RFT(x) ((((x) >> 10) & 0xf) + 1)
556 #define SSCR1_EFWR (1 << 14)
557 #define SSCR1_PINTE (1 << 18)
558 #define SSCR1_TINTE (1 << 19)
559 #define SSCR1_RSRE (1 << 20)
560 #define SSCR1_TSRE (1 << 21)
561 #define SSCR1_EBCEI (1 << 29)
562 #define SSITR_INT (7 << 5)
563 #define SSSR_TNF (1 << 2)
564 #define SSSR_RNE (1 << 3)
565 #define SSSR_TFS (1 << 5)
566 #define SSSR_RFS (1 << 6)
567 #define SSSR_ROR (1 << 7)
568 #define SSSR_PINT (1 << 18)
569 #define SSSR_TINT (1 << 19)
570 #define SSSR_EOC (1 << 20)
571 #define SSSR_TUR (1 << 21)
572 #define SSSR_BCE (1 << 23)
573 #define SSSR_RW 0x00bc0080
574
575 static void pxa2xx_ssp_int_update(PXA2xxSSPState *s)
576 {
577 int level = 0;
578
579 level |= s->ssitr & SSITR_INT;
580 level |= (s->sssr & SSSR_BCE) && (s->sscr[1] & SSCR1_EBCEI);
581 level |= (s->sssr & SSSR_TUR) && !(s->sscr[0] & SSCR0_TIM);
582 level |= (s->sssr & SSSR_EOC) && (s->sssr & (SSSR_TINT | SSSR_PINT));
583 level |= (s->sssr & SSSR_TINT) && (s->sscr[1] & SSCR1_TINTE);
584 level |= (s->sssr & SSSR_PINT) && (s->sscr[1] & SSCR1_PINTE);
585 level |= (s->sssr & SSSR_ROR) && !(s->sscr[0] & SSCR0_RIM);
586 level |= (s->sssr & SSSR_RFS) && (s->sscr[1] & SSCR1_RIE);
587 level |= (s->sssr & SSSR_TFS) && (s->sscr[1] & SSCR1_TIE);
588 qemu_set_irq(s->irq, !!level);
589 }
590
591 static void pxa2xx_ssp_fifo_update(PXA2xxSSPState *s)
592 {
593 s->sssr &= ~(0xf << 12); /* Clear RFL */
594 s->sssr &= ~(0xf << 8); /* Clear TFL */
595 s->sssr &= ~SSSR_TFS;
596 s->sssr &= ~SSSR_TNF;
597 if (s->enable) {
598 s->sssr |= ((s->rx_level - 1) & 0xf) << 12;
599 if (s->rx_level >= SSCR1_RFT(s->sscr[1]))
600 s->sssr |= SSSR_RFS;
601 else
602 s->sssr &= ~SSSR_RFS;
603 if (s->rx_level)
604 s->sssr |= SSSR_RNE;
605 else
606 s->sssr &= ~SSSR_RNE;
607 /* TX FIFO is never filled, so it is always in underrun
608 condition if SSP is enabled */
609 s->sssr |= SSSR_TFS;
610 s->sssr |= SSSR_TNF;
611 }
612
613 pxa2xx_ssp_int_update(s);
614 }
615
616 static uint64_t pxa2xx_ssp_read(void *opaque, target_phys_addr_t addr,
617 unsigned size)
618 {
619 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
620 uint32_t retval;
621
622 switch (addr) {
623 case SSCR0:
624 return s->sscr[0];
625 case SSCR1:
626 return s->sscr[1];
627 case SSPSP:
628 return s->sspsp;
629 case SSTO:
630 return s->ssto;
631 case SSITR:
632 return s->ssitr;
633 case SSSR:
634 return s->sssr | s->ssitr;
635 case SSDR:
636 if (!s->enable)
637 return 0xffffffff;
638 if (s->rx_level < 1) {
639 printf("%s: SSP Rx Underrun\n", __FUNCTION__);
640 return 0xffffffff;
641 }
642 s->rx_level --;
643 retval = s->rx_fifo[s->rx_start ++];
644 s->rx_start &= 0xf;
645 pxa2xx_ssp_fifo_update(s);
646 return retval;
647 case SSTSA:
648 return s->sstsa;
649 case SSRSA:
650 return s->ssrsa;
651 case SSTSS:
652 return 0;
653 case SSACD:
654 return s->ssacd;
655 default:
656 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
657 break;
658 }
659 return 0;
660 }
661
662 static void pxa2xx_ssp_write(void *opaque, target_phys_addr_t addr,
663 uint64_t value64, unsigned size)
664 {
665 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
666 uint32_t value = value64;
667
668 switch (addr) {
669 case SSCR0:
670 s->sscr[0] = value & 0xc7ffffff;
671 s->enable = value & SSCR0_SSE;
672 if (value & SSCR0_MOD)
673 printf("%s: Attempt to use network mode\n", __FUNCTION__);
674 if (s->enable && SSCR0_DSS(value) < 4)
675 printf("%s: Wrong data size: %i bits\n", __FUNCTION__,
676 SSCR0_DSS(value));
677 if (!(value & SSCR0_SSE)) {
678 s->sssr = 0;
679 s->ssitr = 0;
680 s->rx_level = 0;
681 }
682 pxa2xx_ssp_fifo_update(s);
683 break;
684
685 case SSCR1:
686 s->sscr[1] = value;
687 if (value & (SSCR1_LBM | SSCR1_EFWR))
688 printf("%s: Attempt to use SSP test mode\n", __FUNCTION__);
689 pxa2xx_ssp_fifo_update(s);
690 break;
691
692 case SSPSP:
693 s->sspsp = value;
694 break;
695
696 case SSTO:
697 s->ssto = value;
698 break;
699
700 case SSITR:
701 s->ssitr = value & SSITR_INT;
702 pxa2xx_ssp_int_update(s);
703 break;
704
705 case SSSR:
706 s->sssr &= ~(value & SSSR_RW);
707 pxa2xx_ssp_int_update(s);
708 break;
709
710 case SSDR:
711 if (SSCR0_UWIRE(s->sscr[0])) {
712 if (s->sscr[1] & SSCR1_MWDS)
713 value &= 0xffff;
714 else
715 value &= 0xff;
716 } else
717 /* Note how 32bits overflow does no harm here */
718 value &= (1 << SSCR0_DSS(s->sscr[0])) - 1;
719
720 /* Data goes from here to the Tx FIFO and is shifted out from
721 * there directly to the slave, no need to buffer it.
722 */
723 if (s->enable) {
724 uint32_t readval;
725 readval = ssi_transfer(s->bus, value);
726 if (s->rx_level < 0x10) {
727 s->rx_fifo[(s->rx_start + s->rx_level ++) & 0xf] = readval;
728 } else {
729 s->sssr |= SSSR_ROR;
730 }
731 }
732 pxa2xx_ssp_fifo_update(s);
733 break;
734
735 case SSTSA:
736 s->sstsa = value;
737 break;
738
739 case SSRSA:
740 s->ssrsa = value;
741 break;
742
743 case SSACD:
744 s->ssacd = value;
745 break;
746
747 default:
748 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
749 break;
750 }
751 }
752
753 static const MemoryRegionOps pxa2xx_ssp_ops = {
754 .read = pxa2xx_ssp_read,
755 .write = pxa2xx_ssp_write,
756 .endianness = DEVICE_NATIVE_ENDIAN,
757 };
758
759 static void pxa2xx_ssp_save(QEMUFile *f, void *opaque)
760 {
761 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
762 int i;
763
764 qemu_put_be32(f, s->enable);
765
766 qemu_put_be32s(f, &s->sscr[0]);
767 qemu_put_be32s(f, &s->sscr[1]);
768 qemu_put_be32s(f, &s->sspsp);
769 qemu_put_be32s(f, &s->ssto);
770 qemu_put_be32s(f, &s->ssitr);
771 qemu_put_be32s(f, &s->sssr);
772 qemu_put_8s(f, &s->sstsa);
773 qemu_put_8s(f, &s->ssrsa);
774 qemu_put_8s(f, &s->ssacd);
775
776 qemu_put_byte(f, s->rx_level);
777 for (i = 0; i < s->rx_level; i ++)
778 qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 0xf]);
779 }
780
781 static int pxa2xx_ssp_load(QEMUFile *f, void *opaque, int version_id)
782 {
783 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
784 int i;
785
786 s->enable = qemu_get_be32(f);
787
788 qemu_get_be32s(f, &s->sscr[0]);
789 qemu_get_be32s(f, &s->sscr[1]);
790 qemu_get_be32s(f, &s->sspsp);
791 qemu_get_be32s(f, &s->ssto);
792 qemu_get_be32s(f, &s->ssitr);
793 qemu_get_be32s(f, &s->sssr);
794 qemu_get_8s(f, &s->sstsa);
795 qemu_get_8s(f, &s->ssrsa);
796 qemu_get_8s(f, &s->ssacd);
797
798 s->rx_level = qemu_get_byte(f);
799 s->rx_start = 0;
800 for (i = 0; i < s->rx_level; i ++)
801 s->rx_fifo[i] = qemu_get_byte(f);
802
803 return 0;
804 }
805
806 static int pxa2xx_ssp_init(SysBusDevice *dev)
807 {
808 PXA2xxSSPState *s = FROM_SYSBUS(PXA2xxSSPState, dev);
809
810 sysbus_init_irq(dev, &s->irq);
811
812 memory_region_init_io(&s->iomem, &pxa2xx_ssp_ops, s, "pxa2xx-ssp", 0x1000);
813 sysbus_init_mmio_region(dev, &s->iomem);
814 register_savevm(&dev->qdev, "pxa2xx_ssp", -1, 0,
815 pxa2xx_ssp_save, pxa2xx_ssp_load, s);
816
817 s->bus = ssi_create_bus(&dev->qdev, "ssi");
818 return 0;
819 }
820
821 /* Real-Time Clock */
822 #define RCNR 0x00 /* RTC Counter register */
823 #define RTAR 0x04 /* RTC Alarm register */
824 #define RTSR 0x08 /* RTC Status register */
825 #define RTTR 0x0c /* RTC Timer Trim register */
826 #define RDCR 0x10 /* RTC Day Counter register */
827 #define RYCR 0x14 /* RTC Year Counter register */
828 #define RDAR1 0x18 /* RTC Wristwatch Day Alarm register 1 */
829 #define RYAR1 0x1c /* RTC Wristwatch Year Alarm register 1 */
830 #define RDAR2 0x20 /* RTC Wristwatch Day Alarm register 2 */
831 #define RYAR2 0x24 /* RTC Wristwatch Year Alarm register 2 */
832 #define SWCR 0x28 /* RTC Stopwatch Counter register */
833 #define SWAR1 0x2c /* RTC Stopwatch Alarm register 1 */
834 #define SWAR2 0x30 /* RTC Stopwatch Alarm register 2 */
835 #define RTCPICR 0x34 /* RTC Periodic Interrupt Counter register */
836 #define PIAR 0x38 /* RTC Periodic Interrupt Alarm register */
837
838 typedef struct {
839 SysBusDevice busdev;
840 MemoryRegion iomem;
841 uint32_t rttr;
842 uint32_t rtsr;
843 uint32_t rtar;
844 uint32_t rdar1;
845 uint32_t rdar2;
846 uint32_t ryar1;
847 uint32_t ryar2;
848 uint32_t swar1;
849 uint32_t swar2;
850 uint32_t piar;
851 uint32_t last_rcnr;
852 uint32_t last_rdcr;
853 uint32_t last_rycr;
854 uint32_t last_swcr;
855 uint32_t last_rtcpicr;
856 int64_t last_hz;
857 int64_t last_sw;
858 int64_t last_pi;
859 QEMUTimer *rtc_hz;
860 QEMUTimer *rtc_rdal1;
861 QEMUTimer *rtc_rdal2;
862 QEMUTimer *rtc_swal1;
863 QEMUTimer *rtc_swal2;
864 QEMUTimer *rtc_pi;
865 qemu_irq rtc_irq;
866 } PXA2xxRTCState;
867
868 static inline void pxa2xx_rtc_int_update(PXA2xxRTCState *s)
869 {
870 qemu_set_irq(s->rtc_irq, !!(s->rtsr & 0x2553));
871 }
872
873 static void pxa2xx_rtc_hzupdate(PXA2xxRTCState *s)
874 {
875 int64_t rt = qemu_get_clock_ms(rt_clock);
876 s->last_rcnr += ((rt - s->last_hz) << 15) /
877 (1000 * ((s->rttr & 0xffff) + 1));
878 s->last_rdcr += ((rt - s->last_hz) << 15) /
879 (1000 * ((s->rttr & 0xffff) + 1));
880 s->last_hz = rt;
881 }
882
883 static void pxa2xx_rtc_swupdate(PXA2xxRTCState *s)
884 {
885 int64_t rt = qemu_get_clock_ms(rt_clock);
886 if (s->rtsr & (1 << 12))
887 s->last_swcr += (rt - s->last_sw) / 10;
888 s->last_sw = rt;
889 }
890
891 static void pxa2xx_rtc_piupdate(PXA2xxRTCState *s)
892 {
893 int64_t rt = qemu_get_clock_ms(rt_clock);
894 if (s->rtsr & (1 << 15))
895 s->last_swcr += rt - s->last_pi;
896 s->last_pi = rt;
897 }
898
899 static inline void pxa2xx_rtc_alarm_update(PXA2xxRTCState *s,
900 uint32_t rtsr)
901 {
902 if ((rtsr & (1 << 2)) && !(rtsr & (1 << 0)))
903 qemu_mod_timer(s->rtc_hz, s->last_hz +
904 (((s->rtar - s->last_rcnr) * 1000 *
905 ((s->rttr & 0xffff) + 1)) >> 15));
906 else
907 qemu_del_timer(s->rtc_hz);
908
909 if ((rtsr & (1 << 5)) && !(rtsr & (1 << 4)))
910 qemu_mod_timer(s->rtc_rdal1, s->last_hz +
911 (((s->rdar1 - s->last_rdcr) * 1000 *
912 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */
913 else
914 qemu_del_timer(s->rtc_rdal1);
915
916 if ((rtsr & (1 << 7)) && !(rtsr & (1 << 6)))
917 qemu_mod_timer(s->rtc_rdal2, s->last_hz +
918 (((s->rdar2 - s->last_rdcr) * 1000 *
919 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */
920 else
921 qemu_del_timer(s->rtc_rdal2);
922
923 if ((rtsr & 0x1200) == 0x1200 && !(rtsr & (1 << 8)))
924 qemu_mod_timer(s->rtc_swal1, s->last_sw +
925 (s->swar1 - s->last_swcr) * 10); /* TODO: fixup */
926 else
927 qemu_del_timer(s->rtc_swal1);
928
929 if ((rtsr & 0x1800) == 0x1800 && !(rtsr & (1 << 10)))
930 qemu_mod_timer(s->rtc_swal2, s->last_sw +
931 (s->swar2 - s->last_swcr) * 10); /* TODO: fixup */
932 else
933 qemu_del_timer(s->rtc_swal2);
934
935 if ((rtsr & 0xc000) == 0xc000 && !(rtsr & (1 << 13)))
936 qemu_mod_timer(s->rtc_pi, s->last_pi +
937 (s->piar & 0xffff) - s->last_rtcpicr);
938 else
939 qemu_del_timer(s->rtc_pi);
940 }
941
942 static inline void pxa2xx_rtc_hz_tick(void *opaque)
943 {
944 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
945 s->rtsr |= (1 << 0);
946 pxa2xx_rtc_alarm_update(s, s->rtsr);
947 pxa2xx_rtc_int_update(s);
948 }
949
950 static inline void pxa2xx_rtc_rdal1_tick(void *opaque)
951 {
952 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
953 s->rtsr |= (1 << 4);
954 pxa2xx_rtc_alarm_update(s, s->rtsr);
955 pxa2xx_rtc_int_update(s);
956 }
957
958 static inline void pxa2xx_rtc_rdal2_tick(void *opaque)
959 {
960 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
961 s->rtsr |= (1 << 6);
962 pxa2xx_rtc_alarm_update(s, s->rtsr);
963 pxa2xx_rtc_int_update(s);
964 }
965
966 static inline void pxa2xx_rtc_swal1_tick(void *opaque)
967 {
968 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
969 s->rtsr |= (1 << 8);
970 pxa2xx_rtc_alarm_update(s, s->rtsr);
971 pxa2xx_rtc_int_update(s);
972 }
973
974 static inline void pxa2xx_rtc_swal2_tick(void *opaque)
975 {
976 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
977 s->rtsr |= (1 << 10);
978 pxa2xx_rtc_alarm_update(s, s->rtsr);
979 pxa2xx_rtc_int_update(s);
980 }
981
982 static inline void pxa2xx_rtc_pi_tick(void *opaque)
983 {
984 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
985 s->rtsr |= (1 << 13);
986 pxa2xx_rtc_piupdate(s);
987 s->last_rtcpicr = 0;
988 pxa2xx_rtc_alarm_update(s, s->rtsr);
989 pxa2xx_rtc_int_update(s);
990 }
991
992 static uint64_t pxa2xx_rtc_read(void *opaque, target_phys_addr_t addr,
993 unsigned size)
994 {
995 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
996
997 switch (addr) {
998 case RTTR:
999 return s->rttr;
1000 case RTSR:
1001 return s->rtsr;
1002 case RTAR:
1003 return s->rtar;
1004 case RDAR1:
1005 return s->rdar1;
1006 case RDAR2:
1007 return s->rdar2;
1008 case RYAR1:
1009 return s->ryar1;
1010 case RYAR2:
1011 return s->ryar2;
1012 case SWAR1:
1013 return s->swar1;
1014 case SWAR2:
1015 return s->swar2;
1016 case PIAR:
1017 return s->piar;
1018 case RCNR:
1019 return s->last_rcnr + ((qemu_get_clock_ms(rt_clock) - s->last_hz) << 15) /
1020 (1000 * ((s->rttr & 0xffff) + 1));
1021 case RDCR:
1022 return s->last_rdcr + ((qemu_get_clock_ms(rt_clock) - s->last_hz) << 15) /
1023 (1000 * ((s->rttr & 0xffff) + 1));
1024 case RYCR:
1025 return s->last_rycr;
1026 case SWCR:
1027 if (s->rtsr & (1 << 12))
1028 return s->last_swcr + (qemu_get_clock_ms(rt_clock) - s->last_sw) / 10;
1029 else
1030 return s->last_swcr;
1031 default:
1032 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1033 break;
1034 }
1035 return 0;
1036 }
1037
1038 static void pxa2xx_rtc_write(void *opaque, target_phys_addr_t addr,
1039 uint64_t value64, unsigned size)
1040 {
1041 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
1042 uint32_t value = value64;
1043
1044 switch (addr) {
1045 case RTTR:
1046 if (!(s->rttr & (1 << 31))) {
1047 pxa2xx_rtc_hzupdate(s);
1048 s->rttr = value;
1049 pxa2xx_rtc_alarm_update(s, s->rtsr);
1050 }
1051 break;
1052
1053 case RTSR:
1054 if ((s->rtsr ^ value) & (1 << 15))
1055 pxa2xx_rtc_piupdate(s);
1056
1057 if ((s->rtsr ^ value) & (1 << 12))
1058 pxa2xx_rtc_swupdate(s);
1059
1060 if (((s->rtsr ^ value) & 0x4aac) | (value & ~0xdaac))
1061 pxa2xx_rtc_alarm_update(s, value);
1062
1063 s->rtsr = (value & 0xdaac) | (s->rtsr & ~(value & ~0xdaac));
1064 pxa2xx_rtc_int_update(s);
1065 break;
1066
1067 case RTAR:
1068 s->rtar = value;
1069 pxa2xx_rtc_alarm_update(s, s->rtsr);
1070 break;
1071
1072 case RDAR1:
1073 s->rdar1 = value;
1074 pxa2xx_rtc_alarm_update(s, s->rtsr);
1075 break;
1076
1077 case RDAR2:
1078 s->rdar2 = value;
1079 pxa2xx_rtc_alarm_update(s, s->rtsr);
1080 break;
1081
1082 case RYAR1:
1083 s->ryar1 = value;
1084 pxa2xx_rtc_alarm_update(s, s->rtsr);
1085 break;
1086
1087 case RYAR2:
1088 s->ryar2 = value;
1089 pxa2xx_rtc_alarm_update(s, s->rtsr);
1090 break;
1091
1092 case SWAR1:
1093 pxa2xx_rtc_swupdate(s);
1094 s->swar1 = value;
1095 s->last_swcr = 0;
1096 pxa2xx_rtc_alarm_update(s, s->rtsr);
1097 break;
1098
1099 case SWAR2:
1100 s->swar2 = value;
1101 pxa2xx_rtc_alarm_update(s, s->rtsr);
1102 break;
1103
1104 case PIAR:
1105 s->piar = value;
1106 pxa2xx_rtc_alarm_update(s, s->rtsr);
1107 break;
1108
1109 case RCNR:
1110 pxa2xx_rtc_hzupdate(s);
1111 s->last_rcnr = value;
1112 pxa2xx_rtc_alarm_update(s, s->rtsr);
1113 break;
1114
1115 case RDCR:
1116 pxa2xx_rtc_hzupdate(s);
1117 s->last_rdcr = value;
1118 pxa2xx_rtc_alarm_update(s, s->rtsr);
1119 break;
1120
1121 case RYCR:
1122 s->last_rycr = value;
1123 break;
1124
1125 case SWCR:
1126 pxa2xx_rtc_swupdate(s);
1127 s->last_swcr = value;
1128 pxa2xx_rtc_alarm_update(s, s->rtsr);
1129 break;
1130
1131 case RTCPICR:
1132 pxa2xx_rtc_piupdate(s);
1133 s->last_rtcpicr = value & 0xffff;
1134 pxa2xx_rtc_alarm_update(s, s->rtsr);
1135 break;
1136
1137 default:
1138 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1139 }
1140 }
1141
1142 static const MemoryRegionOps pxa2xx_rtc_ops = {
1143 .read = pxa2xx_rtc_read,
1144 .write = pxa2xx_rtc_write,
1145 .endianness = DEVICE_NATIVE_ENDIAN,
1146 };
1147
1148 static int pxa2xx_rtc_init(SysBusDevice *dev)
1149 {
1150 PXA2xxRTCState *s = FROM_SYSBUS(PXA2xxRTCState, dev);
1151 struct tm tm;
1152 int wom;
1153
1154 s->rttr = 0x7fff;
1155 s->rtsr = 0;
1156
1157 qemu_get_timedate(&tm, 0);
1158 wom = ((tm.tm_mday - 1) / 7) + 1;
1159
1160 s->last_rcnr = (uint32_t) mktimegm(&tm);
1161 s->last_rdcr = (wom << 20) | ((tm.tm_wday + 1) << 17) |
1162 (tm.tm_hour << 12) | (tm.tm_min << 6) | tm.tm_sec;
1163 s->last_rycr = ((tm.tm_year + 1900) << 9) |
1164 ((tm.tm_mon + 1) << 5) | tm.tm_mday;
1165 s->last_swcr = (tm.tm_hour << 19) |
1166 (tm.tm_min << 13) | (tm.tm_sec << 7);
1167 s->last_rtcpicr = 0;
1168 s->last_hz = s->last_sw = s->last_pi = qemu_get_clock_ms(rt_clock);
1169
1170 s->rtc_hz = qemu_new_timer_ms(rt_clock, pxa2xx_rtc_hz_tick, s);
1171 s->rtc_rdal1 = qemu_new_timer_ms(rt_clock, pxa2xx_rtc_rdal1_tick, s);
1172 s->rtc_rdal2 = qemu_new_timer_ms(rt_clock, pxa2xx_rtc_rdal2_tick, s);
1173 s->rtc_swal1 = qemu_new_timer_ms(rt_clock, pxa2xx_rtc_swal1_tick, s);
1174 s->rtc_swal2 = qemu_new_timer_ms(rt_clock, pxa2xx_rtc_swal2_tick, s);
1175 s->rtc_pi = qemu_new_timer_ms(rt_clock, pxa2xx_rtc_pi_tick, s);
1176
1177 sysbus_init_irq(dev, &s->rtc_irq);
1178
1179 memory_region_init_io(&s->iomem, &pxa2xx_rtc_ops, s, "pxa2xx-rtc", 0x10000);
1180 sysbus_init_mmio_region(dev, &s->iomem);
1181
1182 return 0;
1183 }
1184
1185 static void pxa2xx_rtc_pre_save(void *opaque)
1186 {
1187 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
1188
1189 pxa2xx_rtc_hzupdate(s);
1190 pxa2xx_rtc_piupdate(s);
1191 pxa2xx_rtc_swupdate(s);
1192 }
1193
1194 static int pxa2xx_rtc_post_load(void *opaque, int version_id)
1195 {
1196 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
1197
1198 pxa2xx_rtc_alarm_update(s, s->rtsr);
1199
1200 return 0;
1201 }
1202
1203 static const VMStateDescription vmstate_pxa2xx_rtc_regs = {
1204 .name = "pxa2xx_rtc",
1205 .version_id = 0,
1206 .minimum_version_id = 0,
1207 .minimum_version_id_old = 0,
1208 .pre_save = pxa2xx_rtc_pre_save,
1209 .post_load = pxa2xx_rtc_post_load,
1210 .fields = (VMStateField[]) {
1211 VMSTATE_UINT32(rttr, PXA2xxRTCState),
1212 VMSTATE_UINT32(rtsr, PXA2xxRTCState),
1213 VMSTATE_UINT32(rtar, PXA2xxRTCState),
1214 VMSTATE_UINT32(rdar1, PXA2xxRTCState),
1215 VMSTATE_UINT32(rdar2, PXA2xxRTCState),
1216 VMSTATE_UINT32(ryar1, PXA2xxRTCState),
1217 VMSTATE_UINT32(ryar2, PXA2xxRTCState),
1218 VMSTATE_UINT32(swar1, PXA2xxRTCState),
1219 VMSTATE_UINT32(swar2, PXA2xxRTCState),
1220 VMSTATE_UINT32(piar, PXA2xxRTCState),
1221 VMSTATE_UINT32(last_rcnr, PXA2xxRTCState),
1222 VMSTATE_UINT32(last_rdcr, PXA2xxRTCState),
1223 VMSTATE_UINT32(last_rycr, PXA2xxRTCState),
1224 VMSTATE_UINT32(last_swcr, PXA2xxRTCState),
1225 VMSTATE_UINT32(last_rtcpicr, PXA2xxRTCState),
1226 VMSTATE_INT64(last_hz, PXA2xxRTCState),
1227 VMSTATE_INT64(last_sw, PXA2xxRTCState),
1228 VMSTATE_INT64(last_pi, PXA2xxRTCState),
1229 VMSTATE_END_OF_LIST(),
1230 },
1231 };
1232
1233 static SysBusDeviceInfo pxa2xx_rtc_sysbus_info = {
1234 .init = pxa2xx_rtc_init,
1235 .qdev.name = "pxa2xx_rtc",
1236 .qdev.desc = "PXA2xx RTC Controller",
1237 .qdev.size = sizeof(PXA2xxRTCState),
1238 .qdev.vmsd = &vmstate_pxa2xx_rtc_regs,
1239 };
1240
1241 /* I2C Interface */
1242 typedef struct {
1243 i2c_slave i2c;
1244 PXA2xxI2CState *host;
1245 } PXA2xxI2CSlaveState;
1246
1247 struct PXA2xxI2CState {
1248 SysBusDevice busdev;
1249 MemoryRegion iomem;
1250 PXA2xxI2CSlaveState *slave;
1251 i2c_bus *bus;
1252 qemu_irq irq;
1253 uint32_t offset;
1254 uint32_t region_size;
1255
1256 uint16_t control;
1257 uint16_t status;
1258 uint8_t ibmr;
1259 uint8_t data;
1260 };
1261
1262 #define IBMR 0x80 /* I2C Bus Monitor register */
1263 #define IDBR 0x88 /* I2C Data Buffer register */
1264 #define ICR 0x90 /* I2C Control register */
1265 #define ISR 0x98 /* I2C Status register */
1266 #define ISAR 0xa0 /* I2C Slave Address register */
1267
1268 static void pxa2xx_i2c_update(PXA2xxI2CState *s)
1269 {
1270 uint16_t level = 0;
1271 level |= s->status & s->control & (1 << 10); /* BED */
1272 level |= (s->status & (1 << 7)) && (s->control & (1 << 9)); /* IRF */
1273 level |= (s->status & (1 << 6)) && (s->control & (1 << 8)); /* ITE */
1274 level |= s->status & (1 << 9); /* SAD */
1275 qemu_set_irq(s->irq, !!level);
1276 }
1277
1278 /* These are only stubs now. */
1279 static void pxa2xx_i2c_event(i2c_slave *i2c, enum i2c_event event)
1280 {
1281 PXA2xxI2CSlaveState *slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, i2c);
1282 PXA2xxI2CState *s = slave->host;
1283
1284 switch (event) {
1285 case I2C_START_SEND:
1286 s->status |= (1 << 9); /* set SAD */
1287 s->status &= ~(1 << 0); /* clear RWM */
1288 break;
1289 case I2C_START_RECV:
1290 s->status |= (1 << 9); /* set SAD */
1291 s->status |= 1 << 0; /* set RWM */
1292 break;
1293 case I2C_FINISH:
1294 s->status |= (1 << 4); /* set SSD */
1295 break;
1296 case I2C_NACK:
1297 s->status |= 1 << 1; /* set ACKNAK */
1298 break;
1299 }
1300 pxa2xx_i2c_update(s);
1301 }
1302
1303 static int pxa2xx_i2c_rx(i2c_slave *i2c)
1304 {
1305 PXA2xxI2CSlaveState *slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, i2c);
1306 PXA2xxI2CState *s = slave->host;
1307 if ((s->control & (1 << 14)) || !(s->control & (1 << 6)))
1308 return 0;
1309
1310 if (s->status & (1 << 0)) { /* RWM */
1311 s->status |= 1 << 6; /* set ITE */
1312 }
1313 pxa2xx_i2c_update(s);
1314
1315 return s->data;
1316 }
1317
1318 static int pxa2xx_i2c_tx(i2c_slave *i2c, uint8_t data)
1319 {
1320 PXA2xxI2CSlaveState *slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, i2c);
1321 PXA2xxI2CState *s = slave->host;
1322 if ((s->control & (1 << 14)) || !(s->control & (1 << 6)))
1323 return 1;
1324
1325 if (!(s->status & (1 << 0))) { /* RWM */
1326 s->status |= 1 << 7; /* set IRF */
1327 s->data = data;
1328 }
1329 pxa2xx_i2c_update(s);
1330
1331 return 1;
1332 }
1333
1334 static uint64_t pxa2xx_i2c_read(void *opaque, target_phys_addr_t addr,
1335 unsigned size)
1336 {
1337 PXA2xxI2CState *s = (PXA2xxI2CState *) opaque;
1338
1339 addr -= s->offset;
1340 switch (addr) {
1341 case ICR:
1342 return s->control;
1343 case ISR:
1344 return s->status | (i2c_bus_busy(s->bus) << 2);
1345 case ISAR:
1346 return s->slave->i2c.address;
1347 case IDBR:
1348 return s->data;
1349 case IBMR:
1350 if (s->status & (1 << 2))
1351 s->ibmr ^= 3; /* Fake SCL and SDA pin changes */
1352 else
1353 s->ibmr = 0;
1354 return s->ibmr;
1355 default:
1356 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1357 break;
1358 }
1359 return 0;
1360 }
1361
1362 static void pxa2xx_i2c_write(void *opaque, target_phys_addr_t addr,
1363 uint64_t value64, unsigned size)
1364 {
1365 PXA2xxI2CState *s = (PXA2xxI2CState *) opaque;
1366 uint32_t value = value64;
1367 int ack;
1368
1369 addr -= s->offset;
1370 switch (addr) {
1371 case ICR:
1372 s->control = value & 0xfff7;
1373 if ((value & (1 << 3)) && (value & (1 << 6))) { /* TB and IUE */
1374 /* TODO: slave mode */
1375 if (value & (1 << 0)) { /* START condition */
1376 if (s->data & 1)
1377 s->status |= 1 << 0; /* set RWM */
1378 else
1379 s->status &= ~(1 << 0); /* clear RWM */
1380 ack = !i2c_start_transfer(s->bus, s->data >> 1, s->data & 1);
1381 } else {
1382 if (s->status & (1 << 0)) { /* RWM */
1383 s->data = i2c_recv(s->bus);
1384 if (value & (1 << 2)) /* ACKNAK */
1385 i2c_nack(s->bus);
1386 ack = 1;
1387 } else
1388 ack = !i2c_send(s->bus, s->data);
1389 }
1390
1391 if (value & (1 << 1)) /* STOP condition */
1392 i2c_end_transfer(s->bus);
1393
1394 if (ack) {
1395 if (value & (1 << 0)) /* START condition */
1396 s->status |= 1 << 6; /* set ITE */
1397 else
1398 if (s->status & (1 << 0)) /* RWM */
1399 s->status |= 1 << 7; /* set IRF */
1400 else
1401 s->status |= 1 << 6; /* set ITE */
1402 s->status &= ~(1 << 1); /* clear ACKNAK */
1403 } else {
1404 s->status |= 1 << 6; /* set ITE */
1405 s->status |= 1 << 10; /* set BED */
1406 s->status |= 1 << 1; /* set ACKNAK */
1407 }
1408 }
1409 if (!(value & (1 << 3)) && (value & (1 << 6))) /* !TB and IUE */
1410 if (value & (1 << 4)) /* MA */
1411 i2c_end_transfer(s->bus);
1412 pxa2xx_i2c_update(s);
1413 break;
1414
1415 case ISR:
1416 s->status &= ~(value & 0x07f0);
1417 pxa2xx_i2c_update(s);
1418 break;
1419
1420 case ISAR:
1421 i2c_set_slave_address(&s->slave->i2c, value & 0x7f);
1422 break;
1423
1424 case IDBR:
1425 s->data = value & 0xff;
1426 break;
1427
1428 default:
1429 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1430 }
1431 }
1432
1433 static const MemoryRegionOps pxa2xx_i2c_ops = {
1434 .read = pxa2xx_i2c_read,
1435 .write = pxa2xx_i2c_write,
1436 .endianness = DEVICE_NATIVE_ENDIAN,
1437 };
1438
1439 static const VMStateDescription vmstate_pxa2xx_i2c_slave = {
1440 .name = "pxa2xx_i2c_slave",
1441 .version_id = 1,
1442 .minimum_version_id = 1,
1443 .minimum_version_id_old = 1,
1444 .fields = (VMStateField []) {
1445 VMSTATE_I2C_SLAVE(i2c, PXA2xxI2CSlaveState),
1446 VMSTATE_END_OF_LIST()
1447 }
1448 };
1449
1450 static const VMStateDescription vmstate_pxa2xx_i2c = {
1451 .name = "pxa2xx_i2c",
1452 .version_id = 1,
1453 .minimum_version_id = 1,
1454 .minimum_version_id_old = 1,
1455 .fields = (VMStateField []) {
1456 VMSTATE_UINT16(control, PXA2xxI2CState),
1457 VMSTATE_UINT16(status, PXA2xxI2CState),
1458 VMSTATE_UINT8(ibmr, PXA2xxI2CState),
1459 VMSTATE_UINT8(data, PXA2xxI2CState),
1460 VMSTATE_STRUCT_POINTER(slave, PXA2xxI2CState,
1461 vmstate_pxa2xx_i2c_slave, PXA2xxI2CSlaveState *),
1462 VMSTATE_END_OF_LIST()
1463 }
1464 };
1465
1466 static int pxa2xx_i2c_slave_init(i2c_slave *i2c)
1467 {
1468 /* Nothing to do. */
1469 return 0;
1470 }
1471
1472 static I2CSlaveInfo pxa2xx_i2c_slave_info = {
1473 .qdev.name = "pxa2xx-i2c-slave",
1474 .qdev.size = sizeof(PXA2xxI2CSlaveState),
1475 .init = pxa2xx_i2c_slave_init,
1476 .event = pxa2xx_i2c_event,
1477 .recv = pxa2xx_i2c_rx,
1478 .send = pxa2xx_i2c_tx
1479 };
1480
1481 PXA2xxI2CState *pxa2xx_i2c_init(target_phys_addr_t base,
1482 qemu_irq irq, uint32_t region_size)
1483 {
1484 DeviceState *dev;
1485 SysBusDevice *i2c_dev;
1486 PXA2xxI2CState *s;
1487
1488 i2c_dev = sysbus_from_qdev(qdev_create(NULL, "pxa2xx_i2c"));
1489 qdev_prop_set_uint32(&i2c_dev->qdev, "size", region_size + 1);
1490 qdev_prop_set_uint32(&i2c_dev->qdev, "offset",
1491 base - (base & (~region_size) & TARGET_PAGE_MASK));
1492
1493 qdev_init_nofail(&i2c_dev->qdev);
1494
1495 sysbus_mmio_map(i2c_dev, 0, base & ~region_size);
1496 sysbus_connect_irq(i2c_dev, 0, irq);
1497
1498 s = FROM_SYSBUS(PXA2xxI2CState, i2c_dev);
1499 /* FIXME: Should the slave device really be on a separate bus? */
1500 dev = i2c_create_slave(i2c_init_bus(NULL, "dummy"), "pxa2xx-i2c-slave", 0);
1501 s->slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, I2C_SLAVE_FROM_QDEV(dev));
1502 s->slave->host = s;
1503
1504 return s;
1505 }
1506
1507 static int pxa2xx_i2c_initfn(SysBusDevice *dev)
1508 {
1509 PXA2xxI2CState *s = FROM_SYSBUS(PXA2xxI2CState, dev);
1510
1511 s->bus = i2c_init_bus(&dev->qdev, "i2c");
1512
1513 memory_region_init_io(&s->iomem, &pxa2xx_i2c_ops, s,
1514 "pxa2xx-i2x", s->region_size);
1515 sysbus_init_mmio_region(dev, &s->iomem);
1516 sysbus_init_irq(dev, &s->irq);
1517
1518 return 0;
1519 }
1520
1521 i2c_bus *pxa2xx_i2c_bus(PXA2xxI2CState *s)
1522 {
1523 return s->bus;
1524 }
1525
1526 static SysBusDeviceInfo pxa2xx_i2c_info = {
1527 .init = pxa2xx_i2c_initfn,
1528 .qdev.name = "pxa2xx_i2c",
1529 .qdev.desc = "PXA2xx I2C Bus Controller",
1530 .qdev.size = sizeof(PXA2xxI2CState),
1531 .qdev.vmsd = &vmstate_pxa2xx_i2c,
1532 .qdev.props = (Property[]) {
1533 DEFINE_PROP_UINT32("size", PXA2xxI2CState, region_size, 0x10000),
1534 DEFINE_PROP_UINT32("offset", PXA2xxI2CState, offset, 0),
1535 DEFINE_PROP_END_OF_LIST(),
1536 },
1537 };
1538
1539 /* PXA Inter-IC Sound Controller */
1540 static void pxa2xx_i2s_reset(PXA2xxI2SState *i2s)
1541 {
1542 i2s->rx_len = 0;
1543 i2s->tx_len = 0;
1544 i2s->fifo_len = 0;
1545 i2s->clk = 0x1a;
1546 i2s->control[0] = 0x00;
1547 i2s->control[1] = 0x00;
1548 i2s->status = 0x00;
1549 i2s->mask = 0x00;
1550 }
1551
1552 #define SACR_TFTH(val) ((val >> 8) & 0xf)
1553 #define SACR_RFTH(val) ((val >> 12) & 0xf)
1554 #define SACR_DREC(val) (val & (1 << 3))
1555 #define SACR_DPRL(val) (val & (1 << 4))
1556
1557 static inline void pxa2xx_i2s_update(PXA2xxI2SState *i2s)
1558 {
1559 int rfs, tfs;
1560 rfs = SACR_RFTH(i2s->control[0]) < i2s->rx_len &&
1561 !SACR_DREC(i2s->control[1]);
1562 tfs = (i2s->tx_len || i2s->fifo_len < SACR_TFTH(i2s->control[0])) &&
1563 i2s->enable && !SACR_DPRL(i2s->control[1]);
1564
1565 qemu_set_irq(i2s->rx_dma, rfs);
1566 qemu_set_irq(i2s->tx_dma, tfs);
1567
1568 i2s->status &= 0xe0;
1569 if (i2s->fifo_len < 16 || !i2s->enable)
1570 i2s->status |= 1 << 0; /* TNF */
1571 if (i2s->rx_len)
1572 i2s->status |= 1 << 1; /* RNE */
1573 if (i2s->enable)
1574 i2s->status |= 1 << 2; /* BSY */
1575 if (tfs)
1576 i2s->status |= 1 << 3; /* TFS */
1577 if (rfs)
1578 i2s->status |= 1 << 4; /* RFS */
1579 if (!(i2s->tx_len && i2s->enable))
1580 i2s->status |= i2s->fifo_len << 8; /* TFL */
1581 i2s->status |= MAX(i2s->rx_len, 0xf) << 12; /* RFL */
1582
1583 qemu_set_irq(i2s->irq, i2s->status & i2s->mask);
1584 }
1585
1586 #define SACR0 0x00 /* Serial Audio Global Control register */
1587 #define SACR1 0x04 /* Serial Audio I2S/MSB-Justified Control register */
1588 #define SASR0 0x0c /* Serial Audio Interface and FIFO Status register */
1589 #define SAIMR 0x14 /* Serial Audio Interrupt Mask register */
1590 #define SAICR 0x18 /* Serial Audio Interrupt Clear register */
1591 #define SADIV 0x60 /* Serial Audio Clock Divider register */
1592 #define SADR 0x80 /* Serial Audio Data register */
1593
1594 static uint64_t pxa2xx_i2s_read(void *opaque, target_phys_addr_t addr,
1595 unsigned size)
1596 {
1597 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1598
1599 switch (addr) {
1600 case SACR0:
1601 return s->control[0];
1602 case SACR1:
1603 return s->control[1];
1604 case SASR0:
1605 return s->status;
1606 case SAIMR:
1607 return s->mask;
1608 case SAICR:
1609 return 0;
1610 case SADIV:
1611 return s->clk;
1612 case SADR:
1613 if (s->rx_len > 0) {
1614 s->rx_len --;
1615 pxa2xx_i2s_update(s);
1616 return s->codec_in(s->opaque);
1617 }
1618 return 0;
1619 default:
1620 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1621 break;
1622 }
1623 return 0;
1624 }
1625
1626 static void pxa2xx_i2s_write(void *opaque, target_phys_addr_t addr,
1627 uint64_t value, unsigned size)
1628 {
1629 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1630 uint32_t *sample;
1631
1632 switch (addr) {
1633 case SACR0:
1634 if (value & (1 << 3)) /* RST */
1635 pxa2xx_i2s_reset(s);
1636 s->control[0] = value & 0xff3d;
1637 if (!s->enable && (value & 1) && s->tx_len) { /* ENB */
1638 for (sample = s->fifo; s->fifo_len > 0; s->fifo_len --, sample ++)
1639 s->codec_out(s->opaque, *sample);
1640 s->status &= ~(1 << 7); /* I2SOFF */
1641 }
1642 if (value & (1 << 4)) /* EFWR */
1643 printf("%s: Attempt to use special function\n", __FUNCTION__);
1644 s->enable = (value & 9) == 1; /* ENB && !RST*/
1645 pxa2xx_i2s_update(s);
1646 break;
1647 case SACR1:
1648 s->control[1] = value & 0x0039;
1649 if (value & (1 << 5)) /* ENLBF */
1650 printf("%s: Attempt to use loopback function\n", __FUNCTION__);
1651 if (value & (1 << 4)) /* DPRL */
1652 s->fifo_len = 0;
1653 pxa2xx_i2s_update(s);
1654 break;
1655 case SAIMR:
1656 s->mask = value & 0x0078;
1657 pxa2xx_i2s_update(s);
1658 break;
1659 case SAICR:
1660 s->status &= ~(value & (3 << 5));
1661 pxa2xx_i2s_update(s);
1662 break;
1663 case SADIV:
1664 s->clk = value & 0x007f;
1665 break;
1666 case SADR:
1667 if (s->tx_len && s->enable) {
1668 s->tx_len --;
1669 pxa2xx_i2s_update(s);
1670 s->codec_out(s->opaque, value);
1671 } else if (s->fifo_len < 16) {
1672 s->fifo[s->fifo_len ++] = value;
1673 pxa2xx_i2s_update(s);
1674 }
1675 break;
1676 default:
1677 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1678 }
1679 }
1680
1681 static const MemoryRegionOps pxa2xx_i2s_ops = {
1682 .read = pxa2xx_i2s_read,
1683 .write = pxa2xx_i2s_write,
1684 .endianness = DEVICE_NATIVE_ENDIAN,
1685 };
1686
1687 static const VMStateDescription vmstate_pxa2xx_i2s = {
1688 .name = "pxa2xx_i2s",
1689 .version_id = 0,
1690 .minimum_version_id = 0,
1691 .minimum_version_id_old = 0,
1692 .fields = (VMStateField[]) {
1693 VMSTATE_UINT32_ARRAY(control, PXA2xxI2SState, 2),
1694 VMSTATE_UINT32(status, PXA2xxI2SState),
1695 VMSTATE_UINT32(mask, PXA2xxI2SState),
1696 VMSTATE_UINT32(clk, PXA2xxI2SState),
1697 VMSTATE_INT32(enable, PXA2xxI2SState),
1698 VMSTATE_INT32(rx_len, PXA2xxI2SState),
1699 VMSTATE_INT32(tx_len, PXA2xxI2SState),
1700 VMSTATE_INT32(fifo_len, PXA2xxI2SState),
1701 VMSTATE_END_OF_LIST()
1702 }
1703 };
1704
1705 static void pxa2xx_i2s_data_req(void *opaque, int tx, int rx)
1706 {
1707 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1708 uint32_t *sample;
1709
1710 /* Signal FIFO errors */
1711 if (s->enable && s->tx_len)
1712 s->status |= 1 << 5; /* TUR */
1713 if (s->enable && s->rx_len)
1714 s->status |= 1 << 6; /* ROR */
1715
1716 /* Should be tx - MIN(tx, s->fifo_len) but we don't really need to
1717 * handle the cases where it makes a difference. */
1718 s->tx_len = tx - s->fifo_len;
1719 s->rx_len = rx;
1720 /* Note that is s->codec_out wasn't set, we wouldn't get called. */
1721 if (s->enable)
1722 for (sample = s->fifo; s->fifo_len; s->fifo_len --, sample ++)
1723 s->codec_out(s->opaque, *sample);
1724 pxa2xx_i2s_update(s);
1725 }
1726
1727 static PXA2xxI2SState *pxa2xx_i2s_init(MemoryRegion *sysmem,
1728 target_phys_addr_t base,
1729 qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma)
1730 {
1731 PXA2xxI2SState *s = (PXA2xxI2SState *)
1732 g_malloc0(sizeof(PXA2xxI2SState));
1733
1734 s->irq = irq;
1735 s->rx_dma = rx_dma;
1736 s->tx_dma = tx_dma;
1737 s->data_req = pxa2xx_i2s_data_req;
1738
1739 pxa2xx_i2s_reset(s);
1740
1741 memory_region_init_io(&s->iomem, &pxa2xx_i2s_ops, s,
1742 "pxa2xx-i2s", 0x100000);
1743 memory_region_add_subregion(sysmem, base, &s->iomem);
1744
1745 vmstate_register(NULL, base, &vmstate_pxa2xx_i2s, s);
1746
1747 return s;
1748 }
1749
1750 /* PXA Fast Infra-red Communications Port */
1751 struct PXA2xxFIrState {
1752 MemoryRegion iomem;
1753 qemu_irq irq;
1754 qemu_irq rx_dma;
1755 qemu_irq tx_dma;
1756 int enable;
1757 CharDriverState *chr;
1758
1759 uint8_t control[3];
1760 uint8_t status[2];
1761
1762 int rx_len;
1763 int rx_start;
1764 uint8_t rx_fifo[64];
1765 };
1766
1767 static void pxa2xx_fir_reset(PXA2xxFIrState *s)
1768 {
1769 s->control[0] = 0x00;
1770 s->control[1] = 0x00;
1771 s->control[2] = 0x00;
1772 s->status[0] = 0x00;
1773 s->status[1] = 0x00;
1774 s->enable = 0;
1775 }
1776
1777 static inline void pxa2xx_fir_update(PXA2xxFIrState *s)
1778 {
1779 static const int tresh[4] = { 8, 16, 32, 0 };
1780 int intr = 0;
1781 if ((s->control[0] & (1 << 4)) && /* RXE */
1782 s->rx_len >= tresh[s->control[2] & 3]) /* TRIG */
1783 s->status[0] |= 1 << 4; /* RFS */
1784 else
1785 s->status[0] &= ~(1 << 4); /* RFS */
1786 if (s->control[0] & (1 << 3)) /* TXE */
1787 s->status[0] |= 1 << 3; /* TFS */
1788 else
1789 s->status[0] &= ~(1 << 3); /* TFS */
1790 if (s->rx_len)
1791 s->status[1] |= 1 << 2; /* RNE */
1792 else
1793 s->status[1] &= ~(1 << 2); /* RNE */
1794 if (s->control[0] & (1 << 4)) /* RXE */
1795 s->status[1] |= 1 << 0; /* RSY */
1796 else
1797 s->status[1] &= ~(1 << 0); /* RSY */
1798
1799 intr |= (s->control[0] & (1 << 5)) && /* RIE */
1800 (s->status[0] & (1 << 4)); /* RFS */
1801 intr |= (s->control[0] & (1 << 6)) && /* TIE */
1802 (s->status[0] & (1 << 3)); /* TFS */
1803 intr |= (s->control[2] & (1 << 4)) && /* TRAIL */
1804 (s->status[0] & (1 << 6)); /* EOC */
1805 intr |= (s->control[0] & (1 << 2)) && /* TUS */
1806 (s->status[0] & (1 << 1)); /* TUR */
1807 intr |= s->status[0] & 0x25; /* FRE, RAB, EIF */
1808
1809 qemu_set_irq(s->rx_dma, (s->status[0] >> 4) & 1);
1810 qemu_set_irq(s->tx_dma, (s->status[0] >> 3) & 1);
1811
1812 qemu_set_irq(s->irq, intr && s->enable);
1813 }
1814
1815 #define ICCR0 0x00 /* FICP Control register 0 */
1816 #define ICCR1 0x04 /* FICP Control register 1 */
1817 #define ICCR2 0x08 /* FICP Control register 2 */
1818 #define ICDR 0x0c /* FICP Data register */
1819 #define ICSR0 0x14 /* FICP Status register 0 */
1820 #define ICSR1 0x18 /* FICP Status register 1 */
1821 #define ICFOR 0x1c /* FICP FIFO Occupancy Status register */
1822
1823 static uint64_t pxa2xx_fir_read(void *opaque, target_phys_addr_t addr,
1824 unsigned size)
1825 {
1826 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1827 uint8_t ret;
1828
1829 switch (addr) {
1830 case ICCR0:
1831 return s->control[0];
1832 case ICCR1:
1833 return s->control[1];
1834 case ICCR2:
1835 return s->control[2];
1836 case ICDR:
1837 s->status[0] &= ~0x01;
1838 s->status[1] &= ~0x72;
1839 if (s->rx_len) {
1840 s->rx_len --;
1841 ret = s->rx_fifo[s->rx_start ++];
1842 s->rx_start &= 63;
1843 pxa2xx_fir_update(s);
1844 return ret;
1845 }
1846 printf("%s: Rx FIFO underrun.\n", __FUNCTION__);
1847 break;
1848 case ICSR0:
1849 return s->status[0];
1850 case ICSR1:
1851 return s->status[1] | (1 << 3); /* TNF */
1852 case ICFOR:
1853 return s->rx_len;
1854 default:
1855 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1856 break;
1857 }
1858 return 0;
1859 }
1860
1861 static void pxa2xx_fir_write(void *opaque, target_phys_addr_t addr,
1862 uint64_t value64, unsigned size)
1863 {
1864 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1865 uint32_t value = value64;
1866 uint8_t ch;
1867
1868 switch (addr) {
1869 case ICCR0:
1870 s->control[0] = value;
1871 if (!(value & (1 << 4))) /* RXE */
1872 s->rx_len = s->rx_start = 0;
1873 if (!(value & (1 << 3))) { /* TXE */
1874 /* Nop */
1875 }
1876 s->enable = value & 1; /* ITR */
1877 if (!s->enable)
1878 s->status[0] = 0;
1879 pxa2xx_fir_update(s);
1880 break;
1881 case ICCR1:
1882 s->control[1] = value;
1883 break;
1884 case ICCR2:
1885 s->control[2] = value & 0x3f;
1886 pxa2xx_fir_update(s);
1887 break;
1888 case ICDR:
1889 if (s->control[2] & (1 << 2)) /* TXP */
1890 ch = value;
1891 else
1892 ch = ~value;
1893 if (s->chr && s->enable && (s->control[0] & (1 << 3))) /* TXE */
1894 qemu_chr_fe_write(s->chr, &ch, 1);
1895 break;
1896 case ICSR0:
1897 s->status[0] &= ~(value & 0x66);
1898 pxa2xx_fir_update(s);
1899 break;
1900 case ICFOR:
1901 break;
1902 default:
1903 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1904 }
1905 }
1906
1907 static const MemoryRegionOps pxa2xx_fir_ops = {
1908 .read = pxa2xx_fir_read,
1909 .write = pxa2xx_fir_write,
1910 .endianness = DEVICE_NATIVE_ENDIAN,
1911 };
1912
1913 static int pxa2xx_fir_is_empty(void *opaque)
1914 {
1915 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1916 return (s->rx_len < 64);
1917 }
1918
1919 static void pxa2xx_fir_rx(void *opaque, const uint8_t *buf, int size)
1920 {
1921 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1922 if (!(s->control[0] & (1 << 4))) /* RXE */
1923 return;
1924
1925 while (size --) {
1926 s->status[1] |= 1 << 4; /* EOF */
1927 if (s->rx_len >= 64) {
1928 s->status[1] |= 1 << 6; /* ROR */
1929 break;
1930 }
1931
1932 if (s->control[2] & (1 << 3)) /* RXP */
1933 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = *(buf ++);
1934 else
1935 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = ~*(buf ++);
1936 }
1937
1938 pxa2xx_fir_update(s);
1939 }
1940
1941 static void pxa2xx_fir_event(void *opaque, int event)
1942 {
1943 }
1944
1945 static void pxa2xx_fir_save(QEMUFile *f, void *opaque)
1946 {
1947 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1948 int i;
1949
1950 qemu_put_be32(f, s->enable);
1951
1952 qemu_put_8s(f, &s->control[0]);
1953 qemu_put_8s(f, &s->control[1]);
1954 qemu_put_8s(f, &s->control[2]);
1955 qemu_put_8s(f, &s->status[0]);
1956 qemu_put_8s(f, &s->status[1]);
1957
1958 qemu_put_byte(f, s->rx_len);
1959 for (i = 0; i < s->rx_len; i ++)
1960 qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 63]);
1961 }
1962
1963 static int pxa2xx_fir_load(QEMUFile *f, void *opaque, int version_id)
1964 {
1965 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1966 int i;
1967
1968 s->enable = qemu_get_be32(f);
1969
1970 qemu_get_8s(f, &s->control[0]);
1971 qemu_get_8s(f, &s->control[1]);
1972 qemu_get_8s(f, &s->control[2]);
1973 qemu_get_8s(f, &s->status[0]);
1974 qemu_get_8s(f, &s->status[1]);
1975
1976 s->rx_len = qemu_get_byte(f);
1977 s->rx_start = 0;
1978 for (i = 0; i < s->rx_len; i ++)
1979 s->rx_fifo[i] = qemu_get_byte(f);
1980
1981 return 0;
1982 }
1983
1984 static PXA2xxFIrState *pxa2xx_fir_init(MemoryRegion *sysmem,
1985 target_phys_addr_t base,
1986 qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma,
1987 CharDriverState *chr)
1988 {
1989 PXA2xxFIrState *s = (PXA2xxFIrState *)
1990 g_malloc0(sizeof(PXA2xxFIrState));
1991
1992 s->irq = irq;
1993 s->rx_dma = rx_dma;
1994 s->tx_dma = tx_dma;
1995 s->chr = chr;
1996
1997 pxa2xx_fir_reset(s);
1998
1999 memory_region_init_io(&s->iomem, &pxa2xx_fir_ops, s, "pxa2xx-fir", 0x1000);
2000 memory_region_add_subregion(sysmem, base, &s->iomem);
2001
2002 if (chr)
2003 qemu_chr_add_handlers(chr, pxa2xx_fir_is_empty,
2004 pxa2xx_fir_rx, pxa2xx_fir_event, s);
2005
2006 register_savevm(NULL, "pxa2xx_fir", 0, 0, pxa2xx_fir_save,
2007 pxa2xx_fir_load, s);
2008
2009 return s;
2010 }
2011
2012 static void pxa2xx_reset(void *opaque, int line, int level)
2013 {
2014 PXA2xxState *s = (PXA2xxState *) opaque;
2015
2016 if (level && (s->pm_regs[PCFR >> 2] & 0x10)) { /* GPR_EN */
2017 cpu_reset(s->env);
2018 /* TODO: reset peripherals */
2019 }
2020 }
2021
2022 /* Initialise a PXA270 integrated chip (ARM based core). */
2023 PXA2xxState *pxa270_init(MemoryRegion *address_space,
2024 unsigned int sdram_size, const char *revision)
2025 {
2026 PXA2xxState *s;
2027 int i;
2028 DriveInfo *dinfo;
2029 s = (PXA2xxState *) g_malloc0(sizeof(PXA2xxState));
2030
2031 if (revision && strncmp(revision, "pxa27", 5)) {
2032 fprintf(stderr, "Machine requires a PXA27x processor.\n");
2033 exit(1);
2034 }
2035 if (!revision)
2036 revision = "pxa270";
2037
2038 s->env = cpu_init(revision);
2039 if (!s->env) {
2040 fprintf(stderr, "Unable to find CPU definition\n");
2041 exit(1);
2042 }
2043 s->reset = qemu_allocate_irqs(pxa2xx_reset, s, 1)[0];
2044
2045 /* SDRAM & Internal Memory Storage */
2046 memory_region_init_ram(&s->sdram, NULL, "pxa270.sdram", sdram_size);
2047 memory_region_add_subregion(address_space, PXA2XX_SDRAM_BASE, &s->sdram);
2048 memory_region_init_ram(&s->internal, NULL, "pxa270.internal", 0x40000);
2049 memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE,
2050 &s->internal);
2051
2052 s->pic = pxa2xx_pic_init(0x40d00000, s->env);
2053
2054 s->dma = pxa27x_dma_init(0x40000000,
2055 qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA));
2056
2057 sysbus_create_varargs("pxa27x-timer", 0x40a00000,
2058 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 0),
2059 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 1),
2060 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 2),
2061 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 3),
2062 qdev_get_gpio_in(s->pic, PXA27X_PIC_OST_4_11),
2063 NULL);
2064
2065 s->gpio = pxa2xx_gpio_init(0x40e00000, s->env, s->pic, 121);
2066
2067 dinfo = drive_get(IF_SD, 0, 0);
2068 if (!dinfo) {
2069 fprintf(stderr, "qemu: missing SecureDigital device\n");
2070 exit(1);
2071 }
2072 s->mmc = pxa2xx_mmci_init(0x41100000, dinfo->bdrv,
2073 qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC),
2074 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI),
2075 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI));
2076
2077 for (i = 0; pxa270_serial[i].io_base; i++) {
2078 if (serial_hds[i]) {
2079 serial_mm_init(address_space, pxa270_serial[i].io_base, 2,
2080 qdev_get_gpio_in(s->pic, pxa270_serial[i].irqn),
2081 14857000 / 16, serial_hds[i],
2082 DEVICE_NATIVE_ENDIAN);
2083 } else {
2084 break;
2085 }
2086 }
2087 if (serial_hds[i])
2088 s->fir = pxa2xx_fir_init(address_space, 0x40800000,
2089 qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP),
2090 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP),
2091 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP),
2092 serial_hds[i]);
2093
2094 s->lcd = pxa2xx_lcdc_init(0x44000000,
2095 qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD));
2096
2097 s->cm_base = 0x41300000;
2098 s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */
2099 s->clkcfg = 0x00000009; /* Turbo mode active */
2100 memory_region_init_io(&s->cm_iomem, &pxa2xx_cm_ops, s, "pxa2xx-cm", 0x1000);
2101 memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem);
2102 vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s);
2103
2104 cpu_arm_set_cp_io(s->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s);
2105
2106 s->mm_base = 0x48000000;
2107 s->mm_regs[MDMRS >> 2] = 0x00020002;
2108 s->mm_regs[MDREFR >> 2] = 0x03ca4000;
2109 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */
2110 memory_region_init_io(&s->mm_iomem, &pxa2xx_mm_ops, s, "pxa2xx-mm", 0x1000);
2111 memory_region_add_subregion(address_space, s->mm_base, &s->mm_iomem);
2112 vmstate_register(NULL, 0, &vmstate_pxa2xx_mm, s);
2113
2114 s->pm_base = 0x40f00000;
2115 memory_region_init_io(&s->pm_iomem, &pxa2xx_pm_ops, s, "pxa2xx-pm", 0x100);
2116 memory_region_add_subregion(address_space, s->pm_base, &s->pm_iomem);
2117 vmstate_register(NULL, 0, &vmstate_pxa2xx_pm, s);
2118
2119 for (i = 0; pxa27x_ssp[i].io_base; i ++);
2120 s->ssp = (SSIBus **)g_malloc0(sizeof(SSIBus *) * i);
2121 for (i = 0; pxa27x_ssp[i].io_base; i ++) {
2122 DeviceState *dev;
2123 dev = sysbus_create_simple("pxa2xx-ssp", pxa27x_ssp[i].io_base,
2124 qdev_get_gpio_in(s->pic, pxa27x_ssp[i].irqn));
2125 s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi");
2126 }
2127
2128 if (usb_enabled) {
2129 sysbus_create_simple("sysbus-ohci", 0x4c000000,
2130 qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1));
2131 }
2132
2133 s->pcmcia[0] = pxa2xx_pcmcia_init(0x20000000);
2134 s->pcmcia[1] = pxa2xx_pcmcia_init(0x30000000);
2135
2136 sysbus_create_simple("pxa2xx_rtc", 0x40900000,
2137 qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM));
2138
2139 s->i2c[0] = pxa2xx_i2c_init(0x40301600,
2140 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff);
2141 s->i2c[1] = pxa2xx_i2c_init(0x40f00100,
2142 qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff);
2143
2144 s->i2s = pxa2xx_i2s_init(address_space, 0x40400000,
2145 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S),
2146 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S),
2147 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S));
2148
2149 s->kp = pxa27x_keypad_init(0x41500000,
2150 qdev_get_gpio_in(s->pic, PXA2XX_PIC_KEYPAD));
2151
2152 /* GPIO1 resets the processor */
2153 /* The handler can be overridden by board-specific code */
2154 qdev_connect_gpio_out(s->gpio, 1, s->reset);
2155 return s;
2156 }
2157
2158 /* Initialise a PXA255 integrated chip (ARM based core). */
2159 PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size)
2160 {
2161 PXA2xxState *s;
2162 int i;
2163 DriveInfo *dinfo;
2164
2165 s = (PXA2xxState *) g_malloc0(sizeof(PXA2xxState));
2166
2167 s->env = cpu_init("pxa255");
2168 if (!s->env) {
2169 fprintf(stderr, "Unable to find CPU definition\n");
2170 exit(1);
2171 }
2172 s->reset = qemu_allocate_irqs(pxa2xx_reset, s, 1)[0];
2173
2174 /* SDRAM & Internal Memory Storage */
2175 memory_region_init_ram(&s->sdram, NULL, "pxa255.sdram", sdram_size);
2176 memory_region_add_subregion(address_space, PXA2XX_SDRAM_BASE, &s->sdram);
2177 memory_region_init_ram(&s->internal, NULL, "pxa255.internal",
2178 PXA2XX_INTERNAL_SIZE);
2179 memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE,
2180 &s->internal);
2181
2182 s->pic = pxa2xx_pic_init(0x40d00000, s->env);
2183
2184 s->dma = pxa255_dma_init(0x40000000,
2185 qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA));
2186
2187 sysbus_create_varargs("pxa25x-timer", 0x40a00000,
2188 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 0),
2189 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 1),
2190 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 2),
2191 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 3),
2192 NULL);
2193
2194 s->gpio = pxa2xx_gpio_init(0x40e00000, s->env, s->pic, 85);
2195
2196 dinfo = drive_get(IF_SD, 0, 0);
2197 if (!dinfo) {
2198 fprintf(stderr, "qemu: missing SecureDigital device\n");
2199 exit(1);
2200 }
2201 s->mmc = pxa2xx_mmci_init(0x41100000, dinfo->bdrv,
2202 qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC),
2203 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI),
2204 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI));
2205
2206 for (i = 0; pxa255_serial[i].io_base; i++) {
2207 if (serial_hds[i]) {
2208 serial_mm_init(address_space, pxa255_serial[i].io_base, 2,
2209 qdev_get_gpio_in(s->pic, pxa255_serial[i].irqn),
2210 14745600 / 16, serial_hds[i],
2211 DEVICE_NATIVE_ENDIAN);
2212 } else {
2213 break;
2214 }
2215 }
2216 if (serial_hds[i])
2217 s->fir = pxa2xx_fir_init(address_space, 0x40800000,
2218 qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP),
2219 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP),
2220 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP),
2221 serial_hds[i]);
2222
2223 s->lcd = pxa2xx_lcdc_init(0x44000000,
2224 qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD));
2225
2226 s->cm_base = 0x41300000;
2227 s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */
2228 s->clkcfg = 0x00000009; /* Turbo mode active */
2229 memory_region_init_io(&s->cm_iomem, &pxa2xx_cm_ops, s, "pxa2xx-cm", 0x1000);
2230 memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem);
2231 vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s);
2232
2233 cpu_arm_set_cp_io(s->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s);
2234
2235 s->mm_base = 0x48000000;
2236 s->mm_regs[MDMRS >> 2] = 0x00020002;
2237 s->mm_regs[MDREFR >> 2] = 0x03ca4000;
2238 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */
2239 memory_region_init_io(&s->mm_iomem, &pxa2xx_mm_ops, s, "pxa2xx-mm", 0x1000);
2240 memory_region_add_subregion(address_space, s->mm_base, &s->mm_iomem);
2241 vmstate_register(NULL, 0, &vmstate_pxa2xx_mm, s);
2242
2243 s->pm_base = 0x40f00000;
2244 memory_region_init_io(&s->pm_iomem, &pxa2xx_pm_ops, s, "pxa2xx-pm", 0x100);
2245 memory_region_add_subregion(address_space, s->pm_base, &s->pm_iomem);
2246 vmstate_register(NULL, 0, &vmstate_pxa2xx_pm, s);
2247
2248 for (i = 0; pxa255_ssp[i].io_base; i ++);
2249 s->ssp = (SSIBus **)g_malloc0(sizeof(SSIBus *) * i);
2250 for (i = 0; pxa255_ssp[i].io_base; i ++) {
2251 DeviceState *dev;
2252 dev = sysbus_create_simple("pxa2xx-ssp", pxa255_ssp[i].io_base,
2253 qdev_get_gpio_in(s->pic, pxa255_ssp[i].irqn));
2254 s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi");
2255 }
2256
2257 if (usb_enabled) {
2258 sysbus_create_simple("sysbus-ohci", 0x4c000000,
2259 qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1));
2260 }
2261
2262 s->pcmcia[0] = pxa2xx_pcmcia_init(0x20000000);
2263 s->pcmcia[1] = pxa2xx_pcmcia_init(0x30000000);
2264
2265 sysbus_create_simple("pxa2xx_rtc", 0x40900000,
2266 qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM));
2267
2268 s->i2c[0] = pxa2xx_i2c_init(0x40301600,
2269 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff);
2270 s->i2c[1] = pxa2xx_i2c_init(0x40f00100,
2271 qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff);
2272
2273 s->i2s = pxa2xx_i2s_init(address_space, 0x40400000,
2274 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S),
2275 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S),
2276 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S));
2277
2278 /* GPIO1 resets the processor */
2279 /* The handler can be overridden by board-specific code */
2280 qdev_connect_gpio_out(s->gpio, 1, s->reset);
2281 return s;
2282 }
2283
2284 static void pxa2xx_register_devices(void)
2285 {
2286 i2c_register_slave(&pxa2xx_i2c_slave_info);
2287 sysbus_register_dev("pxa2xx-ssp", sizeof(PXA2xxSSPState), pxa2xx_ssp_init);
2288 sysbus_register_withprop(&pxa2xx_i2c_info);
2289 sysbus_register_withprop(&pxa2xx_rtc_sysbus_info);
2290 }
2291
2292 device_init(pxa2xx_register_devices)
QEmu