hw/arm/realview.c

   1 /*
   2  * ARM RealView Baseboard System emulation.
   3  *
   4  * Copyright (c) 2006-2007 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GPL.
   8  */
   9
  10 #include "hw/sysbus.h"
  11 #include "hw/arm/arm.h"
  12 #include "hw/arm/primecell.h"
  13 #include "hw/devices.h"
  14 #include "hw/pci/pci.h"
  15 #include "net/net.h"
  16 #include "sysemu/sysemu.h"
  17 #include "hw/boards.h"
  18 #include "hw/i2c/i2c.h"
  19 #include "sysemu/blockdev.h"
  20 #include "exec/address-spaces.h"
  21 #include "qemu/error-report.h"
  22
  23 #define SMP_BOOT_ADDR 0xe0000000
  24 #define SMP_BOOTREG_ADDR 0x10000030
  25
  26 /* Board init.  */
  27
  28 static struct arm_boot_info realview_binfo = {
  29     .smp_loader_start = SMP_BOOT_ADDR,
  30     .smp_bootreg_addr = SMP_BOOTREG_ADDR,
  31 };
  32
  33 /* The following two lists must be consistent.  */
  34 enum realview_board_type {
  35     BOARD_EB,
  36     BOARD_EB_MPCORE,
  37     BOARD_PB_A8,
  38     BOARD_PBX_A9,
  39 };
  40
  41 static const int realview_board_id[] = {
  42     0x33b,
  43     0x33b,
  44     0x769,
  45     0x76d
  46 };
  47
  48 static void realview_init(MachineState *machine,
  49                           enum realview_board_type board_type)
  50 {
  51     ARMCPU *cpu = NULL;
  52     CPUARMState *env;
  53     ObjectClass *cpu_oc;
  54     MemoryRegion *sysmem = get_system_memory();
  55     MemoryRegion *ram_lo = g_new(MemoryRegion, 1);
  56     MemoryRegion *ram_hi = g_new(MemoryRegion, 1);
  57     MemoryRegion *ram_alias = g_new(MemoryRegion, 1);
  58     MemoryRegion *ram_hack = g_new(MemoryRegion, 1);
  59     DeviceState *dev, *sysctl, *gpio2, *pl041;
  60     SysBusDevice *busdev;
  61     qemu_irq pic[64];
  62     qemu_irq mmc_irq[2];
  63     PCIBus *pci_bus = NULL;
  64     NICInfo *nd;
  65     I2CBus *i2c;
  66     int n;
  67     int done_nic = 0;
  68     qemu_irq cpu_irq[4];
  69     int is_mpcore = 0;
  70     int is_pb = 0;
  71     uint32_t proc_id = 0;
  72     uint32_t sys_id;
  73     ram_addr_t low_ram_size;
  74     ram_addr_t ram_size = machine->ram_size;
  75     hwaddr periphbase = 0;
  76
  77     switch (board_type) {
  78     case BOARD_EB:
  79         break;
  80     case BOARD_EB_MPCORE:
  81         is_mpcore = 1;
  82         periphbase = 0x10100000;
  83         break;
  84     case BOARD_PB_A8:
  85         is_pb = 1;
  86         break;
  87     case BOARD_PBX_A9:
  88         is_mpcore = 1;
  89         is_pb = 1;
  90         periphbase = 0x1f000000;
  91         break;
  92     }
  93
  94     cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, machine->cpu_model);
  95     if (!cpu_oc) {
  96         fprintf(stderr, "Unable to find CPU definition\n");
  97         exit(1);
  98     }
  99
 100     for (n = 0; n < smp_cpus; n++) {
 101         Object *cpuobj = object_new(object_class_get_name(cpu_oc));
 102         Error *err = NULL;
 103
 104         if (is_pb && is_mpcore) {
 105             object_property_set_int(cpuobj, periphbase, "reset-cbar", &err);
 106             if (err) {
 107                 error_report("%s", error_get_pretty(err));
 108                 exit(1);
 109             }
 110         }
 111
 112         object_property_set_bool(cpuobj, true, "realized", &err);
 113         if (err) {
 114             error_report("%s", error_get_pretty(err));
 115             exit(1);
 116         }
 117
 118         cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpuobj), ARM_CPU_IRQ);
 119     }
 120     cpu = ARM_CPU(first_cpu);
 121     env = &cpu->env;
 122     if (arm_feature(env, ARM_FEATURE_V7)) {
 123         if (is_mpcore) {
 124             proc_id = 0x0c000000;
 125         } else {
 126             proc_id = 0x0e000000;
 127         }
 128     } else if (arm_feature(env, ARM_FEATURE_V6K)) {
 129         proc_id = 0x06000000;
 130     } else if (arm_feature(env, ARM_FEATURE_V6)) {
 131         proc_id = 0x04000000;
 132     } else {
 133         proc_id = 0x02000000;
 134     }
 135
 136     if (is_pb && ram_size > 0x20000000) {
 137         /* Core tile RAM.  */
 138         low_ram_size = ram_size - 0x20000000;
 139         ram_size = 0x20000000;
 140         memory_region_init_ram(ram_lo, NULL, "realview.lowmem", low_ram_size);
 141         vmstate_register_ram_global(ram_lo);
 142         memory_region_add_subregion(sysmem, 0x20000000, ram_lo);
 143     }
 144
 145     memory_region_init_ram(ram_hi, NULL, "realview.highmem", ram_size);
 146     vmstate_register_ram_global(ram_hi);
 147     low_ram_size = ram_size;
 148     if (low_ram_size > 0x10000000)
 149       low_ram_size = 0x10000000;
 150     /* SDRAM at address zero.  */
 151     memory_region_init_alias(ram_alias, NULL, "realview.alias",
 152                              ram_hi, 0, low_ram_size);
 153     memory_region_add_subregion(sysmem, 0, ram_alias);
 154     if (is_pb) {
 155         /* And again at a high address.  */
 156         memory_region_add_subregion(sysmem, 0x70000000, ram_hi);
 157     } else {
 158         ram_size = low_ram_size;
 159     }
 160
 161     sys_id = is_pb ? 0x01780500 : 0xc1400400;
 162     sysctl = qdev_create(NULL, "realview_sysctl");
 163     qdev_prop_set_uint32(sysctl, "sys_id", sys_id);
 164     qdev_prop_set_uint32(sysctl, "proc_id", proc_id);
 165     qdev_init_nofail(sysctl);
 166     sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, 0x10000000);
 167
 168     if (is_mpcore) {
 169         dev = qdev_create(NULL, is_pb ? "a9mpcore_priv": "realview_mpcore");
 170         qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
 171         qdev_init_nofail(dev);
 172         busdev = SYS_BUS_DEVICE(dev);
 173         sysbus_mmio_map(busdev, 0, periphbase);
 174         for (n = 0; n < smp_cpus; n++) {
 175             sysbus_connect_irq(busdev, n, cpu_irq[n]);
 176         }
 177         sysbus_create_varargs("l2x0", periphbase + 0x2000, NULL);
 178         /* Both A9 and 11MPCore put the GIC CPU i/f at base + 0x100 */
 179         realview_binfo.gic_cpu_if_addr = periphbase + 0x100;
 180     } else {
 181         uint32_t gic_addr = is_pb ? 0x1e000000 : 0x10040000;
 182         /* For now just create the nIRQ GIC, and ignore the others.  */
 183         dev = sysbus_create_simple("realview_gic", gic_addr, cpu_irq[0]);
 184     }
 185     for (n = 0; n < 64; n++) {
 186         pic[n] = qdev_get_gpio_in(dev, n);
 187     }
 188
 189     pl041 = qdev_create(NULL, "pl041");
 190     qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512);
 191     qdev_init_nofail(pl041);
 192     sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, 0x10004000);
 193     sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[19]);
 194
 195     sysbus_create_simple("pl050_keyboard", 0x10006000, pic[20]);
 196     sysbus_create_simple("pl050_mouse", 0x10007000, pic[21]);
 197
 198     sysbus_create_simple("pl011", 0x10009000, pic[12]);
 199     sysbus_create_simple("pl011", 0x1000a000, pic[13]);
 200     sysbus_create_simple("pl011", 0x1000b000, pic[14]);
 201     sysbus_create_simple("pl011", 0x1000c000, pic[15]);
 202
 203     /* DMA controller is optional, apparently.  */
 204     sysbus_create_simple("pl081", 0x10030000, pic[24]);
 205
 206     sysbus_create_simple("sp804", 0x10011000, pic[4]);
 207     sysbus_create_simple("sp804", 0x10012000, pic[5]);
 208
 209     sysbus_create_simple("pl061", 0x10013000, pic[6]);
 210     sysbus_create_simple("pl061", 0x10014000, pic[7]);
 211     gpio2 = sysbus_create_simple("pl061", 0x10015000, pic[8]);
 212
 213     sysbus_create_simple("pl111", 0x10020000, pic[23]);
 214
 215     dev = sysbus_create_varargs("pl181", 0x10005000, pic[17], pic[18], NULL);
 216     /* Wire up MMC card detect and read-only signals. These have
 217      * to go to both the PL061 GPIO and the sysctl register.
 218      * Note that the PL181 orders these lines (readonly,inserted)
 219      * and the PL061 has them the other way about. Also the card
 220      * detect line is inverted.
 221      */
 222     mmc_irq[0] = qemu_irq_split(
 223         qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT),
 224         qdev_get_gpio_in(gpio2, 1));
 225     mmc_irq[1] = qemu_irq_split(
 226         qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN),
 227         qemu_irq_invert(qdev_get_gpio_in(gpio2, 0)));
 228     qdev_connect_gpio_out(dev, 0, mmc_irq[0]);
 229     qdev_connect_gpio_out(dev, 1, mmc_irq[1]);
 230
 231     sysbus_create_simple("pl031", 0x10017000, pic[10]);
 232
 233     if (!is_pb) {
 234         dev = qdev_create(NULL, "realview_pci");
 235         busdev = SYS_BUS_DEVICE(dev);
 236         qdev_init_nofail(dev);
 237         sysbus_mmio_map(busdev, 0, 0x10019000); /* PCI controller registers */
 238         sysbus_mmio_map(busdev, 1, 0x60000000); /* PCI self-config */
 239         sysbus_mmio_map(busdev, 2, 0x61000000); /* PCI config */
 240         sysbus_mmio_map(busdev, 3, 0x62000000); /* PCI I/O */
 241         sysbus_mmio_map(busdev, 4, 0x63000000); /* PCI memory window 1 */
 242         sysbus_mmio_map(busdev, 5, 0x64000000); /* PCI memory window 2 */
 243         sysbus_mmio_map(busdev, 6, 0x68000000); /* PCI memory window 3 */
 244         sysbus_connect_irq(busdev, 0, pic[48]);
 245         sysbus_connect_irq(busdev, 1, pic[49]);
 246         sysbus_connect_irq(busdev, 2, pic[50]);
 247         sysbus_connect_irq(busdev, 3, pic[51]);
 248         pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci");
 249         if (usb_enabled(false)) {
 250             pci_create_simple(pci_bus, -1, "pci-ohci");
 251         }
 252         n = drive_get_max_bus(IF_SCSI);
 253         while (n >= 0) {
 254             pci_create_simple(pci_bus, -1, "lsi53c895a");
 255             n--;
 256         }
 257     }
 258     for(n = 0; n < nb_nics; n++) {
 259         nd = &nd_table[n];
 260
 261         if (!done_nic && (!nd->model ||
 262                     strcmp(nd->model, is_pb ? "lan9118" : "smc91c111") == 0)) {
 263             if (is_pb) {
 264                 lan9118_init(nd, 0x4e000000, pic[28]);
 265             } else {
 266                 smc91c111_init(nd, 0x4e000000, pic[28]);
 267             }
 268             done_nic = 1;
 269         } else {
 270             if (pci_bus) {
 271                 pci_nic_init_nofail(nd, pci_bus, "rtl8139", NULL);
 272             }
 273         }
 274     }
 275
 276     dev = sysbus_create_simple("versatile_i2c", 0x10002000, NULL);
 277     i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
 278     i2c_create_slave(i2c, "ds1338", 0x68);
 279
 280     /* Memory map for RealView Emulation Baseboard:  */
 281     /* 0x10000000 System registers.  */
 282     /*  0x10001000 System controller.  */
 283     /* 0x10002000 Two-Wire Serial Bus.  */
 284     /* 0x10003000 Reserved.  */
 285     /*  0x10004000 AACI.  */
 286     /*  0x10005000 MCI.  */
 287     /* 0x10006000 KMI0.  */
 288     /* 0x10007000 KMI1.  */
 289     /*  0x10008000 Character LCD. (EB) */
 290     /* 0x10009000 UART0.  */
 291     /* 0x1000a000 UART1.  */
 292     /* 0x1000b000 UART2.  */
 293     /* 0x1000c000 UART3.  */
 294     /*  0x1000d000 SSPI.  */
 295     /*  0x1000e000 SCI.  */
 296     /* 0x1000f000 Reserved.  */
 297     /*  0x10010000 Watchdog.  */
 298     /* 0x10011000 Timer 0+1.  */
 299     /* 0x10012000 Timer 2+3.  */
 300     /*  0x10013000 GPIO 0.  */
 301     /*  0x10014000 GPIO 1.  */
 302     /*  0x10015000 GPIO 2.  */
 303     /*  0x10002000 Two-Wire Serial Bus - DVI. (PB) */
 304     /* 0x10017000 RTC.  */
 305     /*  0x10018000 DMC.  */
 306     /*  0x10019000 PCI controller config.  */
 307     /*  0x10020000 CLCD.  */
 308     /* 0x10030000 DMA Controller.  */
 309     /* 0x10040000 GIC1. (EB) */
 310     /*  0x10050000 GIC2. (EB) */
 311     /*  0x10060000 GIC3. (EB) */
 312     /*  0x10070000 GIC4. (EB) */
 313     /*  0x10080000 SMC.  */
 314     /* 0x1e000000 GIC1. (PB) */
 315     /*  0x1e001000 GIC2. (PB) */
 316     /*  0x1e002000 GIC3. (PB) */
 317     /*  0x1e003000 GIC4. (PB) */
 318     /*  0x40000000 NOR flash.  */
 319     /*  0x44000000 DoC flash.  */
 320     /*  0x48000000 SRAM.  */
 321     /*  0x4c000000 Configuration flash.  */
 322     /* 0x4e000000 Ethernet.  */
 323     /*  0x4f000000 USB.  */
 324     /*  0x50000000 PISMO.  */
 325     /*  0x54000000 PISMO.  */
 326     /*  0x58000000 PISMO.  */
 327     /*  0x5c000000 PISMO.  */
 328     /* 0x60000000 PCI.  */
 329     /* 0x60000000 PCI Self Config.  */
 330     /* 0x61000000 PCI Config.  */
 331     /* 0x62000000 PCI IO.  */
 332     /* 0x63000000 PCI mem 0.  */
 333     /* 0x64000000 PCI mem 1.  */
 334     /* 0x68000000 PCI mem 2.  */
 335
 336     /* ??? Hack to map an additional page of ram for the secondary CPU
 337        startup code.  I guess this works on real hardware because the
 338        BootROM happens to be in ROM/flash or in memory that isn't clobbered
 339        until after Linux boots the secondary CPUs.  */
 340     memory_region_init_ram(ram_hack, NULL, "realview.hack", 0x1000);
 341     vmstate_register_ram_global(ram_hack);
 342     memory_region_add_subregion(sysmem, SMP_BOOT_ADDR, ram_hack);
 343
 344     realview_binfo.ram_size = ram_size;
 345     realview_binfo.kernel_filename = machine->kernel_filename;
 346     realview_binfo.kernel_cmdline = machine->kernel_cmdline;
 347     realview_binfo.initrd_filename = machine->initrd_filename;
 348     realview_binfo.nb_cpus = smp_cpus;
 349     realview_binfo.board_id = realview_board_id[board_type];
 350     realview_binfo.loader_start = (board_type == BOARD_PB_A8 ? 0x70000000 : 0);
 351     arm_load_kernel(ARM_CPU(first_cpu), &realview_binfo);
 352 }
 353
 354 static void realview_eb_init(MachineState *machine)
 355 {
 356     if (!machine->cpu_model) {
 357         machine->cpu_model = "arm926";
 358     }
 359     realview_init(machine, BOARD_EB);
 360 }
 361
 362 static void realview_eb_mpcore_init(MachineState *machine)
 363 {
 364     if (!machine->cpu_model) {
 365         machine->cpu_model = "arm11mpcore";
 366     }
 367     realview_init(machine, BOARD_EB_MPCORE);
 368 }
 369
 370 static void realview_pb_a8_init(MachineState *machine)
 371 {
 372     if (!machine->cpu_model) {
 373         machine->cpu_model = "cortex-a8";
 374     }
 375     realview_init(machine, BOARD_PB_A8);
 376 }
 377
 378 static void realview_pbx_a9_init(MachineState *machine)
 379 {
 380     if (!machine->cpu_model) {
 381         machine->cpu_model = "cortex-a9";
 382     }
 383     realview_init(machine, BOARD_PBX_A9);
 384 }
 385
 386 static QEMUMachine realview_eb_machine = {
 387     .name = "realview-eb",
 388     .desc = "ARM RealView Emulation Baseboard (ARM926EJ-S)",
 389     .init = realview_eb_init,
 390     .block_default_type = IF_SCSI,
 391 };
 392
 393 static QEMUMachine realview_eb_mpcore_machine = {
 394     .name = "realview-eb-mpcore",
 395     .desc = "ARM RealView Emulation Baseboard (ARM11MPCore)",
 396     .init = realview_eb_mpcore_init,
 397     .block_default_type = IF_SCSI,
 398     .max_cpus = 4,
 399 };
 400
 401 static QEMUMachine realview_pb_a8_machine = {
 402     .name = "realview-pb-a8",
 403     .desc = "ARM RealView Platform Baseboard for Cortex-A8",
 404     .init = realview_pb_a8_init,
 405 };
 406
 407 static QEMUMachine realview_pbx_a9_machine = {
 408     .name = "realview-pbx-a9",
 409     .desc = "ARM RealView Platform Baseboard Explore for Cortex-A9",
 410     .init = realview_pbx_a9_init,
 411     .block_default_type = IF_SCSI,
 412     .max_cpus = 4,
 413 };
 414
 415 static void realview_machine_init(void)
 416 {
 417     qemu_register_machine(&realview_eb_machine);
 418     qemu_register_machine(&realview_eb_mpcore_machine);
 419     qemu_register_machine(&realview_pb_a8_machine);
 420     qemu_register_machine(&realview_pbx_a9_machine);
 421 }
 422
 423 machine_init(realview_machine_init);