hw/arm/highbank.c

   1 /*
   2  * Calxeda Highbank SoC emulation
   3  *
   4  * Copyright (c) 2010-2012 Calxeda
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2 or later, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  *
  18  */
  19
  20 #include "hw/sysbus.h"
  21 #include "hw/arm/arm.h"
  22 #include "hw/devices.h"
  23 #include "hw/loader.h"
  24 #include "net/net.h"
  25 #include "sysemu/sysemu.h"
  26 #include "hw/boards.h"
  27 #include "sysemu/blockdev.h"
  28 #include "exec/address-spaces.h"
  29 #include "qemu/error-report.h"
  30
  31 #define SMP_BOOT_ADDR           0x100
  32 #define SMP_BOOT_REG            0x40
  33 #define MPCORE_PERIPHBASE       0xfff10000
  34
  35 #define NIRQ_GIC                160
  36
  37 /* Board init.  */
  38
  39 static void hb_write_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
  40 {
  41     int n;
  42     uint32_t smpboot[] = {
  43         0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 - read current core id */
  44         0xe210000f, /* ands r0, r0, #0x0f */
  45         0xe3a03040, /* mov r3, #0x40 - jump address is 0x40 + 0x10 * core id */
  46         0xe0830200, /* add r0, r3, r0, lsl #4 */
  47         0xe59f2024, /* ldr r2, privbase */
  48         0xe3a01001, /* mov r1, #1 */
  49         0xe5821100, /* str r1, [r2, #256] - set GICC_CTLR.Enable */
  50         0xe3a010ff, /* mov r1, #0xff */
  51         0xe5821104, /* str r1, [r2, #260] - set GICC_PMR.Priority to 0xff */
  52         0xf57ff04f, /* dsb */
  53         0xe320f003, /* wfi */
  54         0xe5901000, /* ldr     r1, [r0] */
  55         0xe1110001, /* tst     r1, r1 */
  56         0x0afffffb, /* beq     <wfi> */
  57         0xe12fff11, /* bx      r1 */
  58         MPCORE_PERIPHBASE   /* privbase: MPCore peripheral base address.  */
  59     };
  60     for (n = 0; n < ARRAY_SIZE(smpboot); n++) {
  61         smpboot[n] = tswap32(smpboot[n]);
  62     }
  63     rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), SMP_BOOT_ADDR);
  64 }
  65
  66 static void hb_reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
  67 {
  68     CPUARMState *env = &cpu->env;
  69
  70     switch (info->nb_cpus) {
  71     case 4:
  72         stl_phys_notdirty(&address_space_memory, SMP_BOOT_REG + 0x30, 0);
  73     case 3:
  74         stl_phys_notdirty(&address_space_memory, SMP_BOOT_REG + 0x20, 0);
  75     case 2:
  76         stl_phys_notdirty(&address_space_memory, SMP_BOOT_REG + 0x10, 0);
  77         env->regs[15] = SMP_BOOT_ADDR;
  78         break;
  79     default:
  80         break;
  81     }
  82 }
  83
  84 #define NUM_REGS      0x200
  85 static void hb_regs_write(void *opaque, hwaddr offset,
  86                           uint64_t value, unsigned size)
  87 {
  88     uint32_t *regs = opaque;
  89
  90     if (offset == 0xf00) {
  91         if (value == 1 || value == 2) {
  92             qemu_system_reset_request();
  93         } else if (value == 3) {
  94             qemu_system_shutdown_request();
  95         }
  96     }
  97
  98     regs[offset/4] = value;
  99 }
 100
 101 static uint64_t hb_regs_read(void *opaque, hwaddr offset,
 102                              unsigned size)
 103 {
 104     uint32_t *regs = opaque;
 105     uint32_t value = regs[offset/4];
 106
 107     if ((offset == 0x100) || (offset == 0x108) || (offset == 0x10C)) {
 108         value |= 0x30000000;
 109     }
 110
 111     return value;
 112 }
 113
 114 static const MemoryRegionOps hb_mem_ops = {
 115     .read = hb_regs_read,
 116     .write = hb_regs_write,
 117     .endianness = DEVICE_NATIVE_ENDIAN,
 118 };
 119
 120 #define TYPE_HIGHBANK_REGISTERS "highbank-regs"
 121 #define HIGHBANK_REGISTERS(obj) \
 122     OBJECT_CHECK(HighbankRegsState, (obj), TYPE_HIGHBANK_REGISTERS)
 123
 124 typedef struct {
 125     /*< private >*/
 126     SysBusDevice parent_obj;
 127     /*< public >*/
 128
 129     MemoryRegion iomem;
 130     uint32_t regs[NUM_REGS];
 131 } HighbankRegsState;
 132
 133 static VMStateDescription vmstate_highbank_regs = {
 134     .name = "highbank-regs",
 135     .version_id = 0,
 136     .minimum_version_id = 0,
 137     .fields = (VMStateField[]) {
 138         VMSTATE_UINT32_ARRAY(regs, HighbankRegsState, NUM_REGS),
 139         VMSTATE_END_OF_LIST(),
 140     },
 141 };
 142
 143 static void highbank_regs_reset(DeviceState *dev)
 144 {
 145     HighbankRegsState *s = HIGHBANK_REGISTERS(dev);
 146
 147     s->regs[0x40] = 0x05F20121;
 148     s->regs[0x41] = 0x2;
 149     s->regs[0x42] = 0x05F30121;
 150     s->regs[0x43] = 0x05F40121;
 151 }
 152
 153 static int highbank_regs_init(SysBusDevice *dev)
 154 {
 155     HighbankRegsState *s = HIGHBANK_REGISTERS(dev);
 156
 157     memory_region_init_io(&s->iomem, OBJECT(s), &hb_mem_ops, s->regs,
 158                           "highbank_regs", 0x1000);
 159     sysbus_init_mmio(dev, &s->iomem);
 160
 161     return 0;
 162 }
 163
 164 static void highbank_regs_class_init(ObjectClass *klass, void *data)
 165 {
 166     SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
 167     DeviceClass *dc = DEVICE_CLASS(klass);
 168
 169     sbc->init = highbank_regs_init;
 170     dc->desc = "Calxeda Highbank registers";
 171     dc->vmsd = &vmstate_highbank_regs;
 172     dc->reset = highbank_regs_reset;
 173 }
 174
 175 static const TypeInfo highbank_regs_info = {
 176     .name          = TYPE_HIGHBANK_REGISTERS,
 177     .parent        = TYPE_SYS_BUS_DEVICE,
 178     .instance_size = sizeof(HighbankRegsState),
 179     .class_init    = highbank_regs_class_init,
 180 };
 181
 182 static void highbank_regs_register_types(void)
 183 {
 184     type_register_static(&highbank_regs_info);
 185 }
 186
 187 type_init(highbank_regs_register_types)
 188
 189 static struct arm_boot_info highbank_binfo;
 190
 191 enum cxmachines {
 192     CALXEDA_HIGHBANK,
 193     CALXEDA_MIDWAY,
 194 };
 195
 196 /* ram_size must be set to match the upper bound of memory in the
 197  * device tree (linux/arch/arm/boot/dts/highbank.dts), which is
 198  * normally 0xff900000 or -m 4089. When running this board on a
 199  * 32-bit host, set the reg value of memory to 0xf7ff00000 in the
 200  * device tree and pass -m 2047 to QEMU.
 201  */
 202 static void calxeda_init(MachineState *machine, enum cxmachines machine_id)
 203 {
 204     ram_addr_t ram_size = machine->ram_size;
 205     const char *cpu_model = machine->cpu_model;
 206     const char *kernel_filename = machine->kernel_filename;
 207     const char *kernel_cmdline = machine->kernel_cmdline;
 208     const char *initrd_filename = machine->initrd_filename;
 209     DeviceState *dev = NULL;
 210     SysBusDevice *busdev;
 211     qemu_irq pic[128];
 212     int n;
 213     qemu_irq cpu_irq[4];
 214     MemoryRegion *sysram;
 215     MemoryRegion *dram;
 216     MemoryRegion *sysmem;
 217     char *sysboot_filename;
 218
 219     if (!cpu_model) {
 220         switch (machine_id) {
 221         case CALXEDA_HIGHBANK:
 222             cpu_model = "cortex-a9";
 223             break;
 224         case CALXEDA_MIDWAY:
 225             cpu_model = "cortex-a15";
 226             break;
 227         }
 228     }
 229
 230     for (n = 0; n < smp_cpus; n++) {
 231         ObjectClass *oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);
 232         Object *cpuobj;
 233         ARMCPU *cpu;
 234         Error *err = NULL;
 235
 236         if (!oc) {
 237             error_report("Unable to find CPU definition");
 238             exit(1);
 239         }
 240
 241         cpuobj = object_new(object_class_get_name(oc));
 242         cpu = ARM_CPU(cpuobj);
 243
 244         if (object_property_find(cpuobj, "reset-cbar", NULL)) {
 245             object_property_set_int(cpuobj, MPCORE_PERIPHBASE,
 246                                     "reset-cbar", &error_abort);
 247         }
 248         object_property_set_bool(cpuobj, true, "realized", &err);
 249         if (err) {
 250             error_report("%s", error_get_pretty(err));
 251             exit(1);
 252         }
 253         cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ);
 254     }
 255
 256     sysmem = get_system_memory();
 257     dram = g_new(MemoryRegion, 1);
 258     memory_region_init_ram(dram, NULL, "highbank.dram", ram_size);
 259     /* SDRAM at address zero.  */
 260     memory_region_add_subregion(sysmem, 0, dram);
 261
 262     sysram = g_new(MemoryRegion, 1);
 263     memory_region_init_ram(sysram, NULL, "highbank.sysram", 0x8000);
 264     memory_region_add_subregion(sysmem, 0xfff88000, sysram);
 265     if (bios_name != NULL) {
 266         sysboot_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 267         if (sysboot_filename != NULL) {
 268             uint32_t filesize = get_image_size(sysboot_filename);
 269             if (load_image_targphys("sysram.bin", 0xfff88000, filesize) < 0) {
 270                 hw_error("Unable to load %s\n", bios_name);
 271             }
 272         } else {
 273            hw_error("Unable to find %s\n", bios_name);
 274         }
 275     }
 276
 277     switch (machine_id) {
 278     case CALXEDA_HIGHBANK:
 279         dev = qdev_create(NULL, "l2x0");
 280         qdev_init_nofail(dev);
 281         busdev = SYS_BUS_DEVICE(dev);
 282         sysbus_mmio_map(busdev, 0, 0xfff12000);
 283
 284         dev = qdev_create(NULL, "a9mpcore_priv");
 285         break;
 286     case CALXEDA_MIDWAY:
 287         dev = qdev_create(NULL, "a15mpcore_priv");
 288         break;
 289     }
 290     qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
 291     qdev_prop_set_uint32(dev, "num-irq", NIRQ_GIC);
 292     qdev_init_nofail(dev);
 293     busdev = SYS_BUS_DEVICE(dev);
 294     sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
 295     for (n = 0; n < smp_cpus; n++) {
 296         sysbus_connect_irq(busdev, n, cpu_irq[n]);
 297     }
 298
 299     for (n = 0; n < 128; n++) {
 300         pic[n] = qdev_get_gpio_in(dev, n);
 301     }
 302
 303     dev = qdev_create(NULL, "sp804");
 304     qdev_prop_set_uint32(dev, "freq0", 150000000);
 305     qdev_prop_set_uint32(dev, "freq1", 150000000);
 306     qdev_init_nofail(dev);
 307     busdev = SYS_BUS_DEVICE(dev);
 308     sysbus_mmio_map(busdev, 0, 0xfff34000);
 309     sysbus_connect_irq(busdev, 0, pic[18]);
 310     sysbus_create_simple("pl011", 0xfff36000, pic[20]);
 311
 312     dev = qdev_create(NULL, "highbank-regs");
 313     qdev_init_nofail(dev);
 314     busdev = SYS_BUS_DEVICE(dev);
 315     sysbus_mmio_map(busdev, 0, 0xfff3c000);
 316
 317     sysbus_create_simple("pl061", 0xfff30000, pic[14]);
 318     sysbus_create_simple("pl061", 0xfff31000, pic[15]);
 319     sysbus_create_simple("pl061", 0xfff32000, pic[16]);
 320     sysbus_create_simple("pl061", 0xfff33000, pic[17]);
 321     sysbus_create_simple("pl031", 0xfff35000, pic[19]);
 322     sysbus_create_simple("pl022", 0xfff39000, pic[23]);
 323
 324     sysbus_create_simple("sysbus-ahci", 0xffe08000, pic[83]);
 325
 326     if (nd_table[0].used) {
 327         qemu_check_nic_model(&nd_table[0], "xgmac");
 328         dev = qdev_create(NULL, "xgmac");
 329         qdev_set_nic_properties(dev, &nd_table[0]);
 330         qdev_init_nofail(dev);
 331         sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff50000);
 332         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[77]);
 333         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[78]);
 334         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[79]);
 335
 336         qemu_check_nic_model(&nd_table[1], "xgmac");
 337         dev = qdev_create(NULL, "xgmac");
 338         qdev_set_nic_properties(dev, &nd_table[1]);
 339         qdev_init_nofail(dev);
 340         sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff51000);
 341         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[80]);
 342         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[81]);
 343         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[82]);
 344     }
 345
 346     highbank_binfo.ram_size = ram_size;
 347     highbank_binfo.kernel_filename = kernel_filename;
 348     highbank_binfo.kernel_cmdline = kernel_cmdline;
 349     highbank_binfo.initrd_filename = initrd_filename;
 350     /* highbank requires a dtb in order to boot, and the dtb will override
 351      * the board ID. The following value is ignored, so set it to -1 to be
 352      * clear that the value is meaningless.
 353      */
 354     highbank_binfo.board_id = -1;
 355     highbank_binfo.nb_cpus = smp_cpus;
 356     highbank_binfo.loader_start = 0;
 357     highbank_binfo.write_secondary_boot = hb_write_secondary;
 358     highbank_binfo.secondary_cpu_reset_hook = hb_reset_secondary;
 359     arm_load_kernel(ARM_CPU(first_cpu), &highbank_binfo);
 360 }
 361
 362 static void highbank_init(MachineState *machine)
 363 {
 364     calxeda_init(machine, CALXEDA_HIGHBANK);
 365 }
 366
 367 static void midway_init(MachineState *machine)
 368 {
 369     calxeda_init(machine, CALXEDA_MIDWAY);
 370 }
 371
 372 static QEMUMachine highbank_machine = {
 373     .name = "highbank",
 374     .desc = "Calxeda Highbank (ECX-1000)",
 375     .init = highbank_init,
 376     .block_default_type = IF_SCSI,
 377     .max_cpus = 4,
 378 };
 379
 380 static QEMUMachine midway_machine = {
 381     .name = "midway",
 382     .desc = "Calxeda Midway (ECX-2000)",
 383     .init = midway_init,
 384     .block_default_type = IF_SCSI,
 385     .max_cpus = 4,
 386 };
 387
 388 static void calxeda_machines_init(void)
 389 {
 390     qemu_register_machine(&highbank_machine);
 391     qemu_register_machine(&midway_machine);
 392 }
 393
 394 machine_init(calxeda_machines_init);