target-arm/cpu64.c

   1 /*
   2  * QEMU AArch64 CPU
   3  *
   4  * Copyright (c) 2013 Linaro Ltd
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  */
  20
  21 #include "cpu.h"
  22 #include "qemu-common.h"
  23 #if !defined(CONFIG_USER_ONLY)
  24 #include "hw/loader.h"
  25 #endif
  26 #include "hw/arm/arm.h"
  27 #include "sysemu/sysemu.h"
  28 #include "sysemu/kvm.h"
  29
  30 static inline void set_feature(CPUARMState *env, int feature)
  31 {
  32     env->features |= 1ULL << feature;
  33 }
  34
  35 static inline void unset_feature(CPUARMState *env, int feature)
  36 {
  37     env->features &= ~(1ULL << feature);
  38 }
  39
  40 #ifndef CONFIG_USER_ONLY
  41 static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
  42 {
  43     /* Number of processors is in [25:24]; otherwise we RAZ */
  44     return (smp_cpus - 1) << 24;
  45 }
  46 #endif
  47
  48 static const ARMCPRegInfo cortex_a57_a53_cp_reginfo[] = {
  49 #ifndef CONFIG_USER_ONLY
  50     { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
  51       .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
  52       .access = PL1_RW, .readfn = a57_a53_l2ctlr_read,
  53       .writefn = arm_cp_write_ignore },
  54     { .name = "L2CTLR",
  55       .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
  56       .access = PL1_RW, .readfn = a57_a53_l2ctlr_read,
  57       .writefn = arm_cp_write_ignore },
  58 #endif
  59     { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
  60       .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
  61       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
  62     { .name = "L2ECTLR",
  63       .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
  64       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
  65     { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH,
  66       .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
  67       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
  68     { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
  69       .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
  70       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
  71     { .name = "CPUACTLR",
  72       .cp = 15, .opc1 = 0, .crm = 15,
  73       .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
  74     { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
  75       .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
  76       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
  77     { .name = "CPUECTLR",
  78       .cp = 15, .opc1 = 1, .crm = 15,
  79       .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
  80     { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64,
  81       .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
  82       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
  83     { .name = "CPUMERRSR",
  84       .cp = 15, .opc1 = 2, .crm = 15,
  85       .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
  86     { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64,
  87       .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3,
  88       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
  89     { .name = "L2MERRSR",
  90       .cp = 15, .opc1 = 3, .crm = 15,
  91       .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
  92     REGINFO_SENTINEL
  93 };
  94
  95 static void aarch64_a57_initfn(Object *obj)
  96 {
  97     ARMCPU *cpu = ARM_CPU(obj);
  98
  99     cpu->dtb_compatible = "arm,cortex-a57";
 100     set_feature(&cpu->env, ARM_FEATURE_V8);
 101     set_feature(&cpu->env, ARM_FEATURE_VFP4);
 102     set_feature(&cpu->env, ARM_FEATURE_NEON);
 103     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 104     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 105     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 106     set_feature(&cpu->env, ARM_FEATURE_V8_AES);
 107     set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
 108     set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
 109     set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
 110     set_feature(&cpu->env, ARM_FEATURE_CRC);
 111     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
 112     cpu->midr = 0x411fd070;
 113     cpu->reset_fpsid = 0x41034070;
 114     cpu->mvfr0 = 0x10110222;
 115     cpu->mvfr1 = 0x12111111;
 116     cpu->mvfr2 = 0x00000043;
 117     cpu->ctr = 0x8444c004;
 118     cpu->reset_sctlr = 0x00c50838;
 119     cpu->id_pfr0 = 0x00000131;
 120     cpu->id_pfr1 = 0x00011011;
 121     cpu->id_dfr0 = 0x03010066;
 122     cpu->id_afr0 = 0x00000000;
 123     cpu->id_mmfr0 = 0x10101105;
 124     cpu->id_mmfr1 = 0x40000000;
 125     cpu->id_mmfr2 = 0x01260000;
 126     cpu->id_mmfr3 = 0x02102211;
 127     cpu->id_isar0 = 0x02101110;
 128     cpu->id_isar1 = 0x13112111;
 129     cpu->id_isar2 = 0x21232042;
 130     cpu->id_isar3 = 0x01112131;
 131     cpu->id_isar4 = 0x00011142;
 132     cpu->id_isar5 = 0x00011121;
 133     cpu->id_aa64pfr0 = 0x00002222;
 134     cpu->id_aa64dfr0 = 0x10305106;
 135     cpu->id_aa64isar0 = 0x00011120;
 136     cpu->id_aa64mmfr0 = 0x00001124;
 137     cpu->dbgdidr = 0x3516d000;
 138     cpu->clidr = 0x0a200023;
 139     cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
 140     cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
 141     cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
 142     cpu->dcz_blocksize = 4; /* 64 bytes */
 143     define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo);
 144 }
 145
 146 static void aarch64_a53_initfn(Object *obj)
 147 {
 148     ARMCPU *cpu = ARM_CPU(obj);
 149
 150     cpu->dtb_compatible = "arm,cortex-a53";
 151     set_feature(&cpu->env, ARM_FEATURE_V8);
 152     set_feature(&cpu->env, ARM_FEATURE_VFP4);
 153     set_feature(&cpu->env, ARM_FEATURE_NEON);
 154     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 155     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 156     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 157     set_feature(&cpu->env, ARM_FEATURE_V8_AES);
 158     set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
 159     set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
 160     set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
 161     set_feature(&cpu->env, ARM_FEATURE_CRC);
 162     cpu->midr = 0x410fd034;
 163     cpu->reset_fpsid = 0x41034070;
 164     cpu->mvfr0 = 0x10110222;
 165     cpu->mvfr1 = 0x12111111;
 166     cpu->mvfr2 = 0x00000043;
 167     cpu->ctr = 0x84448004; /* L1Ip = VIPT */
 168     cpu->reset_sctlr = 0x00c50838;
 169     cpu->id_pfr0 = 0x00000131;
 170     cpu->id_pfr1 = 0x00011011;
 171     cpu->id_dfr0 = 0x03010066;
 172     cpu->id_afr0 = 0x00000000;
 173     cpu->id_mmfr0 = 0x10101105;
 174     cpu->id_mmfr1 = 0x40000000;
 175     cpu->id_mmfr2 = 0x01260000;
 176     cpu->id_mmfr3 = 0x02102211;
 177     cpu->id_isar0 = 0x02101110;
 178     cpu->id_isar1 = 0x13112111;
 179     cpu->id_isar2 = 0x21232042;
 180     cpu->id_isar3 = 0x01112131;
 181     cpu->id_isar4 = 0x00011142;
 182     cpu->id_isar5 = 0x00011121;
 183     cpu->id_aa64pfr0 = 0x00002222;
 184     cpu->id_aa64dfr0 = 0x10305106;
 185     cpu->id_aa64isar0 = 0x00011120;
 186     cpu->id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
 187     cpu->dbgdidr = 0x3516d000;
 188     cpu->clidr = 0x0a200023;
 189     cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
 190     cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
 191     cpu->ccsidr[2] = 0x707fe07a; /* 1024KB L2 cache */
 192     cpu->dcz_blocksize = 4; /* 64 bytes */
 193     define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo);
 194 }
 195
 196 #ifdef CONFIG_USER_ONLY
 197 static void aarch64_any_initfn(Object *obj)
 198 {
 199     ARMCPU *cpu = ARM_CPU(obj);
 200
 201     set_feature(&cpu->env, ARM_FEATURE_V8);
 202     set_feature(&cpu->env, ARM_FEATURE_VFP4);
 203     set_feature(&cpu->env, ARM_FEATURE_NEON);
 204     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 205     set_feature(&cpu->env, ARM_FEATURE_V8_AES);
 206     set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
 207     set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
 208     set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
 209     set_feature(&cpu->env, ARM_FEATURE_CRC);
 210     cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
 211     cpu->dcz_blocksize = 7; /*  512 bytes */
 212 }
 213 #endif
 214
 215 typedef struct ARMCPUInfo {
 216     const char *name;
 217     void (*initfn)(Object *obj);
 218     void (*class_init)(ObjectClass *oc, void *data);
 219 } ARMCPUInfo;
 220
 221 static const ARMCPUInfo aarch64_cpus[] = {
 222     { .name = "cortex-a57",         .initfn = aarch64_a57_initfn },
 223     { .name = "cortex-a53",         .initfn = aarch64_a53_initfn },
 224 #ifdef CONFIG_USER_ONLY
 225     { .name = "any",         .initfn = aarch64_any_initfn },
 226 #endif
 227     { .name = NULL }
 228 };
 229
 230 static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp)
 231 {
 232     ARMCPU *cpu = ARM_CPU(obj);
 233
 234     return arm_feature(&cpu->env, ARM_FEATURE_AARCH64);
 235 }
 236
 237 static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp)
 238 {
 239     ARMCPU *cpu = ARM_CPU(obj);
 240
 241     /* At this time, this property is only allowed if KVM is enabled.  This
 242      * restriction allows us to avoid fixing up functionality that assumes a
 243      * uniform execution state like do_interrupt.
 244      */
 245     if (!kvm_enabled()) {
 246         error_setg(errp, "'aarch64' feature cannot be disabled "
 247                          "unless KVM is enabled");
 248         return;
 249     }
 250
 251     if (value == false) {
 252         unset_feature(&cpu->env, ARM_FEATURE_AARCH64);
 253     } else {
 254         set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 255     }
 256 }
 257
 258 static void aarch64_cpu_initfn(Object *obj)
 259 {
 260     object_property_add_bool(obj, "aarch64", aarch64_cpu_get_aarch64,
 261                              aarch64_cpu_set_aarch64, NULL);
 262     object_property_set_description(obj, "aarch64",
 263                                     "Set on/off to enable/disable aarch64 "
 264                                     "execution state ",
 265                                     NULL);
 266 }
 267
 268 static void aarch64_cpu_finalizefn(Object *obj)
 269 {
 270 }
 271
 272 static void aarch64_cpu_set_pc(CPUState *cs, vaddr value)
 273 {
 274     ARMCPU *cpu = ARM_CPU(cs);
 275     /* It's OK to look at env for the current mode here, because it's
 276      * never possible for an AArch64 TB to chain to an AArch32 TB.
 277      * (Otherwise we would need to use synchronize_from_tb instead.)
 278      */
 279     if (is_a64(&cpu->env)) {
 280         cpu->env.pc = value;
 281     } else {
 282         cpu->env.regs[15] = value;
 283     }
 284 }
 285
 286 static void aarch64_cpu_class_init(ObjectClass *oc, void *data)
 287 {
 288     CPUClass *cc = CPU_CLASS(oc);
 289
 290 #if !defined(CONFIG_USER_ONLY)
 291     cc->do_interrupt = aarch64_cpu_do_interrupt;
 292 #endif
 293     cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
 294     cc->set_pc = aarch64_cpu_set_pc;
 295     cc->gdb_read_register = aarch64_cpu_gdb_read_register;
 296     cc->gdb_write_register = aarch64_cpu_gdb_write_register;
 297     cc->gdb_num_core_regs = 34;
 298     cc->gdb_core_xml_file = "aarch64-core.xml";
 299 }
 300
 301 static void aarch64_cpu_register(const ARMCPUInfo *info)
 302 {
 303     TypeInfo type_info = {
 304         .parent = TYPE_AARCH64_CPU,
 305         .instance_size = sizeof(ARMCPU),
 306         .instance_init = info->initfn,
 307         .class_size = sizeof(ARMCPUClass),
 308         .class_init = info->class_init,
 309     };
 310
 311     type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
 312     type_register(&type_info);
 313     g_free((void *)type_info.name);
 314 }
 315
 316 static const TypeInfo aarch64_cpu_type_info = {
 317     .name = TYPE_AARCH64_CPU,
 318     .parent = TYPE_ARM_CPU,
 319     .instance_size = sizeof(ARMCPU),
 320     .instance_init = aarch64_cpu_initfn,
 321     .instance_finalize = aarch64_cpu_finalizefn,
 322     .abstract = true,
 323     .class_size = sizeof(AArch64CPUClass),
 324     .class_init = aarch64_cpu_class_init,
 325 };
 326
 327 static void aarch64_cpu_register_types(void)
 328 {
 329     const ARMCPUInfo *info = aarch64_cpus;
 330
 331     type_register_static(&aarch64_cpu_type_info);
 332
 333     while (info->name) {
 334         aarch64_cpu_register(info);
 335         info++;
 336     }
 337 }
 338
 339 type_init(aarch64_cpu_register_types)