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hw/display: QOM'ify milkymist-vgafb.c
[qemu.git] / target-i386 / kvm.c
blobff92b1d118e1d516cc21731fd3c464a44eb1beeb
1 /*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15 #include "qemu/osdep.h"
16 #include "qapi/error.h"
17 #include <sys/ioctl.h>
18 #include <sys/utsname.h>
19
20 #include <linux/kvm.h>
21 #include <linux/kvm_para.h>
22
23 #include "qemu-common.h"
24 #include "cpu.h"
25 #include "sysemu/sysemu.h"
26 #include "sysemu/kvm_int.h"
27 #include "kvm_i386.h"
28 #include "hyperv.h"
29
30 #include "exec/gdbstub.h"
31 #include "qemu/host-utils.h"
32 #include "qemu/config-file.h"
33 #include "qemu/error-report.h"
34 #include "hw/i386/pc.h"
35 #include "hw/i386/apic.h"
36 #include "hw/i386/apic_internal.h"
37 #include "hw/i386/apic-msidef.h"
38
39 #include "exec/ioport.h"
40 #include "standard-headers/asm-x86/hyperv.h"
41 #include "hw/pci/pci.h"
42 #include "hw/pci/msi.h"
43 #include "migration/migration.h"
44 #include "exec/memattrs.h"
45
46 //#define DEBUG_KVM
47
48 #ifdef DEBUG_KVM
49 #define DPRINTF(fmt, ...) \
50 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
51 #else
52 #define DPRINTF(fmt, ...) \
53 do { } while (0)
54 #endif
55
56 #define MSR_KVM_WALL_CLOCK 0x11
57 #define MSR_KVM_SYSTEM_TIME 0x12
58
59 /* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
60 * 255 kvm_msr_entry structs */
61 #define MSR_BUF_SIZE 4096
62
63 #ifndef BUS_MCEERR_AR
64 #define BUS_MCEERR_AR 4
65 #endif
66 #ifndef BUS_MCEERR_AO
67 #define BUS_MCEERR_AO 5
68 #endif
69
70 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
71 KVM_CAP_INFO(SET_TSS_ADDR),
72 KVM_CAP_INFO(EXT_CPUID),
73 KVM_CAP_INFO(MP_STATE),
74 KVM_CAP_LAST_INFO
75 };
76
77 static bool has_msr_star;
78 static bool has_msr_hsave_pa;
79 static bool has_msr_tsc_aux;
80 static bool has_msr_tsc_adjust;
81 static bool has_msr_tsc_deadline;
82 static bool has_msr_feature_control;
83 static bool has_msr_async_pf_en;
84 static bool has_msr_pv_eoi_en;
85 static bool has_msr_misc_enable;
86 static bool has_msr_smbase;
87 static bool has_msr_bndcfgs;
88 static bool has_msr_kvm_steal_time;
89 static int lm_capable_kernel;
90 static bool has_msr_hv_hypercall;
91 static bool has_msr_hv_vapic;
92 static bool has_msr_hv_tsc;
93 static bool has_msr_hv_crash;
94 static bool has_msr_hv_reset;
95 static bool has_msr_hv_vpindex;
96 static bool has_msr_hv_runtime;
97 static bool has_msr_hv_synic;
98 static bool has_msr_hv_stimer;
99 static bool has_msr_mtrr;
100 static bool has_msr_xss;
101
102 static bool has_msr_architectural_pmu;
103 static uint32_t num_architectural_pmu_counters;
104
105 static int has_xsave;
106 static int has_xcrs;
107 static int has_pit_state2;
108
109 static struct kvm_cpuid2 *cpuid_cache;
110
111 int kvm_has_pit_state2(void)
112 {
113 return has_pit_state2;
114 }
115
116 bool kvm_has_smm(void)
117 {
118 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
119 }
120
121 bool kvm_allows_irq0_override(void)
122 {
123 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
124 }
125
126 static int kvm_get_tsc(CPUState *cs)
127 {
128 X86CPU *cpu = X86_CPU(cs);
129 CPUX86State *env = &cpu->env;
130 struct {
131 struct kvm_msrs info;
132 struct kvm_msr_entry entries[1];
133 } msr_data;
134 int ret;
135
136 if (env->tsc_valid) {
137 return 0;
138 }
139
140 msr_data.info.nmsrs = 1;
141 msr_data.entries[0].index = MSR_IA32_TSC;
142 env->tsc_valid = !runstate_is_running();
143
144 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
145 if (ret < 0) {
146 return ret;
147 }
148
149 assert(ret == 1);
150 env->tsc = msr_data.entries[0].data;
151 return 0;
152 }
153
154 static inline void do_kvm_synchronize_tsc(void *arg)
155 {
156 CPUState *cpu = arg;
157
158 kvm_get_tsc(cpu);
159 }
160
161 void kvm_synchronize_all_tsc(void)
162 {
163 CPUState *cpu;
164
165 if (kvm_enabled()) {
166 CPU_FOREACH(cpu) {
167 run_on_cpu(cpu, do_kvm_synchronize_tsc, cpu);
168 }
169 }
170 }
171
172 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
173 {
174 struct kvm_cpuid2 *cpuid;
175 int r, size;
176
177 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
178 cpuid = g_malloc0(size);
179 cpuid->nent = max;
180 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
181 if (r == 0 && cpuid->nent >= max) {
182 r = -E2BIG;
183 }
184 if (r < 0) {
185 if (r == -E2BIG) {
186 g_free(cpuid);
187 return NULL;
188 } else {
189 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
190 strerror(-r));
191 exit(1);
192 }
193 }
194 return cpuid;
195 }
196
197 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
198 * for all entries.
199 */
200 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
201 {
202 struct kvm_cpuid2 *cpuid;
203 int max = 1;
204
205 if (cpuid_cache != NULL) {
206 return cpuid_cache;
207 }
208 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
209 max *= 2;
210 }
211 cpuid_cache = cpuid;
212 return cpuid;
213 }
214
215 static const struct kvm_para_features {
216 int cap;
217 int feature;
218 } para_features[] = {
219 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
220 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
221 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
222 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
223 };
224
225 static int get_para_features(KVMState *s)
226 {
227 int i, features = 0;
228
229 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
230 if (kvm_check_extension(s, para_features[i].cap)) {
231 features |= (1 << para_features[i].feature);
232 }
233 }
234
235 return features;
236 }
237
238
239 /* Returns the value for a specific register on the cpuid entry
240 */
241 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
242 {
243 uint32_t ret = 0;
244 switch (reg) {
245 case R_EAX:
246 ret = entry->eax;
247 break;
248 case R_EBX:
249 ret = entry->ebx;
250 break;
251 case R_ECX:
252 ret = entry->ecx;
253 break;
254 case R_EDX:
255 ret = entry->edx;
256 break;
257 }
258 return ret;
259 }
260
261 /* Find matching entry for function/index on kvm_cpuid2 struct
262 */
263 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
264 uint32_t function,
265 uint32_t index)
266 {
267 int i;
268 for (i = 0; i < cpuid->nent; ++i) {
269 if (cpuid->entries[i].function == function &&
270 cpuid->entries[i].index == index) {
271 return &cpuid->entries[i];
272 }
273 }
274 /* not found: */
275 return NULL;
276 }
277
278 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
279 uint32_t index, int reg)
280 {
281 struct kvm_cpuid2 *cpuid;
282 uint32_t ret = 0;
283 uint32_t cpuid_1_edx;
284 bool found = false;
285
286 cpuid = get_supported_cpuid(s);
287
288 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
289 if (entry) {
290 found = true;
291 ret = cpuid_entry_get_reg(entry, reg);
292 }
293
294 /* Fixups for the data returned by KVM, below */
295
296 if (function == 1 && reg == R_EDX) {
297 /* KVM before 2.6.30 misreports the following features */
298 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
299 } else if (function == 1 && reg == R_ECX) {
300 /* We can set the hypervisor flag, even if KVM does not return it on
301 * GET_SUPPORTED_CPUID
302 */
303 ret |= CPUID_EXT_HYPERVISOR;
304 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
305 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
306 * and the irqchip is in the kernel.
307 */
308 if (kvm_irqchip_in_kernel() &&
309 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
310 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
311 }
312
313 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
314 * without the in-kernel irqchip
315 */
316 if (!kvm_irqchip_in_kernel()) {
317 ret &= ~CPUID_EXT_X2APIC;
318 }
319 } else if (function == 6 && reg == R_EAX) {
320 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
321 } else if (function == 0x80000001 && reg == R_EDX) {
322 /* On Intel, kvm returns cpuid according to the Intel spec,
323 * so add missing bits according to the AMD spec:
324 */
325 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
326 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
327 }
328
329 /* fallback for older kernels */
330 if ((function == KVM_CPUID_FEATURES) && !found) {
331 ret = get_para_features(s);
332 }
333
334 return ret;
335 }
336
337 typedef struct HWPoisonPage {
338 ram_addr_t ram_addr;
339 QLIST_ENTRY(HWPoisonPage) list;
340 } HWPoisonPage;
341
342 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
343 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
344
345 static void kvm_unpoison_all(void *param)
346 {
347 HWPoisonPage *page, *next_page;
348
349 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
350 QLIST_REMOVE(page, list);
351 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
352 g_free(page);
353 }
354 }
355
356 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
357 {
358 HWPoisonPage *page;
359
360 QLIST_FOREACH(page, &hwpoison_page_list, list) {
361 if (page->ram_addr == ram_addr) {
362 return;
363 }
364 }
365 page = g_new(HWPoisonPage, 1);
366 page->ram_addr = ram_addr;
367 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
368 }
369
370 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
371 int *max_banks)
372 {
373 int r;
374
375 r = kvm_check_extension(s, KVM_CAP_MCE);
376 if (r > 0) {
377 *max_banks = r;
378 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
379 }
380 return -ENOSYS;
381 }
382
383 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
384 {
385 CPUX86State *env = &cpu->env;
386 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
387 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
388 uint64_t mcg_status = MCG_STATUS_MCIP;
389
390 if (code == BUS_MCEERR_AR) {
391 status |= MCI_STATUS_AR | 0x134;
392 mcg_status |= MCG_STATUS_EIPV;
393 } else {
394 status |= 0xc0;
395 mcg_status |= MCG_STATUS_RIPV;
396 }
397 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
398 (MCM_ADDR_PHYS << 6) | 0xc,
399 cpu_x86_support_mca_broadcast(env) ?
400 MCE_INJECT_BROADCAST : 0);
401 }
402
403 static void hardware_memory_error(void)
404 {
405 fprintf(stderr, "Hardware memory error!\n");
406 exit(1);
407 }
408
409 int kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
410 {
411 X86CPU *cpu = X86_CPU(c);
412 CPUX86State *env = &cpu->env;
413 ram_addr_t ram_addr;
414 hwaddr paddr;
415
416 if ((env->mcg_cap & MCG_SER_P) && addr
417 && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
418 ram_addr = qemu_ram_addr_from_host(addr);
419 if (ram_addr == RAM_ADDR_INVALID ||
420 !kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
421 fprintf(stderr, "Hardware memory error for memory used by "
422 "QEMU itself instead of guest system!\n");
423 /* Hope we are lucky for AO MCE */
424 if (code == BUS_MCEERR_AO) {
425 return 0;
426 } else {
427 hardware_memory_error();
428 }
429 }
430 kvm_hwpoison_page_add(ram_addr);
431 kvm_mce_inject(cpu, paddr, code);
432 } else {
433 if (code == BUS_MCEERR_AO) {
434 return 0;
435 } else if (code == BUS_MCEERR_AR) {
436 hardware_memory_error();
437 } else {
438 return 1;
439 }
440 }
441 return 0;
442 }
443
444 int kvm_arch_on_sigbus(int code, void *addr)
445 {
446 X86CPU *cpu = X86_CPU(first_cpu);
447
448 if ((cpu->env.mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
449 ram_addr_t ram_addr;
450 hwaddr paddr;
451
452 /* Hope we are lucky for AO MCE */
453 ram_addr = qemu_ram_addr_from_host(addr);
454 if (ram_addr == RAM_ADDR_INVALID ||
455 !kvm_physical_memory_addr_from_host(first_cpu->kvm_state,
456 addr, &paddr)) {
457 fprintf(stderr, "Hardware memory error for memory used by "
458 "QEMU itself instead of guest system!: %p\n", addr);
459 return 0;
460 }
461 kvm_hwpoison_page_add(ram_addr);
462 kvm_mce_inject(X86_CPU(first_cpu), paddr, code);
463 } else {
464 if (code == BUS_MCEERR_AO) {
465 return 0;
466 } else if (code == BUS_MCEERR_AR) {
467 hardware_memory_error();
468 } else {
469 return 1;
470 }
471 }
472 return 0;
473 }
474
475 static int kvm_inject_mce_oldstyle(X86CPU *cpu)
476 {
477 CPUX86State *env = &cpu->env;
478
479 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
480 unsigned int bank, bank_num = env->mcg_cap & 0xff;
481 struct kvm_x86_mce mce;
482
483 env->exception_injected = -1;
484
485 /*
486 * There must be at least one bank in use if an MCE is pending.
487 * Find it and use its values for the event injection.
488 */
489 for (bank = 0; bank < bank_num; bank++) {
490 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
491 break;
492 }
493 }
494 assert(bank < bank_num);
495
496 mce.bank = bank;
497 mce.status = env->mce_banks[bank * 4 + 1];
498 mce.mcg_status = env->mcg_status;
499 mce.addr = env->mce_banks[bank * 4 + 2];
500 mce.misc = env->mce_banks[bank * 4 + 3];
501
502 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
503 }
504 return 0;
505 }
506
507 static void cpu_update_state(void *opaque, int running, RunState state)
508 {
509 CPUX86State *env = opaque;
510
511 if (running) {
512 env->tsc_valid = false;
513 }
514 }
515
516 unsigned long kvm_arch_vcpu_id(CPUState *cs)
517 {
518 X86CPU *cpu = X86_CPU(cs);
519 return cpu->apic_id;
520 }
521
522 #ifndef KVM_CPUID_SIGNATURE_NEXT
523 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100
524 #endif
525
526 static bool hyperv_hypercall_available(X86CPU *cpu)
527 {
528 return cpu->hyperv_vapic ||
529 (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
530 }
531
532 static bool hyperv_enabled(X86CPU *cpu)
533 {
534 CPUState *cs = CPU(cpu);
535 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
536 (hyperv_hypercall_available(cpu) ||
537 cpu->hyperv_time ||
538 cpu->hyperv_relaxed_timing ||
539 cpu->hyperv_crash ||
540 cpu->hyperv_reset ||
541 cpu->hyperv_vpindex ||
542 cpu->hyperv_runtime ||
543 cpu->hyperv_synic ||
544 cpu->hyperv_stimer);
545 }
546
547 static int kvm_arch_set_tsc_khz(CPUState *cs)
548 {
549 X86CPU *cpu = X86_CPU(cs);
550 CPUX86State *env = &cpu->env;
551 int r;
552
553 if (!env->tsc_khz) {
554 return 0;
555 }
556
557 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL) ?
558 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
559 -ENOTSUP;
560 if (r < 0) {
561 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
562 * TSC frequency doesn't match the one we want.
563 */
564 int cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
565 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
566 -ENOTSUP;
567 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
568 error_report("warning: TSC frequency mismatch between "
569 "VM and host, and TSC scaling unavailable");
570 return r;
571 }
572 }
573
574 return 0;
575 }
576
577 static Error *invtsc_mig_blocker;
578
579 #define KVM_MAX_CPUID_ENTRIES 100
580
581 int kvm_arch_init_vcpu(CPUState *cs)
582 {
583 struct {
584 struct kvm_cpuid2 cpuid;
585 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
586 } QEMU_PACKED cpuid_data;
587 X86CPU *cpu = X86_CPU(cs);
588 CPUX86State *env = &cpu->env;
589 uint32_t limit, i, j, cpuid_i;
590 uint32_t unused;
591 struct kvm_cpuid_entry2 *c;
592 uint32_t signature[3];
593 int kvm_base = KVM_CPUID_SIGNATURE;
594 int r;
595
596 memset(&cpuid_data, 0, sizeof(cpuid_data));
597
598 cpuid_i = 0;
599
600 /* Paravirtualization CPUIDs */
601 if (hyperv_enabled(cpu)) {
602 c = &cpuid_data.entries[cpuid_i++];
603 c->function = HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
604 if (!cpu->hyperv_vendor_id) {
605 memcpy(signature, "Microsoft Hv", 12);
606 } else {
607 size_t len = strlen(cpu->hyperv_vendor_id);
608
609 if (len > 12) {
610 error_report("hv-vendor-id truncated to 12 characters");
611 len = 12;
612 }
613 memset(signature, 0, 12);
614 memcpy(signature, cpu->hyperv_vendor_id, len);
615 }
616 c->eax = HYPERV_CPUID_MIN;
617 c->ebx = signature[0];
618 c->ecx = signature[1];
619 c->edx = signature[2];
620
621 c = &cpuid_data.entries[cpuid_i++];
622 c->function = HYPERV_CPUID_INTERFACE;
623 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
624 c->eax = signature[0];
625 c->ebx = 0;
626 c->ecx = 0;
627 c->edx = 0;
628
629 c = &cpuid_data.entries[cpuid_i++];
630 c->function = HYPERV_CPUID_VERSION;
631 c->eax = 0x00001bbc;
632 c->ebx = 0x00060001;
633
634 c = &cpuid_data.entries[cpuid_i++];
635 c->function = HYPERV_CPUID_FEATURES;
636 if (cpu->hyperv_relaxed_timing) {
637 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
638 }
639 if (cpu->hyperv_vapic) {
640 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
641 c->eax |= HV_X64_MSR_APIC_ACCESS_AVAILABLE;
642 has_msr_hv_vapic = true;
643 }
644 if (cpu->hyperv_time &&
645 kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) {
646 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
647 c->eax |= HV_X64_MSR_TIME_REF_COUNT_AVAILABLE;
648 c->eax |= 0x200;
649 has_msr_hv_tsc = true;
650 }
651 if (cpu->hyperv_crash && has_msr_hv_crash) {
652 c->edx |= HV_X64_GUEST_CRASH_MSR_AVAILABLE;
653 }
654 c->edx |= HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
655 if (cpu->hyperv_reset && has_msr_hv_reset) {
656 c->eax |= HV_X64_MSR_RESET_AVAILABLE;
657 }
658 if (cpu->hyperv_vpindex && has_msr_hv_vpindex) {
659 c->eax |= HV_X64_MSR_VP_INDEX_AVAILABLE;
660 }
661 if (cpu->hyperv_runtime && has_msr_hv_runtime) {
662 c->eax |= HV_X64_MSR_VP_RUNTIME_AVAILABLE;
663 }
664 if (cpu->hyperv_synic) {
665 int sint;
666
667 if (!has_msr_hv_synic ||
668 kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_SYNIC, 0)) {
669 fprintf(stderr, "Hyper-V SynIC is not supported by kernel\n");
670 return -ENOSYS;
671 }
672
673 c->eax |= HV_X64_MSR_SYNIC_AVAILABLE;
674 env->msr_hv_synic_version = HV_SYNIC_VERSION_1;
675 for (sint = 0; sint < ARRAY_SIZE(env->msr_hv_synic_sint); sint++) {
676 env->msr_hv_synic_sint[sint] = HV_SYNIC_SINT_MASKED;
677 }
678 }
679 if (cpu->hyperv_stimer) {
680 if (!has_msr_hv_stimer) {
681 fprintf(stderr, "Hyper-V timers aren't supported by kernel\n");
682 return -ENOSYS;
683 }
684 c->eax |= HV_X64_MSR_SYNTIMER_AVAILABLE;
685 }
686 c = &cpuid_data.entries[cpuid_i++];
687 c->function = HYPERV_CPUID_ENLIGHTMENT_INFO;
688 if (cpu->hyperv_relaxed_timing) {
689 c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED;
690 }
691 if (has_msr_hv_vapic) {
692 c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED;
693 }
694 c->ebx = cpu->hyperv_spinlock_attempts;
695
696 c = &cpuid_data.entries[cpuid_i++];
697 c->function = HYPERV_CPUID_IMPLEMENT_LIMITS;
698 c->eax = 0x40;
699 c->ebx = 0x40;
700
701 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
702 has_msr_hv_hypercall = true;
703 }
704
705 if (cpu->expose_kvm) {
706 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
707 c = &cpuid_data.entries[cpuid_i++];
708 c->function = KVM_CPUID_SIGNATURE | kvm_base;
709 c->eax = KVM_CPUID_FEATURES | kvm_base;
710 c->ebx = signature[0];
711 c->ecx = signature[1];
712 c->edx = signature[2];
713
714 c = &cpuid_data.entries[cpuid_i++];
715 c->function = KVM_CPUID_FEATURES | kvm_base;
716 c->eax = env->features[FEAT_KVM];
717
718 has_msr_async_pf_en = c->eax & (1 << KVM_FEATURE_ASYNC_PF);
719
720 has_msr_pv_eoi_en = c->eax & (1 << KVM_FEATURE_PV_EOI);
721
722 has_msr_kvm_steal_time = c->eax & (1 << KVM_FEATURE_STEAL_TIME);
723 }
724
725 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
726
727 for (i = 0; i <= limit; i++) {
728 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
729 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
730 abort();
731 }
732 c = &cpuid_data.entries[cpuid_i++];
733
734 switch (i) {
735 case 2: {
736 /* Keep reading function 2 till all the input is received */
737 int times;
738
739 c->function = i;
740 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
741 KVM_CPUID_FLAG_STATE_READ_NEXT;
742 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
743 times = c->eax & 0xff;
744
745 for (j = 1; j < times; ++j) {
746 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
747 fprintf(stderr, "cpuid_data is full, no space for "
748 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
749 abort();
750 }
751 c = &cpuid_data.entries[cpuid_i++];
752 c->function = i;
753 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
754 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
755 }
756 break;
757 }
758 case 4:
759 case 0xb:
760 case 0xd:
761 for (j = 0; ; j++) {
762 if (i == 0xd && j == 64) {
763 break;
764 }
765 c->function = i;
766 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
767 c->index = j;
768 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
769
770 if (i == 4 && c->eax == 0) {
771 break;
772 }
773 if (i == 0xb && !(c->ecx & 0xff00)) {
774 break;
775 }
776 if (i == 0xd && c->eax == 0) {
777 continue;
778 }
779 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
780 fprintf(stderr, "cpuid_data is full, no space for "
781 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
782 abort();
783 }
784 c = &cpuid_data.entries[cpuid_i++];
785 }
786 break;
787 default:
788 c->function = i;
789 c->flags = 0;
790 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
791 break;
792 }
793 }
794
795 if (limit >= 0x0a) {
796 uint32_t ver;
797
798 cpu_x86_cpuid(env, 0x0a, 0, &ver, &unused, &unused, &unused);
799 if ((ver & 0xff) > 0) {
800 has_msr_architectural_pmu = true;
801 num_architectural_pmu_counters = (ver & 0xff00) >> 8;
802
803 /* Shouldn't be more than 32, since that's the number of bits
804 * available in EBX to tell us _which_ counters are available.
805 * Play it safe.
806 */
807 if (num_architectural_pmu_counters > MAX_GP_COUNTERS) {
808 num_architectural_pmu_counters = MAX_GP_COUNTERS;
809 }
810 }
811 }
812
813 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
814
815 for (i = 0x80000000; i <= limit; i++) {
816 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
817 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
818 abort();
819 }
820 c = &cpuid_data.entries[cpuid_i++];
821
822 c->function = i;
823 c->flags = 0;
824 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
825 }
826
827 /* Call Centaur's CPUID instructions they are supported. */
828 if (env->cpuid_xlevel2 > 0) {
829 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
830
831 for (i = 0xC0000000; i <= limit; i++) {
832 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
833 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
834 abort();
835 }
836 c = &cpuid_data.entries[cpuid_i++];
837
838 c->function = i;
839 c->flags = 0;
840 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
841 }
842 }
843
844 cpuid_data.cpuid.nent = cpuid_i;
845
846 if (((env->cpuid_version >> 8)&0xF) >= 6
847 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
848 (CPUID_MCE | CPUID_MCA)
849 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
850 uint64_t mcg_cap, unsupported_caps;
851 int banks;
852 int ret;
853
854 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
855 if (ret < 0) {
856 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
857 return ret;
858 }
859
860 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
861 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
862 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
863 return -ENOTSUP;
864 }
865
866 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
867 if (unsupported_caps) {
868 error_report("warning: Unsupported MCG_CAP bits: 0x%" PRIx64,
869 unsupported_caps);
870 }
871
872 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
873 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
874 if (ret < 0) {
875 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
876 return ret;
877 }
878 }
879
880 qemu_add_vm_change_state_handler(cpu_update_state, env);
881
882 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
883 if (c) {
884 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
885 !!(c->ecx & CPUID_EXT_SMX);
886 }
887
888 c = cpuid_find_entry(&cpuid_data.cpuid, 0x80000007, 0);
889 if (c && (c->edx & 1<<8) && invtsc_mig_blocker == NULL) {
890 /* for migration */
891 error_setg(&invtsc_mig_blocker,
892 "State blocked by non-migratable CPU device"
893 " (invtsc flag)");
894 migrate_add_blocker(invtsc_mig_blocker);
895 /* for savevm */
896 vmstate_x86_cpu.unmigratable = 1;
897 }
898
899 cpuid_data.cpuid.padding = 0;
900 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
901 if (r) {
902 return r;
903 }
904
905 r = kvm_arch_set_tsc_khz(cs);
906 if (r < 0) {
907 return r;
908 }
909
910 /* vcpu's TSC frequency is either specified by user, or following
911 * the value used by KVM if the former is not present. In the
912 * latter case, we query it from KVM and record in env->tsc_khz,
913 * so that vcpu's TSC frequency can be migrated later via this field.
914 */
915 if (!env->tsc_khz) {
916 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
917 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
918 -ENOTSUP;
919 if (r > 0) {
920 env->tsc_khz = r;
921 }
922 }
923
924 if (has_xsave) {
925 env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
926 }
927 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
928
929 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
930 has_msr_mtrr = true;
931 }
932 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
933 has_msr_tsc_aux = false;
934 }
935
936 return 0;
937 }
938
939 void kvm_arch_reset_vcpu(X86CPU *cpu)
940 {
941 CPUX86State *env = &cpu->env;
942
943 env->exception_injected = -1;
944 env->interrupt_injected = -1;
945 env->xcr0 = 1;
946 if (kvm_irqchip_in_kernel()) {
947 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
948 KVM_MP_STATE_UNINITIALIZED;
949 } else {
950 env->mp_state = KVM_MP_STATE_RUNNABLE;
951 }
952 }
953
954 void kvm_arch_do_init_vcpu(X86CPU *cpu)
955 {
956 CPUX86State *env = &cpu->env;
957
958 /* APs get directly into wait-for-SIPI state. */
959 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
960 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
961 }
962 }
963
964 static int kvm_get_supported_msrs(KVMState *s)
965 {
966 static int kvm_supported_msrs;
967 int ret = 0;
968
969 /* first time */
970 if (kvm_supported_msrs == 0) {
971 struct kvm_msr_list msr_list, *kvm_msr_list;
972
973 kvm_supported_msrs = -1;
974
975 /* Obtain MSR list from KVM. These are the MSRs that we must
976 * save/restore */
977 msr_list.nmsrs = 0;
978 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
979 if (ret < 0 && ret != -E2BIG) {
980 return ret;
981 }
982 /* Old kernel modules had a bug and could write beyond the provided
983 memory. Allocate at least a safe amount of 1K. */
984 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
985 msr_list.nmsrs *
986 sizeof(msr_list.indices[0])));
987
988 kvm_msr_list->nmsrs = msr_list.nmsrs;
989 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
990 if (ret >= 0) {
991 int i;
992
993 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
994 if (kvm_msr_list->indices[i] == MSR_STAR) {
995 has_msr_star = true;
996 continue;
997 }
998 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
999 has_msr_hsave_pa = true;
1000 continue;
1001 }
1002 if (kvm_msr_list->indices[i] == MSR_TSC_AUX) {
1003 has_msr_tsc_aux = true;
1004 continue;
1005 }
1006 if (kvm_msr_list->indices[i] == MSR_TSC_ADJUST) {
1007 has_msr_tsc_adjust = true;
1008 continue;
1009 }
1010 if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
1011 has_msr_tsc_deadline = true;
1012 continue;
1013 }
1014 if (kvm_msr_list->indices[i] == MSR_IA32_SMBASE) {
1015 has_msr_smbase = true;
1016 continue;
1017 }
1018 if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) {
1019 has_msr_misc_enable = true;
1020 continue;
1021 }
1022 if (kvm_msr_list->indices[i] == MSR_IA32_BNDCFGS) {
1023 has_msr_bndcfgs = true;
1024 continue;
1025 }
1026 if (kvm_msr_list->indices[i] == MSR_IA32_XSS) {
1027 has_msr_xss = true;
1028 continue;
1029 }
1030 if (kvm_msr_list->indices[i] == HV_X64_MSR_CRASH_CTL) {
1031 has_msr_hv_crash = true;
1032 continue;
1033 }
1034 if (kvm_msr_list->indices[i] == HV_X64_MSR_RESET) {
1035 has_msr_hv_reset = true;
1036 continue;
1037 }
1038 if (kvm_msr_list->indices[i] == HV_X64_MSR_VP_INDEX) {
1039 has_msr_hv_vpindex = true;
1040 continue;
1041 }
1042 if (kvm_msr_list->indices[i] == HV_X64_MSR_VP_RUNTIME) {
1043 has_msr_hv_runtime = true;
1044 continue;
1045 }
1046 if (kvm_msr_list->indices[i] == HV_X64_MSR_SCONTROL) {
1047 has_msr_hv_synic = true;
1048 continue;
1049 }
1050 if (kvm_msr_list->indices[i] == HV_X64_MSR_STIMER0_CONFIG) {
1051 has_msr_hv_stimer = true;
1052 continue;
1053 }
1054 }
1055 }
1056
1057 g_free(kvm_msr_list);
1058 }
1059
1060 return ret;
1061 }
1062
1063 static Notifier smram_machine_done;
1064 static KVMMemoryListener smram_listener;
1065 static AddressSpace smram_address_space;
1066 static MemoryRegion smram_as_root;
1067 static MemoryRegion smram_as_mem;
1068
1069 static void register_smram_listener(Notifier *n, void *unused)
1070 {
1071 MemoryRegion *smram =
1072 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
1073
1074 /* Outer container... */
1075 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
1076 memory_region_set_enabled(&smram_as_root, true);
1077
1078 /* ... with two regions inside: normal system memory with low
1079 * priority, and...
1080 */
1081 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
1082 get_system_memory(), 0, ~0ull);
1083 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
1084 memory_region_set_enabled(&smram_as_mem, true);
1085
1086 if (smram) {
1087 /* ... SMRAM with higher priority */
1088 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
1089 memory_region_set_enabled(smram, true);
1090 }
1091
1092 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
1093 kvm_memory_listener_register(kvm_state, &smram_listener,
1094 &smram_address_space, 1);
1095 }
1096
1097 int kvm_arch_init(MachineState *ms, KVMState *s)
1098 {
1099 uint64_t identity_base = 0xfffbc000;
1100 uint64_t shadow_mem;
1101 int ret;
1102 struct utsname utsname;
1103
1104 #ifdef KVM_CAP_XSAVE
1105 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
1106 #endif
1107
1108 #ifdef KVM_CAP_XCRS
1109 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
1110 #endif
1111
1112 #ifdef KVM_CAP_PIT_STATE2
1113 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
1114 #endif
1115
1116 ret = kvm_get_supported_msrs(s);
1117 if (ret < 0) {
1118 return ret;
1119 }
1120
1121 uname(&utsname);
1122 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
1123
1124 /*
1125 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
1126 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
1127 * Since these must be part of guest physical memory, we need to allocate
1128 * them, both by setting their start addresses in the kernel and by
1129 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
1130 *
1131 * Older KVM versions may not support setting the identity map base. In
1132 * that case we need to stick with the default, i.e. a 256K maximum BIOS
1133 * size.
1134 */
1135 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
1136 /* Allows up to 16M BIOSes. */
1137 identity_base = 0xfeffc000;
1138
1139 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
1140 if (ret < 0) {
1141 return ret;
1142 }
1143 }
1144
1145 /* Set TSS base one page after EPT identity map. */
1146 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
1147 if (ret < 0) {
1148 return ret;
1149 }
1150
1151 /* Tell fw_cfg to notify the BIOS to reserve the range. */
1152 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
1153 if (ret < 0) {
1154 fprintf(stderr, "e820_add_entry() table is full\n");
1155 return ret;
1156 }
1157 qemu_register_reset(kvm_unpoison_all, NULL);
1158
1159 shadow_mem = machine_kvm_shadow_mem(ms);
1160 if (shadow_mem != -1) {
1161 shadow_mem /= 4096;
1162 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
1163 if (ret < 0) {
1164 return ret;
1165 }
1166 }
1167
1168 if (kvm_check_extension(s, KVM_CAP_X86_SMM)) {
1169 smram_machine_done.notify = register_smram_listener;
1170 qemu_add_machine_init_done_notifier(&smram_machine_done);
1171 }
1172 return 0;
1173 }
1174
1175 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1176 {
1177 lhs->selector = rhs->selector;
1178 lhs->base = rhs->base;
1179 lhs->limit = rhs->limit;
1180 lhs->type = 3;
1181 lhs->present = 1;
1182 lhs->dpl = 3;
1183 lhs->db = 0;
1184 lhs->s = 1;
1185 lhs->l = 0;
1186 lhs->g = 0;
1187 lhs->avl = 0;
1188 lhs->unusable = 0;
1189 }
1190
1191 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1192 {
1193 unsigned flags = rhs->flags;
1194 lhs->selector = rhs->selector;
1195 lhs->base = rhs->base;
1196 lhs->limit = rhs->limit;
1197 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
1198 lhs->present = (flags & DESC_P_MASK) != 0;
1199 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
1200 lhs->db = (flags >> DESC_B_SHIFT) & 1;
1201 lhs->s = (flags & DESC_S_MASK) != 0;
1202 lhs->l = (flags >> DESC_L_SHIFT) & 1;
1203 lhs->g = (flags & DESC_G_MASK) != 0;
1204 lhs->avl = (flags & DESC_AVL_MASK) != 0;
1205 lhs->unusable = !lhs->present;
1206 lhs->padding = 0;
1207 }
1208
1209 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
1210 {
1211 lhs->selector = rhs->selector;
1212 lhs->base = rhs->base;
1213 lhs->limit = rhs->limit;
1214 if (rhs->unusable) {
1215 lhs->flags = 0;
1216 } else {
1217 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
1218 (rhs->present * DESC_P_MASK) |
1219 (rhs->dpl << DESC_DPL_SHIFT) |
1220 (rhs->db << DESC_B_SHIFT) |
1221 (rhs->s * DESC_S_MASK) |
1222 (rhs->l << DESC_L_SHIFT) |
1223 (rhs->g * DESC_G_MASK) |
1224 (rhs->avl * DESC_AVL_MASK);
1225 }
1226 }
1227
1228 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
1229 {
1230 if (set) {
1231 *kvm_reg = *qemu_reg;
1232 } else {
1233 *qemu_reg = *kvm_reg;
1234 }
1235 }
1236
1237 static int kvm_getput_regs(X86CPU *cpu, int set)
1238 {
1239 CPUX86State *env = &cpu->env;
1240 struct kvm_regs regs;
1241 int ret = 0;
1242
1243 if (!set) {
1244 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
1245 if (ret < 0) {
1246 return ret;
1247 }
1248 }
1249
1250 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
1251 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
1252 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
1253 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
1254 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
1255 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
1256 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
1257 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
1258 #ifdef TARGET_X86_64
1259 kvm_getput_reg(&regs.r8, &env->regs[8], set);
1260 kvm_getput_reg(&regs.r9, &env->regs[9], set);
1261 kvm_getput_reg(&regs.r10, &env->regs[10], set);
1262 kvm_getput_reg(&regs.r11, &env->regs[11], set);
1263 kvm_getput_reg(&regs.r12, &env->regs[12], set);
1264 kvm_getput_reg(&regs.r13, &env->regs[13], set);
1265 kvm_getput_reg(&regs.r14, &env->regs[14], set);
1266 kvm_getput_reg(&regs.r15, &env->regs[15], set);
1267 #endif
1268
1269 kvm_getput_reg(&regs.rflags, &env->eflags, set);
1270 kvm_getput_reg(&regs.rip, &env->eip, set);
1271
1272 if (set) {
1273 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
1274 }
1275
1276 return ret;
1277 }
1278
1279 static int kvm_put_fpu(X86CPU *cpu)
1280 {
1281 CPUX86State *env = &cpu->env;
1282 struct kvm_fpu fpu;
1283 int i;
1284
1285 memset(&fpu, 0, sizeof fpu);
1286 fpu.fsw = env->fpus & ~(7 << 11);
1287 fpu.fsw |= (env->fpstt & 7) << 11;
1288 fpu.fcw = env->fpuc;
1289 fpu.last_opcode = env->fpop;
1290 fpu.last_ip = env->fpip;
1291 fpu.last_dp = env->fpdp;
1292 for (i = 0; i < 8; ++i) {
1293 fpu.ftwx |= (!env->fptags[i]) << i;
1294 }
1295 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
1296 for (i = 0; i < CPU_NB_REGS; i++) {
1297 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
1298 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
1299 }
1300 fpu.mxcsr = env->mxcsr;
1301
1302 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
1303 }
1304
1305 #define XSAVE_FCW_FSW 0
1306 #define XSAVE_FTW_FOP 1
1307 #define XSAVE_CWD_RIP 2
1308 #define XSAVE_CWD_RDP 4
1309 #define XSAVE_MXCSR 6
1310 #define XSAVE_ST_SPACE 8
1311 #define XSAVE_XMM_SPACE 40
1312 #define XSAVE_XSTATE_BV 128
1313 #define XSAVE_YMMH_SPACE 144
1314 #define XSAVE_BNDREGS 240
1315 #define XSAVE_BNDCSR 256
1316 #define XSAVE_OPMASK 272
1317 #define XSAVE_ZMM_Hi256 288
1318 #define XSAVE_Hi16_ZMM 416
1319 #define XSAVE_PKRU 672
1320
1321 #define XSAVE_BYTE_OFFSET(word_offset) \
1322 ((word_offset) * sizeof(((struct kvm_xsave *)0)->region[0]))
1323
1324 #define ASSERT_OFFSET(word_offset, field) \
1325 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
1326 offsetof(X86XSaveArea, field))
1327
1328 ASSERT_OFFSET(XSAVE_FCW_FSW, legacy.fcw);
1329 ASSERT_OFFSET(XSAVE_FTW_FOP, legacy.ftw);
1330 ASSERT_OFFSET(XSAVE_CWD_RIP, legacy.fpip);
1331 ASSERT_OFFSET(XSAVE_CWD_RDP, legacy.fpdp);
1332 ASSERT_OFFSET(XSAVE_MXCSR, legacy.mxcsr);
1333 ASSERT_OFFSET(XSAVE_ST_SPACE, legacy.fpregs);
1334 ASSERT_OFFSET(XSAVE_XMM_SPACE, legacy.xmm_regs);
1335 ASSERT_OFFSET(XSAVE_XSTATE_BV, header.xstate_bv);
1336 ASSERT_OFFSET(XSAVE_YMMH_SPACE, avx_state);
1337 ASSERT_OFFSET(XSAVE_BNDREGS, bndreg_state);
1338 ASSERT_OFFSET(XSAVE_BNDCSR, bndcsr_state);
1339 ASSERT_OFFSET(XSAVE_OPMASK, opmask_state);
1340 ASSERT_OFFSET(XSAVE_ZMM_Hi256, zmm_hi256_state);
1341 ASSERT_OFFSET(XSAVE_Hi16_ZMM, hi16_zmm_state);
1342 ASSERT_OFFSET(XSAVE_PKRU, pkru_state);
1343
1344 static int kvm_put_xsave(X86CPU *cpu)
1345 {
1346 CPUX86State *env = &cpu->env;
1347 X86XSaveArea *xsave = env->kvm_xsave_buf;
1348 uint16_t cwd, swd, twd;
1349 int i, r;
1350
1351 if (!has_xsave) {
1352 return kvm_put_fpu(cpu);
1353 }
1354
1355 memset(xsave, 0, sizeof(struct kvm_xsave));
1356 twd = 0;
1357 swd = env->fpus & ~(7 << 11);
1358 swd |= (env->fpstt & 7) << 11;
1359 cwd = env->fpuc;
1360 for (i = 0; i < 8; ++i) {
1361 twd |= (!env->fptags[i]) << i;
1362 }
1363 xsave->legacy.fcw = cwd;
1364 xsave->legacy.fsw = swd;
1365 xsave->legacy.ftw = twd;
1366 xsave->legacy.fpop = env->fpop;
1367 xsave->legacy.fpip = env->fpip;
1368 xsave->legacy.fpdp = env->fpdp;
1369 memcpy(&xsave->legacy.fpregs, env->fpregs,
1370 sizeof env->fpregs);
1371 xsave->legacy.mxcsr = env->mxcsr;
1372 xsave->header.xstate_bv = env->xstate_bv;
1373 memcpy(&xsave->bndreg_state.bnd_regs, env->bnd_regs,
1374 sizeof env->bnd_regs);
1375 xsave->bndcsr_state.bndcsr = env->bndcs_regs;
1376 memcpy(&xsave->opmask_state.opmask_regs, env->opmask_regs,
1377 sizeof env->opmask_regs);
1378
1379 for (i = 0; i < CPU_NB_REGS; i++) {
1380 uint8_t *xmm = xsave->legacy.xmm_regs[i];
1381 uint8_t *ymmh = xsave->avx_state.ymmh[i];
1382 uint8_t *zmmh = xsave->zmm_hi256_state.zmm_hi256[i];
1383 stq_p(xmm, env->xmm_regs[i].ZMM_Q(0));
1384 stq_p(xmm+8, env->xmm_regs[i].ZMM_Q(1));
1385 stq_p(ymmh, env->xmm_regs[i].ZMM_Q(2));
1386 stq_p(ymmh+8, env->xmm_regs[i].ZMM_Q(3));
1387 stq_p(zmmh, env->xmm_regs[i].ZMM_Q(4));
1388 stq_p(zmmh+8, env->xmm_regs[i].ZMM_Q(5));
1389 stq_p(zmmh+16, env->xmm_regs[i].ZMM_Q(6));
1390 stq_p(zmmh+24, env->xmm_regs[i].ZMM_Q(7));
1391 }
1392
1393 #ifdef TARGET_X86_64
1394 memcpy(&xsave->hi16_zmm_state.hi16_zmm, &env->xmm_regs[16],
1395 16 * sizeof env->xmm_regs[16]);
1396 memcpy(&xsave->pkru_state, &env->pkru, sizeof env->pkru);
1397 #endif
1398 r = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
1399 return r;
1400 }
1401
1402 static int kvm_put_xcrs(X86CPU *cpu)
1403 {
1404 CPUX86State *env = &cpu->env;
1405 struct kvm_xcrs xcrs = {};
1406
1407 if (!has_xcrs) {
1408 return 0;
1409 }
1410
1411 xcrs.nr_xcrs = 1;
1412 xcrs.flags = 0;
1413 xcrs.xcrs[0].xcr = 0;
1414 xcrs.xcrs[0].value = env->xcr0;
1415 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
1416 }
1417
1418 static int kvm_put_sregs(X86CPU *cpu)
1419 {
1420 CPUX86State *env = &cpu->env;
1421 struct kvm_sregs sregs;
1422
1423 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1424 if (env->interrupt_injected >= 0) {
1425 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1426 (uint64_t)1 << (env->interrupt_injected % 64);
1427 }
1428
1429 if ((env->eflags & VM_MASK)) {
1430 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1431 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1432 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1433 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1434 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1435 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
1436 } else {
1437 set_seg(&sregs.cs, &env->segs[R_CS]);
1438 set_seg(&sregs.ds, &env->segs[R_DS]);
1439 set_seg(&sregs.es, &env->segs[R_ES]);
1440 set_seg(&sregs.fs, &env->segs[R_FS]);
1441 set_seg(&sregs.gs, &env->segs[R_GS]);
1442 set_seg(&sregs.ss, &env->segs[R_SS]);
1443 }
1444
1445 set_seg(&sregs.tr, &env->tr);
1446 set_seg(&sregs.ldt, &env->ldt);
1447
1448 sregs.idt.limit = env->idt.limit;
1449 sregs.idt.base = env->idt.base;
1450 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
1451 sregs.gdt.limit = env->gdt.limit;
1452 sregs.gdt.base = env->gdt.base;
1453 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
1454
1455 sregs.cr0 = env->cr[0];
1456 sregs.cr2 = env->cr[2];
1457 sregs.cr3 = env->cr[3];
1458 sregs.cr4 = env->cr[4];
1459
1460 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1461 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
1462
1463 sregs.efer = env->efer;
1464
1465 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
1466 }
1467
1468 static void kvm_msr_buf_reset(X86CPU *cpu)
1469 {
1470 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
1471 }
1472
1473 static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
1474 {
1475 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
1476 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
1477 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
1478
1479 assert((void *)(entry + 1) <= limit);
1480
1481 entry->index = index;
1482 entry->reserved = 0;
1483 entry->data = value;
1484 msrs->nmsrs++;
1485 }
1486
1487 static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1488 {
1489 CPUX86State *env = &cpu->env;
1490 int ret;
1491
1492 if (!has_msr_tsc_deadline) {
1493 return 0;
1494 }
1495
1496 kvm_msr_buf_reset(cpu);
1497 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
1498
1499 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1500 if (ret < 0) {
1501 return ret;
1502 }
1503
1504 assert(ret == 1);
1505 return 0;
1506 }
1507
1508 /*
1509 * Provide a separate write service for the feature control MSR in order to
1510 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1511 * before writing any other state because forcibly leaving nested mode
1512 * invalidates the VCPU state.
1513 */
1514 static int kvm_put_msr_feature_control(X86CPU *cpu)
1515 {
1516 int ret;
1517
1518 if (!has_msr_feature_control) {
1519 return 0;
1520 }
1521
1522 kvm_msr_buf_reset(cpu);
1523 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL,
1524 cpu->env.msr_ia32_feature_control);
1525
1526 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1527 if (ret < 0) {
1528 return ret;
1529 }
1530
1531 assert(ret == 1);
1532 return 0;
1533 }
1534
1535 static int kvm_put_msrs(X86CPU *cpu, int level)
1536 {
1537 CPUX86State *env = &cpu->env;
1538 int i;
1539 int ret;
1540
1541 kvm_msr_buf_reset(cpu);
1542
1543 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1544 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1545 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1546 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
1547 if (has_msr_star) {
1548 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
1549 }
1550 if (has_msr_hsave_pa) {
1551 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
1552 }
1553 if (has_msr_tsc_aux) {
1554 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
1555 }
1556 if (has_msr_tsc_adjust) {
1557 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
1558 }
1559 if (has_msr_misc_enable) {
1560 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
1561 env->msr_ia32_misc_enable);
1562 }
1563 if (has_msr_smbase) {
1564 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
1565 }
1566 if (has_msr_bndcfgs) {
1567 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
1568 }
1569 if (has_msr_xss) {
1570 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
1571 }
1572 #ifdef TARGET_X86_64
1573 if (lm_capable_kernel) {
1574 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
1575 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
1576 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
1577 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
1578 }
1579 #endif
1580 /*
1581 * The following MSRs have side effects on the guest or are too heavy
1582 * for normal writeback. Limit them to reset or full state updates.
1583 */
1584 if (level >= KVM_PUT_RESET_STATE) {
1585 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
1586 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
1587 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
1588 if (has_msr_async_pf_en) {
1589 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
1590 }
1591 if (has_msr_pv_eoi_en) {
1592 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
1593 }
1594 if (has_msr_kvm_steal_time) {
1595 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
1596 }
1597 if (has_msr_architectural_pmu) {
1598 /* Stop the counter. */
1599 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1600 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
1601
1602 /* Set the counter values. */
1603 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
1604 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
1605 env->msr_fixed_counters[i]);
1606 }
1607 for (i = 0; i < num_architectural_pmu_counters; i++) {
1608 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
1609 env->msr_gp_counters[i]);
1610 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
1611 env->msr_gp_evtsel[i]);
1612 }
1613 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
1614 env->msr_global_status);
1615 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1616 env->msr_global_ovf_ctrl);
1617
1618 /* Now start the PMU. */
1619 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
1620 env->msr_fixed_ctr_ctrl);
1621 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
1622 env->msr_global_ctrl);
1623 }
1624 if (has_msr_hv_hypercall) {
1625 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
1626 env->msr_hv_guest_os_id);
1627 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
1628 env->msr_hv_hypercall);
1629 }
1630 if (has_msr_hv_vapic) {
1631 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
1632 env->msr_hv_vapic);
1633 }
1634 if (has_msr_hv_tsc) {
1635 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, env->msr_hv_tsc);
1636 }
1637 if (has_msr_hv_crash) {
1638 int j;
1639
1640 for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++)
1641 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
1642 env->msr_hv_crash_params[j]);
1643
1644 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL,
1645 HV_X64_MSR_CRASH_CTL_NOTIFY);
1646 }
1647 if (has_msr_hv_runtime) {
1648 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
1649 }
1650 if (cpu->hyperv_synic) {
1651 int j;
1652
1653 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
1654 env->msr_hv_synic_control);
1655 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION,
1656 env->msr_hv_synic_version);
1657 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
1658 env->msr_hv_synic_evt_page);
1659 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
1660 env->msr_hv_synic_msg_page);
1661
1662 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
1663 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
1664 env->msr_hv_synic_sint[j]);
1665 }
1666 }
1667 if (has_msr_hv_stimer) {
1668 int j;
1669
1670 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
1671 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
1672 env->msr_hv_stimer_config[j]);
1673 }
1674
1675 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
1676 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
1677 env->msr_hv_stimer_count[j]);
1678 }
1679 }
1680 if (has_msr_mtrr) {
1681 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
1682 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
1683 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
1684 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
1685 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
1686 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
1687 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
1688 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
1689 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
1690 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
1691 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
1692 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
1693 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
1694 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
1695 env->mtrr_var[i].base);
1696 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i),
1697 env->mtrr_var[i].mask);
1698 }
1699 }
1700
1701 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
1702 * kvm_put_msr_feature_control. */
1703 }
1704 if (env->mcg_cap) {
1705 int i;
1706
1707 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
1708 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
1709 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1710 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
1711 }
1712 }
1713
1714 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1715 if (ret < 0) {
1716 return ret;
1717 }
1718
1719 assert(ret == cpu->kvm_msr_buf->nmsrs);
1720 return 0;
1721 }
1722
1723
1724 static int kvm_get_fpu(X86CPU *cpu)
1725 {
1726 CPUX86State *env = &cpu->env;
1727 struct kvm_fpu fpu;
1728 int i, ret;
1729
1730 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
1731 if (ret < 0) {
1732 return ret;
1733 }
1734
1735 env->fpstt = (fpu.fsw >> 11) & 7;
1736 env->fpus = fpu.fsw;
1737 env->fpuc = fpu.fcw;
1738 env->fpop = fpu.last_opcode;
1739 env->fpip = fpu.last_ip;
1740 env->fpdp = fpu.last_dp;
1741 for (i = 0; i < 8; ++i) {
1742 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1743 }
1744 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
1745 for (i = 0; i < CPU_NB_REGS; i++) {
1746 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
1747 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
1748 }
1749 env->mxcsr = fpu.mxcsr;
1750
1751 return 0;
1752 }
1753
1754 static int kvm_get_xsave(X86CPU *cpu)
1755 {
1756 CPUX86State *env = &cpu->env;
1757 X86XSaveArea *xsave = env->kvm_xsave_buf;
1758 int ret, i;
1759 uint16_t cwd, swd, twd;
1760
1761 if (!has_xsave) {
1762 return kvm_get_fpu(cpu);
1763 }
1764
1765 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
1766 if (ret < 0) {
1767 return ret;
1768 }
1769
1770 cwd = xsave->legacy.fcw;
1771 swd = xsave->legacy.fsw;
1772 twd = xsave->legacy.ftw;
1773 env->fpop = xsave->legacy.fpop;
1774 env->fpstt = (swd >> 11) & 7;
1775 env->fpus = swd;
1776 env->fpuc = cwd;
1777 for (i = 0; i < 8; ++i) {
1778 env->fptags[i] = !((twd >> i) & 1);
1779 }
1780 env->fpip = xsave->legacy.fpip;
1781 env->fpdp = xsave->legacy.fpdp;
1782 env->mxcsr = xsave->legacy.mxcsr;
1783 memcpy(env->fpregs, &xsave->legacy.fpregs,
1784 sizeof env->fpregs);
1785 env->xstate_bv = xsave->header.xstate_bv;
1786 memcpy(env->bnd_regs, &xsave->bndreg_state.bnd_regs,
1787 sizeof env->bnd_regs);
1788 env->bndcs_regs = xsave->bndcsr_state.bndcsr;
1789 memcpy(env->opmask_regs, &xsave->opmask_state.opmask_regs,
1790 sizeof env->opmask_regs);
1791
1792 for (i = 0; i < CPU_NB_REGS; i++) {
1793 uint8_t *xmm = xsave->legacy.xmm_regs[i];
1794 uint8_t *ymmh = xsave->avx_state.ymmh[i];
1795 uint8_t *zmmh = xsave->zmm_hi256_state.zmm_hi256[i];
1796 env->xmm_regs[i].ZMM_Q(0) = ldq_p(xmm);
1797 env->xmm_regs[i].ZMM_Q(1) = ldq_p(xmm+8);
1798 env->xmm_regs[i].ZMM_Q(2) = ldq_p(ymmh);
1799 env->xmm_regs[i].ZMM_Q(3) = ldq_p(ymmh+8);
1800 env->xmm_regs[i].ZMM_Q(4) = ldq_p(zmmh);
1801 env->xmm_regs[i].ZMM_Q(5) = ldq_p(zmmh+8);
1802 env->xmm_regs[i].ZMM_Q(6) = ldq_p(zmmh+16);
1803 env->xmm_regs[i].ZMM_Q(7) = ldq_p(zmmh+24);
1804 }
1805
1806 #ifdef TARGET_X86_64
1807 memcpy(&env->xmm_regs[16], &xsave->hi16_zmm_state.hi16_zmm,
1808 16 * sizeof env->xmm_regs[16]);
1809 memcpy(&env->pkru, &xsave->pkru_state, sizeof env->pkru);
1810 #endif
1811 return 0;
1812 }
1813
1814 static int kvm_get_xcrs(X86CPU *cpu)
1815 {
1816 CPUX86State *env = &cpu->env;
1817 int i, ret;
1818 struct kvm_xcrs xcrs;
1819
1820 if (!has_xcrs) {
1821 return 0;
1822 }
1823
1824 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
1825 if (ret < 0) {
1826 return ret;
1827 }
1828
1829 for (i = 0; i < xcrs.nr_xcrs; i++) {
1830 /* Only support xcr0 now */
1831 if (xcrs.xcrs[i].xcr == 0) {
1832 env->xcr0 = xcrs.xcrs[i].value;
1833 break;
1834 }
1835 }
1836 return 0;
1837 }
1838
1839 static int kvm_get_sregs(X86CPU *cpu)
1840 {
1841 CPUX86State *env = &cpu->env;
1842 struct kvm_sregs sregs;
1843 uint32_t hflags;
1844 int bit, i, ret;
1845
1846 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1847 if (ret < 0) {
1848 return ret;
1849 }
1850
1851 /* There can only be one pending IRQ set in the bitmap at a time, so try
1852 to find it and save its number instead (-1 for none). */
1853 env->interrupt_injected = -1;
1854 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1855 if (sregs.interrupt_bitmap[i]) {
1856 bit = ctz64(sregs.interrupt_bitmap[i]);
1857 env->interrupt_injected = i * 64 + bit;
1858 break;
1859 }
1860 }
1861
1862 get_seg(&env->segs[R_CS], &sregs.cs);
1863 get_seg(&env->segs[R_DS], &sregs.ds);
1864 get_seg(&env->segs[R_ES], &sregs.es);
1865 get_seg(&env->segs[R_FS], &sregs.fs);
1866 get_seg(&env->segs[R_GS], &sregs.gs);
1867 get_seg(&env->segs[R_SS], &sregs.ss);
1868
1869 get_seg(&env->tr, &sregs.tr);
1870 get_seg(&env->ldt, &sregs.ldt);
1871
1872 env->idt.limit = sregs.idt.limit;
1873 env->idt.base = sregs.idt.base;
1874 env->gdt.limit = sregs.gdt.limit;
1875 env->gdt.base = sregs.gdt.base;
1876
1877 env->cr[0] = sregs.cr0;
1878 env->cr[2] = sregs.cr2;
1879 env->cr[3] = sregs.cr3;
1880 env->cr[4] = sregs.cr4;
1881
1882 env->efer = sregs.efer;
1883
1884 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
1885
1886 #define HFLAG_COPY_MASK \
1887 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1888 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1889 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1890 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1891
1892 hflags = env->hflags & HFLAG_COPY_MASK;
1893 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1894 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1895 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1896 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1897 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1898
1899 if (env->cr[4] & CR4_OSFXSR_MASK) {
1900 hflags |= HF_OSFXSR_MASK;
1901 }
1902
1903 if (env->efer & MSR_EFER_LMA) {
1904 hflags |= HF_LMA_MASK;
1905 }
1906
1907 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1908 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1909 } else {
1910 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1911 (DESC_B_SHIFT - HF_CS32_SHIFT);
1912 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1913 (DESC_B_SHIFT - HF_SS32_SHIFT);
1914 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1915 !(hflags & HF_CS32_MASK)) {
1916 hflags |= HF_ADDSEG_MASK;
1917 } else {
1918 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1919 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1920 }
1921 }
1922 env->hflags = hflags;
1923
1924 return 0;
1925 }
1926
1927 static int kvm_get_msrs(X86CPU *cpu)
1928 {
1929 CPUX86State *env = &cpu->env;
1930 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
1931 int ret, i;
1932
1933 kvm_msr_buf_reset(cpu);
1934
1935 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
1936 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
1937 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
1938 kvm_msr_entry_add(cpu, MSR_PAT, 0);
1939 if (has_msr_star) {
1940 kvm_msr_entry_add(cpu, MSR_STAR, 0);
1941 }
1942 if (has_msr_hsave_pa) {
1943 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
1944 }
1945 if (has_msr_tsc_aux) {
1946 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
1947 }
1948 if (has_msr_tsc_adjust) {
1949 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
1950 }
1951 if (has_msr_tsc_deadline) {
1952 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
1953 }
1954 if (has_msr_misc_enable) {
1955 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
1956 }
1957 if (has_msr_smbase) {
1958 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
1959 }
1960 if (has_msr_feature_control) {
1961 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
1962 }
1963 if (has_msr_bndcfgs) {
1964 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
1965 }
1966 if (has_msr_xss) {
1967 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
1968 }
1969
1970
1971 if (!env->tsc_valid) {
1972 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
1973 env->tsc_valid = !runstate_is_running();
1974 }
1975
1976 #ifdef TARGET_X86_64
1977 if (lm_capable_kernel) {
1978 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
1979 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
1980 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
1981 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
1982 }
1983 #endif
1984 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
1985 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
1986 if (has_msr_async_pf_en) {
1987 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
1988 }
1989 if (has_msr_pv_eoi_en) {
1990 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
1991 }
1992 if (has_msr_kvm_steal_time) {
1993 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
1994 }
1995 if (has_msr_architectural_pmu) {
1996 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1997 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
1998 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
1999 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
2000 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
2001 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
2002 }
2003 for (i = 0; i < num_architectural_pmu_counters; i++) {
2004 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
2005 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
2006 }
2007 }
2008
2009 if (env->mcg_cap) {
2010 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
2011 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
2012 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
2013 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
2014 }
2015 }
2016
2017 if (has_msr_hv_hypercall) {
2018 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
2019 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
2020 }
2021 if (has_msr_hv_vapic) {
2022 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
2023 }
2024 if (has_msr_hv_tsc) {
2025 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
2026 }
2027 if (has_msr_hv_crash) {
2028 int j;
2029
2030 for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++) {
2031 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
2032 }
2033 }
2034 if (has_msr_hv_runtime) {
2035 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
2036 }
2037 if (cpu->hyperv_synic) {
2038 uint32_t msr;
2039
2040 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
2041 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, 0);
2042 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
2043 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
2044 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
2045 kvm_msr_entry_add(cpu, msr, 0);
2046 }
2047 }
2048 if (has_msr_hv_stimer) {
2049 uint32_t msr;
2050
2051 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
2052 msr++) {
2053 kvm_msr_entry_add(cpu, msr, 0);
2054 }
2055 }
2056 if (has_msr_mtrr) {
2057 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
2058 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
2059 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
2060 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
2061 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
2062 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
2063 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
2064 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
2065 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
2066 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
2067 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
2068 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
2069 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
2070 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
2071 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
2072 }
2073 }
2074
2075 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
2076 if (ret < 0) {
2077 return ret;
2078 }
2079
2080 assert(ret == cpu->kvm_msr_buf->nmsrs);
2081 for (i = 0; i < ret; i++) {
2082 uint32_t index = msrs[i].index;
2083 switch (index) {
2084 case MSR_IA32_SYSENTER_CS:
2085 env->sysenter_cs = msrs[i].data;
2086 break;
2087 case MSR_IA32_SYSENTER_ESP:
2088 env->sysenter_esp = msrs[i].data;
2089 break;
2090 case MSR_IA32_SYSENTER_EIP:
2091 env->sysenter_eip = msrs[i].data;
2092 break;
2093 case MSR_PAT:
2094 env->pat = msrs[i].data;
2095 break;
2096 case MSR_STAR:
2097 env->star = msrs[i].data;
2098 break;
2099 #ifdef TARGET_X86_64
2100 case MSR_CSTAR:
2101 env->cstar = msrs[i].data;
2102 break;
2103 case MSR_KERNELGSBASE:
2104 env->kernelgsbase = msrs[i].data;
2105 break;
2106 case MSR_FMASK:
2107 env->fmask = msrs[i].data;
2108 break;
2109 case MSR_LSTAR:
2110 env->lstar = msrs[i].data;
2111 break;
2112 #endif
2113 case MSR_IA32_TSC:
2114 env->tsc = msrs[i].data;
2115 break;
2116 case MSR_TSC_AUX:
2117 env->tsc_aux = msrs[i].data;
2118 break;
2119 case MSR_TSC_ADJUST:
2120 env->tsc_adjust = msrs[i].data;
2121 break;
2122 case MSR_IA32_TSCDEADLINE:
2123 env->tsc_deadline = msrs[i].data;
2124 break;
2125 case MSR_VM_HSAVE_PA:
2126 env->vm_hsave = msrs[i].data;
2127 break;
2128 case MSR_KVM_SYSTEM_TIME:
2129 env->system_time_msr = msrs[i].data;
2130 break;
2131 case MSR_KVM_WALL_CLOCK:
2132 env->wall_clock_msr = msrs[i].data;
2133 break;
2134 case MSR_MCG_STATUS:
2135 env->mcg_status = msrs[i].data;
2136 break;
2137 case MSR_MCG_CTL:
2138 env->mcg_ctl = msrs[i].data;
2139 break;
2140 case MSR_IA32_MISC_ENABLE:
2141 env->msr_ia32_misc_enable = msrs[i].data;
2142 break;
2143 case MSR_IA32_SMBASE:
2144 env->smbase = msrs[i].data;
2145 break;
2146 case MSR_IA32_FEATURE_CONTROL:
2147 env->msr_ia32_feature_control = msrs[i].data;
2148 break;
2149 case MSR_IA32_BNDCFGS:
2150 env->msr_bndcfgs = msrs[i].data;
2151 break;
2152 case MSR_IA32_XSS:
2153 env->xss = msrs[i].data;
2154 break;
2155 default:
2156 if (msrs[i].index >= MSR_MC0_CTL &&
2157 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
2158 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
2159 }
2160 break;
2161 case MSR_KVM_ASYNC_PF_EN:
2162 env->async_pf_en_msr = msrs[i].data;
2163 break;
2164 case MSR_KVM_PV_EOI_EN:
2165 env->pv_eoi_en_msr = msrs[i].data;
2166 break;
2167 case MSR_KVM_STEAL_TIME:
2168 env->steal_time_msr = msrs[i].data;
2169 break;
2170 case MSR_CORE_PERF_FIXED_CTR_CTRL:
2171 env->msr_fixed_ctr_ctrl = msrs[i].data;
2172 break;
2173 case MSR_CORE_PERF_GLOBAL_CTRL:
2174 env->msr_global_ctrl = msrs[i].data;
2175 break;
2176 case MSR_CORE_PERF_GLOBAL_STATUS:
2177 env->msr_global_status = msrs[i].data;
2178 break;
2179 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
2180 env->msr_global_ovf_ctrl = msrs[i].data;
2181 break;
2182 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
2183 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
2184 break;
2185 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
2186 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
2187 break;
2188 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
2189 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
2190 break;
2191 case HV_X64_MSR_HYPERCALL:
2192 env->msr_hv_hypercall = msrs[i].data;
2193 break;
2194 case HV_X64_MSR_GUEST_OS_ID:
2195 env->msr_hv_guest_os_id = msrs[i].data;
2196 break;
2197 case HV_X64_MSR_APIC_ASSIST_PAGE:
2198 env->msr_hv_vapic = msrs[i].data;
2199 break;
2200 case HV_X64_MSR_REFERENCE_TSC:
2201 env->msr_hv_tsc = msrs[i].data;
2202 break;
2203 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2204 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
2205 break;
2206 case HV_X64_MSR_VP_RUNTIME:
2207 env->msr_hv_runtime = msrs[i].data;
2208 break;
2209 case HV_X64_MSR_SCONTROL:
2210 env->msr_hv_synic_control = msrs[i].data;
2211 break;
2212 case HV_X64_MSR_SVERSION:
2213 env->msr_hv_synic_version = msrs[i].data;
2214 break;
2215 case HV_X64_MSR_SIEFP:
2216 env->msr_hv_synic_evt_page = msrs[i].data;
2217 break;
2218 case HV_X64_MSR_SIMP:
2219 env->msr_hv_synic_msg_page = msrs[i].data;
2220 break;
2221 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
2222 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
2223 break;
2224 case HV_X64_MSR_STIMER0_CONFIG:
2225 case HV_X64_MSR_STIMER1_CONFIG:
2226 case HV_X64_MSR_STIMER2_CONFIG:
2227 case HV_X64_MSR_STIMER3_CONFIG:
2228 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
2229 msrs[i].data;
2230 break;
2231 case HV_X64_MSR_STIMER0_COUNT:
2232 case HV_X64_MSR_STIMER1_COUNT:
2233 case HV_X64_MSR_STIMER2_COUNT:
2234 case HV_X64_MSR_STIMER3_COUNT:
2235 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
2236 msrs[i].data;
2237 break;
2238 case MSR_MTRRdefType:
2239 env->mtrr_deftype = msrs[i].data;
2240 break;
2241 case MSR_MTRRfix64K_00000:
2242 env->mtrr_fixed[0] = msrs[i].data;
2243 break;
2244 case MSR_MTRRfix16K_80000:
2245 env->mtrr_fixed[1] = msrs[i].data;
2246 break;
2247 case MSR_MTRRfix16K_A0000:
2248 env->mtrr_fixed[2] = msrs[i].data;
2249 break;
2250 case MSR_MTRRfix4K_C0000:
2251 env->mtrr_fixed[3] = msrs[i].data;
2252 break;
2253 case MSR_MTRRfix4K_C8000:
2254 env->mtrr_fixed[4] = msrs[i].data;
2255 break;
2256 case MSR_MTRRfix4K_D0000:
2257 env->mtrr_fixed[5] = msrs[i].data;
2258 break;
2259 case MSR_MTRRfix4K_D8000:
2260 env->mtrr_fixed[6] = msrs[i].data;
2261 break;
2262 case MSR_MTRRfix4K_E0000:
2263 env->mtrr_fixed[7] = msrs[i].data;
2264 break;
2265 case MSR_MTRRfix4K_E8000:
2266 env->mtrr_fixed[8] = msrs[i].data;
2267 break;
2268 case MSR_MTRRfix4K_F0000:
2269 env->mtrr_fixed[9] = msrs[i].data;
2270 break;
2271 case MSR_MTRRfix4K_F8000:
2272 env->mtrr_fixed[10] = msrs[i].data;
2273 break;
2274 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
2275 if (index & 1) {
2276 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data;
2277 } else {
2278 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
2279 }
2280 break;
2281 }
2282 }
2283
2284 return 0;
2285 }
2286
2287 static int kvm_put_mp_state(X86CPU *cpu)
2288 {
2289 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
2290
2291 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
2292 }
2293
2294 static int kvm_get_mp_state(X86CPU *cpu)
2295 {
2296 CPUState *cs = CPU(cpu);
2297 CPUX86State *env = &cpu->env;
2298 struct kvm_mp_state mp_state;
2299 int ret;
2300
2301 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
2302 if (ret < 0) {
2303 return ret;
2304 }
2305 env->mp_state = mp_state.mp_state;
2306 if (kvm_irqchip_in_kernel()) {
2307 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
2308 }
2309 return 0;
2310 }
2311
2312 static int kvm_get_apic(X86CPU *cpu)
2313 {
2314 DeviceState *apic = cpu->apic_state;
2315 struct kvm_lapic_state kapic;
2316 int ret;
2317
2318 if (apic && kvm_irqchip_in_kernel()) {
2319 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
2320 if (ret < 0) {
2321 return ret;
2322 }
2323
2324 kvm_get_apic_state(apic, &kapic);
2325 }
2326 return 0;
2327 }
2328
2329 static int kvm_put_apic(X86CPU *cpu)
2330 {
2331 DeviceState *apic = cpu->apic_state;
2332 struct kvm_lapic_state kapic;
2333
2334 if (apic && kvm_irqchip_in_kernel()) {
2335 kvm_put_apic_state(apic, &kapic);
2336
2337 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_LAPIC, &kapic);
2338 }
2339 return 0;
2340 }
2341
2342 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
2343 {
2344 CPUState *cs = CPU(cpu);
2345 CPUX86State *env = &cpu->env;
2346 struct kvm_vcpu_events events = {};
2347
2348 if (!kvm_has_vcpu_events()) {
2349 return 0;
2350 }
2351
2352 events.exception.injected = (env->exception_injected >= 0);
2353 events.exception.nr = env->exception_injected;
2354 events.exception.has_error_code = env->has_error_code;
2355 events.exception.error_code = env->error_code;
2356 events.exception.pad = 0;
2357
2358 events.interrupt.injected = (env->interrupt_injected >= 0);
2359 events.interrupt.nr = env->interrupt_injected;
2360 events.interrupt.soft = env->soft_interrupt;
2361
2362 events.nmi.injected = env->nmi_injected;
2363 events.nmi.pending = env->nmi_pending;
2364 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
2365 events.nmi.pad = 0;
2366
2367 events.sipi_vector = env->sipi_vector;
2368
2369 if (has_msr_smbase) {
2370 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
2371 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
2372 if (kvm_irqchip_in_kernel()) {
2373 /* As soon as these are moved to the kernel, remove them
2374 * from cs->interrupt_request.
2375 */
2376 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
2377 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
2378 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
2379 } else {
2380 /* Keep these in cs->interrupt_request. */
2381 events.smi.pending = 0;
2382 events.smi.latched_init = 0;
2383 }
2384 events.flags |= KVM_VCPUEVENT_VALID_SMM;
2385 }
2386
2387 events.flags = 0;
2388 if (level >= KVM_PUT_RESET_STATE) {
2389 events.flags |=
2390 KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
2391 }
2392
2393 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
2394 }
2395
2396 static int kvm_get_vcpu_events(X86CPU *cpu)
2397 {
2398 CPUX86State *env = &cpu->env;
2399 struct kvm_vcpu_events events;
2400 int ret;
2401
2402 if (!kvm_has_vcpu_events()) {
2403 return 0;
2404 }
2405
2406 memset(&events, 0, sizeof(events));
2407 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
2408 if (ret < 0) {
2409 return ret;
2410 }
2411 env->exception_injected =
2412 events.exception.injected ? events.exception.nr : -1;
2413 env->has_error_code = events.exception.has_error_code;
2414 env->error_code = events.exception.error_code;
2415
2416 env->interrupt_injected =
2417 events.interrupt.injected ? events.interrupt.nr : -1;
2418 env->soft_interrupt = events.interrupt.soft;
2419
2420 env->nmi_injected = events.nmi.injected;
2421 env->nmi_pending = events.nmi.pending;
2422 if (events.nmi.masked) {
2423 env->hflags2 |= HF2_NMI_MASK;
2424 } else {
2425 env->hflags2 &= ~HF2_NMI_MASK;
2426 }
2427
2428 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
2429 if (events.smi.smm) {
2430 env->hflags |= HF_SMM_MASK;
2431 } else {
2432 env->hflags &= ~HF_SMM_MASK;
2433 }
2434 if (events.smi.pending) {
2435 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2436 } else {
2437 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2438 }
2439 if (events.smi.smm_inside_nmi) {
2440 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
2441 } else {
2442 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
2443 }
2444 if (events.smi.latched_init) {
2445 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2446 } else {
2447 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2448 }
2449 }
2450
2451 env->sipi_vector = events.sipi_vector;
2452
2453 return 0;
2454 }
2455
2456 static int kvm_guest_debug_workarounds(X86CPU *cpu)
2457 {
2458 CPUState *cs = CPU(cpu);
2459 CPUX86State *env = &cpu->env;
2460 int ret = 0;
2461 unsigned long reinject_trap = 0;
2462
2463 if (!kvm_has_vcpu_events()) {
2464 if (env->exception_injected == 1) {
2465 reinject_trap = KVM_GUESTDBG_INJECT_DB;
2466 } else if (env->exception_injected == 3) {
2467 reinject_trap = KVM_GUESTDBG_INJECT_BP;
2468 }
2469 env->exception_injected = -1;
2470 }
2471
2472 /*
2473 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
2474 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
2475 * by updating the debug state once again if single-stepping is on.
2476 * Another reason to call kvm_update_guest_debug here is a pending debug
2477 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
2478 * reinject them via SET_GUEST_DEBUG.
2479 */
2480 if (reinject_trap ||
2481 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
2482 ret = kvm_update_guest_debug(cs, reinject_trap);
2483 }
2484 return ret;
2485 }
2486
2487 static int kvm_put_debugregs(X86CPU *cpu)
2488 {
2489 CPUX86State *env = &cpu->env;
2490 struct kvm_debugregs dbgregs;
2491 int i;
2492
2493 if (!kvm_has_debugregs()) {
2494 return 0;
2495 }
2496
2497 for (i = 0; i < 4; i++) {
2498 dbgregs.db[i] = env->dr[i];
2499 }
2500 dbgregs.dr6 = env->dr[6];
2501 dbgregs.dr7 = env->dr[7];
2502 dbgregs.flags = 0;
2503
2504 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
2505 }
2506
2507 static int kvm_get_debugregs(X86CPU *cpu)
2508 {
2509 CPUX86State *env = &cpu->env;
2510 struct kvm_debugregs dbgregs;
2511 int i, ret;
2512
2513 if (!kvm_has_debugregs()) {
2514 return 0;
2515 }
2516
2517 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
2518 if (ret < 0) {
2519 return ret;
2520 }
2521 for (i = 0; i < 4; i++) {
2522 env->dr[i] = dbgregs.db[i];
2523 }
2524 env->dr[4] = env->dr[6] = dbgregs.dr6;
2525 env->dr[5] = env->dr[7] = dbgregs.dr7;
2526
2527 return 0;
2528 }
2529
2530 int kvm_arch_put_registers(CPUState *cpu, int level)
2531 {
2532 X86CPU *x86_cpu = X86_CPU(cpu);
2533 int ret;
2534
2535 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
2536
2537 if (level >= KVM_PUT_RESET_STATE) {
2538 ret = kvm_put_msr_feature_control(x86_cpu);
2539 if (ret < 0) {
2540 return ret;
2541 }
2542 }
2543
2544 if (level == KVM_PUT_FULL_STATE) {
2545 /* We don't check for kvm_arch_set_tsc_khz() errors here,
2546 * because TSC frequency mismatch shouldn't abort migration,
2547 * unless the user explicitly asked for a more strict TSC
2548 * setting (e.g. using an explicit "tsc-freq" option).
2549 */
2550 kvm_arch_set_tsc_khz(cpu);
2551 }
2552
2553 ret = kvm_getput_regs(x86_cpu, 1);
2554 if (ret < 0) {
2555 return ret;
2556 }
2557 ret = kvm_put_xsave(x86_cpu);
2558 if (ret < 0) {
2559 return ret;
2560 }
2561 ret = kvm_put_xcrs(x86_cpu);
2562 if (ret < 0) {
2563 return ret;
2564 }
2565 ret = kvm_put_sregs(x86_cpu);
2566 if (ret < 0) {
2567 return ret;
2568 }
2569 /* must be before kvm_put_msrs */
2570 ret = kvm_inject_mce_oldstyle(x86_cpu);
2571 if (ret < 0) {
2572 return ret;
2573 }
2574 ret = kvm_put_msrs(x86_cpu, level);
2575 if (ret < 0) {
2576 return ret;
2577 }
2578 if (level >= KVM_PUT_RESET_STATE) {
2579 ret = kvm_put_mp_state(x86_cpu);
2580 if (ret < 0) {
2581 return ret;
2582 }
2583 ret = kvm_put_apic(x86_cpu);
2584 if (ret < 0) {
2585 return ret;
2586 }
2587 }
2588
2589 ret = kvm_put_tscdeadline_msr(x86_cpu);
2590 if (ret < 0) {
2591 return ret;
2592 }
2593
2594 ret = kvm_put_vcpu_events(x86_cpu, level);
2595 if (ret < 0) {
2596 return ret;
2597 }
2598 ret = kvm_put_debugregs(x86_cpu);
2599 if (ret < 0) {
2600 return ret;
2601 }
2602 /* must be last */
2603 ret = kvm_guest_debug_workarounds(x86_cpu);
2604 if (ret < 0) {
2605 return ret;
2606 }
2607 return 0;
2608 }
2609
2610 int kvm_arch_get_registers(CPUState *cs)
2611 {
2612 X86CPU *cpu = X86_CPU(cs);
2613 int ret;
2614
2615 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
2616
2617 ret = kvm_getput_regs(cpu, 0);
2618 if (ret < 0) {
2619 goto out;
2620 }
2621 ret = kvm_get_xsave(cpu);
2622 if (ret < 0) {
2623 goto out;
2624 }
2625 ret = kvm_get_xcrs(cpu);
2626 if (ret < 0) {
2627 goto out;
2628 }
2629 ret = kvm_get_sregs(cpu);
2630 if (ret < 0) {
2631 goto out;
2632 }
2633 ret = kvm_get_msrs(cpu);
2634 if (ret < 0) {
2635 goto out;
2636 }
2637 ret = kvm_get_mp_state(cpu);
2638 if (ret < 0) {
2639 goto out;
2640 }
2641 ret = kvm_get_apic(cpu);
2642 if (ret < 0) {
2643 goto out;
2644 }
2645 ret = kvm_get_vcpu_events(cpu);
2646 if (ret < 0) {
2647 goto out;
2648 }
2649 ret = kvm_get_debugregs(cpu);
2650 if (ret < 0) {
2651 goto out;
2652 }
2653 ret = 0;
2654 out:
2655 cpu_sync_bndcs_hflags(&cpu->env);
2656 return ret;
2657 }
2658
2659 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
2660 {
2661 X86CPU *x86_cpu = X86_CPU(cpu);
2662 CPUX86State *env = &x86_cpu->env;
2663 int ret;
2664
2665 /* Inject NMI */
2666 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
2667 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
2668 qemu_mutex_lock_iothread();
2669 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
2670 qemu_mutex_unlock_iothread();
2671 DPRINTF("injected NMI\n");
2672 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
2673 if (ret < 0) {
2674 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
2675 strerror(-ret));
2676 }
2677 }
2678 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
2679 qemu_mutex_lock_iothread();
2680 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
2681 qemu_mutex_unlock_iothread();
2682 DPRINTF("injected SMI\n");
2683 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
2684 if (ret < 0) {
2685 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
2686 strerror(-ret));
2687 }
2688 }
2689 }
2690
2691 if (!kvm_pic_in_kernel()) {
2692 qemu_mutex_lock_iothread();
2693 }
2694
2695 /* Force the VCPU out of its inner loop to process any INIT requests
2696 * or (for userspace APIC, but it is cheap to combine the checks here)
2697 * pending TPR access reports.
2698 */
2699 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
2700 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
2701 !(env->hflags & HF_SMM_MASK)) {
2702 cpu->exit_request = 1;
2703 }
2704 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
2705 cpu->exit_request = 1;
2706 }
2707 }
2708
2709 if (!kvm_pic_in_kernel()) {
2710 /* Try to inject an interrupt if the guest can accept it */
2711 if (run->ready_for_interrupt_injection &&
2712 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
2713 (env->eflags & IF_MASK)) {
2714 int irq;
2715
2716 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
2717 irq = cpu_get_pic_interrupt(env);
2718 if (irq >= 0) {
2719 struct kvm_interrupt intr;
2720
2721 intr.irq = irq;
2722 DPRINTF("injected interrupt %d\n", irq);
2723 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
2724 if (ret < 0) {
2725 fprintf(stderr,
2726 "KVM: injection failed, interrupt lost (%s)\n",
2727 strerror(-ret));
2728 }
2729 }
2730 }
2731
2732 /* If we have an interrupt but the guest is not ready to receive an
2733 * interrupt, request an interrupt window exit. This will
2734 * cause a return to userspace as soon as the guest is ready to
2735 * receive interrupts. */
2736 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
2737 run->request_interrupt_window = 1;
2738 } else {
2739 run->request_interrupt_window = 0;
2740 }
2741
2742 DPRINTF("setting tpr\n");
2743 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
2744
2745 qemu_mutex_unlock_iothread();
2746 }
2747 }
2748
2749 MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
2750 {
2751 X86CPU *x86_cpu = X86_CPU(cpu);
2752 CPUX86State *env = &x86_cpu->env;
2753
2754 if (run->flags & KVM_RUN_X86_SMM) {
2755 env->hflags |= HF_SMM_MASK;
2756 } else {
2757 env->hflags &= HF_SMM_MASK;
2758 }
2759 if (run->if_flag) {
2760 env->eflags |= IF_MASK;
2761 } else {
2762 env->eflags &= ~IF_MASK;
2763 }
2764
2765 /* We need to protect the apic state against concurrent accesses from
2766 * different threads in case the userspace irqchip is used. */
2767 if (!kvm_irqchip_in_kernel()) {
2768 qemu_mutex_lock_iothread();
2769 }
2770 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
2771 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
2772 if (!kvm_irqchip_in_kernel()) {
2773 qemu_mutex_unlock_iothread();
2774 }
2775 return cpu_get_mem_attrs(env);
2776 }
2777
2778 int kvm_arch_process_async_events(CPUState *cs)
2779 {
2780 X86CPU *cpu = X86_CPU(cs);
2781 CPUX86State *env = &cpu->env;
2782
2783 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
2784 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
2785 assert(env->mcg_cap);
2786
2787 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
2788
2789 kvm_cpu_synchronize_state(cs);
2790
2791 if (env->exception_injected == EXCP08_DBLE) {
2792 /* this means triple fault */
2793 qemu_system_reset_request();
2794 cs->exit_request = 1;
2795 return 0;
2796 }
2797 env->exception_injected = EXCP12_MCHK;
2798 env->has_error_code = 0;
2799
2800 cs->halted = 0;
2801 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
2802 env->mp_state = KVM_MP_STATE_RUNNABLE;
2803 }
2804 }
2805
2806 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
2807 !(env->hflags & HF_SMM_MASK)) {
2808 kvm_cpu_synchronize_state(cs);
2809 do_cpu_init(cpu);
2810 }
2811
2812 if (kvm_irqchip_in_kernel()) {
2813 return 0;
2814 }
2815
2816 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
2817 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
2818 apic_poll_irq(cpu->apic_state);
2819 }
2820 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2821 (env->eflags & IF_MASK)) ||
2822 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2823 cs->halted = 0;
2824 }
2825 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
2826 kvm_cpu_synchronize_state(cs);
2827 do_cpu_sipi(cpu);
2828 }
2829 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
2830 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
2831 kvm_cpu_synchronize_state(cs);
2832 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
2833 env->tpr_access_type);
2834 }
2835
2836 return cs->halted;
2837 }
2838
2839 static int kvm_handle_halt(X86CPU *cpu)
2840 {
2841 CPUState *cs = CPU(cpu);
2842 CPUX86State *env = &cpu->env;
2843
2844 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2845 (env->eflags & IF_MASK)) &&
2846 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2847 cs->halted = 1;
2848 return EXCP_HLT;
2849 }
2850
2851 return 0;
2852 }
2853
2854 static int kvm_handle_tpr_access(X86CPU *cpu)
2855 {
2856 CPUState *cs = CPU(cpu);
2857 struct kvm_run *run = cs->kvm_run;
2858
2859 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
2860 run->tpr_access.is_write ? TPR_ACCESS_WRITE
2861 : TPR_ACCESS_READ);
2862 return 1;
2863 }
2864
2865 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2866 {
2867 static const uint8_t int3 = 0xcc;
2868
2869 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
2870 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
2871 return -EINVAL;
2872 }
2873 return 0;
2874 }
2875
2876 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2877 {
2878 uint8_t int3;
2879
2880 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
2881 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
2882 return -EINVAL;
2883 }
2884 return 0;
2885 }
2886
2887 static struct {
2888 target_ulong addr;
2889 int len;
2890 int type;
2891 } hw_breakpoint[4];
2892
2893 static int nb_hw_breakpoint;
2894
2895 static int find_hw_breakpoint(target_ulong addr, int len, int type)
2896 {
2897 int n;
2898
2899 for (n = 0; n < nb_hw_breakpoint; n++) {
2900 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
2901 (hw_breakpoint[n].len == len || len == -1)) {
2902 return n;
2903 }
2904 }
2905 return -1;
2906 }
2907
2908 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
2909 target_ulong len, int type)
2910 {
2911 switch (type) {
2912 case GDB_BREAKPOINT_HW:
2913 len = 1;
2914 break;
2915 case GDB_WATCHPOINT_WRITE:
2916 case GDB_WATCHPOINT_ACCESS:
2917 switch (len) {
2918 case 1:
2919 break;
2920 case 2:
2921 case 4:
2922 case 8:
2923 if (addr & (len - 1)) {
2924 return -EINVAL;
2925 }
2926 break;
2927 default:
2928 return -EINVAL;
2929 }
2930 break;
2931 default:
2932 return -ENOSYS;
2933 }
2934
2935 if (nb_hw_breakpoint == 4) {
2936 return -ENOBUFS;
2937 }
2938 if (find_hw_breakpoint(addr, len, type) >= 0) {
2939 return -EEXIST;
2940 }
2941 hw_breakpoint[nb_hw_breakpoint].addr = addr;
2942 hw_breakpoint[nb_hw_breakpoint].len = len;
2943 hw_breakpoint[nb_hw_breakpoint].type = type;
2944 nb_hw_breakpoint++;
2945
2946 return 0;
2947 }
2948
2949 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
2950 target_ulong len, int type)
2951 {
2952 int n;
2953
2954 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
2955 if (n < 0) {
2956 return -ENOENT;
2957 }
2958 nb_hw_breakpoint--;
2959 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
2960
2961 return 0;
2962 }
2963
2964 void kvm_arch_remove_all_hw_breakpoints(void)
2965 {
2966 nb_hw_breakpoint = 0;
2967 }
2968
2969 static CPUWatchpoint hw_watchpoint;
2970
2971 static int kvm_handle_debug(X86CPU *cpu,
2972 struct kvm_debug_exit_arch *arch_info)
2973 {
2974 CPUState *cs = CPU(cpu);
2975 CPUX86State *env = &cpu->env;
2976 int ret = 0;
2977 int n;
2978
2979 if (arch_info->exception == 1) {
2980 if (arch_info->dr6 & (1 << 14)) {
2981 if (cs->singlestep_enabled) {
2982 ret = EXCP_DEBUG;
2983 }
2984 } else {
2985 for (n = 0; n < 4; n++) {
2986 if (arch_info->dr6 & (1 << n)) {
2987 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
2988 case 0x0:
2989 ret = EXCP_DEBUG;
2990 break;
2991 case 0x1:
2992 ret = EXCP_DEBUG;
2993 cs->watchpoint_hit = &hw_watchpoint;
2994 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
2995 hw_watchpoint.flags = BP_MEM_WRITE;
2996 break;
2997 case 0x3:
2998 ret = EXCP_DEBUG;
2999 cs->watchpoint_hit = &hw_watchpoint;
3000 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3001 hw_watchpoint.flags = BP_MEM_ACCESS;
3002 break;
3003 }
3004 }
3005 }
3006 }
3007 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
3008 ret = EXCP_DEBUG;
3009 }
3010 if (ret == 0) {
3011 cpu_synchronize_state(cs);
3012 assert(env->exception_injected == -1);
3013
3014 /* pass to guest */
3015 env->exception_injected = arch_info->exception;
3016 env->has_error_code = 0;
3017 }
3018
3019 return ret;
3020 }
3021
3022 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
3023 {
3024 const uint8_t type_code[] = {
3025 [GDB_BREAKPOINT_HW] = 0x0,
3026 [GDB_WATCHPOINT_WRITE] = 0x1,
3027 [GDB_WATCHPOINT_ACCESS] = 0x3
3028 };
3029 const uint8_t len_code[] = {
3030 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
3031 };
3032 int n;
3033
3034 if (kvm_sw_breakpoints_active(cpu)) {
3035 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
3036 }
3037 if (nb_hw_breakpoint > 0) {
3038 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
3039 dbg->arch.debugreg[7] = 0x0600;
3040 for (n = 0; n < nb_hw_breakpoint; n++) {
3041 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
3042 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
3043 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
3044 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
3045 }
3046 }
3047 }
3048
3049 static bool host_supports_vmx(void)
3050 {
3051 uint32_t ecx, unused;
3052
3053 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
3054 return ecx & CPUID_EXT_VMX;
3055 }
3056
3057 #define VMX_INVALID_GUEST_STATE 0x80000021
3058
3059 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
3060 {
3061 X86CPU *cpu = X86_CPU(cs);
3062 uint64_t code;
3063 int ret;
3064
3065 switch (run->exit_reason) {
3066 case KVM_EXIT_HLT:
3067 DPRINTF("handle_hlt\n");
3068 qemu_mutex_lock_iothread();
3069 ret = kvm_handle_halt(cpu);
3070 qemu_mutex_unlock_iothread();
3071 break;
3072 case KVM_EXIT_SET_TPR:
3073 ret = 0;
3074 break;
3075 case KVM_EXIT_TPR_ACCESS:
3076 qemu_mutex_lock_iothread();
3077 ret = kvm_handle_tpr_access(cpu);
3078 qemu_mutex_unlock_iothread();
3079 break;
3080 case KVM_EXIT_FAIL_ENTRY:
3081 code = run->fail_entry.hardware_entry_failure_reason;
3082 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
3083 code);
3084 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
3085 fprintf(stderr,
3086 "\nIf you're running a guest on an Intel machine without "
3087 "unrestricted mode\n"
3088 "support, the failure can be most likely due to the guest "
3089 "entering an invalid\n"
3090 "state for Intel VT. For example, the guest maybe running "
3091 "in big real mode\n"
3092 "which is not supported on less recent Intel processors."
3093 "\n\n");
3094 }
3095 ret = -1;
3096 break;
3097 case KVM_EXIT_EXCEPTION:
3098 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
3099 run->ex.exception, run->ex.error_code);
3100 ret = -1;
3101 break;
3102 case KVM_EXIT_DEBUG:
3103 DPRINTF("kvm_exit_debug\n");
3104 qemu_mutex_lock_iothread();
3105 ret = kvm_handle_debug(cpu, &run->debug.arch);
3106 qemu_mutex_unlock_iothread();
3107 break;
3108 case KVM_EXIT_HYPERV:
3109 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
3110 break;
3111 case KVM_EXIT_IOAPIC_EOI:
3112 ioapic_eoi_broadcast(run->eoi.vector);
3113 ret = 0;
3114 break;
3115 default:
3116 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
3117 ret = -1;
3118 break;
3119 }
3120
3121 return ret;
3122 }
3123
3124 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
3125 {
3126 X86CPU *cpu = X86_CPU(cs);
3127 CPUX86State *env = &cpu->env;
3128
3129 kvm_cpu_synchronize_state(cs);
3130 return !(env->cr[0] & CR0_PE_MASK) ||
3131 ((env->segs[R_CS].selector & 3) != 3);
3132 }
3133
3134 void kvm_arch_init_irq_routing(KVMState *s)
3135 {
3136 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
3137 /* If kernel can't do irq routing, interrupt source
3138 * override 0->2 cannot be set up as required by HPET.
3139 * So we have to disable it.
3140 */
3141 no_hpet = 1;
3142 }
3143 /* We know at this point that we're using the in-kernel
3144 * irqchip, so we can use irqfds, and on x86 we know
3145 * we can use msi via irqfd and GSI routing.
3146 */
3147 kvm_msi_via_irqfd_allowed = true;
3148 kvm_gsi_routing_allowed = true;
3149
3150 if (kvm_irqchip_is_split()) {
3151 int i;
3152
3153 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
3154 MSI routes for signaling interrupts to the local apics. */
3155 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
3156 struct MSIMessage msg = { 0x0, 0x0 };
3157 if (kvm_irqchip_add_msi_route(s, msg, NULL) < 0) {
3158 error_report("Could not enable split IRQ mode.");
3159 exit(1);
3160 }
3161 }
3162 }
3163 }
3164
3165 int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
3166 {
3167 int ret;
3168 if (machine_kernel_irqchip_split(ms)) {
3169 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
3170 if (ret) {
3171 error_report("Could not enable split irqchip mode: %s\n",
3172 strerror(-ret));
3173 exit(1);
3174 } else {
3175 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
3176 kvm_split_irqchip = true;
3177 return 1;
3178 }
3179 } else {
3180 return 0;
3181 }
3182 }
3183
3184 /* Classic KVM device assignment interface. Will remain x86 only. */
3185 int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
3186 uint32_t flags, uint32_t *dev_id)
3187 {
3188 struct kvm_assigned_pci_dev dev_data = {
3189 .segnr = dev_addr->domain,
3190 .busnr = dev_addr->bus,
3191 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
3192 .flags = flags,
3193 };
3194 int ret;
3195
3196 dev_data.assigned_dev_id =
3197 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
3198
3199 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
3200 if (ret < 0) {
3201 return ret;
3202 }
3203
3204 *dev_id = dev_data.assigned_dev_id;
3205
3206 return 0;
3207 }
3208
3209 int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
3210 {
3211 struct kvm_assigned_pci_dev dev_data = {
3212 .assigned_dev_id = dev_id,
3213 };
3214
3215 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
3216 }
3217
3218 static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
3219 uint32_t irq_type, uint32_t guest_irq)
3220 {
3221 struct kvm_assigned_irq assigned_irq = {
3222 .assigned_dev_id = dev_id,
3223 .guest_irq = guest_irq,
3224 .flags = irq_type,
3225 };
3226
3227 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
3228 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
3229 } else {
3230 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
3231 }
3232 }
3233
3234 int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
3235 uint32_t guest_irq)
3236 {
3237 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
3238 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
3239
3240 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
3241 }
3242
3243 int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
3244 {
3245 struct kvm_assigned_pci_dev dev_data = {
3246 .assigned_dev_id = dev_id,
3247 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
3248 };
3249
3250 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
3251 }
3252
3253 static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
3254 uint32_t type)
3255 {
3256 struct kvm_assigned_irq assigned_irq = {
3257 .assigned_dev_id = dev_id,
3258 .flags = type,
3259 };
3260
3261 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
3262 }
3263
3264 int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
3265 {
3266 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
3267 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
3268 }
3269
3270 int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
3271 {
3272 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
3273 KVM_DEV_IRQ_GUEST_MSI, virq);
3274 }
3275
3276 int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
3277 {
3278 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
3279 KVM_DEV_IRQ_HOST_MSI);
3280 }
3281
3282 bool kvm_device_msix_supported(KVMState *s)
3283 {
3284 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
3285 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
3286 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
3287 }
3288
3289 int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
3290 uint32_t nr_vectors)
3291 {
3292 struct kvm_assigned_msix_nr msix_nr = {
3293 .assigned_dev_id = dev_id,
3294 .entry_nr = nr_vectors,
3295 };
3296
3297 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
3298 }
3299
3300 int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
3301 int virq)
3302 {
3303 struct kvm_assigned_msix_entry msix_entry = {
3304 .assigned_dev_id = dev_id,
3305 .gsi = virq,
3306 .entry = vector,
3307 };
3308
3309 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
3310 }
3311
3312 int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
3313 {
3314 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
3315 KVM_DEV_IRQ_GUEST_MSIX, 0);
3316 }
3317
3318 int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
3319 {
3320 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
3321 KVM_DEV_IRQ_HOST_MSIX);
3322 }
3323
3324 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
3325 uint64_t address, uint32_t data, PCIDevice *dev)
3326 {
3327 return 0;
3328 }
3329
3330 int kvm_arch_msi_data_to_gsi(uint32_t data)
3331 {
3332 abort();
3333 }
QEmu