include/hw/block/flash.h

   1 #ifndef HW_FLASH_H
   2 #define HW_FLASH_H
   3
   4 /* NOR flash devices */
   5
   6 #include "exec/memory.h"
   7
   8 /* pflash_cfi01.c */
   9
  10 #define TYPE_CFI_PFLASH01 "cfi.pflash01"
  11
  12 typedef struct PFlashCFI01 PFlashCFI01;
  13
  14 PFlashCFI01 *pflash_cfi01_register(hwaddr base,
  15                                    DeviceState *qdev, const char *name,
  16                                    hwaddr size,
  17                                    BlockBackend *blk,
  18                                    uint32_t sector_len, int nb_blocs,
  19                                    int width,
  20                                    uint16_t id0, uint16_t id1,
  21                                    uint16_t id2, uint16_t id3,
  22                                    int be);
  23 MemoryRegion *pflash_cfi01_get_memory(PFlashCFI01 *fl);
  24
  25 /* pflash_cfi02.c */
  26
  27 #define TYPE_CFI_PFLASH02 "cfi.pflash02"
  28
  29 typedef struct PFlashCFI02 PFlashCFI02;
  30
  31 PFlashCFI02 *pflash_cfi02_register(hwaddr base,
  32                                    DeviceState *qdev, const char *name,
  33                                    hwaddr size,
  34                                    BlockBackend *blk,
  35                                    uint32_t sector_len, int nb_blocs,
  36                                    int nb_mappings,
  37                                    int width,
  38                                    uint16_t id0, uint16_t id1,
  39                                    uint16_t id2, uint16_t id3,
  40                                    uint16_t unlock_addr0,
  41                                    uint16_t unlock_addr1,
  42                                    int be);
  43
  44 /* nand.c */
  45 DeviceState *nand_init(BlockBackend *blk, int manf_id, int chip_id);
  46 void nand_setpins(DeviceState *dev, uint8_t cle, uint8_t ale,
  47                   uint8_t ce, uint8_t wp, uint8_t gnd);
  48 void nand_getpins(DeviceState *dev, int *rb);
  49 void nand_setio(DeviceState *dev, uint32_t value);
  50 uint32_t nand_getio(DeviceState *dev);
  51 uint32_t nand_getbuswidth(DeviceState *dev);
  52
  53 #define NAND_MFR_TOSHIBA        0x98
  54 #define NAND_MFR_SAMSUNG        0xec
  55 #define NAND_MFR_FUJITSU        0x04
  56 #define NAND_MFR_NATIONAL       0x8f
  57 #define NAND_MFR_RENESAS        0x07
  58 #define NAND_MFR_STMICRO        0x20
  59 #define NAND_MFR_HYNIX          0xad
  60 #define NAND_MFR_MICRON         0x2c
  61
  62 /* onenand.c */
  63 void *onenand_raw_otp(DeviceState *onenand_device);
  64
  65 /* ecc.c */
  66 typedef struct {
  67     uint8_t cp;         /* Column parity */
  68     uint16_t lp[2];     /* Line parity */
  69     uint16_t count;
  70 } ECCState;
  71
  72 uint8_t ecc_digest(ECCState *s, uint8_t sample);
  73 void ecc_reset(ECCState *s);
  74 extern VMStateDescription vmstate_ecc_state;
  75
  76 #endif