target-mips/helper.c

   1 /*
   2  *  MIPS emulation helpers for qemu.
   3  *
   4  *  Copyright (c) 2004-2005 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include <stdarg.h>
  20 #include <stdlib.h>
  21 #include <stdio.h>
  22 #include <string.h>
  23 #include <inttypes.h>
  24 #include <signal.h>
  25
  26 #include "cpu.h"
  27 #include "exec-all.h"
  28
  29 enum {
  30     TLBRET_DIRTY = -4,
  31     TLBRET_INVALID = -3,
  32     TLBRET_NOMATCH = -2,
  33     TLBRET_BADADDR = -1,
  34     TLBRET_MATCH = 0
  35 };
  36
  37 #if !defined(CONFIG_USER_ONLY)
  38
  39 /* no MMU emulation */
  40 int no_mmu_map_address (CPUState *env, target_phys_addr_t *physical, int *prot,
  41                         target_ulong address, int rw, int access_type)
  42 {
  43     *physical = address;
  44     *prot = PAGE_READ | PAGE_WRITE;
  45     return TLBRET_MATCH;
  46 }
  47
  48 /* fixed mapping MMU emulation */
  49 int fixed_mmu_map_address (CPUState *env, target_phys_addr_t *physical, int *prot,
  50                            target_ulong address, int rw, int access_type)
  51 {
  52     if (address <= (int32_t)0x7FFFFFFFUL) {
  53         if (!(env->CP0_Status & (1 << CP0St_ERL)))
  54             *physical = address + 0x40000000UL;
  55         else
  56             *physical = address;
  57     } else if (address <= (int32_t)0xBFFFFFFFUL)
  58         *physical = address & 0x1FFFFFFF;
  59     else
  60         *physical = address;
  61
  62     *prot = PAGE_READ | PAGE_WRITE;
  63     return TLBRET_MATCH;
  64 }
  65
  66 /* MIPS32/MIPS64 R4000-style MMU emulation */
  67 int r4k_map_address (CPUState *env, target_phys_addr_t *physical, int *prot,
  68                      target_ulong address, int rw, int access_type)
  69 {
  70     uint8_t ASID = env->CP0_EntryHi & 0xFF;
  71     int i;
  72
  73     for (i = 0; i < env->tlb->tlb_in_use; i++) {
  74         r4k_tlb_t *tlb = &env->tlb->mmu.r4k.tlb[i];
  75         /* 1k pages are not supported. */
  76         target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
  77         target_ulong tag = address & ~mask;
  78         target_ulong VPN = tlb->VPN & ~mask;
  79 #if defined(TARGET_MIPS64)
  80         tag &= env->SEGMask;
  81 #endif
  82
  83         /* Check ASID, virtual page number & size */
  84         if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
  85             /* TLB match */
  86             int n = !!(address & mask & ~(mask >> 1));
  87             /* Check access rights */
  88             if (!(n ? tlb->V1 : tlb->V0))
  89                 return TLBRET_INVALID;
  90             if (rw == 0 || (n ? tlb->D1 : tlb->D0)) {
  91                 *physical = tlb->PFN[n] | (address & (mask >> 1));
  92                 *prot = PAGE_READ;
  93                 if (n ? tlb->D1 : tlb->D0)
  94                     *prot |= PAGE_WRITE;
  95                 return TLBRET_MATCH;
  96             }
  97             return TLBRET_DIRTY;
  98         }
  99     }
 100     return TLBRET_NOMATCH;
 101 }
 102
 103 static int get_physical_address (CPUState *env, target_phys_addr_t *physical,
 104                                 int *prot, target_ulong address,
 105                                 int rw, int access_type)
 106 {
 107     /* User mode can only access useg/xuseg */
 108     int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM;
 109     int supervisor_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_SM;
 110     int kernel_mode = !user_mode && !supervisor_mode;
 111 #if defined(TARGET_MIPS64)
 112     int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
 113     int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
 114     int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
 115 #endif
 116     int ret = TLBRET_MATCH;
 117
 118 #if 0
 119     qemu_log("user mode %d h %08x\n", user_mode, env->hflags);
 120 #endif
 121
 122     if (address <= (int32_t)0x7FFFFFFFUL) {
 123         /* useg */
 124         if (env->CP0_Status & (1 << CP0St_ERL)) {
 125             *physical = address & 0xFFFFFFFF;
 126             *prot = PAGE_READ | PAGE_WRITE;
 127         } else {
 128             ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
 129         }
 130 #if defined(TARGET_MIPS64)
 131     } else if (address < 0x4000000000000000ULL) {
 132         /* xuseg */
 133         if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) {
 134             ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
 135         } else {
 136             ret = TLBRET_BADADDR;
 137         }
 138     } else if (address < 0x8000000000000000ULL) {
 139         /* xsseg */
 140         if ((supervisor_mode || kernel_mode) &&
 141             SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) {
 142             ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
 143         } else {
 144             ret = TLBRET_BADADDR;
 145         }
 146     } else if (address < 0xC000000000000000ULL) {
 147         /* xkphys */
 148         if (kernel_mode && KX &&
 149             (address & 0x07FFFFFFFFFFFFFFULL) <= env->PAMask) {
 150             *physical = address & env->PAMask;
 151             *prot = PAGE_READ | PAGE_WRITE;
 152         } else {
 153             ret = TLBRET_BADADDR;
 154         }
 155     } else if (address < 0xFFFFFFFF80000000ULL) {
 156         /* xkseg */
 157         if (kernel_mode && KX &&
 158             address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) {
 159             ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
 160         } else {
 161             ret = TLBRET_BADADDR;
 162         }
 163 #endif
 164     } else if (address < (int32_t)0xA0000000UL) {
 165         /* kseg0 */
 166         if (kernel_mode) {
 167             *physical = address - (int32_t)0x80000000UL;
 168             *prot = PAGE_READ | PAGE_WRITE;
 169         } else {
 170             ret = TLBRET_BADADDR;
 171         }
 172     } else if (address < (int32_t)0xC0000000UL) {
 173         /* kseg1 */
 174         if (kernel_mode) {
 175             *physical = address - (int32_t)0xA0000000UL;
 176             *prot = PAGE_READ | PAGE_WRITE;
 177         } else {
 178             ret = TLBRET_BADADDR;
 179         }
 180     } else if (address < (int32_t)0xE0000000UL) {
 181         /* sseg (kseg2) */
 182         if (supervisor_mode || kernel_mode) {
 183             ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
 184         } else {
 185             ret = TLBRET_BADADDR;
 186         }
 187     } else {
 188         /* kseg3 */
 189         /* XXX: debug segment is not emulated */
 190         if (kernel_mode) {
 191             ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
 192         } else {
 193             ret = TLBRET_BADADDR;
 194         }
 195     }
 196 #if 0
 197     qemu_log(TARGET_FMT_lx " %d %d => " TARGET_FMT_lx " %d (%d)\n",
 198             address, rw, access_type, *physical, *prot, ret);
 199 #endif
 200
 201     return ret;
 202 }
 203 #endif
 204
 205 static void raise_mmu_exception(CPUState *env, target_ulong address,
 206                                 int rw, int tlb_error)
 207 {
 208     int exception = 0, error_code = 0;
 209
 210     switch (tlb_error) {
 211     default:
 212     case TLBRET_BADADDR:
 213         /* Reference to kernel address from user mode or supervisor mode */
 214         /* Reference to supervisor address from user mode */
 215         if (rw)
 216             exception = EXCP_AdES;
 217         else
 218             exception = EXCP_AdEL;
 219         break;
 220     case TLBRET_NOMATCH:
 221         /* No TLB match for a mapped address */
 222         if (rw)
 223             exception = EXCP_TLBS;
 224         else
 225             exception = EXCP_TLBL;
 226         error_code = 1;
 227         break;
 228     case TLBRET_INVALID:
 229         /* TLB match with no valid bit */
 230         if (rw)
 231             exception = EXCP_TLBS;
 232         else
 233             exception = EXCP_TLBL;
 234         break;
 235     case TLBRET_DIRTY:
 236         /* TLB match but 'D' bit is cleared */
 237         exception = EXCP_LTLBL;
 238         break;
 239
 240     }
 241     /* Raise exception */
 242     env->CP0_BadVAddr = address;
 243     env->CP0_Context = (env->CP0_Context & ~0x007fffff) |
 244                        ((address >> 9) & 0x007ffff0);
 245     env->CP0_EntryHi =
 246         (env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1));
 247 #if defined(TARGET_MIPS64)
 248     env->CP0_EntryHi &= env->SEGMask;
 249     env->CP0_XContext = (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) |
 250                         ((address & 0xC00000000000ULL) >> (55 - env->SEGBITS)) |
 251                         ((address & ((1ULL << env->SEGBITS) - 1) & 0xFFFFFFFFFFFFE000ULL) >> 9);
 252 #endif
 253     env->exception_index = exception;
 254     env->error_code = error_code;
 255 }
 256
 257 #if !defined(CONFIG_USER_ONLY)
 258 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
 259 {
 260     target_phys_addr_t phys_addr;
 261     int prot;
 262
 263     if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0)
 264         return -1;
 265     return phys_addr;
 266 }
 267 #endif
 268
 269 int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
 270                                int mmu_idx, int is_softmmu)
 271 {
 272 #if !defined(CONFIG_USER_ONLY)
 273     target_phys_addr_t physical;
 274     int prot;
 275 #endif
 276     int access_type;
 277     int ret = 0;
 278
 279 #if 0
 280     log_cpu_state(env, 0);
 281 #endif
 282     qemu_log("%s pc " TARGET_FMT_lx " ad " TARGET_FMT_lx " rw %d mmu_idx %d smmu %d\n",
 283               __func__, env->active_tc.PC, address, rw, mmu_idx, is_softmmu);
 284
 285     rw &= 1;
 286
 287     /* data access */
 288     /* XXX: put correct access by using cpu_restore_state()
 289        correctly */
 290     access_type = ACCESS_INT;
 291 #if defined(CONFIG_USER_ONLY)
 292     ret = TLBRET_NOMATCH;
 293 #else
 294     ret = get_physical_address(env, &physical, &prot,
 295                                address, rw, access_type);
 296     qemu_log("%s address=" TARGET_FMT_lx " ret %d physical " TARGET_FMT_plx " prot %d\n",
 297               __func__, address, ret, physical, prot);
 298     if (ret == TLBRET_MATCH) {
 299        ret = tlb_set_page(env, address & TARGET_PAGE_MASK,
 300                           physical & TARGET_PAGE_MASK, prot,
 301                           mmu_idx, is_softmmu);
 302     } else if (ret < 0)
 303 #endif
 304     {
 305         raise_mmu_exception(env, address, rw, ret);
 306         ret = 1;
 307     }
 308
 309     return ret;
 310 }
 311
 312 #if !defined(CONFIG_USER_ONLY)
 313 target_phys_addr_t cpu_mips_translate_address(CPUState *env, target_ulong address, int rw)
 314 {
 315     target_phys_addr_t physical;
 316     int prot;
 317     int access_type;
 318     int ret = 0;
 319
 320     rw &= 1;
 321
 322     /* data access */
 323     access_type = ACCESS_INT;
 324     ret = get_physical_address(env, &physical, &prot,
 325                                address, rw, access_type);
 326     if (ret != TLBRET_MATCH) {
 327         raise_mmu_exception(env, address, rw, ret);
 328         return -1LL;
 329     } else {
 330         return physical;
 331     }
 332 }
 333 #endif
 334
 335 static const char * const excp_names[EXCP_LAST + 1] = {
 336     [EXCP_RESET] = "reset",
 337     [EXCP_SRESET] = "soft reset",
 338     [EXCP_DSS] = "debug single step",
 339     [EXCP_DINT] = "debug interrupt",
 340     [EXCP_NMI] = "non-maskable interrupt",
 341     [EXCP_MCHECK] = "machine check",
 342     [EXCP_EXT_INTERRUPT] = "interrupt",
 343     [EXCP_DFWATCH] = "deferred watchpoint",
 344     [EXCP_DIB] = "debug instruction breakpoint",
 345     [EXCP_IWATCH] = "instruction fetch watchpoint",
 346     [EXCP_AdEL] = "address error load",
 347     [EXCP_AdES] = "address error store",
 348     [EXCP_TLBF] = "TLB refill",
 349     [EXCP_IBE] = "instruction bus error",
 350     [EXCP_DBp] = "debug breakpoint",
 351     [EXCP_SYSCALL] = "syscall",
 352     [EXCP_BREAK] = "break",
 353     [EXCP_CpU] = "coprocessor unusable",
 354     [EXCP_RI] = "reserved instruction",
 355     [EXCP_OVERFLOW] = "arithmetic overflow",
 356     [EXCP_TRAP] = "trap",
 357     [EXCP_FPE] = "floating point",
 358     [EXCP_DDBS] = "debug data break store",
 359     [EXCP_DWATCH] = "data watchpoint",
 360     [EXCP_LTLBL] = "TLB modify",
 361     [EXCP_TLBL] = "TLB load",
 362     [EXCP_TLBS] = "TLB store",
 363     [EXCP_DBE] = "data bus error",
 364     [EXCP_DDBL] = "debug data break load",
 365     [EXCP_THREAD] = "thread",
 366     [EXCP_MDMX] = "MDMX",
 367     [EXCP_C2E] = "precise coprocessor 2",
 368     [EXCP_CACHE] = "cache error",
 369 };
 370
 371 #if !defined(CONFIG_USER_ONLY)
 372 static target_ulong exception_resume_pc (CPUState *env)
 373 {
 374     target_ulong bad_pc;
 375     target_ulong isa_mode;
 376
 377     isa_mode = !!(env->hflags & MIPS_HFLAG_M16);
 378     bad_pc = env->active_tc.PC | isa_mode;
 379     if (env->hflags & MIPS_HFLAG_BMASK) {
 380         /* If the exception was raised from a delay slot, come back to
 381            the jump.  */
 382         bad_pc -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);
 383     }
 384
 385     return bad_pc;
 386 }
 387 #endif
 388
 389 void do_interrupt (CPUState *env)
 390 {
 391 #if !defined(CONFIG_USER_ONLY)
 392     target_ulong offset;
 393     int cause = -1;
 394     const char *name;
 395
 396     if (qemu_log_enabled() && env->exception_index != EXCP_EXT_INTERRUPT) {
 397         if (env->exception_index < 0 || env->exception_index > EXCP_LAST)
 398             name = "unknown";
 399         else
 400             name = excp_names[env->exception_index];
 401
 402         qemu_log("%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " %s exception\n",
 403                  __func__, env->active_tc.PC, env->CP0_EPC, name);
 404     }
 405     if (env->exception_index == EXCP_EXT_INTERRUPT &&
 406         (env->hflags & MIPS_HFLAG_DM))
 407         env->exception_index = EXCP_DINT;
 408     offset = 0x180;
 409     switch (env->exception_index) {
 410     case EXCP_DSS:
 411         env->CP0_Debug |= 1 << CP0DB_DSS;
 412         /* Debug single step cannot be raised inside a delay slot and
 413            resume will always occur on the next instruction
 414            (but we assume the pc has always been updated during
 415            code translation). */
 416         env->CP0_DEPC = env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16);
 417         goto enter_debug_mode;
 418     case EXCP_DINT:
 419         env->CP0_Debug |= 1 << CP0DB_DINT;
 420         goto set_DEPC;
 421     case EXCP_DIB:
 422         env->CP0_Debug |= 1 << CP0DB_DIB;
 423         goto set_DEPC;
 424     case EXCP_DBp:
 425         env->CP0_Debug |= 1 << CP0DB_DBp;
 426         goto set_DEPC;
 427     case EXCP_DDBS:
 428         env->CP0_Debug |= 1 << CP0DB_DDBS;
 429         goto set_DEPC;
 430     case EXCP_DDBL:
 431         env->CP0_Debug |= 1 << CP0DB_DDBL;
 432     set_DEPC:
 433         env->CP0_DEPC = exception_resume_pc(env);
 434         env->hflags &= ~MIPS_HFLAG_BMASK;
 435  enter_debug_mode:
 436         env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
 437         env->hflags &= ~(MIPS_HFLAG_KSU);
 438         /* EJTAG probe trap enable is not implemented... */
 439         if (!(env->CP0_Status & (1 << CP0St_EXL)))
 440             env->CP0_Cause &= ~(1 << CP0Ca_BD);
 441         env->active_tc.PC = (int32_t)0xBFC00480;
 442         /* Exception handlers are entered in 32-bit mode.  */
 443         env->hflags &= ~(MIPS_HFLAG_M16);
 444         break;
 445     case EXCP_RESET:
 446         cpu_reset(env);
 447         break;
 448     case EXCP_SRESET:
 449         env->CP0_Status |= (1 << CP0St_SR);
 450         memset(env->CP0_WatchLo, 0, sizeof(*env->CP0_WatchLo));
 451         goto set_error_EPC;
 452     case EXCP_NMI:
 453         env->CP0_Status |= (1 << CP0St_NMI);
 454  set_error_EPC:
 455         env->CP0_ErrorEPC = exception_resume_pc(env);
 456         env->hflags &= ~MIPS_HFLAG_BMASK;
 457         env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
 458         env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
 459         env->hflags &= ~(MIPS_HFLAG_KSU);
 460         if (!(env->CP0_Status & (1 << CP0St_EXL)))
 461             env->CP0_Cause &= ~(1 << CP0Ca_BD);
 462         env->active_tc.PC = (int32_t)0xBFC00000;
 463         /* Exception handlers are entered in 32-bit mode.  */
 464         env->hflags &= ~(MIPS_HFLAG_M16);
 465         break;
 466     case EXCP_EXT_INTERRUPT:
 467         cause = 0;
 468         if (env->CP0_Cause & (1 << CP0Ca_IV))
 469             offset = 0x200;
 470         goto set_EPC;
 471     case EXCP_LTLBL:
 472         cause = 1;
 473         goto set_EPC;
 474     case EXCP_TLBL:
 475         cause = 2;
 476         if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
 477 #if defined(TARGET_MIPS64)
 478             int R = env->CP0_BadVAddr >> 62;
 479             int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
 480             int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
 481             int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
 482
 483             if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX))
 484                 offset = 0x080;
 485             else
 486 #endif
 487                 offset = 0x000;
 488         }
 489         goto set_EPC;
 490     case EXCP_TLBS:
 491         cause = 3;
 492         if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
 493 #if defined(TARGET_MIPS64)
 494             int R = env->CP0_BadVAddr >> 62;
 495             int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
 496             int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
 497             int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
 498
 499             if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX))
 500                 offset = 0x080;
 501             else
 502 #endif
 503                 offset = 0x000;
 504         }
 505         goto set_EPC;
 506     case EXCP_AdEL:
 507         cause = 4;
 508         goto set_EPC;
 509     case EXCP_AdES:
 510         cause = 5;
 511         goto set_EPC;
 512     case EXCP_IBE:
 513         cause = 6;
 514         goto set_EPC;
 515     case EXCP_DBE:
 516         cause = 7;
 517         goto set_EPC;
 518     case EXCP_SYSCALL:
 519         cause = 8;
 520         goto set_EPC;
 521     case EXCP_BREAK:
 522         cause = 9;
 523         goto set_EPC;
 524     case EXCP_RI:
 525         cause = 10;
 526         goto set_EPC;
 527     case EXCP_CpU:
 528         cause = 11;
 529         env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) |
 530                          (env->error_code << CP0Ca_CE);
 531         goto set_EPC;
 532     case EXCP_OVERFLOW:
 533         cause = 12;
 534         goto set_EPC;
 535     case EXCP_TRAP:
 536         cause = 13;
 537         goto set_EPC;
 538     case EXCP_FPE:
 539         cause = 15;
 540         goto set_EPC;
 541     case EXCP_C2E:
 542         cause = 18;
 543         goto set_EPC;
 544     case EXCP_MDMX:
 545         cause = 22;
 546         goto set_EPC;
 547     case EXCP_DWATCH:
 548         cause = 23;
 549         /* XXX: TODO: manage defered watch exceptions */
 550         goto set_EPC;
 551     case EXCP_MCHECK:
 552         cause = 24;
 553         goto set_EPC;
 554     case EXCP_THREAD:
 555         cause = 25;
 556         goto set_EPC;
 557     case EXCP_CACHE:
 558         cause = 30;
 559         if (env->CP0_Status & (1 << CP0St_BEV)) {
 560             offset = 0x100;
 561         } else {
 562             offset = 0x20000100;
 563         }
 564  set_EPC:
 565         if (!(env->CP0_Status & (1 << CP0St_EXL))) {
 566             env->CP0_EPC = exception_resume_pc(env);
 567             if (env->hflags & MIPS_HFLAG_BMASK) {
 568                 env->CP0_Cause |= (1 << CP0Ca_BD);
 569             } else {
 570                 env->CP0_Cause &= ~(1 << CP0Ca_BD);
 571             }
 572             env->CP0_Status |= (1 << CP0St_EXL);
 573             env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
 574             env->hflags &= ~(MIPS_HFLAG_KSU);
 575         }
 576         env->hflags &= ~MIPS_HFLAG_BMASK;
 577         if (env->CP0_Status & (1 << CP0St_BEV)) {
 578             env->active_tc.PC = (int32_t)0xBFC00200;
 579         } else {
 580             env->active_tc.PC = (int32_t)(env->CP0_EBase & ~0x3ff);
 581         }
 582         env->active_tc.PC += offset;
 583         /* Exception handlers are entered in 32-bit mode.  */
 584         env->hflags &= ~(MIPS_HFLAG_M16);
 585         env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC);
 586         break;
 587     default:
 588         qemu_log("Invalid MIPS exception %d. Exiting\n", env->exception_index);
 589         printf("Invalid MIPS exception %d. Exiting\n", env->exception_index);
 590         exit(1);
 591     }
 592     if (qemu_log_enabled() && env->exception_index != EXCP_EXT_INTERRUPT) {
 593         qemu_log("%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d\n"
 594                 "    S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n",
 595                 __func__, env->active_tc.PC, env->CP0_EPC, cause,
 596                 env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
 597                 env->CP0_DEPC);
 598     }
 599 #endif
 600     env->exception_index = EXCP_NONE;
 601 }
 602
 603 #if !defined(CONFIG_USER_ONLY)
 604 void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra)
 605 {
 606     r4k_tlb_t *tlb;
 607     target_ulong addr;
 608     target_ulong end;
 609     uint8_t ASID = env->CP0_EntryHi & 0xFF;
 610     target_ulong mask;
 611
 612     tlb = &env->tlb->mmu.r4k.tlb[idx];
 613     /* The qemu TLB is flushed when the ASID changes, so no need to
 614        flush these entries again.  */
 615     if (tlb->G == 0 && tlb->ASID != ASID) {
 616         return;
 617     }
 618
 619     if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) {
 620         /* For tlbwr, we can shadow the discarded entry into
 621            a new (fake) TLB entry, as long as the guest can not
 622            tell that it's there.  */
 623         env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] = *tlb;
 624         env->tlb->tlb_in_use++;
 625         return;
 626     }
 627
 628     /* 1k pages are not supported. */
 629     mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
 630     if (tlb->V0) {
 631         addr = tlb->VPN & ~mask;
 632 #if defined(TARGET_MIPS64)
 633         if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
 634             addr |= 0x3FFFFF0000000000ULL;
 635         }
 636 #endif
 637         end = addr | (mask >> 1);
 638         while (addr < end) {
 639             tlb_flush_page (env, addr);
 640             addr += TARGET_PAGE_SIZE;
 641         }
 642     }
 643     if (tlb->V1) {
 644         addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1);
 645 #if defined(TARGET_MIPS64)
 646         if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
 647             addr |= 0x3FFFFF0000000000ULL;
 648         }
 649 #endif
 650         end = addr | mask;
 651         while (addr - 1 < end) {
 652             tlb_flush_page (env, addr);
 653             addr += TARGET_PAGE_SIZE;
 654         }
 655     }
 656 }
 657 #endif