pcie/slot: fix hotplug event
[qemu.git] / hw / versatilepb.c
blob49f8f5fc56348385e606716500574fffaf63d996
1 /*
2 * ARM Versatile Platform/Application Baseboard System emulation.
4 * Copyright (c) 2005-2007 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licensed under the GPL.
8 */
10 #include "sysbus.h"
11 #include "arm-misc.h"
12 #include "primecell.h"
13 #include "devices.h"
14 #include "net.h"
15 #include "sysemu.h"
16 #include "pci.h"
17 #include "usb-ohci.h"
18 #include "boards.h"
19 #include "blockdev.h"
21 /* Primary interrupt controller. */
23 typedef struct vpb_sic_state
25 SysBusDevice busdev;
26 uint32_t level;
27 uint32_t mask;
28 uint32_t pic_enable;
29 qemu_irq parent[32];
30 int irq;
31 } vpb_sic_state;
33 static const VMStateDescription vmstate_vpb_sic = {
34 .name = "versatilepb_sic",
35 .version_id = 1,
36 .minimum_version_id = 1,
37 .fields = (VMStateField[]) {
38 VMSTATE_UINT32(level, vpb_sic_state),
39 VMSTATE_UINT32(mask, vpb_sic_state),
40 VMSTATE_UINT32(pic_enable, vpb_sic_state),
41 VMSTATE_END_OF_LIST()
45 static void vpb_sic_update(vpb_sic_state *s)
47 uint32_t flags;
49 flags = s->level & s->mask;
50 qemu_set_irq(s->parent[s->irq], flags != 0);
53 static void vpb_sic_update_pic(vpb_sic_state *s)
55 int i;
56 uint32_t mask;
58 for (i = 21; i <= 30; i++) {
59 mask = 1u << i;
60 if (!(s->pic_enable & mask))
61 continue;
62 qemu_set_irq(s->parent[i], (s->level & mask) != 0);
66 static void vpb_sic_set_irq(void *opaque, int irq, int level)
68 vpb_sic_state *s = (vpb_sic_state *)opaque;
69 if (level)
70 s->level |= 1u << irq;
71 else
72 s->level &= ~(1u << irq);
73 if (s->pic_enable & (1u << irq))
74 qemu_set_irq(s->parent[irq], level);
75 vpb_sic_update(s);
78 static uint32_t vpb_sic_read(void *opaque, target_phys_addr_t offset)
80 vpb_sic_state *s = (vpb_sic_state *)opaque;
82 switch (offset >> 2) {
83 case 0: /* STATUS */
84 return s->level & s->mask;
85 case 1: /* RAWSTAT */
86 return s->level;
87 case 2: /* ENABLE */
88 return s->mask;
89 case 4: /* SOFTINT */
90 return s->level & 1;
91 case 8: /* PICENABLE */
92 return s->pic_enable;
93 default:
94 printf ("vpb_sic_read: Bad register offset 0x%x\n", (int)offset);
95 return 0;
99 static void vpb_sic_write(void *opaque, target_phys_addr_t offset,
100 uint32_t value)
102 vpb_sic_state *s = (vpb_sic_state *)opaque;
104 switch (offset >> 2) {
105 case 2: /* ENSET */
106 s->mask |= value;
107 break;
108 case 3: /* ENCLR */
109 s->mask &= ~value;
110 break;
111 case 4: /* SOFTINTSET */
112 if (value)
113 s->mask |= 1;
114 break;
115 case 5: /* SOFTINTCLR */
116 if (value)
117 s->mask &= ~1u;
118 break;
119 case 8: /* PICENSET */
120 s->pic_enable |= (value & 0x7fe00000);
121 vpb_sic_update_pic(s);
122 break;
123 case 9: /* PICENCLR */
124 s->pic_enable &= ~value;
125 vpb_sic_update_pic(s);
126 break;
127 default:
128 printf ("vpb_sic_write: Bad register offset 0x%x\n", (int)offset);
129 return;
131 vpb_sic_update(s);
134 static CPUReadMemoryFunc * const vpb_sic_readfn[] = {
135 vpb_sic_read,
136 vpb_sic_read,
137 vpb_sic_read
140 static CPUWriteMemoryFunc * const vpb_sic_writefn[] = {
141 vpb_sic_write,
142 vpb_sic_write,
143 vpb_sic_write
146 static int vpb_sic_init(SysBusDevice *dev)
148 vpb_sic_state *s = FROM_SYSBUS(vpb_sic_state, dev);
149 int iomemtype;
150 int i;
152 qdev_init_gpio_in(&dev->qdev, vpb_sic_set_irq, 32);
153 for (i = 0; i < 32; i++) {
154 sysbus_init_irq(dev, &s->parent[i]);
156 s->irq = 31;
157 iomemtype = cpu_register_io_memory(vpb_sic_readfn,
158 vpb_sic_writefn, s,
159 DEVICE_NATIVE_ENDIAN);
160 sysbus_init_mmio(dev, 0x1000, iomemtype);
161 return 0;
164 /* Board init. */
166 /* The AB and PB boards both use the same core, just with different
167 peripherans and expansion busses. For now we emulate a subset of the
168 PB peripherals and just change the board ID. */
170 static struct arm_boot_info versatile_binfo;
172 static void versatile_init(ram_addr_t ram_size,
173 const char *boot_device,
174 const char *kernel_filename, const char *kernel_cmdline,
175 const char *initrd_filename, const char *cpu_model,
176 int board_id)
178 CPUState *env;
179 ram_addr_t ram_offset;
180 qemu_irq *cpu_pic;
181 qemu_irq pic[32];
182 qemu_irq sic[32];
183 DeviceState *dev, *sysctl;
184 PCIBus *pci_bus;
185 NICInfo *nd;
186 int n;
187 int done_smc = 0;
189 if (!cpu_model)
190 cpu_model = "arm926";
191 env = cpu_init(cpu_model);
192 if (!env) {
193 fprintf(stderr, "Unable to find CPU definition\n");
194 exit(1);
196 ram_offset = qemu_ram_alloc(NULL, "versatile.ram", ram_size);
197 /* ??? RAM should repeat to fill physical memory space. */
198 /* SDRAM at address zero. */
199 cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);
201 sysctl = qdev_create(NULL, "realview_sysctl");
202 qdev_prop_set_uint32(sysctl, "sys_id", 0x41007004);
203 qdev_init_nofail(sysctl);
204 qdev_prop_set_uint32(sysctl, "proc_id", 0x02000000);
205 sysbus_mmio_map(sysbus_from_qdev(sysctl), 0, 0x10000000);
207 cpu_pic = arm_pic_init_cpu(env);
208 dev = sysbus_create_varargs("pl190", 0x10140000,
209 cpu_pic[0], cpu_pic[1], NULL);
210 for (n = 0; n < 32; n++) {
211 pic[n] = qdev_get_gpio_in(dev, n);
213 dev = sysbus_create_simple("versatilepb_sic", 0x10003000, NULL);
214 for (n = 0; n < 32; n++) {
215 sysbus_connect_irq(sysbus_from_qdev(dev), n, pic[n]);
216 sic[n] = qdev_get_gpio_in(dev, n);
219 sysbus_create_simple("pl050_keyboard", 0x10006000, sic[3]);
220 sysbus_create_simple("pl050_mouse", 0x10007000, sic[4]);
222 dev = sysbus_create_varargs("versatile_pci", 0x40000000,
223 sic[27], sic[28], sic[29], sic[30], NULL);
224 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci");
226 /* The Versatile PCI bridge does not provide access to PCI IO space,
227 so many of the qemu PCI devices are not useable. */
228 for(n = 0; n < nb_nics; n++) {
229 nd = &nd_table[n];
231 if (!done_smc && (!nd->model || strcmp(nd->model, "smc91c111") == 0)) {
232 smc91c111_init(nd, 0x10010000, sic[25]);
233 done_smc = 1;
234 } else {
235 pci_nic_init_nofail(nd, "rtl8139", NULL);
238 if (usb_enabled) {
239 usb_ohci_init_pci(pci_bus, -1);
241 n = drive_get_max_bus(IF_SCSI);
242 while (n >= 0) {
243 pci_create_simple(pci_bus, -1, "lsi53c895a");
244 n--;
247 sysbus_create_simple("pl011", 0x101f1000, pic[12]);
248 sysbus_create_simple("pl011", 0x101f2000, pic[13]);
249 sysbus_create_simple("pl011", 0x101f3000, pic[14]);
250 sysbus_create_simple("pl011", 0x10009000, sic[6]);
252 sysbus_create_simple("pl080", 0x10130000, pic[17]);
253 sysbus_create_simple("sp804", 0x101e2000, pic[4]);
254 sysbus_create_simple("sp804", 0x101e3000, pic[5]);
256 /* The versatile/PB actually has a modified Color LCD controller
257 that includes hardware cursor support from the PL111. */
258 dev = sysbus_create_simple("pl110_versatile", 0x10120000, pic[16]);
259 /* Wire up the mux control signals from the SYS_CLCD register */
260 qdev_connect_gpio_out(sysctl, 0, qdev_get_gpio_in(dev, 0));
262 sysbus_create_varargs("pl181", 0x10005000, sic[22], sic[1], NULL);
263 sysbus_create_varargs("pl181", 0x1000b000, sic[23], sic[2], NULL);
265 /* Add PL031 Real Time Clock. */
266 sysbus_create_simple("pl031", 0x101e8000, pic[10]);
268 /* Memory map for Versatile/PB: */
269 /* 0x10000000 System registers. */
270 /* 0x10001000 PCI controller config registers. */
271 /* 0x10002000 Serial bus interface. */
272 /* 0x10003000 Secondary interrupt controller. */
273 /* 0x10004000 AACI (audio). */
274 /* 0x10005000 MMCI0. */
275 /* 0x10006000 KMI0 (keyboard). */
276 /* 0x10007000 KMI1 (mouse). */
277 /* 0x10008000 Character LCD Interface. */
278 /* 0x10009000 UART3. */
279 /* 0x1000a000 Smart card 1. */
280 /* 0x1000b000 MMCI1. */
281 /* 0x10010000 Ethernet. */
282 /* 0x10020000 USB. */
283 /* 0x10100000 SSMC. */
284 /* 0x10110000 MPMC. */
285 /* 0x10120000 CLCD Controller. */
286 /* 0x10130000 DMA Controller. */
287 /* 0x10140000 Vectored interrupt controller. */
288 /* 0x101d0000 AHB Monitor Interface. */
289 /* 0x101e0000 System Controller. */
290 /* 0x101e1000 Watchdog Interface. */
291 /* 0x101e2000 Timer 0/1. */
292 /* 0x101e3000 Timer 2/3. */
293 /* 0x101e4000 GPIO port 0. */
294 /* 0x101e5000 GPIO port 1. */
295 /* 0x101e6000 GPIO port 2. */
296 /* 0x101e7000 GPIO port 3. */
297 /* 0x101e8000 RTC. */
298 /* 0x101f0000 Smart card 0. */
299 /* 0x101f1000 UART0. */
300 /* 0x101f2000 UART1. */
301 /* 0x101f3000 UART2. */
302 /* 0x101f4000 SSPI. */
304 versatile_binfo.ram_size = ram_size;
305 versatile_binfo.kernel_filename = kernel_filename;
306 versatile_binfo.kernel_cmdline = kernel_cmdline;
307 versatile_binfo.initrd_filename = initrd_filename;
308 versatile_binfo.board_id = board_id;
309 arm_load_kernel(env, &versatile_binfo);
312 static void vpb_init(ram_addr_t ram_size,
313 const char *boot_device,
314 const char *kernel_filename, const char *kernel_cmdline,
315 const char *initrd_filename, const char *cpu_model)
317 versatile_init(ram_size,
318 boot_device,
319 kernel_filename, kernel_cmdline,
320 initrd_filename, cpu_model, 0x183);
323 static void vab_init(ram_addr_t ram_size,
324 const char *boot_device,
325 const char *kernel_filename, const char *kernel_cmdline,
326 const char *initrd_filename, const char *cpu_model)
328 versatile_init(ram_size,
329 boot_device,
330 kernel_filename, kernel_cmdline,
331 initrd_filename, cpu_model, 0x25e);
334 static QEMUMachine versatilepb_machine = {
335 .name = "versatilepb",
336 .desc = "ARM Versatile/PB (ARM926EJ-S)",
337 .init = vpb_init,
338 .use_scsi = 1,
341 static QEMUMachine versatileab_machine = {
342 .name = "versatileab",
343 .desc = "ARM Versatile/AB (ARM926EJ-S)",
344 .init = vab_init,
345 .use_scsi = 1,
348 static void versatile_machine_init(void)
350 qemu_register_machine(&versatilepb_machine);
351 qemu_register_machine(&versatileab_machine);
354 machine_init(versatile_machine_init);
356 static SysBusDeviceInfo vpb_sic_info = {
357 .init = vpb_sic_init,
358 .qdev.name = "versatilepb_sic",
359 .qdev.size = sizeof(vpb_sic_state),
360 .qdev.vmsd = &vmstate_vpb_sic,
361 .qdev.no_user = 1,
364 static void versatilepb_register_devices(void)
366 sysbus_register_withprop(&vpb_sic_info);
369 device_init(versatilepb_register_devices)