hw/versatile_pci.c

   1 /*
   2  * ARM Versatile/PB PCI host controller
   3  *
   4  * Copyright (c) 2006-2009 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the LGPL.
   8  */
   9
  10 #include "sysbus.h"
  11 #include "pci.h"
  12 #include "pci_host.h"
  13 #include "exec-memory.h"
  14
  15 typedef struct {
  16     SysBusDevice busdev;
  17     qemu_irq irq[4];
  18     int realview;
  19     MemoryRegion mem_config;
  20     MemoryRegion mem_config2;
  21     MemoryRegion isa;
  22 } PCIVPBState;
  23
  24 static inline uint32_t vpb_pci_config_addr(target_phys_addr_t addr)
  25 {
  26     return addr & 0xffffff;
  27 }
  28
  29 static void pci_vpb_config_write(void *opaque, target_phys_addr_t addr,
  30                                  uint64_t val, unsigned size)
  31 {
  32     pci_data_write(opaque, vpb_pci_config_addr(addr), val, size);
  33 }
  34
  35 static uint64_t pci_vpb_config_read(void *opaque, target_phys_addr_t addr,
  36                                     unsigned size)
  37 {
  38     uint32_t val;
  39     val = pci_data_read(opaque, vpb_pci_config_addr(addr), size);
  40     return val;
  41 }
  42
  43 static const MemoryRegionOps pci_vpb_config_ops = {
  44     .read = pci_vpb_config_read,
  45     .write = pci_vpb_config_write,
  46     .endianness = DEVICE_NATIVE_ENDIAN,
  47 };
  48
  49 static int pci_vpb_map_irq(PCIDevice *d, int irq_num)
  50 {
  51     return irq_num;
  52 }
  53
  54 static void pci_vpb_set_irq(void *opaque, int irq_num, int level)
  55 {
  56     qemu_irq *pic = opaque;
  57
  58     qemu_set_irq(pic[irq_num], level);
  59 }
  60
  61
  62 static void pci_vpb_map(SysBusDevice *dev, target_phys_addr_t base)
  63 {
  64     PCIVPBState *s = (PCIVPBState *)dev;
  65     /* Selfconfig area.  */
  66     memory_region_add_subregion(get_system_memory(), base + 0x01000000,
  67                                 &s->mem_config);
  68     /* Normal config area.  */
  69     memory_region_add_subregion(get_system_memory(), base + 0x02000000,
  70                                 &s->mem_config2);
  71
  72     if (s->realview) {
  73         /* IO memory area.  */
  74         memory_region_add_subregion(get_system_memory(), base + 0x03000000,
  75                                     &s->isa);
  76     }
  77 }
  78
  79 static void pci_vpb_unmap(SysBusDevice *dev, target_phys_addr_t base)
  80 {
  81     PCIVPBState *s = (PCIVPBState *)dev;
  82     /* Selfconfig area.  */
  83     memory_region_del_subregion(get_system_memory(), &s->mem_config);
  84     /* Normal config area.  */
  85     memory_region_del_subregion(get_system_memory(), &s->mem_config2);
  86
  87     if (s->realview) {
  88         /* IO memory area.  */
  89         memory_region_del_subregion(get_system_memory(), &s->isa);
  90     }
  91 }
  92
  93 static int pci_vpb_init(SysBusDevice *dev)
  94 {
  95     PCIVPBState *s = FROM_SYSBUS(PCIVPBState, dev);
  96     PCIBus *bus;
  97     int i;
  98
  99     for (i = 0; i < 4; i++) {
 100         sysbus_init_irq(dev, &s->irq[i]);
 101     }
 102     bus = pci_register_bus(&dev->qdev, "pci",
 103                            pci_vpb_set_irq, pci_vpb_map_irq, s->irq,
 104                            get_system_memory(), get_system_io(),
 105                            PCI_DEVFN(11, 0), 4);
 106
 107     /* ??? Register memory space.  */
 108
 109     memory_region_init_io(&s->mem_config, &pci_vpb_config_ops, bus,
 110                           "pci-vpb-selfconfig", 0x1000000);
 111     memory_region_init_io(&s->mem_config2, &pci_vpb_config_ops, bus,
 112                           "pci-vpb-config", 0x1000000);
 113     if (s->realview) {
 114         isa_mmio_setup(&s->isa, 0x0100000);
 115     }
 116
 117     sysbus_init_mmio_cb2(dev, pci_vpb_map, pci_vpb_unmap);
 118
 119     pci_create_simple(bus, -1, "versatile_pci_host");
 120     return 0;
 121 }
 122
 123 static int pci_realview_init(SysBusDevice *dev)
 124 {
 125     PCIVPBState *s = FROM_SYSBUS(PCIVPBState, dev);
 126     s->realview = 1;
 127     return pci_vpb_init(dev);
 128 }
 129
 130 static int versatile_pci_host_init(PCIDevice *d)
 131 {
 132     pci_set_word(d->config + PCI_STATUS,
 133                  PCI_STATUS_66MHZ | PCI_STATUS_DEVSEL_MEDIUM);
 134     pci_set_byte(d->config + PCI_LATENCY_TIMER, 0x10);
 135     return 0;
 136 }
 137
 138 static PCIDeviceInfo versatile_pci_host_info = {
 139     .qdev.name = "versatile_pci_host",
 140     .qdev.size = sizeof(PCIDevice),
 141     .init      = versatile_pci_host_init,
 142     .vendor_id = PCI_VENDOR_ID_XILINX,
 143     /* Both boards have the same device ID.  Oh well.  */
 144     .device_id = PCI_DEVICE_ID_XILINX_XC2VP30,
 145     .class_id  = PCI_CLASS_PROCESSOR_CO,
 146 };
 147
 148 static void versatile_pci_register_devices(void)
 149 {
 150     sysbus_register_dev("versatile_pci", sizeof(PCIVPBState), pci_vpb_init);
 151     sysbus_register_dev("realview_pci", sizeof(PCIVPBState),
 152                         pci_realview_init);
 153     pci_qdev_register(&versatile_pci_host_info);
 154 }
 155
 156 device_init(versatile_pci_register_devices)