hw/sun4u.c

   1 /*
   2  * QEMU Sun4u/Sun4v System Emulator
   3  *
   4  * Copyright (c) 2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pci.h"
  26 #include "apb_pci.h"
  27 #include "pc.h"
  28 #include "nvram.h"
  29 #include "fdc.h"
  30 #include "net.h"
  31 #include "qemu-timer.h"
  32 #include "sysemu.h"
  33 #include "boards.h"
  34 #include "firmware_abi.h"
  35 #include "fw_cfg.h"
  36 #include "sysbus.h"
  37 #include "ide.h"
  38 #include "loader.h"
  39 #include "elf.h"
  40 #include "blockdev.h"
  41
  42 //#define DEBUG_IRQ
  43 //#define DEBUG_EBUS
  44 //#define DEBUG_TIMER
  45
  46 #ifdef DEBUG_IRQ
  47 #define CPUIRQ_DPRINTF(fmt, ...)                                \
  48     do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
  49 #else
  50 #define CPUIRQ_DPRINTF(fmt, ...)
  51 #endif
  52
  53 #ifdef DEBUG_EBUS
  54 #define EBUS_DPRINTF(fmt, ...)                                  \
  55     do { printf("EBUS: " fmt , ## __VA_ARGS__); } while (0)
  56 #else
  57 #define EBUS_DPRINTF(fmt, ...)
  58 #endif
  59
  60 #ifdef DEBUG_TIMER
  61 #define TIMER_DPRINTF(fmt, ...)                                  \
  62     do { printf("TIMER: " fmt , ## __VA_ARGS__); } while (0)
  63 #else
  64 #define TIMER_DPRINTF(fmt, ...)
  65 #endif
  66
  67 #define KERNEL_LOAD_ADDR     0x00404000
  68 #define CMDLINE_ADDR         0x003ff000
  69 #define INITRD_LOAD_ADDR     0x00300000
  70 #define PROM_SIZE_MAX        (4 * 1024 * 1024)
  71 #define PROM_VADDR           0x000ffd00000ULL
  72 #define APB_SPECIAL_BASE     0x1fe00000000ULL
  73 #define APB_MEM_BASE         0x1ff00000000ULL
  74 #define APB_PCI_IO_BASE      (APB_SPECIAL_BASE + 0x02000000ULL)
  75 #define PROM_FILENAME        "openbios-sparc64"
  76 #define NVRAM_SIZE           0x2000
  77 #define MAX_IDE_BUS          2
  78 #define BIOS_CFG_IOPORT      0x510
  79 #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00)
  80 #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01)
  81 #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02)
  82
  83 #define MAX_PILS 16
  84
  85 #define TICK_MAX             0x7fffffffffffffffULL
  86
  87 struct hwdef {
  88     const char * const default_cpu_model;
  89     uint16_t machine_id;
  90     uint64_t prom_addr;
  91     uint64_t console_serial_base;
  92 };
  93
  94 typedef struct EbusState {
  95     PCIDevice pci_dev;
  96     MemoryRegion bar0;
  97     MemoryRegion bar1;
  98 } EbusState;
  99
 100 int DMA_get_channel_mode (int nchan)
 101 {
 102     return 0;
 103 }
 104 int DMA_read_memory (int nchan, void *buf, int pos, int size)
 105 {
 106     return 0;
 107 }
 108 int DMA_write_memory (int nchan, void *buf, int pos, int size)
 109 {
 110     return 0;
 111 }
 112 void DMA_hold_DREQ (int nchan) {}
 113 void DMA_release_DREQ (int nchan) {}
 114 void DMA_schedule(int nchan) {}
 115
 116 void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit)
 117 {
 118 }
 119
 120 void DMA_register_channel (int nchan,
 121                            DMA_transfer_handler transfer_handler,
 122                            void *opaque)
 123 {
 124 }
 125
 126 static int fw_cfg_boot_set(void *opaque, const char *boot_device)
 127 {
 128     fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
 129     return 0;
 130 }
 131
 132 static int sun4u_NVRAM_set_params(M48t59State *nvram, uint16_t NVRAM_size,
 133                                   const char *arch, ram_addr_t RAM_size,
 134                                   const char *boot_devices,
 135                                   uint32_t kernel_image, uint32_t kernel_size,
 136                                   const char *cmdline,
 137                                   uint32_t initrd_image, uint32_t initrd_size,
 138                                   uint32_t NVRAM_image,
 139                                   int width, int height, int depth,
 140                                   const uint8_t *macaddr)
 141 {
 142     unsigned int i;
 143     uint32_t start, end;
 144     uint8_t image[0x1ff0];
 145     struct OpenBIOS_nvpart_v1 *part_header;
 146
 147     memset(image, '\0', sizeof(image));
 148
 149     start = 0;
 150
 151     // OpenBIOS nvram variables
 152     // Variable partition
 153     part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
 154     part_header->signature = OPENBIOS_PART_SYSTEM;
 155     pstrcpy(part_header->name, sizeof(part_header->name), "system");
 156
 157     end = start + sizeof(struct OpenBIOS_nvpart_v1);
 158     for (i = 0; i < nb_prom_envs; i++)
 159         end = OpenBIOS_set_var(image, end, prom_envs[i]);
 160
 161     // End marker
 162     image[end++] = '\0';
 163
 164     end = start + ((end - start + 15) & ~15);
 165     OpenBIOS_finish_partition(part_header, end - start);
 166
 167     // free partition
 168     start = end;
 169     part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
 170     part_header->signature = OPENBIOS_PART_FREE;
 171     pstrcpy(part_header->name, sizeof(part_header->name), "free");
 172
 173     end = 0x1fd0;
 174     OpenBIOS_finish_partition(part_header, end - start);
 175
 176     Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80);
 177
 178     for (i = 0; i < sizeof(image); i++)
 179         m48t59_write(nvram, i, image[i]);
 180
 181     return 0;
 182 }
 183 static unsigned long sun4u_load_kernel(const char *kernel_filename,
 184                                        const char *initrd_filename,
 185                                        ram_addr_t RAM_size, long *initrd_size)
 186 {
 187     int linux_boot;
 188     unsigned int i;
 189     long kernel_size;
 190     uint8_t *ptr;
 191
 192     linux_boot = (kernel_filename != NULL);
 193
 194     kernel_size = 0;
 195     if (linux_boot) {
 196         int bswap_needed;
 197
 198 #ifdef BSWAP_NEEDED
 199         bswap_needed = 1;
 200 #else
 201         bswap_needed = 0;
 202 #endif
 203         kernel_size = load_elf(kernel_filename, NULL, NULL, NULL,
 204                                NULL, NULL, 1, ELF_MACHINE, 0);
 205         if (kernel_size < 0)
 206             kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
 207                                     RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
 208                                     TARGET_PAGE_SIZE);
 209         if (kernel_size < 0)
 210             kernel_size = load_image_targphys(kernel_filename,
 211                                               KERNEL_LOAD_ADDR,
 212                                               RAM_size - KERNEL_LOAD_ADDR);
 213         if (kernel_size < 0) {
 214             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 215                     kernel_filename);
 216             exit(1);
 217         }
 218
 219         /* load initrd */
 220         *initrd_size = 0;
 221         if (initrd_filename) {
 222             *initrd_size = load_image_targphys(initrd_filename,
 223                                                INITRD_LOAD_ADDR,
 224                                                RAM_size - INITRD_LOAD_ADDR);
 225             if (*initrd_size < 0) {
 226                 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 227                         initrd_filename);
 228                 exit(1);
 229             }
 230         }
 231         if (*initrd_size > 0) {
 232             for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
 233                 ptr = rom_ptr(KERNEL_LOAD_ADDR + i);
 234                 if (ldl_p(ptr + 8) == 0x48647253) { /* HdrS */
 235                     stl_p(ptr + 24, INITRD_LOAD_ADDR + KERNEL_LOAD_ADDR - 0x4000);
 236                     stl_p(ptr + 28, *initrd_size);
 237                     break;
 238                 }
 239             }
 240         }
 241     }
 242     return kernel_size;
 243 }
 244
 245 void pic_info(Monitor *mon)
 246 {
 247 }
 248
 249 void irq_info(Monitor *mon)
 250 {
 251 }
 252
 253 void cpu_check_irqs(CPUState *env)
 254 {
 255     uint32_t pil = env->pil_in |
 256                   (env->softint & ~(SOFTINT_TIMER | SOFTINT_STIMER));
 257
 258     /* check if TM or SM in SOFTINT are set
 259        setting these also causes interrupt 14 */
 260     if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) {
 261         pil |= 1 << 14;
 262     }
 263
 264     if (!pil) {
 265         if (env->interrupt_request & CPU_INTERRUPT_HARD) {
 266             CPUIRQ_DPRINTF("Reset CPU IRQ (current interrupt %x)\n",
 267                            env->interrupt_index);
 268             env->interrupt_index = 0;
 269             cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
 270         }
 271         return;
 272     }
 273
 274     if (cpu_interrupts_enabled(env)) {
 275
 276         unsigned int i;
 277
 278         for (i = 15; i > env->psrpil; i--) {
 279             if (pil & (1 << i)) {
 280                 int old_interrupt = env->interrupt_index;
 281                 int new_interrupt = TT_EXTINT | i;
 282
 283                 if (env->tl > 0 && cpu_tsptr(env)->tt > new_interrupt) {
 284                     CPUIRQ_DPRINTF("Not setting CPU IRQ: TL=%d "
 285                                    "current %x >= pending %x\n",
 286                                    env->tl, cpu_tsptr(env)->tt, new_interrupt);
 287                 } else if (old_interrupt != new_interrupt) {
 288                     env->interrupt_index = new_interrupt;
 289                     CPUIRQ_DPRINTF("Set CPU IRQ %d old=%x new=%x\n", i,
 290                                    old_interrupt, new_interrupt);
 291                     cpu_interrupt(env, CPU_INTERRUPT_HARD);
 292                 }
 293                 break;
 294             }
 295         }
 296     } else {
 297         CPUIRQ_DPRINTF("Interrupts disabled, pil=%08x pil_in=%08x softint=%08x "
 298                        "current interrupt %x\n",
 299                        pil, env->pil_in, env->softint, env->interrupt_index);
 300     }
 301 }
 302
 303 static void cpu_kick_irq(CPUState *env)
 304 {
 305     env->halted = 0;
 306     cpu_check_irqs(env);
 307     qemu_cpu_kick(env);
 308 }
 309
 310 static void cpu_set_irq(void *opaque, int irq, int level)
 311 {
 312     CPUState *env = opaque;
 313
 314     if (level) {
 315         CPUIRQ_DPRINTF("Raise CPU IRQ %d\n", irq);
 316         env->pil_in |= 1 << irq;
 317         cpu_kick_irq(env);
 318     } else {
 319         CPUIRQ_DPRINTF("Lower CPU IRQ %d\n", irq);
 320         env->pil_in &= ~(1 << irq);
 321         cpu_check_irqs(env);
 322     }
 323 }
 324
 325 typedef struct ResetData {
 326     CPUState *env;
 327     uint64_t prom_addr;
 328 } ResetData;
 329
 330 void cpu_put_timer(QEMUFile *f, CPUTimer *s)
 331 {
 332     qemu_put_be32s(f, &s->frequency);
 333     qemu_put_be32s(f, &s->disabled);
 334     qemu_put_be64s(f, &s->disabled_mask);
 335     qemu_put_sbe64s(f, &s->clock_offset);
 336
 337     qemu_put_timer(f, s->qtimer);
 338 }
 339
 340 void cpu_get_timer(QEMUFile *f, CPUTimer *s)
 341 {
 342     qemu_get_be32s(f, &s->frequency);
 343     qemu_get_be32s(f, &s->disabled);
 344     qemu_get_be64s(f, &s->disabled_mask);
 345     qemu_get_sbe64s(f, &s->clock_offset);
 346
 347     qemu_get_timer(f, s->qtimer);
 348 }
 349
 350 static CPUTimer* cpu_timer_create(const char* name, CPUState *env,
 351                                   QEMUBHFunc *cb, uint32_t frequency,
 352                                   uint64_t disabled_mask)
 353 {
 354     CPUTimer *timer = g_malloc0(sizeof (CPUTimer));
 355
 356     timer->name = name;
 357     timer->frequency = frequency;
 358     timer->disabled_mask = disabled_mask;
 359
 360     timer->disabled = 1;
 361     timer->clock_offset = qemu_get_clock_ns(vm_clock);
 362
 363     timer->qtimer = qemu_new_timer_ns(vm_clock, cb, env);
 364
 365     return timer;
 366 }
 367
 368 static void cpu_timer_reset(CPUTimer *timer)
 369 {
 370     timer->disabled = 1;
 371     timer->clock_offset = qemu_get_clock_ns(vm_clock);
 372
 373     qemu_del_timer(timer->qtimer);
 374 }
 375
 376 static void main_cpu_reset(void *opaque)
 377 {
 378     ResetData *s = (ResetData *)opaque;
 379     CPUState *env = s->env;
 380     static unsigned int nr_resets;
 381
 382     cpu_reset(env);
 383
 384     cpu_timer_reset(env->tick);
 385     cpu_timer_reset(env->stick);
 386     cpu_timer_reset(env->hstick);
 387
 388     env->gregs[1] = 0; // Memory start
 389     env->gregs[2] = ram_size; // Memory size
 390     env->gregs[3] = 0; // Machine description XXX
 391     if (nr_resets++ == 0) {
 392         /* Power on reset */
 393         env->pc = s->prom_addr + 0x20ULL;
 394     } else {
 395         env->pc = s->prom_addr + 0x40ULL;
 396     }
 397     env->npc = env->pc + 4;
 398 }
 399
 400 static void tick_irq(void *opaque)
 401 {
 402     CPUState *env = opaque;
 403
 404     CPUTimer* timer = env->tick;
 405
 406     if (timer->disabled) {
 407         CPUIRQ_DPRINTF("tick_irq: softint disabled\n");
 408         return;
 409     } else {
 410         CPUIRQ_DPRINTF("tick: fire\n");
 411     }
 412
 413     env->softint |= SOFTINT_TIMER;
 414     cpu_kick_irq(env);
 415 }
 416
 417 static void stick_irq(void *opaque)
 418 {
 419     CPUState *env = opaque;
 420
 421     CPUTimer* timer = env->stick;
 422
 423     if (timer->disabled) {
 424         CPUIRQ_DPRINTF("stick_irq: softint disabled\n");
 425         return;
 426     } else {
 427         CPUIRQ_DPRINTF("stick: fire\n");
 428     }
 429
 430     env->softint |= SOFTINT_STIMER;
 431     cpu_kick_irq(env);
 432 }
 433
 434 static void hstick_irq(void *opaque)
 435 {
 436     CPUState *env = opaque;
 437
 438     CPUTimer* timer = env->hstick;
 439
 440     if (timer->disabled) {
 441         CPUIRQ_DPRINTF("hstick_irq: softint disabled\n");
 442         return;
 443     } else {
 444         CPUIRQ_DPRINTF("hstick: fire\n");
 445     }
 446
 447     env->softint |= SOFTINT_STIMER;
 448     cpu_kick_irq(env);
 449 }
 450
 451 static int64_t cpu_to_timer_ticks(int64_t cpu_ticks, uint32_t frequency)
 452 {
 453     return muldiv64(cpu_ticks, get_ticks_per_sec(), frequency);
 454 }
 455
 456 static uint64_t timer_to_cpu_ticks(int64_t timer_ticks, uint32_t frequency)
 457 {
 458     return muldiv64(timer_ticks, frequency, get_ticks_per_sec());
 459 }
 460
 461 void cpu_tick_set_count(CPUTimer *timer, uint64_t count)
 462 {
 463     uint64_t real_count = count & ~timer->disabled_mask;
 464     uint64_t disabled_bit = count & timer->disabled_mask;
 465
 466     int64_t vm_clock_offset = qemu_get_clock_ns(vm_clock) -
 467                     cpu_to_timer_ticks(real_count, timer->frequency);
 468
 469     TIMER_DPRINTF("%s set_count count=0x%016lx (%s) p=%p\n",
 470                   timer->name, real_count,
 471                   timer->disabled?"disabled":"enabled", timer);
 472
 473     timer->disabled = disabled_bit ? 1 : 0;
 474     timer->clock_offset = vm_clock_offset;
 475 }
 476
 477 uint64_t cpu_tick_get_count(CPUTimer *timer)
 478 {
 479     uint64_t real_count = timer_to_cpu_ticks(
 480                     qemu_get_clock_ns(vm_clock) - timer->clock_offset,
 481                     timer->frequency);
 482
 483     TIMER_DPRINTF("%s get_count count=0x%016lx (%s) p=%p\n",
 484            timer->name, real_count,
 485            timer->disabled?"disabled":"enabled", timer);
 486
 487     if (timer->disabled)
 488         real_count |= timer->disabled_mask;
 489
 490     return real_count;
 491 }
 492
 493 void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit)
 494 {
 495     int64_t now = qemu_get_clock_ns(vm_clock);
 496
 497     uint64_t real_limit = limit & ~timer->disabled_mask;
 498     timer->disabled = (limit & timer->disabled_mask) ? 1 : 0;
 499
 500     int64_t expires = cpu_to_timer_ticks(real_limit, timer->frequency) +
 501                     timer->clock_offset;
 502
 503     if (expires < now) {
 504         expires = now + 1;
 505     }
 506
 507     TIMER_DPRINTF("%s set_limit limit=0x%016lx (%s) p=%p "
 508                   "called with limit=0x%016lx at 0x%016lx (delta=0x%016lx)\n",
 509                   timer->name, real_limit,
 510                   timer->disabled?"disabled":"enabled",
 511                   timer, limit,
 512                   timer_to_cpu_ticks(now - timer->clock_offset,
 513                                      timer->frequency),
 514                   timer_to_cpu_ticks(expires - now, timer->frequency));
 515
 516     if (!real_limit) {
 517         TIMER_DPRINTF("%s set_limit limit=ZERO - not starting timer\n",
 518                 timer->name);
 519         qemu_del_timer(timer->qtimer);
 520     } else if (timer->disabled) {
 521         qemu_del_timer(timer->qtimer);
 522     } else {
 523         qemu_mod_timer(timer->qtimer, expires);
 524     }
 525 }
 526
 527 static void dummy_isa_irq_handler(void *opaque, int n, int level)
 528 {
 529 }
 530
 531 /* EBUS (Eight bit bus) bridge */
 532 static void
 533 pci_ebus_init(PCIBus *bus, int devfn)
 534 {
 535     qemu_irq *isa_irq;
 536
 537     pci_create_simple(bus, devfn, "ebus");
 538     isa_irq = qemu_allocate_irqs(dummy_isa_irq_handler, NULL, 16);
 539     isa_bus_irqs(isa_irq);
 540 }
 541
 542 static int
 543 pci_ebus_init1(PCIDevice *pci_dev)
 544 {
 545     EbusState *s = DO_UPCAST(EbusState, pci_dev, pci_dev);
 546
 547     isa_bus_new(&pci_dev->qdev);
 548
 549     pci_dev->config[0x04] = 0x06; // command = bus master, pci mem
 550     pci_dev->config[0x05] = 0x00;
 551     pci_dev->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
 552     pci_dev->config[0x07] = 0x03; // status = medium devsel
 553     pci_dev->config[0x09] = 0x00; // programming i/f
 554     pci_dev->config[0x0D] = 0x0a; // latency_timer
 555
 556     isa_mmio_setup(&s->bar0, 0x1000000);
 557     pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0);
 558     isa_mmio_setup(&s->bar1, 0x800000);
 559     pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar1);
 560     return 0;
 561 }
 562
 563 static PCIDeviceInfo ebus_info = {
 564     .qdev.name = "ebus",
 565     .qdev.size = sizeof(EbusState),
 566     .init = pci_ebus_init1,
 567     .vendor_id = PCI_VENDOR_ID_SUN,
 568     .device_id = PCI_DEVICE_ID_SUN_EBUS,
 569     .revision = 0x01,
 570     .class_id = PCI_CLASS_BRIDGE_OTHER,
 571 };
 572
 573 static void pci_ebus_register(void)
 574 {
 575     pci_qdev_register(&ebus_info);
 576 }
 577
 578 device_init(pci_ebus_register);
 579
 580 static uint64_t translate_prom_address(void *opaque, uint64_t addr)
 581 {
 582     target_phys_addr_t *base_addr = (target_phys_addr_t *)opaque;
 583     return addr + *base_addr - PROM_VADDR;
 584 }
 585
 586 /* Boot PROM (OpenBIOS) */
 587 static void prom_init(target_phys_addr_t addr, const char *bios_name)
 588 {
 589     DeviceState *dev;
 590     SysBusDevice *s;
 591     char *filename;
 592     int ret;
 593
 594     dev = qdev_create(NULL, "openprom");
 595     qdev_init_nofail(dev);
 596     s = sysbus_from_qdev(dev);
 597
 598     sysbus_mmio_map(s, 0, addr);
 599
 600     /* load boot prom */
 601     if (bios_name == NULL) {
 602         bios_name = PROM_FILENAME;
 603     }
 604     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 605     if (filename) {
 606         ret = load_elf(filename, translate_prom_address, &addr,
 607                        NULL, NULL, NULL, 1, ELF_MACHINE, 0);
 608         if (ret < 0 || ret > PROM_SIZE_MAX) {
 609             ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
 610         }
 611         g_free(filename);
 612     } else {
 613         ret = -1;
 614     }
 615     if (ret < 0 || ret > PROM_SIZE_MAX) {
 616         fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
 617         exit(1);
 618     }
 619 }
 620
 621 static int prom_init1(SysBusDevice *dev)
 622 {
 623     ram_addr_t prom_offset;
 624
 625     prom_offset = qemu_ram_alloc(NULL, "sun4u.prom", PROM_SIZE_MAX);
 626     sysbus_init_mmio(dev, PROM_SIZE_MAX, prom_offset | IO_MEM_ROM);
 627     return 0;
 628 }
 629
 630 static SysBusDeviceInfo prom_info = {
 631     .init = prom_init1,
 632     .qdev.name  = "openprom",
 633     .qdev.size  = sizeof(SysBusDevice),
 634     .qdev.props = (Property[]) {
 635         {/* end of property list */}
 636     }
 637 };
 638
 639 static void prom_register_devices(void)
 640 {
 641     sysbus_register_withprop(&prom_info);
 642 }
 643
 644 device_init(prom_register_devices);
 645
 646
 647 typedef struct RamDevice
 648 {
 649     SysBusDevice busdev;
 650     uint64_t size;
 651 } RamDevice;
 652
 653 /* System RAM */
 654 static int ram_init1(SysBusDevice *dev)
 655 {
 656     ram_addr_t RAM_size, ram_offset;
 657     RamDevice *d = FROM_SYSBUS(RamDevice, dev);
 658
 659     RAM_size = d->size;
 660
 661     ram_offset = qemu_ram_alloc(NULL, "sun4u.ram", RAM_size);
 662     sysbus_init_mmio(dev, RAM_size, ram_offset);
 663     return 0;
 664 }
 665
 666 static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size)
 667 {
 668     DeviceState *dev;
 669     SysBusDevice *s;
 670     RamDevice *d;
 671
 672     /* allocate RAM */
 673     dev = qdev_create(NULL, "memory");
 674     s = sysbus_from_qdev(dev);
 675
 676     d = FROM_SYSBUS(RamDevice, s);
 677     d->size = RAM_size;
 678     qdev_init_nofail(dev);
 679
 680     sysbus_mmio_map(s, 0, addr);
 681 }
 682
 683 static SysBusDeviceInfo ram_info = {
 684     .init = ram_init1,
 685     .qdev.name  = "memory",
 686     .qdev.size  = sizeof(RamDevice),
 687     .qdev.props = (Property[]) {
 688         DEFINE_PROP_UINT64("size", RamDevice, size, 0),
 689         DEFINE_PROP_END_OF_LIST(),
 690     }
 691 };
 692
 693 static void ram_register_devices(void)
 694 {
 695     sysbus_register_withprop(&ram_info);
 696 }
 697
 698 device_init(ram_register_devices);
 699
 700 static CPUState *cpu_devinit(const char *cpu_model, const struct hwdef *hwdef)
 701 {
 702     CPUState *env;
 703     ResetData *reset_info;
 704
 705     uint32_t   tick_frequency = 100*1000000;
 706     uint32_t  stick_frequency = 100*1000000;
 707     uint32_t hstick_frequency = 100*1000000;
 708
 709     if (!cpu_model)
 710         cpu_model = hwdef->default_cpu_model;
 711     env = cpu_init(cpu_model);
 712     if (!env) {
 713         fprintf(stderr, "Unable to find Sparc CPU definition\n");
 714         exit(1);
 715     }
 716
 717     env->tick = cpu_timer_create("tick", env, tick_irq,
 718                                   tick_frequency, TICK_NPT_MASK);
 719
 720     env->stick = cpu_timer_create("stick", env, stick_irq,
 721                                    stick_frequency, TICK_INT_DIS);
 722
 723     env->hstick = cpu_timer_create("hstick", env, hstick_irq,
 724                                     hstick_frequency, TICK_INT_DIS);
 725
 726     reset_info = g_malloc0(sizeof(ResetData));
 727     reset_info->env = env;
 728     reset_info->prom_addr = hwdef->prom_addr;
 729     qemu_register_reset(main_cpu_reset, reset_info);
 730
 731     return env;
 732 }
 733
 734 static void sun4uv_init(ram_addr_t RAM_size,
 735                         const char *boot_devices,
 736                         const char *kernel_filename, const char *kernel_cmdline,
 737                         const char *initrd_filename, const char *cpu_model,
 738                         const struct hwdef *hwdef)
 739 {
 740     CPUState *env;
 741     M48t59State *nvram;
 742     unsigned int i;
 743     long initrd_size, kernel_size;
 744     PCIBus *pci_bus, *pci_bus2, *pci_bus3;
 745     qemu_irq *irq;
 746     DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 747     DriveInfo *fd[MAX_FD];
 748     void *fw_cfg;
 749
 750     /* init CPUs */
 751     env = cpu_devinit(cpu_model, hwdef);
 752
 753     /* set up devices */
 754     ram_init(0, RAM_size);
 755
 756     prom_init(hwdef->prom_addr, bios_name);
 757
 758
 759     irq = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
 760     pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, irq, &pci_bus2,
 761                            &pci_bus3);
 762     isa_mem_base = APB_PCI_IO_BASE;
 763     pci_vga_init(pci_bus);
 764
 765     // XXX Should be pci_bus3
 766     pci_ebus_init(pci_bus, -1);
 767
 768     i = 0;
 769     if (hwdef->console_serial_base) {
 770         serial_mm_init(hwdef->console_serial_base, 0, NULL, 115200,
 771                        serial_hds[i], 1, 1);
 772         i++;
 773     }
 774     for(; i < MAX_SERIAL_PORTS; i++) {
 775         if (serial_hds[i]) {
 776             serial_isa_init(i, serial_hds[i]);
 777         }
 778     }
 779
 780     for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
 781         if (parallel_hds[i]) {
 782             parallel_init(i, parallel_hds[i]);
 783         }
 784     }
 785
 786     for(i = 0; i < nb_nics; i++)
 787         pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL);
 788
 789     ide_drive_get(hd, MAX_IDE_BUS);
 790
 791     pci_cmd646_ide_init(pci_bus, hd, 1);
 792
 793     isa_create_simple("i8042");
 794     for(i = 0; i < MAX_FD; i++) {
 795         fd[i] = drive_get(IF_FLOPPY, 0, i);
 796     }
 797     fdctrl_init_isa(fd);
 798     nvram = m48t59_init_isa(0x0074, NVRAM_SIZE, 59);
 799
 800     initrd_size = 0;
 801     kernel_size = sun4u_load_kernel(kernel_filename, initrd_filename,
 802                                     ram_size, &initrd_size);
 803
 804     sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", RAM_size, boot_devices,
 805                            KERNEL_LOAD_ADDR, kernel_size,
 806                            kernel_cmdline,
 807                            INITRD_LOAD_ADDR, initrd_size,
 808                            /* XXX: need an option to load a NVRAM image */
 809                            0,
 810                            graphic_width, graphic_height, graphic_depth,
 811                            (uint8_t *)&nd_table[0].macaddr);
 812
 813     fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
 814     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
 815     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 816     fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
 817     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
 818     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 819     if (kernel_cmdline) {
 820         fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
 821                        strlen(kernel_cmdline) + 1);
 822         fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
 823                          (uint8_t*)strdup(kernel_cmdline),
 824                          strlen(kernel_cmdline) + 1);
 825     } else {
 826         fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
 827     }
 828     fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
 829     fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 830     fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_devices[0]);
 831
 832     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width);
 833     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height);
 834     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth);
 835
 836     qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
 837 }
 838
 839 enum {
 840     sun4u_id = 0,
 841     sun4v_id = 64,
 842     niagara_id,
 843 };
 844
 845 static const struct hwdef hwdefs[] = {
 846     /* Sun4u generic PC-like machine */
 847     {
 848         .default_cpu_model = "TI UltraSparc IIi",
 849         .machine_id = sun4u_id,
 850         .prom_addr = 0x1fff0000000ULL,
 851         .console_serial_base = 0,
 852     },
 853     /* Sun4v generic PC-like machine */
 854     {
 855         .default_cpu_model = "Sun UltraSparc T1",
 856         .machine_id = sun4v_id,
 857         .prom_addr = 0x1fff0000000ULL,
 858         .console_serial_base = 0,
 859     },
 860     /* Sun4v generic Niagara machine */
 861     {
 862         .default_cpu_model = "Sun UltraSparc T1",
 863         .machine_id = niagara_id,
 864         .prom_addr = 0xfff0000000ULL,
 865         .console_serial_base = 0xfff0c2c000ULL,
 866     },
 867 };
 868
 869 /* Sun4u hardware initialisation */
 870 static void sun4u_init(ram_addr_t RAM_size,
 871                        const char *boot_devices,
 872                        const char *kernel_filename, const char *kernel_cmdline,
 873                        const char *initrd_filename, const char *cpu_model)
 874 {
 875     sun4uv_init(RAM_size, boot_devices, kernel_filename,
 876                 kernel_cmdline, initrd_filename, cpu_model, &hwdefs[0]);
 877 }
 878
 879 /* Sun4v hardware initialisation */
 880 static void sun4v_init(ram_addr_t RAM_size,
 881                        const char *boot_devices,
 882                        const char *kernel_filename, const char *kernel_cmdline,
 883                        const char *initrd_filename, const char *cpu_model)
 884 {
 885     sun4uv_init(RAM_size, boot_devices, kernel_filename,
 886                 kernel_cmdline, initrd_filename, cpu_model, &hwdefs[1]);
 887 }
 888
 889 /* Niagara hardware initialisation */
 890 static void niagara_init(ram_addr_t RAM_size,
 891                          const char *boot_devices,
 892                          const char *kernel_filename, const char *kernel_cmdline,
 893                          const char *initrd_filename, const char *cpu_model)
 894 {
 895     sun4uv_init(RAM_size, boot_devices, kernel_filename,
 896                 kernel_cmdline, initrd_filename, cpu_model, &hwdefs[2]);
 897 }
 898
 899 static QEMUMachine sun4u_machine = {
 900     .name = "sun4u",
 901     .desc = "Sun4u platform",
 902     .init = sun4u_init,
 903     .max_cpus = 1, // XXX for now
 904     .is_default = 1,
 905 };
 906
 907 static QEMUMachine sun4v_machine = {
 908     .name = "sun4v",
 909     .desc = "Sun4v platform",
 910     .init = sun4v_init,
 911     .max_cpus = 1, // XXX for now
 912 };
 913
 914 static QEMUMachine niagara_machine = {
 915     .name = "Niagara",
 916     .desc = "Sun4v platform, Niagara",
 917     .init = niagara_init,
 918     .max_cpus = 1, // XXX for now
 919 };
 920
 921 static void sun4u_machine_init(void)
 922 {
 923     qemu_register_machine(&sun4u_machine);
 924     qemu_register_machine(&sun4v_machine);
 925     qemu_register_machine(&niagara_machine);
 926 }
 927
 928 machine_init(sun4u_machine_init);