2 * QEMU AMD PC-Net II (Am79C970A) PCI emulation
4 * Copyright (c) 2004 Antony T Curtis
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 /* This software was written to be compatible with the specification:
26 * AMD Am79C970A PCnet-PCI II Ethernet Controller Data-Sheet
27 * AMD Publication# 19436 Rev:E Amendment/0 Issue Date: June 2000
33 #include "qemu-timer.h"
39 //#define PCNET_DEBUG_IO
40 //#define PCNET_DEBUG_BCR
41 //#define PCNET_DEBUG_CSR
42 //#define PCNET_DEBUG_RMD
43 //#define PCNET_DEBUG_TMD
44 //#define PCNET_DEBUG_MATCH
53 static void pcnet_aprom_writeb(void *opaque
, uint32_t addr
, uint32_t val
)
55 PCNetState
*s
= opaque
;
57 printf("pcnet_aprom_writeb addr=0x%08x val=0x%02x\n", addr
, val
);
59 /* Check APROMWE bit to enable write access */
60 if (pcnet_bcr_readw(s
,2) & 0x100)
61 s
->prom
[addr
& 15] = val
;
64 static uint32_t pcnet_aprom_readb(void *opaque
, uint32_t addr
)
66 PCNetState
*s
= opaque
;
67 uint32_t val
= s
->prom
[addr
& 15];
69 printf("pcnet_aprom_readb addr=0x%08x val=0x%02x\n", addr
, val
);
74 static uint64_t pcnet_ioport_read(void *opaque
, target_phys_addr_t addr
,
77 PCNetState
*d
= opaque
;
79 if (addr
< 16 && size
== 1) {
80 return pcnet_aprom_readb(d
, addr
);
81 } else if (addr
>= 0x10 && addr
< 0x20 && size
== 2) {
82 return pcnet_ioport_readw(d
, addr
);
83 } else if (addr
>= 0x10 && addr
< 0x20 && size
== 4) {
84 return pcnet_ioport_readl(d
, addr
);
86 return ((uint64_t)1 << (size
* 8)) - 1;
89 static void pcnet_ioport_write(void *opaque
, target_phys_addr_t addr
,
90 uint64_t data
, unsigned size
)
92 PCNetState
*d
= opaque
;
94 if (addr
< 16 && size
== 1) {
95 return pcnet_aprom_writeb(d
, addr
, data
);
96 } else if (addr
>= 0x10 && addr
< 0x20 && size
== 2) {
97 return pcnet_ioport_writew(d
, addr
, data
);
98 } else if (addr
>= 0x10 && addr
< 0x20 && size
== 4) {
99 return pcnet_ioport_writel(d
, addr
, data
);
103 static const MemoryRegionOps pcnet_io_ops
= {
104 .read
= pcnet_ioport_read
,
105 .write
= pcnet_ioport_write
,
106 .endianness
= DEVICE_NATIVE_ENDIAN
,
109 static void pcnet_mmio_writeb(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
111 PCNetState
*d
= opaque
;
112 #ifdef PCNET_DEBUG_IO
113 printf("pcnet_mmio_writeb addr=0x" TARGET_FMT_plx
" val=0x%02x\n", addr
,
117 pcnet_aprom_writeb(d
, addr
& 0x0f, val
);
120 static uint32_t pcnet_mmio_readb(void *opaque
, target_phys_addr_t addr
)
122 PCNetState
*d
= opaque
;
125 val
= pcnet_aprom_readb(d
, addr
& 0x0f);
126 #ifdef PCNET_DEBUG_IO
127 printf("pcnet_mmio_readb addr=0x" TARGET_FMT_plx
" val=0x%02x\n", addr
,
133 static void pcnet_mmio_writew(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
135 PCNetState
*d
= opaque
;
136 #ifdef PCNET_DEBUG_IO
137 printf("pcnet_mmio_writew addr=0x" TARGET_FMT_plx
" val=0x%04x\n", addr
,
141 pcnet_ioport_writew(d
, addr
& 0x0f, val
);
144 pcnet_aprom_writeb(d
, addr
, val
& 0xff);
145 pcnet_aprom_writeb(d
, addr
+1, (val
& 0xff00) >> 8);
149 static uint32_t pcnet_mmio_readw(void *opaque
, target_phys_addr_t addr
)
151 PCNetState
*d
= opaque
;
154 val
= pcnet_ioport_readw(d
, addr
& 0x0f);
157 val
= pcnet_aprom_readb(d
, addr
+1);
159 val
|= pcnet_aprom_readb(d
, addr
);
161 #ifdef PCNET_DEBUG_IO
162 printf("pcnet_mmio_readw addr=0x" TARGET_FMT_plx
" val = 0x%04x\n", addr
,
168 static void pcnet_mmio_writel(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
170 PCNetState
*d
= opaque
;
171 #ifdef PCNET_DEBUG_IO
172 printf("pcnet_mmio_writel addr=0x" TARGET_FMT_plx
" val=0x%08x\n", addr
,
176 pcnet_ioport_writel(d
, addr
& 0x0f, val
);
179 pcnet_aprom_writeb(d
, addr
, val
& 0xff);
180 pcnet_aprom_writeb(d
, addr
+1, (val
& 0xff00) >> 8);
181 pcnet_aprom_writeb(d
, addr
+2, (val
& 0xff0000) >> 16);
182 pcnet_aprom_writeb(d
, addr
+3, (val
& 0xff000000) >> 24);
186 static uint32_t pcnet_mmio_readl(void *opaque
, target_phys_addr_t addr
)
188 PCNetState
*d
= opaque
;
191 val
= pcnet_ioport_readl(d
, addr
& 0x0f);
194 val
= pcnet_aprom_readb(d
, addr
+3);
196 val
|= pcnet_aprom_readb(d
, addr
+2);
198 val
|= pcnet_aprom_readb(d
, addr
+1);
200 val
|= pcnet_aprom_readb(d
, addr
);
202 #ifdef PCNET_DEBUG_IO
203 printf("pcnet_mmio_readl addr=0x" TARGET_FMT_plx
" val=0x%08x\n", addr
,
209 static const VMStateDescription vmstate_pci_pcnet
= {
212 .minimum_version_id
= 2,
213 .minimum_version_id_old
= 2,
214 .fields
= (VMStateField
[]) {
215 VMSTATE_PCI_DEVICE(pci_dev
, PCIPCNetState
),
216 VMSTATE_STRUCT(state
, PCIPCNetState
, 0, vmstate_pcnet
, PCNetState
),
217 VMSTATE_END_OF_LIST()
223 static const MemoryRegionOps pcnet_mmio_ops
= {
225 .read
= { pcnet_mmio_readb
, pcnet_mmio_readw
, pcnet_mmio_readl
},
226 .write
= { pcnet_mmio_writeb
, pcnet_mmio_writew
, pcnet_mmio_writel
},
228 .endianness
= DEVICE_NATIVE_ENDIAN
,
231 static void pci_physical_memory_write(void *dma_opaque
, target_phys_addr_t addr
,
232 uint8_t *buf
, int len
, int do_bswap
)
234 pci_dma_write(dma_opaque
, addr
, buf
, len
);
237 static void pci_physical_memory_read(void *dma_opaque
, target_phys_addr_t addr
,
238 uint8_t *buf
, int len
, int do_bswap
)
240 pci_dma_read(dma_opaque
, addr
, buf
, len
);
243 static void pci_pcnet_cleanup(VLANClientState
*nc
)
245 PCNetState
*d
= DO_UPCAST(NICState
, nc
, nc
)->opaque
;
247 pcnet_common_cleanup(d
);
250 static int pci_pcnet_uninit(PCIDevice
*dev
)
252 PCIPCNetState
*d
= DO_UPCAST(PCIPCNetState
, pci_dev
, dev
);
254 memory_region_destroy(&d
->state
.mmio
);
255 memory_region_destroy(&d
->io_bar
);
256 qemu_del_timer(d
->state
.poll_timer
);
257 qemu_free_timer(d
->state
.poll_timer
);
258 qemu_del_vlan_client(&d
->state
.nic
->nc
);
262 static NetClientInfo net_pci_pcnet_info
= {
263 .type
= NET_CLIENT_TYPE_NIC
,
264 .size
= sizeof(NICState
),
265 .can_receive
= pcnet_can_receive
,
266 .receive
= pcnet_receive
,
267 .cleanup
= pci_pcnet_cleanup
,
270 static int pci_pcnet_init(PCIDevice
*pci_dev
)
272 PCIPCNetState
*d
= DO_UPCAST(PCIPCNetState
, pci_dev
, pci_dev
);
273 PCNetState
*s
= &d
->state
;
277 printf("sizeof(RMD)=%d, sizeof(TMD)=%d\n",
278 sizeof(struct pcnet_RMD
), sizeof(struct pcnet_TMD
));
281 pci_conf
= pci_dev
->config
;
283 pci_set_word(pci_conf
+ PCI_STATUS
,
284 PCI_STATUS_FAST_BACK
| PCI_STATUS_DEVSEL_MEDIUM
);
286 pci_set_word(pci_conf
+ PCI_SUBSYSTEM_VENDOR_ID
, 0x0);
287 pci_set_word(pci_conf
+ PCI_SUBSYSTEM_ID
, 0x0);
289 pci_conf
[PCI_INTERRUPT_PIN
] = 1; /* interrupt pin A */
290 pci_conf
[PCI_MIN_GNT
] = 0x06;
291 pci_conf
[PCI_MAX_LAT
] = 0xff;
293 /* Handler for memory-mapped I/O */
294 memory_region_init_io(&d
->state
.mmio
, &pcnet_mmio_ops
, s
, "pcnet-mmio",
297 memory_region_init_io(&d
->io_bar
, &pcnet_io_ops
, s
, "pcnet-io",
299 pci_register_bar(pci_dev
, 0, PCI_BASE_ADDRESS_SPACE_IO
, &d
->io_bar
);
301 pci_register_bar(pci_dev
, 1, 0, &s
->mmio
);
303 s
->irq
= pci_dev
->irq
[0];
304 s
->phys_mem_read
= pci_physical_memory_read
;
305 s
->phys_mem_write
= pci_physical_memory_write
;
306 s
->dma_opaque
= pci_dev
;
308 if (!pci_dev
->qdev
.hotplugged
) {
309 static int loaded
= 0;
311 rom_add_option("pxe-pcnet.rom", -1);
316 return pcnet_common_init(&pci_dev
->qdev
, s
, &net_pci_pcnet_info
);
319 static void pci_reset(DeviceState
*dev
)
321 PCIPCNetState
*d
= DO_UPCAST(PCIPCNetState
, pci_dev
.qdev
, dev
);
323 pcnet_h_reset(&d
->state
);
326 static PCIDeviceInfo pcnet_info
= {
327 .qdev
.name
= "pcnet",
328 .qdev
.size
= sizeof(PCIPCNetState
),
329 .qdev
.reset
= pci_reset
,
330 .qdev
.vmsd
= &vmstate_pci_pcnet
,
331 .init
= pci_pcnet_init
,
332 .exit
= pci_pcnet_uninit
,
333 .vendor_id
= PCI_VENDOR_ID_AMD
,
334 .device_id
= PCI_DEVICE_ID_AMD_LANCE
,
336 .class_id
= PCI_CLASS_NETWORK_ETHERNET
,
337 .qdev
.props
= (Property
[]) {
338 DEFINE_NIC_PROPERTIES(PCIPCNetState
, state
.conf
),
339 DEFINE_PROP_END_OF_LIST(),
343 static void pci_pcnet_register_devices(void)
345 pci_qdev_register(&pcnet_info
);
348 device_init(pci_pcnet_register_devices
)