3 * http://www.tensilica.com/products/literature-docs/documentation/xtensa-isa-databook.htm
5 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * * Neither the name of the Open Source and Linux Lab nor the
16 * names of its contributors may be used to endorse or promote products
17 * derived from this software without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 #include "qemu/osdep.h"
34 #include "exec/exec-all.h"
35 #include "disas/disas.h"
38 #include "sysemu/sysemu.h"
39 #include "exec/cpu_ldst.h"
40 #include "exec/semihost.h"
41 #include "exec/translator.h"
43 #include "exec/helper-proto.h"
44 #include "exec/helper-gen.h"
46 #include "trace-tcg.h"
50 /* is_jmp field values */
51 #define DISAS_UPDATE DISAS_TARGET_0 /* cpu state was modified dynamically */
53 typedef struct DisasContext
{
54 const XtensaConfig
*config
;
64 int singlestep_enabled
;
68 bool sar_m32_allocated
;
80 static TCGv_i32 cpu_pc
;
81 static TCGv_i32 cpu_R
[16];
82 static TCGv_i32 cpu_FR
[16];
83 static TCGv_i32 cpu_SR
[256];
84 static TCGv_i32 cpu_UR
[256];
86 #include "exec/gen-icount.h"
88 typedef struct XtensaReg
{
100 #define XTENSA_REG_ACCESS(regname, opt, acc) { \
102 .opt_bits = XTENSA_OPTION_BIT(opt), \
106 #define XTENSA_REG(regname, opt) XTENSA_REG_ACCESS(regname, opt, SR_RWX)
108 #define XTENSA_REG_BITS_ACCESS(regname, opt, acc) { \
114 #define XTENSA_REG_BITS(regname, opt) \
115 XTENSA_REG_BITS_ACCESS(regname, opt, SR_RWX)
117 static const XtensaReg sregnames
[256] = {
118 [LBEG
] = XTENSA_REG("LBEG", XTENSA_OPTION_LOOP
),
119 [LEND
] = XTENSA_REG("LEND", XTENSA_OPTION_LOOP
),
120 [LCOUNT
] = XTENSA_REG("LCOUNT", XTENSA_OPTION_LOOP
),
121 [SAR
] = XTENSA_REG_BITS("SAR", XTENSA_OPTION_ALL
),
122 [BR
] = XTENSA_REG("BR", XTENSA_OPTION_BOOLEAN
),
123 [LITBASE
] = XTENSA_REG("LITBASE", XTENSA_OPTION_EXTENDED_L32R
),
124 [SCOMPARE1
] = XTENSA_REG("SCOMPARE1", XTENSA_OPTION_CONDITIONAL_STORE
),
125 [ACCLO
] = XTENSA_REG("ACCLO", XTENSA_OPTION_MAC16
),
126 [ACCHI
] = XTENSA_REG("ACCHI", XTENSA_OPTION_MAC16
),
127 [MR
] = XTENSA_REG("MR0", XTENSA_OPTION_MAC16
),
128 [MR
+ 1] = XTENSA_REG("MR1", XTENSA_OPTION_MAC16
),
129 [MR
+ 2] = XTENSA_REG("MR2", XTENSA_OPTION_MAC16
),
130 [MR
+ 3] = XTENSA_REG("MR3", XTENSA_OPTION_MAC16
),
131 [WINDOW_BASE
] = XTENSA_REG("WINDOW_BASE", XTENSA_OPTION_WINDOWED_REGISTER
),
132 [WINDOW_START
] = XTENSA_REG("WINDOW_START",
133 XTENSA_OPTION_WINDOWED_REGISTER
),
134 [PTEVADDR
] = XTENSA_REG("PTEVADDR", XTENSA_OPTION_MMU
),
135 [RASID
] = XTENSA_REG("RASID", XTENSA_OPTION_MMU
),
136 [ITLBCFG
] = XTENSA_REG("ITLBCFG", XTENSA_OPTION_MMU
),
137 [DTLBCFG
] = XTENSA_REG("DTLBCFG", XTENSA_OPTION_MMU
),
138 [IBREAKENABLE
] = XTENSA_REG("IBREAKENABLE", XTENSA_OPTION_DEBUG
),
139 [MEMCTL
] = XTENSA_REG_BITS("MEMCTL", XTENSA_OPTION_ALL
),
140 [CACHEATTR
] = XTENSA_REG("CACHEATTR", XTENSA_OPTION_CACHEATTR
),
141 [ATOMCTL
] = XTENSA_REG("ATOMCTL", XTENSA_OPTION_ATOMCTL
),
142 [IBREAKA
] = XTENSA_REG("IBREAKA0", XTENSA_OPTION_DEBUG
),
143 [IBREAKA
+ 1] = XTENSA_REG("IBREAKA1", XTENSA_OPTION_DEBUG
),
144 [DBREAKA
] = XTENSA_REG("DBREAKA0", XTENSA_OPTION_DEBUG
),
145 [DBREAKA
+ 1] = XTENSA_REG("DBREAKA1", XTENSA_OPTION_DEBUG
),
146 [DBREAKC
] = XTENSA_REG("DBREAKC0", XTENSA_OPTION_DEBUG
),
147 [DBREAKC
+ 1] = XTENSA_REG("DBREAKC1", XTENSA_OPTION_DEBUG
),
148 [CONFIGID0
] = XTENSA_REG_BITS_ACCESS("CONFIGID0", XTENSA_OPTION_ALL
, SR_R
),
149 [EPC1
] = XTENSA_REG("EPC1", XTENSA_OPTION_EXCEPTION
),
150 [EPC1
+ 1] = XTENSA_REG("EPC2", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
151 [EPC1
+ 2] = XTENSA_REG("EPC3", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
152 [EPC1
+ 3] = XTENSA_REG("EPC4", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
153 [EPC1
+ 4] = XTENSA_REG("EPC5", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
154 [EPC1
+ 5] = XTENSA_REG("EPC6", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
155 [EPC1
+ 6] = XTENSA_REG("EPC7", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
156 [DEPC
] = XTENSA_REG("DEPC", XTENSA_OPTION_EXCEPTION
),
157 [EPS2
] = XTENSA_REG("EPS2", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
158 [EPS2
+ 1] = XTENSA_REG("EPS3", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
159 [EPS2
+ 2] = XTENSA_REG("EPS4", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
160 [EPS2
+ 3] = XTENSA_REG("EPS5", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
161 [EPS2
+ 4] = XTENSA_REG("EPS6", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
162 [EPS2
+ 5] = XTENSA_REG("EPS7", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
163 [CONFIGID1
] = XTENSA_REG_BITS_ACCESS("CONFIGID1", XTENSA_OPTION_ALL
, SR_R
),
164 [EXCSAVE1
] = XTENSA_REG("EXCSAVE1", XTENSA_OPTION_EXCEPTION
),
165 [EXCSAVE1
+ 1] = XTENSA_REG("EXCSAVE2",
166 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
167 [EXCSAVE1
+ 2] = XTENSA_REG("EXCSAVE3",
168 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
169 [EXCSAVE1
+ 3] = XTENSA_REG("EXCSAVE4",
170 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
171 [EXCSAVE1
+ 4] = XTENSA_REG("EXCSAVE5",
172 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
173 [EXCSAVE1
+ 5] = XTENSA_REG("EXCSAVE6",
174 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
175 [EXCSAVE1
+ 6] = XTENSA_REG("EXCSAVE7",
176 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
177 [CPENABLE
] = XTENSA_REG("CPENABLE", XTENSA_OPTION_COPROCESSOR
),
178 [INTSET
] = XTENSA_REG_ACCESS("INTSET", XTENSA_OPTION_INTERRUPT
, SR_RW
),
179 [INTCLEAR
] = XTENSA_REG_ACCESS("INTCLEAR", XTENSA_OPTION_INTERRUPT
, SR_W
),
180 [INTENABLE
] = XTENSA_REG("INTENABLE", XTENSA_OPTION_INTERRUPT
),
181 [PS
] = XTENSA_REG_BITS("PS", XTENSA_OPTION_ALL
),
182 [VECBASE
] = XTENSA_REG("VECBASE", XTENSA_OPTION_RELOCATABLE_VECTOR
),
183 [EXCCAUSE
] = XTENSA_REG("EXCCAUSE", XTENSA_OPTION_EXCEPTION
),
184 [DEBUGCAUSE
] = XTENSA_REG_ACCESS("DEBUGCAUSE", XTENSA_OPTION_DEBUG
, SR_R
),
185 [CCOUNT
] = XTENSA_REG("CCOUNT", XTENSA_OPTION_TIMER_INTERRUPT
),
186 [PRID
] = XTENSA_REG_ACCESS("PRID", XTENSA_OPTION_PROCESSOR_ID
, SR_R
),
187 [ICOUNT
] = XTENSA_REG("ICOUNT", XTENSA_OPTION_DEBUG
),
188 [ICOUNTLEVEL
] = XTENSA_REG("ICOUNTLEVEL", XTENSA_OPTION_DEBUG
),
189 [EXCVADDR
] = XTENSA_REG("EXCVADDR", XTENSA_OPTION_EXCEPTION
),
190 [CCOMPARE
] = XTENSA_REG("CCOMPARE0", XTENSA_OPTION_TIMER_INTERRUPT
),
191 [CCOMPARE
+ 1] = XTENSA_REG("CCOMPARE1",
192 XTENSA_OPTION_TIMER_INTERRUPT
),
193 [CCOMPARE
+ 2] = XTENSA_REG("CCOMPARE2",
194 XTENSA_OPTION_TIMER_INTERRUPT
),
195 [MISC
] = XTENSA_REG("MISC0", XTENSA_OPTION_MISC_SR
),
196 [MISC
+ 1] = XTENSA_REG("MISC1", XTENSA_OPTION_MISC_SR
),
197 [MISC
+ 2] = XTENSA_REG("MISC2", XTENSA_OPTION_MISC_SR
),
198 [MISC
+ 3] = XTENSA_REG("MISC3", XTENSA_OPTION_MISC_SR
),
201 static const XtensaReg uregnames
[256] = {
202 [THREADPTR
] = XTENSA_REG("THREADPTR", XTENSA_OPTION_THREAD_POINTER
),
203 [FCR
] = XTENSA_REG("FCR", XTENSA_OPTION_FP_COPROCESSOR
),
204 [FSR
] = XTENSA_REG("FSR", XTENSA_OPTION_FP_COPROCESSOR
),
207 void xtensa_translate_init(void)
209 static const char * const regnames
[] = {
210 "ar0", "ar1", "ar2", "ar3",
211 "ar4", "ar5", "ar6", "ar7",
212 "ar8", "ar9", "ar10", "ar11",
213 "ar12", "ar13", "ar14", "ar15",
215 static const char * const fregnames
[] = {
216 "f0", "f1", "f2", "f3",
217 "f4", "f5", "f6", "f7",
218 "f8", "f9", "f10", "f11",
219 "f12", "f13", "f14", "f15",
223 cpu_pc
= tcg_global_mem_new_i32(cpu_env
,
224 offsetof(CPUXtensaState
, pc
), "pc");
226 for (i
= 0; i
< 16; i
++) {
227 cpu_R
[i
] = tcg_global_mem_new_i32(cpu_env
,
228 offsetof(CPUXtensaState
, regs
[i
]),
232 for (i
= 0; i
< 16; i
++) {
233 cpu_FR
[i
] = tcg_global_mem_new_i32(cpu_env
,
234 offsetof(CPUXtensaState
, fregs
[i
].f32
[FP_F32_LOW
]),
238 for (i
= 0; i
< 256; ++i
) {
239 if (sregnames
[i
].name
) {
240 cpu_SR
[i
] = tcg_global_mem_new_i32(cpu_env
,
241 offsetof(CPUXtensaState
, sregs
[i
]),
246 for (i
= 0; i
< 256; ++i
) {
247 if (uregnames
[i
].name
) {
248 cpu_UR
[i
] = tcg_global_mem_new_i32(cpu_env
,
249 offsetof(CPUXtensaState
, uregs
[i
]),
255 static inline bool option_bits_enabled(DisasContext
*dc
, uint64_t opt
)
257 return xtensa_option_bits_enabled(dc
->config
, opt
);
260 static inline bool option_enabled(DisasContext
*dc
, int opt
)
262 return xtensa_option_enabled(dc
->config
, opt
);
265 static void init_litbase(DisasContext
*dc
)
267 if (dc
->tb
->flags
& XTENSA_TBFLAG_LITBASE
) {
268 dc
->litbase
= tcg_temp_local_new_i32();
269 tcg_gen_andi_i32(dc
->litbase
, cpu_SR
[LITBASE
], 0xfffff000);
273 static void reset_litbase(DisasContext
*dc
)
275 if (dc
->tb
->flags
& XTENSA_TBFLAG_LITBASE
) {
276 tcg_temp_free(dc
->litbase
);
280 static void init_sar_tracker(DisasContext
*dc
)
282 dc
->sar_5bit
= false;
283 dc
->sar_m32_5bit
= false;
284 dc
->sar_m32_allocated
= false;
287 static void reset_sar_tracker(DisasContext
*dc
)
289 if (dc
->sar_m32_allocated
) {
290 tcg_temp_free(dc
->sar_m32
);
294 static void gen_right_shift_sar(DisasContext
*dc
, TCGv_i32 sa
)
296 tcg_gen_andi_i32(cpu_SR
[SAR
], sa
, 0x1f);
297 if (dc
->sar_m32_5bit
) {
298 tcg_gen_discard_i32(dc
->sar_m32
);
301 dc
->sar_m32_5bit
= false;
304 static void gen_left_shift_sar(DisasContext
*dc
, TCGv_i32 sa
)
306 TCGv_i32 tmp
= tcg_const_i32(32);
307 if (!dc
->sar_m32_allocated
) {
308 dc
->sar_m32
= tcg_temp_local_new_i32();
309 dc
->sar_m32_allocated
= true;
311 tcg_gen_andi_i32(dc
->sar_m32
, sa
, 0x1f);
312 tcg_gen_sub_i32(cpu_SR
[SAR
], tmp
, dc
->sar_m32
);
313 dc
->sar_5bit
= false;
314 dc
->sar_m32_5bit
= true;
318 static void gen_exception(DisasContext
*dc
, int excp
)
320 TCGv_i32 tmp
= tcg_const_i32(excp
);
321 gen_helper_exception(cpu_env
, tmp
);
325 static void gen_exception_cause(DisasContext
*dc
, uint32_t cause
)
327 TCGv_i32 tpc
= tcg_const_i32(dc
->pc
);
328 TCGv_i32 tcause
= tcg_const_i32(cause
);
329 gen_helper_exception_cause(cpu_env
, tpc
, tcause
);
331 tcg_temp_free(tcause
);
332 if (cause
== ILLEGAL_INSTRUCTION_CAUSE
||
333 cause
== SYSCALL_CAUSE
) {
334 dc
->is_jmp
= DISAS_UPDATE
;
338 static void gen_exception_cause_vaddr(DisasContext
*dc
, uint32_t cause
,
341 TCGv_i32 tpc
= tcg_const_i32(dc
->pc
);
342 TCGv_i32 tcause
= tcg_const_i32(cause
);
343 gen_helper_exception_cause_vaddr(cpu_env
, tpc
, tcause
, vaddr
);
345 tcg_temp_free(tcause
);
348 static void gen_debug_exception(DisasContext
*dc
, uint32_t cause
)
350 TCGv_i32 tpc
= tcg_const_i32(dc
->pc
);
351 TCGv_i32 tcause
= tcg_const_i32(cause
);
352 gen_helper_debug_exception(cpu_env
, tpc
, tcause
);
354 tcg_temp_free(tcause
);
355 if (cause
& (DEBUGCAUSE_IB
| DEBUGCAUSE_BI
| DEBUGCAUSE_BN
)) {
356 dc
->is_jmp
= DISAS_UPDATE
;
360 static bool gen_check_privilege(DisasContext
*dc
)
363 gen_exception_cause(dc
, PRIVILEGED_CAUSE
);
364 dc
->is_jmp
= DISAS_UPDATE
;
370 static bool gen_check_cpenable(DisasContext
*dc
, unsigned cp
)
372 if (option_enabled(dc
, XTENSA_OPTION_COPROCESSOR
) &&
373 !(dc
->cpenable
& (1 << cp
))) {
374 gen_exception_cause(dc
, COPROCESSOR0_DISABLED
+ cp
);
375 dc
->is_jmp
= DISAS_UPDATE
;
381 static void gen_jump_slot(DisasContext
*dc
, TCGv dest
, int slot
)
383 tcg_gen_mov_i32(cpu_pc
, dest
);
385 tcg_gen_mov_i32(cpu_SR
[ICOUNT
], dc
->next_icount
);
387 if (dc
->singlestep_enabled
) {
388 gen_exception(dc
, EXCP_DEBUG
);
391 tcg_gen_goto_tb(slot
);
392 tcg_gen_exit_tb((uintptr_t)dc
->tb
+ slot
);
397 dc
->is_jmp
= DISAS_UPDATE
;
400 static void gen_jump(DisasContext
*dc
, TCGv dest
)
402 gen_jump_slot(dc
, dest
, -1);
405 static void gen_jumpi(DisasContext
*dc
, uint32_t dest
, int slot
)
407 TCGv_i32 tmp
= tcg_const_i32(dest
);
408 #ifndef CONFIG_USER_ONLY
409 if (((dc
->tb
->pc
^ dest
) & TARGET_PAGE_MASK
) != 0) {
413 gen_jump_slot(dc
, tmp
, slot
);
417 static void gen_callw_slot(DisasContext
*dc
, int callinc
, TCGv_i32 dest
,
420 TCGv_i32 tcallinc
= tcg_const_i32(callinc
);
422 tcg_gen_deposit_i32(cpu_SR
[PS
], cpu_SR
[PS
],
423 tcallinc
, PS_CALLINC_SHIFT
, PS_CALLINC_LEN
);
424 tcg_temp_free(tcallinc
);
425 tcg_gen_movi_i32(cpu_R
[callinc
<< 2],
426 (callinc
<< 30) | (dc
->next_pc
& 0x3fffffff));
427 gen_jump_slot(dc
, dest
, slot
);
430 static void gen_callw(DisasContext
*dc
, int callinc
, TCGv_i32 dest
)
432 gen_callw_slot(dc
, callinc
, dest
, -1);
435 static void gen_callwi(DisasContext
*dc
, int callinc
, uint32_t dest
, int slot
)
437 TCGv_i32 tmp
= tcg_const_i32(dest
);
438 #ifndef CONFIG_USER_ONLY
439 if (((dc
->tb
->pc
^ dest
) & TARGET_PAGE_MASK
) != 0) {
443 gen_callw_slot(dc
, callinc
, tmp
, slot
);
447 static bool gen_check_loop_end(DisasContext
*dc
, int slot
)
449 if (option_enabled(dc
, XTENSA_OPTION_LOOP
) &&
450 !(dc
->tb
->flags
& XTENSA_TBFLAG_EXCM
) &&
451 dc
->next_pc
== dc
->lend
) {
452 TCGLabel
*label
= gen_new_label();
454 tcg_gen_brcondi_i32(TCG_COND_EQ
, cpu_SR
[LCOUNT
], 0, label
);
455 tcg_gen_subi_i32(cpu_SR
[LCOUNT
], cpu_SR
[LCOUNT
], 1);
456 gen_jumpi(dc
, dc
->lbeg
, slot
);
457 gen_set_label(label
);
458 gen_jumpi(dc
, dc
->next_pc
, -1);
464 static void gen_jumpi_check_loop_end(DisasContext
*dc
, int slot
)
466 if (!gen_check_loop_end(dc
, slot
)) {
467 gen_jumpi(dc
, dc
->next_pc
, slot
);
471 static void gen_brcond(DisasContext
*dc
, TCGCond cond
,
472 TCGv_i32 t0
, TCGv_i32 t1
, uint32_t offset
)
474 TCGLabel
*label
= gen_new_label();
476 tcg_gen_brcond_i32(cond
, t0
, t1
, label
);
477 gen_jumpi_check_loop_end(dc
, 0);
478 gen_set_label(label
);
479 gen_jumpi(dc
, dc
->pc
+ offset
, 1);
482 static void gen_brcondi(DisasContext
*dc
, TCGCond cond
,
483 TCGv_i32 t0
, uint32_t t1
, uint32_t offset
)
485 TCGv_i32 tmp
= tcg_const_i32(t1
);
486 gen_brcond(dc
, cond
, t0
, tmp
, offset
);
490 static bool gen_check_sr(DisasContext
*dc
, uint32_t sr
, unsigned access
)
492 if (!xtensa_option_bits_enabled(dc
->config
, sregnames
[sr
].opt_bits
)) {
493 if (sregnames
[sr
].name
) {
494 qemu_log_mask(LOG_GUEST_ERROR
, "SR %s is not configured\n", sregnames
[sr
].name
);
496 qemu_log_mask(LOG_UNIMP
, "SR %d is not implemented\n", sr
);
498 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
500 } else if (!(sregnames
[sr
].access
& access
)) {
501 static const char * const access_text
[] = {
506 assert(access
< ARRAY_SIZE(access_text
) && access_text
[access
]);
507 qemu_log_mask(LOG_GUEST_ERROR
, "SR %s is not available for %s\n", sregnames
[sr
].name
,
508 access_text
[access
]);
509 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
515 static bool gen_rsr_ccount(DisasContext
*dc
, TCGv_i32 d
, uint32_t sr
)
517 if (tb_cflags(dc
->tb
) & CF_USE_ICOUNT
) {
520 gen_helper_update_ccount(cpu_env
);
521 tcg_gen_mov_i32(d
, cpu_SR
[sr
]);
522 if (tb_cflags(dc
->tb
) & CF_USE_ICOUNT
) {
529 static bool gen_rsr_ptevaddr(DisasContext
*dc
, TCGv_i32 d
, uint32_t sr
)
531 tcg_gen_shri_i32(d
, cpu_SR
[EXCVADDR
], 10);
532 tcg_gen_or_i32(d
, d
, cpu_SR
[sr
]);
533 tcg_gen_andi_i32(d
, d
, 0xfffffffc);
537 static bool gen_rsr(DisasContext
*dc
, TCGv_i32 d
, uint32_t sr
)
539 static bool (* const rsr_handler
[256])(DisasContext
*dc
,
540 TCGv_i32 d
, uint32_t sr
) = {
541 [CCOUNT
] = gen_rsr_ccount
,
542 [INTSET
] = gen_rsr_ccount
,
543 [PTEVADDR
] = gen_rsr_ptevaddr
,
546 if (rsr_handler
[sr
]) {
547 return rsr_handler
[sr
](dc
, d
, sr
);
549 tcg_gen_mov_i32(d
, cpu_SR
[sr
]);
554 static bool gen_wsr_lbeg(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
556 gen_helper_wsr_lbeg(cpu_env
, s
);
557 gen_jumpi_check_loop_end(dc
, 0);
561 static bool gen_wsr_lend(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
563 gen_helper_wsr_lend(cpu_env
, s
);
564 gen_jumpi_check_loop_end(dc
, 0);
568 static bool gen_wsr_sar(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
570 tcg_gen_andi_i32(cpu_SR
[sr
], s
, 0x3f);
571 if (dc
->sar_m32_5bit
) {
572 tcg_gen_discard_i32(dc
->sar_m32
);
574 dc
->sar_5bit
= false;
575 dc
->sar_m32_5bit
= false;
579 static bool gen_wsr_br(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
581 tcg_gen_andi_i32(cpu_SR
[sr
], s
, 0xffff);
585 static bool gen_wsr_litbase(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
587 tcg_gen_andi_i32(cpu_SR
[sr
], s
, 0xfffff001);
588 /* This can change tb->flags, so exit tb */
589 gen_jumpi_check_loop_end(dc
, -1);
593 static bool gen_wsr_acchi(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
595 tcg_gen_ext8s_i32(cpu_SR
[sr
], s
);
599 static bool gen_wsr_windowbase(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
601 gen_helper_wsr_windowbase(cpu_env
, v
);
602 /* This can change tb->flags, so exit tb */
603 gen_jumpi_check_loop_end(dc
, -1);
607 static bool gen_wsr_windowstart(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
609 tcg_gen_andi_i32(cpu_SR
[sr
], v
, (1 << dc
->config
->nareg
/ 4) - 1);
610 /* This can change tb->flags, so exit tb */
611 gen_jumpi_check_loop_end(dc
, -1);
615 static bool gen_wsr_ptevaddr(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
617 tcg_gen_andi_i32(cpu_SR
[sr
], v
, 0xffc00000);
621 static bool gen_wsr_rasid(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
623 gen_helper_wsr_rasid(cpu_env
, v
);
624 /* This can change tb->flags, so exit tb */
625 gen_jumpi_check_loop_end(dc
, -1);
629 static bool gen_wsr_tlbcfg(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
631 tcg_gen_andi_i32(cpu_SR
[sr
], v
, 0x01130000);
635 static bool gen_wsr_ibreakenable(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
637 gen_helper_wsr_ibreakenable(cpu_env
, v
);
638 gen_jumpi_check_loop_end(dc
, 0);
642 static bool gen_wsr_memctl(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
644 gen_helper_wsr_memctl(cpu_env
, v
);
648 static bool gen_wsr_atomctl(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
650 tcg_gen_andi_i32(cpu_SR
[sr
], v
, 0x3f);
654 static bool gen_wsr_ibreaka(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
656 unsigned id
= sr
- IBREAKA
;
658 if (id
< dc
->config
->nibreak
) {
659 TCGv_i32 tmp
= tcg_const_i32(id
);
660 gen_helper_wsr_ibreaka(cpu_env
, tmp
, v
);
662 gen_jumpi_check_loop_end(dc
, 0);
668 static bool gen_wsr_dbreaka(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
670 unsigned id
= sr
- DBREAKA
;
672 if (id
< dc
->config
->ndbreak
) {
673 TCGv_i32 tmp
= tcg_const_i32(id
);
674 gen_helper_wsr_dbreaka(cpu_env
, tmp
, v
);
680 static bool gen_wsr_dbreakc(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
682 unsigned id
= sr
- DBREAKC
;
684 if (id
< dc
->config
->ndbreak
) {
685 TCGv_i32 tmp
= tcg_const_i32(id
);
686 gen_helper_wsr_dbreakc(cpu_env
, tmp
, v
);
692 static bool gen_wsr_cpenable(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
694 tcg_gen_andi_i32(cpu_SR
[sr
], v
, 0xff);
695 /* This can change tb->flags, so exit tb */
696 gen_jumpi_check_loop_end(dc
, -1);
700 static void gen_check_interrupts(DisasContext
*dc
)
702 if (tb_cflags(dc
->tb
) & CF_USE_ICOUNT
) {
705 gen_helper_check_interrupts(cpu_env
);
706 if (tb_cflags(dc
->tb
) & CF_USE_ICOUNT
) {
711 static bool gen_wsr_intset(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
713 tcg_gen_andi_i32(cpu_SR
[sr
], v
,
714 dc
->config
->inttype_mask
[INTTYPE_SOFTWARE
]);
715 gen_check_interrupts(dc
);
716 gen_jumpi_check_loop_end(dc
, 0);
720 static bool gen_wsr_intclear(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
722 TCGv_i32 tmp
= tcg_temp_new_i32();
724 tcg_gen_andi_i32(tmp
, v
,
725 dc
->config
->inttype_mask
[INTTYPE_EDGE
] |
726 dc
->config
->inttype_mask
[INTTYPE_NMI
] |
727 dc
->config
->inttype_mask
[INTTYPE_SOFTWARE
]);
728 tcg_gen_andc_i32(cpu_SR
[INTSET
], cpu_SR
[INTSET
], tmp
);
730 gen_check_interrupts(dc
);
731 gen_jumpi_check_loop_end(dc
, 0);
735 static bool gen_wsr_intenable(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
737 tcg_gen_mov_i32(cpu_SR
[sr
], v
);
738 gen_check_interrupts(dc
);
739 gen_jumpi_check_loop_end(dc
, 0);
743 static bool gen_wsr_ps(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
745 uint32_t mask
= PS_WOE
| PS_CALLINC
| PS_OWB
|
746 PS_UM
| PS_EXCM
| PS_INTLEVEL
;
748 if (option_enabled(dc
, XTENSA_OPTION_MMU
)) {
751 tcg_gen_andi_i32(cpu_SR
[sr
], v
, mask
);
752 gen_check_interrupts(dc
);
753 /* This can change mmu index and tb->flags, so exit tb */
754 gen_jumpi_check_loop_end(dc
, -1);
758 static bool gen_wsr_ccount(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
760 if (tb_cflags(dc
->tb
) & CF_USE_ICOUNT
) {
763 gen_helper_wsr_ccount(cpu_env
, v
);
764 if (tb_cflags(dc
->tb
) & CF_USE_ICOUNT
) {
766 gen_jumpi_check_loop_end(dc
, 0);
772 static bool gen_wsr_icount(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
775 tcg_gen_mov_i32(dc
->next_icount
, v
);
777 tcg_gen_mov_i32(cpu_SR
[sr
], v
);
782 static bool gen_wsr_icountlevel(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
784 tcg_gen_andi_i32(cpu_SR
[sr
], v
, 0xf);
785 /* This can change tb->flags, so exit tb */
786 gen_jumpi_check_loop_end(dc
, -1);
790 static bool gen_wsr_ccompare(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
792 uint32_t id
= sr
- CCOMPARE
;
795 if (id
< dc
->config
->nccompare
) {
796 uint32_t int_bit
= 1 << dc
->config
->timerint
[id
];
797 TCGv_i32 tmp
= tcg_const_i32(id
);
799 tcg_gen_mov_i32(cpu_SR
[sr
], v
);
800 tcg_gen_andi_i32(cpu_SR
[INTSET
], cpu_SR
[INTSET
], ~int_bit
);
801 if (tb_cflags(dc
->tb
) & CF_USE_ICOUNT
) {
804 gen_helper_update_ccompare(cpu_env
, tmp
);
805 if (tb_cflags(dc
->tb
) & CF_USE_ICOUNT
) {
807 gen_jumpi_check_loop_end(dc
, 0);
815 static bool gen_wsr(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
817 static bool (* const wsr_handler
[256])(DisasContext
*dc
,
818 uint32_t sr
, TCGv_i32 v
) = {
819 [LBEG
] = gen_wsr_lbeg
,
820 [LEND
] = gen_wsr_lend
,
823 [LITBASE
] = gen_wsr_litbase
,
824 [ACCHI
] = gen_wsr_acchi
,
825 [WINDOW_BASE
] = gen_wsr_windowbase
,
826 [WINDOW_START
] = gen_wsr_windowstart
,
827 [PTEVADDR
] = gen_wsr_ptevaddr
,
828 [RASID
] = gen_wsr_rasid
,
829 [ITLBCFG
] = gen_wsr_tlbcfg
,
830 [DTLBCFG
] = gen_wsr_tlbcfg
,
831 [IBREAKENABLE
] = gen_wsr_ibreakenable
,
832 [MEMCTL
] = gen_wsr_memctl
,
833 [ATOMCTL
] = gen_wsr_atomctl
,
834 [IBREAKA
] = gen_wsr_ibreaka
,
835 [IBREAKA
+ 1] = gen_wsr_ibreaka
,
836 [DBREAKA
] = gen_wsr_dbreaka
,
837 [DBREAKA
+ 1] = gen_wsr_dbreaka
,
838 [DBREAKC
] = gen_wsr_dbreakc
,
839 [DBREAKC
+ 1] = gen_wsr_dbreakc
,
840 [CPENABLE
] = gen_wsr_cpenable
,
841 [INTSET
] = gen_wsr_intset
,
842 [INTCLEAR
] = gen_wsr_intclear
,
843 [INTENABLE
] = gen_wsr_intenable
,
845 [CCOUNT
] = gen_wsr_ccount
,
846 [ICOUNT
] = gen_wsr_icount
,
847 [ICOUNTLEVEL
] = gen_wsr_icountlevel
,
848 [CCOMPARE
] = gen_wsr_ccompare
,
849 [CCOMPARE
+ 1] = gen_wsr_ccompare
,
850 [CCOMPARE
+ 2] = gen_wsr_ccompare
,
853 if (wsr_handler
[sr
]) {
854 return wsr_handler
[sr
](dc
, sr
, s
);
856 tcg_gen_mov_i32(cpu_SR
[sr
], s
);
861 static void gen_wur(uint32_t ur
, TCGv_i32 s
)
865 gen_helper_wur_fcr(cpu_env
, s
);
869 tcg_gen_andi_i32(cpu_UR
[ur
], s
, 0xffffff80);
873 tcg_gen_mov_i32(cpu_UR
[ur
], s
);
878 static void gen_load_store_alignment(DisasContext
*dc
, int shift
,
879 TCGv_i32 addr
, bool no_hw_alignment
)
881 if (!option_enabled(dc
, XTENSA_OPTION_UNALIGNED_EXCEPTION
)) {
882 tcg_gen_andi_i32(addr
, addr
, ~0 << shift
);
883 } else if (option_enabled(dc
, XTENSA_OPTION_HW_ALIGNMENT
) &&
885 TCGLabel
*label
= gen_new_label();
886 TCGv_i32 tmp
= tcg_temp_new_i32();
887 tcg_gen_andi_i32(tmp
, addr
, ~(~0 << shift
));
888 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, label
);
889 gen_exception_cause_vaddr(dc
, LOAD_STORE_ALIGNMENT_CAUSE
, addr
);
890 gen_set_label(label
);
895 static void gen_waiti(DisasContext
*dc
, uint32_t imm4
)
897 TCGv_i32 pc
= tcg_const_i32(dc
->next_pc
);
898 TCGv_i32 intlevel
= tcg_const_i32(imm4
);
900 if (tb_cflags(dc
->tb
) & CF_USE_ICOUNT
) {
903 gen_helper_waiti(cpu_env
, pc
, intlevel
);
904 if (tb_cflags(dc
->tb
) & CF_USE_ICOUNT
) {
908 tcg_temp_free(intlevel
);
909 gen_jumpi_check_loop_end(dc
, 0);
912 static bool gen_window_check1(DisasContext
*dc
, unsigned r1
)
914 if (r1
/ 4 > dc
->window
) {
915 TCGv_i32 pc
= tcg_const_i32(dc
->pc
);
916 TCGv_i32 w
= tcg_const_i32(r1
/ 4);
918 gen_helper_window_check(cpu_env
, pc
, w
);
919 dc
->is_jmp
= DISAS_UPDATE
;
925 static bool gen_window_check2(DisasContext
*dc
, unsigned r1
, unsigned r2
)
927 return gen_window_check1(dc
, r1
> r2
? r1
: r2
);
930 static bool gen_window_check3(DisasContext
*dc
, unsigned r1
, unsigned r2
,
933 return gen_window_check2(dc
, r1
, r2
> r3
? r2
: r3
);
936 static TCGv_i32
gen_mac16_m(TCGv_i32 v
, bool hi
, bool is_unsigned
)
938 TCGv_i32 m
= tcg_temp_new_i32();
941 (is_unsigned
? tcg_gen_shri_i32
: tcg_gen_sari_i32
)(m
, v
, 16);
943 (is_unsigned
? tcg_gen_ext16u_i32
: tcg_gen_ext16s_i32
)(m
, v
);
948 static inline unsigned xtensa_op0_insn_len(unsigned op0
)
950 return op0
>= 8 ? 2 : 3;
953 static void disas_xtensa_insn(CPUXtensaState
*env
, DisasContext
*dc
)
955 #define HAS_OPTION_BITS(opt) do { \
956 if (!option_bits_enabled(dc, opt)) { \
957 qemu_log_mask(LOG_GUEST_ERROR, "Option is not enabled %s:%d\n", \
958 __FILE__, __LINE__); \
959 goto invalid_opcode; \
963 #define HAS_OPTION(opt) HAS_OPTION_BITS(XTENSA_OPTION_BIT(opt))
965 #define TBD() qemu_log_mask(LOG_UNIMP, "TBD(pc = %08x): %s:%d\n", dc->pc, __FILE__, __LINE__)
966 #define RESERVED() do { \
967 qemu_log_mask(LOG_GUEST_ERROR, "RESERVED(pc = %08x, %02x%02x%02x): %s:%d\n", \
968 dc->pc, b0, b1, b2, __FILE__, __LINE__); \
969 goto invalid_opcode; \
973 #ifdef TARGET_WORDS_BIGENDIAN
974 #define OP0 (((b0) & 0xf0) >> 4)
975 #define OP1 (((b2) & 0xf0) >> 4)
976 #define OP2 ((b2) & 0xf)
977 #define RRR_R ((b1) & 0xf)
978 #define RRR_S (((b1) & 0xf0) >> 4)
979 #define RRR_T ((b0) & 0xf)
981 #define OP0 (((b0) & 0xf))
982 #define OP1 (((b2) & 0xf))
983 #define OP2 (((b2) & 0xf0) >> 4)
984 #define RRR_R (((b1) & 0xf0) >> 4)
985 #define RRR_S (((b1) & 0xf))
986 #define RRR_T (((b0) & 0xf0) >> 4)
988 #define RRR_X ((RRR_R & 0x4) >> 2)
989 #define RRR_Y ((RRR_T & 0x4) >> 2)
990 #define RRR_W (RRR_R & 0x3)
999 #ifdef TARGET_WORDS_BIGENDIAN
1000 #define RRI4_IMM4 ((b2) & 0xf)
1002 #define RRI4_IMM4 (((b2) & 0xf0) >> 4)
1005 #define RRI8_R RRR_R
1006 #define RRI8_S RRR_S
1007 #define RRI8_T RRR_T
1008 #define RRI8_IMM8 (b2)
1009 #define RRI8_IMM8_SE ((((b2) & 0x80) ? 0xffffff00 : 0) | RRI8_IMM8)
1011 #ifdef TARGET_WORDS_BIGENDIAN
1012 #define RI16_IMM16 (((b1) << 8) | (b2))
1014 #define RI16_IMM16 (((b2) << 8) | (b1))
1017 #ifdef TARGET_WORDS_BIGENDIAN
1018 #define CALL_N (((b0) & 0xc) >> 2)
1019 #define CALL_OFFSET ((((b0) & 0x3) << 16) | ((b1) << 8) | (b2))
1021 #define CALL_N (((b0) & 0x30) >> 4)
1022 #define CALL_OFFSET ((((b0) & 0xc0) >> 6) | ((b1) << 2) | ((b2) << 10))
1024 #define CALL_OFFSET_SE \
1025 (((CALL_OFFSET & 0x20000) ? 0xfffc0000 : 0) | CALL_OFFSET)
1027 #define CALLX_N CALL_N
1028 #ifdef TARGET_WORDS_BIGENDIAN
1029 #define CALLX_M ((b0) & 0x3)
1031 #define CALLX_M (((b0) & 0xc0) >> 6)
1033 #define CALLX_S RRR_S
1035 #define BRI12_M CALLX_M
1036 #define BRI12_S RRR_S
1037 #ifdef TARGET_WORDS_BIGENDIAN
1038 #define BRI12_IMM12 ((((b1) & 0xf) << 8) | (b2))
1040 #define BRI12_IMM12 ((((b1) & 0xf0) >> 4) | ((b2) << 4))
1042 #define BRI12_IMM12_SE (((BRI12_IMM12 & 0x800) ? 0xfffff000 : 0) | BRI12_IMM12)
1044 #define BRI8_M BRI12_M
1045 #define BRI8_R RRI8_R
1046 #define BRI8_S RRI8_S
1047 #define BRI8_IMM8 RRI8_IMM8
1048 #define BRI8_IMM8_SE RRI8_IMM8_SE
1052 uint8_t b0
= cpu_ldub_code(env
, dc
->pc
);
1053 uint8_t b1
= cpu_ldub_code(env
, dc
->pc
+ 1);
1055 unsigned len
= xtensa_op0_insn_len(OP0
);
1057 static const uint32_t B4CONST
[] = {
1058 0xffffffff, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
1061 static const uint32_t B4CONSTU
[] = {
1062 32768, 65536, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
1067 HAS_OPTION(XTENSA_OPTION_CODE_DENSITY
);
1071 b2
= cpu_ldub_code(env
, dc
->pc
+ 2);
1077 dc
->next_pc
= dc
->pc
+ len
;
1085 if ((RRR_R
& 0xc) == 0x8) {
1086 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
1093 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
1096 case 1: /*reserved*/
1104 if (gen_window_check1(dc
, CALLX_S
)) {
1105 gen_jump(dc
, cpu_R
[CALLX_S
]);
1110 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
1112 TCGv_i32 tmp
= tcg_const_i32(dc
->pc
);
1113 gen_helper_retw(tmp
, cpu_env
, tmp
);
1119 case 3: /*reserved*/
1126 if (!gen_window_check2(dc
, CALLX_S
, CALLX_N
<< 2)) {
1132 TCGv_i32 tmp
= tcg_temp_new_i32();
1133 tcg_gen_mov_i32(tmp
, cpu_R
[CALLX_S
]);
1134 tcg_gen_movi_i32(cpu_R
[0], dc
->next_pc
);
1142 case 3: /*CALLX12w*/
1143 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
1145 TCGv_i32 tmp
= tcg_temp_new_i32();
1147 tcg_gen_mov_i32(tmp
, cpu_R
[CALLX_S
]);
1148 gen_callw(dc
, CALLX_N
, tmp
);
1158 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
1159 if (gen_window_check2(dc
, RRR_T
, RRR_S
)) {
1160 TCGv_i32 pc
= tcg_const_i32(dc
->pc
);
1161 gen_helper_movsp(cpu_env
, pc
);
1162 tcg_gen_mov_i32(cpu_R
[RRR_T
], cpu_R
[RRR_S
]);
1182 HAS_OPTION(XTENSA_OPTION_EXCEPTION
);
1194 default: /*reserved*/
1203 HAS_OPTION(XTENSA_OPTION_EXCEPTION
);
1206 if (gen_check_privilege(dc
)) {
1207 tcg_gen_andi_i32(cpu_SR
[PS
], cpu_SR
[PS
], ~PS_EXCM
);
1208 gen_check_interrupts(dc
);
1209 gen_jump(dc
, cpu_SR
[EPC1
]);
1218 if (gen_check_privilege(dc
)) {
1219 gen_jump(dc
, cpu_SR
[
1220 dc
->config
->ndepc
? DEPC
: EPC1
]);
1226 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
1227 if (gen_check_privilege(dc
)) {
1228 TCGv_i32 tmp
= tcg_const_i32(1);
1231 cpu_SR
[PS
], cpu_SR
[PS
], ~PS_EXCM
);
1232 tcg_gen_shl_i32(tmp
, tmp
, cpu_SR
[WINDOW_BASE
]);
1235 tcg_gen_andc_i32(cpu_SR
[WINDOW_START
],
1236 cpu_SR
[WINDOW_START
], tmp
);
1238 tcg_gen_or_i32(cpu_SR
[WINDOW_START
],
1239 cpu_SR
[WINDOW_START
], tmp
);
1242 gen_helper_restore_owb(cpu_env
);
1243 gen_check_interrupts(dc
);
1244 gen_jump(dc
, cpu_SR
[EPC1
]);
1250 default: /*reserved*/
1257 HAS_OPTION(XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
);
1258 if (RRR_S
>= 2 && RRR_S
<= dc
->config
->nlevel
) {
1259 if (gen_check_privilege(dc
)) {
1260 tcg_gen_mov_i32(cpu_SR
[PS
],
1261 cpu_SR
[EPS2
+ RRR_S
- 2]);
1262 gen_check_interrupts(dc
);
1263 gen_jump(dc
, cpu_SR
[EPC1
+ RRR_S
- 1]);
1266 qemu_log_mask(LOG_GUEST_ERROR
, "RFI %d is illegal\n", RRR_S
);
1267 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
1275 default: /*reserved*/
1283 HAS_OPTION(XTENSA_OPTION_DEBUG
);
1285 gen_debug_exception(dc
, DEBUGCAUSE_BI
);
1289 case 5: /*SYSCALLx*/
1290 HAS_OPTION(XTENSA_OPTION_EXCEPTION
);
1292 case 0: /*SYSCALLx*/
1293 gen_exception_cause(dc
, SYSCALL_CAUSE
);
1297 if (semihosting_enabled()) {
1298 if (gen_check_privilege(dc
)) {
1299 gen_helper_simcall(cpu_env
);
1302 qemu_log_mask(LOG_GUEST_ERROR
, "SIMCALL but semihosting is disabled\n");
1303 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
1314 HAS_OPTION(XTENSA_OPTION_INTERRUPT
);
1315 if (gen_check_privilege(dc
) &&
1316 gen_window_check1(dc
, RRR_T
)) {
1317 tcg_gen_mov_i32(cpu_R
[RRR_T
], cpu_SR
[PS
]);
1318 tcg_gen_andi_i32(cpu_SR
[PS
], cpu_SR
[PS
], ~PS_INTLEVEL
);
1319 tcg_gen_ori_i32(cpu_SR
[PS
], cpu_SR
[PS
], RRR_S
);
1320 gen_check_interrupts(dc
);
1321 gen_jumpi_check_loop_end(dc
, 0);
1326 HAS_OPTION(XTENSA_OPTION_INTERRUPT
);
1327 if (gen_check_privilege(dc
)) {
1328 gen_waiti(dc
, RRR_S
);
1336 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
1338 const unsigned shift
= (RRR_R
& 2) ? 8 : 4;
1339 TCGv_i32 mask
= tcg_const_i32(
1340 ((1 << shift
) - 1) << RRR_S
);
1341 TCGv_i32 tmp
= tcg_temp_new_i32();
1343 tcg_gen_and_i32(tmp
, cpu_SR
[BR
], mask
);
1344 if (RRR_R
& 1) { /*ALL*/
1345 tcg_gen_addi_i32(tmp
, tmp
, 1 << RRR_S
);
1347 tcg_gen_add_i32(tmp
, tmp
, mask
);
1349 tcg_gen_shri_i32(tmp
, tmp
, RRR_S
+ shift
);
1350 tcg_gen_deposit_i32(cpu_SR
[BR
], cpu_SR
[BR
],
1352 tcg_temp_free(mask
);
1357 default: /*reserved*/
1365 if (gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
)) {
1366 tcg_gen_and_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1371 if (gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
)) {
1372 tcg_gen_or_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1377 if (gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
)) {
1378 tcg_gen_xor_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1385 if (gen_window_check1(dc
, RRR_S
)) {
1386 gen_right_shift_sar(dc
, cpu_R
[RRR_S
]);
1391 if (gen_window_check1(dc
, RRR_S
)) {
1392 gen_left_shift_sar(dc
, cpu_R
[RRR_S
]);
1397 if (gen_window_check1(dc
, RRR_S
)) {
1398 TCGv_i32 tmp
= tcg_temp_new_i32();
1399 tcg_gen_shli_i32(tmp
, cpu_R
[RRR_S
], 3);
1400 gen_right_shift_sar(dc
, tmp
);
1406 if (gen_window_check1(dc
, RRR_S
)) {
1407 TCGv_i32 tmp
= tcg_temp_new_i32();
1408 tcg_gen_shli_i32(tmp
, cpu_R
[RRR_S
], 3);
1409 gen_left_shift_sar(dc
, tmp
);
1416 TCGv_i32 tmp
= tcg_const_i32(
1417 RRR_S
| ((RRR_T
& 1) << 4));
1418 gen_right_shift_sar(dc
, tmp
);
1424 HAS_OPTION(XTENSA_OPTION_EXTERN_REGS
);
1425 if (gen_check_privilege(dc
) &&
1426 gen_window_check2(dc
, RRR_S
, RRR_T
)) {
1427 gen_helper_rer(cpu_R
[RRR_T
], cpu_env
, cpu_R
[RRR_S
]);
1432 HAS_OPTION(XTENSA_OPTION_EXTERN_REGS
);
1433 if (gen_check_privilege(dc
) &&
1434 gen_window_check2(dc
, RRR_S
, RRR_T
)) {
1435 gen_helper_wer(cpu_env
, cpu_R
[RRR_T
], cpu_R
[RRR_S
]);
1440 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
1441 if (gen_check_privilege(dc
)) {
1442 TCGv_i32 tmp
= tcg_const_i32(
1443 RRR_T
| ((RRR_T
& 8) ? 0xfffffff0 : 0));
1444 gen_helper_rotw(cpu_env
, tmp
);
1446 /* This can change tb->flags, so exit tb */
1447 gen_jumpi_check_loop_end(dc
, -1);
1452 HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA
);
1453 if (gen_window_check2(dc
, RRR_S
, RRR_T
)) {
1454 tcg_gen_clrsb_i32(cpu_R
[RRR_T
], cpu_R
[RRR_S
]);
1459 HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA
);
1460 if (gen_window_check2(dc
, RRR_S
, RRR_T
)) {
1461 tcg_gen_clzi_i32(cpu_R
[RRR_T
], cpu_R
[RRR_S
], 32);
1465 default: /*reserved*/
1473 XTENSA_OPTION_BIT(XTENSA_OPTION_MMU
) |
1474 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION
) |
1475 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION
));
1476 if (gen_check_privilege(dc
) &&
1477 gen_window_check2(dc
, RRR_S
, RRR_T
)) {
1478 TCGv_i32 dtlb
= tcg_const_i32((RRR_R
& 8) != 0);
1480 switch (RRR_R
& 7) {
1481 case 3: /*RITLB0*/ /*RDTLB0*/
1482 gen_helper_rtlb0(cpu_R
[RRR_T
],
1483 cpu_env
, cpu_R
[RRR_S
], dtlb
);
1486 case 4: /*IITLB*/ /*IDTLB*/
1487 gen_helper_itlb(cpu_env
, cpu_R
[RRR_S
], dtlb
);
1488 /* This could change memory mapping, so exit tb */
1489 gen_jumpi_check_loop_end(dc
, -1);
1492 case 5: /*PITLB*/ /*PDTLB*/
1493 tcg_gen_movi_i32(cpu_pc
, dc
->pc
);
1494 gen_helper_ptlb(cpu_R
[RRR_T
],
1495 cpu_env
, cpu_R
[RRR_S
], dtlb
);
1498 case 6: /*WITLB*/ /*WDTLB*/
1500 cpu_env
, cpu_R
[RRR_T
], cpu_R
[RRR_S
], dtlb
);
1501 /* This could change memory mapping, so exit tb */
1502 gen_jumpi_check_loop_end(dc
, -1);
1505 case 7: /*RITLB1*/ /*RDTLB1*/
1506 gen_helper_rtlb1(cpu_R
[RRR_T
],
1507 cpu_env
, cpu_R
[RRR_S
], dtlb
);
1511 tcg_temp_free(dtlb
);
1515 tcg_temp_free(dtlb
);
1520 if (!gen_window_check2(dc
, RRR_R
, RRR_T
)) {
1525 tcg_gen_neg_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
]);
1530 TCGv_i32 zero
= tcg_const_i32(0);
1531 TCGv_i32 neg
= tcg_temp_new_i32();
1533 tcg_gen_neg_i32(neg
, cpu_R
[RRR_T
]);
1534 tcg_gen_movcond_i32(TCG_COND_GE
, cpu_R
[RRR_R
],
1535 cpu_R
[RRR_T
], zero
, cpu_R
[RRR_T
], neg
);
1537 tcg_temp_free(zero
);
1541 default: /*reserved*/
1547 case 7: /*reserved*/
1552 if (gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
)) {
1553 tcg_gen_add_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1560 if (gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
)) {
1561 TCGv_i32 tmp
= tcg_temp_new_i32();
1562 tcg_gen_shli_i32(tmp
, cpu_R
[RRR_S
], OP2
- 8);
1563 tcg_gen_add_i32(cpu_R
[RRR_R
], tmp
, cpu_R
[RRR_T
]);
1569 if (gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
)) {
1570 tcg_gen_sub_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1577 if (gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
)) {
1578 TCGv_i32 tmp
= tcg_temp_new_i32();
1579 tcg_gen_shli_i32(tmp
, cpu_R
[RRR_S
], OP2
- 12);
1580 tcg_gen_sub_i32(cpu_R
[RRR_R
], tmp
, cpu_R
[RRR_T
]);
1591 if (gen_window_check2(dc
, RRR_R
, RRR_S
)) {
1592 tcg_gen_shli_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
],
1593 32 - (RRR_T
| ((OP2
& 1) << 4)));
1599 if (gen_window_check2(dc
, RRR_R
, RRR_T
)) {
1600 tcg_gen_sari_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
],
1601 RRR_S
| ((OP2
& 1) << 4));
1606 if (gen_window_check2(dc
, RRR_R
, RRR_T
)) {
1607 tcg_gen_shri_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
], RRR_S
);
1612 if (gen_check_sr(dc
, RSR_SR
, SR_X
) &&
1613 (RSR_SR
< 64 || gen_check_privilege(dc
)) &&
1614 gen_window_check1(dc
, RRR_T
)) {
1615 TCGv_i32 tmp
= tcg_temp_new_i32();
1616 bool rsr_end
, wsr_end
;
1618 tcg_gen_mov_i32(tmp
, cpu_R
[RRR_T
]);
1619 rsr_end
= gen_rsr(dc
, cpu_R
[RRR_T
], RSR_SR
);
1620 wsr_end
= gen_wsr(dc
, RSR_SR
, tmp
);
1622 if (rsr_end
&& !wsr_end
) {
1623 gen_jumpi_check_loop_end(dc
, 0);
1629 * Note: 64 bit ops are used here solely because SAR values
1632 #define gen_shift_reg(cmd, reg) do { \
1633 TCGv_i64 tmp = tcg_temp_new_i64(); \
1634 tcg_gen_extu_i32_i64(tmp, reg); \
1635 tcg_gen_##cmd##_i64(v, v, tmp); \
1636 tcg_gen_extrl_i64_i32(cpu_R[RRR_R], v); \
1637 tcg_temp_free_i64(v); \
1638 tcg_temp_free_i64(tmp); \
1641 #define gen_shift(cmd) gen_shift_reg(cmd, cpu_SR[SAR])
1644 if (gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
)) {
1645 TCGv_i64 v
= tcg_temp_new_i64();
1646 tcg_gen_concat_i32_i64(v
, cpu_R
[RRR_T
], cpu_R
[RRR_S
]);
1652 if (!gen_window_check2(dc
, RRR_R
, RRR_T
)) {
1656 tcg_gen_shr_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
], cpu_SR
[SAR
]);
1658 TCGv_i64 v
= tcg_temp_new_i64();
1659 tcg_gen_extu_i32_i64(v
, cpu_R
[RRR_T
]);
1665 if (!gen_window_check2(dc
, RRR_R
, RRR_S
)) {
1668 if (dc
->sar_m32_5bit
) {
1669 tcg_gen_shl_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], dc
->sar_m32
);
1671 TCGv_i64 v
= tcg_temp_new_i64();
1672 TCGv_i32 s
= tcg_const_i32(32);
1673 tcg_gen_sub_i32(s
, s
, cpu_SR
[SAR
]);
1674 tcg_gen_andi_i32(s
, s
, 0x3f);
1675 tcg_gen_extu_i32_i64(v
, cpu_R
[RRR_S
]);
1676 gen_shift_reg(shl
, s
);
1682 if (!gen_window_check2(dc
, RRR_R
, RRR_T
)) {
1686 tcg_gen_sar_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
], cpu_SR
[SAR
]);
1688 TCGv_i64 v
= tcg_temp_new_i64();
1689 tcg_gen_ext_i32_i64(v
, cpu_R
[RRR_T
]);
1694 #undef gen_shift_reg
1697 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL
);
1698 if (gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
)) {
1699 TCGv_i32 v1
= tcg_temp_new_i32();
1700 TCGv_i32 v2
= tcg_temp_new_i32();
1701 tcg_gen_ext16u_i32(v1
, cpu_R
[RRR_S
]);
1702 tcg_gen_ext16u_i32(v2
, cpu_R
[RRR_T
]);
1703 tcg_gen_mul_i32(cpu_R
[RRR_R
], v1
, v2
);
1710 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL
);
1711 if (gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
)) {
1712 TCGv_i32 v1
= tcg_temp_new_i32();
1713 TCGv_i32 v2
= tcg_temp_new_i32();
1714 tcg_gen_ext16s_i32(v1
, cpu_R
[RRR_S
]);
1715 tcg_gen_ext16s_i32(v2
, cpu_R
[RRR_T
]);
1716 tcg_gen_mul_i32(cpu_R
[RRR_R
], v1
, v2
);
1722 default: /*reserved*/
1729 if (OP2
>= 8 && !gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
)) {
1734 HAS_OPTION(XTENSA_OPTION_32_BIT_IDIV
);
1735 TCGLabel
*label
= gen_new_label();
1736 tcg_gen_brcondi_i32(TCG_COND_NE
, cpu_R
[RRR_T
], 0, label
);
1737 gen_exception_cause(dc
, INTEGER_DIVIDE_BY_ZERO_CAUSE
);
1738 gen_set_label(label
);
1742 #define BOOLEAN_LOGIC(fn, r, s, t) \
1744 HAS_OPTION(XTENSA_OPTION_BOOLEAN); \
1745 TCGv_i32 tmp1 = tcg_temp_new_i32(); \
1746 TCGv_i32 tmp2 = tcg_temp_new_i32(); \
1748 tcg_gen_shri_i32(tmp1, cpu_SR[BR], s); \
1749 tcg_gen_shri_i32(tmp2, cpu_SR[BR], t); \
1750 tcg_gen_##fn##_i32(tmp1, tmp1, tmp2); \
1751 tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR], tmp1, r, 1); \
1752 tcg_temp_free(tmp1); \
1753 tcg_temp_free(tmp2); \
1757 BOOLEAN_LOGIC(and, RRR_R
, RRR_S
, RRR_T
);
1761 BOOLEAN_LOGIC(andc
, RRR_R
, RRR_S
, RRR_T
);
1765 BOOLEAN_LOGIC(or, RRR_R
, RRR_S
, RRR_T
);
1769 BOOLEAN_LOGIC(orc
, RRR_R
, RRR_S
, RRR_T
);
1773 BOOLEAN_LOGIC(xor, RRR_R
, RRR_S
, RRR_T
);
1776 #undef BOOLEAN_LOGIC
1779 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL
);
1780 tcg_gen_mul_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1785 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL_HIGH
);
1787 TCGv lo
= tcg_temp_new();
1790 tcg_gen_mulu2_i32(lo
, cpu_R
[RRR_R
],
1791 cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1793 tcg_gen_muls2_i32(lo
, cpu_R
[RRR_R
],
1794 cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1801 tcg_gen_divu_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1807 TCGLabel
*label1
= gen_new_label();
1808 TCGLabel
*label2
= gen_new_label();
1810 tcg_gen_brcondi_i32(TCG_COND_NE
, cpu_R
[RRR_S
], 0x80000000,
1812 tcg_gen_brcondi_i32(TCG_COND_NE
, cpu_R
[RRR_T
], 0xffffffff,
1814 tcg_gen_movi_i32(cpu_R
[RRR_R
],
1815 OP2
== 13 ? 0x80000000 : 0);
1817 gen_set_label(label1
);
1819 tcg_gen_div_i32(cpu_R
[RRR_R
],
1820 cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1822 tcg_gen_rem_i32(cpu_R
[RRR_R
],
1823 cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1825 gen_set_label(label2
);
1830 tcg_gen_remu_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1833 default: /*reserved*/
1842 if (gen_check_sr(dc
, RSR_SR
, SR_R
) &&
1843 (RSR_SR
< 64 || gen_check_privilege(dc
)) &&
1844 gen_window_check1(dc
, RRR_T
)) {
1845 if (gen_rsr(dc
, cpu_R
[RRR_T
], RSR_SR
)) {
1846 gen_jumpi_check_loop_end(dc
, 0);
1852 if (gen_check_sr(dc
, RSR_SR
, SR_W
) &&
1853 (RSR_SR
< 64 || gen_check_privilege(dc
)) &&
1854 gen_window_check1(dc
, RRR_T
)) {
1855 gen_wsr(dc
, RSR_SR
, cpu_R
[RRR_T
]);
1860 HAS_OPTION(XTENSA_OPTION_MISC_OP_SEXT
);
1861 if (gen_window_check2(dc
, RRR_R
, RRR_S
)) {
1862 int shift
= 24 - RRR_T
;
1865 tcg_gen_ext8s_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
1866 } else if (shift
== 16) {
1867 tcg_gen_ext16s_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
1869 TCGv_i32 tmp
= tcg_temp_new_i32();
1870 tcg_gen_shli_i32(tmp
, cpu_R
[RRR_S
], shift
);
1871 tcg_gen_sari_i32(cpu_R
[RRR_R
], tmp
, shift
);
1878 HAS_OPTION(XTENSA_OPTION_MISC_OP_CLAMPS
);
1879 if (gen_window_check2(dc
, RRR_R
, RRR_S
)) {
1880 TCGv_i32 tmp1
= tcg_temp_new_i32();
1881 TCGv_i32 tmp2
= tcg_temp_new_i32();
1882 TCGv_i32 zero
= tcg_const_i32(0);
1884 tcg_gen_sari_i32(tmp1
, cpu_R
[RRR_S
], 24 - RRR_T
);
1885 tcg_gen_xor_i32(tmp2
, tmp1
, cpu_R
[RRR_S
]);
1886 tcg_gen_andi_i32(tmp2
, tmp2
, 0xffffffff << (RRR_T
+ 7));
1888 tcg_gen_sari_i32(tmp1
, cpu_R
[RRR_S
], 31);
1889 tcg_gen_xori_i32(tmp1
, tmp1
, 0xffffffff >> (25 - RRR_T
));
1891 tcg_gen_movcond_i32(TCG_COND_EQ
, cpu_R
[RRR_R
], tmp2
, zero
,
1892 cpu_R
[RRR_S
], tmp1
);
1893 tcg_temp_free(tmp1
);
1894 tcg_temp_free(tmp2
);
1895 tcg_temp_free(zero
);
1903 HAS_OPTION(XTENSA_OPTION_MISC_OP_MINMAX
);
1904 if (gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
)) {
1905 static const TCGCond cond
[] = {
1911 tcg_gen_movcond_i32(cond
[OP2
- 4], cpu_R
[RRR_R
],
1912 cpu_R
[RRR_S
], cpu_R
[RRR_T
],
1913 cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1921 if (gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
)) {
1922 static const TCGCond cond
[] = {
1928 TCGv_i32 zero
= tcg_const_i32(0);
1930 tcg_gen_movcond_i32(cond
[OP2
- 8], cpu_R
[RRR_R
],
1931 cpu_R
[RRR_T
], zero
, cpu_R
[RRR_S
], cpu_R
[RRR_R
]);
1932 tcg_temp_free(zero
);
1938 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
1939 if (gen_window_check2(dc
, RRR_R
, RRR_S
)) {
1940 TCGv_i32 zero
= tcg_const_i32(0);
1941 TCGv_i32 tmp
= tcg_temp_new_i32();
1943 tcg_gen_andi_i32(tmp
, cpu_SR
[BR
], 1 << RRR_T
);
1944 tcg_gen_movcond_i32(OP2
& 1 ? TCG_COND_NE
: TCG_COND_EQ
,
1945 cpu_R
[RRR_R
], tmp
, zero
,
1946 cpu_R
[RRR_S
], cpu_R
[RRR_R
]);
1949 tcg_temp_free(zero
);
1954 if (gen_window_check1(dc
, RRR_R
)) {
1955 int st
= (RRR_S
<< 4) + RRR_T
;
1956 if (uregnames
[st
].name
) {
1957 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_UR
[st
]);
1959 qemu_log_mask(LOG_UNIMP
, "RUR %d not implemented, ", st
);
1966 if (gen_window_check1(dc
, RRR_T
)) {
1967 if (uregnames
[RSR_SR
].name
) {
1968 gen_wur(RSR_SR
, cpu_R
[RRR_T
]);
1970 qemu_log_mask(LOG_UNIMP
, "WUR %d not implemented, ", RSR_SR
);
1981 if (gen_window_check2(dc
, RRR_R
, RRR_T
)) {
1982 int shiftimm
= RRR_S
| ((OP1
& 1) << 4);
1983 int maskimm
= (1 << (OP2
+ 1)) - 1;
1985 TCGv_i32 tmp
= tcg_temp_new_i32();
1986 tcg_gen_shri_i32(tmp
, cpu_R
[RRR_T
], shiftimm
);
1987 tcg_gen_andi_i32(cpu_R
[RRR_R
], tmp
, maskimm
);
2006 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR
);
2007 if (gen_window_check2(dc
, RRR_S
, RRR_T
) &&
2008 gen_check_cpenable(dc
, 0)) {
2009 TCGv_i32 addr
= tcg_temp_new_i32();
2010 tcg_gen_add_i32(addr
, cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
2011 gen_load_store_alignment(dc
, 2, addr
, false);
2013 tcg_gen_qemu_st32(cpu_FR
[RRR_R
], addr
, dc
->cring
);
2015 tcg_gen_qemu_ld32u(cpu_FR
[RRR_R
], addr
, dc
->cring
);
2018 tcg_gen_mov_i32(cpu_R
[RRR_S
], addr
);
2020 tcg_temp_free(addr
);
2024 default: /*reserved*/
2031 if (!gen_window_check2(dc
, RRR_S
, RRR_T
)) {
2036 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
2037 if (gen_check_privilege(dc
) &&
2038 gen_window_check2(dc
, RRR_S
, RRR_T
)) {
2039 TCGv_i32 addr
= tcg_temp_new_i32();
2040 tcg_gen_addi_i32(addr
, cpu_R
[RRR_S
],
2041 (0xffffffc0 | (RRR_R
<< 2)));
2042 tcg_gen_qemu_ld32u(cpu_R
[RRR_T
], addr
, dc
->ring
);
2043 tcg_temp_free(addr
);
2048 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
2049 if (gen_check_privilege(dc
) &&
2050 gen_window_check2(dc
, RRR_S
, RRR_T
)) {
2051 TCGv_i32 addr
= tcg_temp_new_i32();
2052 tcg_gen_addi_i32(addr
, cpu_R
[RRR_S
],
2053 (0xffffffc0 | (RRR_R
<< 2)));
2054 tcg_gen_qemu_st32(cpu_R
[RRR_T
], addr
, dc
->ring
);
2055 tcg_temp_free(addr
);
2060 if (gen_window_check2(dc
, RRI4_S
, RRI4_T
)) {
2061 TCGv_i32 addr
= tcg_temp_new_i32();
2063 tcg_gen_addi_i32(addr
, cpu_R
[RRI4_S
], RRI4_IMM4
<< 2);
2064 gen_load_store_alignment(dc
, 2, addr
, false);
2065 tcg_gen_qemu_st32(cpu_R
[RRI4_T
], addr
, dc
->cring
);
2066 tcg_temp_free(addr
);
2078 if (option_enabled(dc
, XTENSA_OPTION_DEPBITS
)) {
2079 if (!gen_window_check2(dc
, RRR_S
, RRR_T
)) {
2082 tcg_gen_deposit_i32(cpu_R
[RRR_T
], cpu_R
[RRR_T
], cpu_R
[RRR_S
],
2087 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR
);
2090 if (gen_check_cpenable(dc
, 0)) {
2091 gen_helper_add_s(cpu_FR
[RRR_R
], cpu_env
,
2092 cpu_FR
[RRR_S
], cpu_FR
[RRR_T
]);
2097 if (gen_check_cpenable(dc
, 0)) {
2098 gen_helper_sub_s(cpu_FR
[RRR_R
], cpu_env
,
2099 cpu_FR
[RRR_S
], cpu_FR
[RRR_T
]);
2104 if (gen_check_cpenable(dc
, 0)) {
2105 gen_helper_mul_s(cpu_FR
[RRR_R
], cpu_env
,
2106 cpu_FR
[RRR_S
], cpu_FR
[RRR_T
]);
2111 if (gen_check_cpenable(dc
, 0)) {
2112 gen_helper_madd_s(cpu_FR
[RRR_R
], cpu_env
,
2113 cpu_FR
[RRR_R
], cpu_FR
[RRR_S
],
2119 if (gen_check_cpenable(dc
, 0)) {
2120 gen_helper_msub_s(cpu_FR
[RRR_R
], cpu_env
,
2121 cpu_FR
[RRR_R
], cpu_FR
[RRR_S
],
2126 case 8: /*ROUND.Sf*/
2127 case 9: /*TRUNC.Sf*/
2128 case 10: /*FLOOR.Sf*/
2129 case 11: /*CEIL.Sf*/
2130 case 14: /*UTRUNC.Sf*/
2131 if (gen_window_check1(dc
, RRR_R
) &&
2132 gen_check_cpenable(dc
, 0)) {
2133 static const unsigned rounding_mode_const
[] = {
2134 float_round_nearest_even
,
2135 float_round_to_zero
,
2138 [6] = float_round_to_zero
,
2140 TCGv_i32 rounding_mode
= tcg_const_i32(
2141 rounding_mode_const
[OP2
& 7]);
2142 TCGv_i32 scale
= tcg_const_i32(RRR_T
);
2145 gen_helper_ftoui(cpu_R
[RRR_R
], cpu_FR
[RRR_S
],
2146 rounding_mode
, scale
);
2148 gen_helper_ftoi(cpu_R
[RRR_R
], cpu_FR
[RRR_S
],
2149 rounding_mode
, scale
);
2152 tcg_temp_free(rounding_mode
);
2153 tcg_temp_free(scale
);
2157 case 12: /*FLOAT.Sf*/
2158 case 13: /*UFLOAT.Sf*/
2159 if (gen_window_check1(dc
, RRR_S
) &&
2160 gen_check_cpenable(dc
, 0)) {
2161 TCGv_i32 scale
= tcg_const_i32(-RRR_T
);
2164 gen_helper_uitof(cpu_FR
[RRR_R
], cpu_env
,
2165 cpu_R
[RRR_S
], scale
);
2167 gen_helper_itof(cpu_FR
[RRR_R
], cpu_env
,
2168 cpu_R
[RRR_S
], scale
);
2170 tcg_temp_free(scale
);
2177 if (gen_check_cpenable(dc
, 0)) {
2178 tcg_gen_mov_i32(cpu_FR
[RRR_R
], cpu_FR
[RRR_S
]);
2183 if (gen_check_cpenable(dc
, 0)) {
2184 gen_helper_abs_s(cpu_FR
[RRR_R
], cpu_FR
[RRR_S
]);
2189 if (gen_window_check1(dc
, RRR_R
) &&
2190 gen_check_cpenable(dc
, 0)) {
2191 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_FR
[RRR_S
]);
2196 if (gen_window_check1(dc
, RRR_S
) &&
2197 gen_check_cpenable(dc
, 0)) {
2198 tcg_gen_mov_i32(cpu_FR
[RRR_R
], cpu_R
[RRR_S
]);
2203 if (gen_check_cpenable(dc
, 0)) {
2204 gen_helper_neg_s(cpu_FR
[RRR_R
], cpu_FR
[RRR_S
]);
2208 default: /*reserved*/
2214 default: /*reserved*/
2222 if (option_enabled(dc
, XTENSA_OPTION_DEPBITS
)) {
2223 if (!gen_window_check2(dc
, RRR_S
, RRR_T
)) {
2226 tcg_gen_deposit_i32(cpu_R
[RRR_T
], cpu_R
[RRR_T
], cpu_R
[RRR_S
],
2227 OP2
+ 16, RRR_R
+ 1);
2231 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR
);
2233 #define gen_compare(rel, br, a, b) \
2235 if (gen_check_cpenable(dc, 0)) { \
2236 TCGv_i32 bit = tcg_const_i32(1 << br); \
2238 gen_helper_##rel(cpu_env, bit, cpu_FR[a], cpu_FR[b]); \
2239 tcg_temp_free(bit); \
2245 gen_compare(un_s
, RRR_R
, RRR_S
, RRR_T
);
2249 gen_compare(oeq_s
, RRR_R
, RRR_S
, RRR_T
);
2253 gen_compare(ueq_s
, RRR_R
, RRR_S
, RRR_T
);
2257 gen_compare(olt_s
, RRR_R
, RRR_S
, RRR_T
);
2261 gen_compare(ult_s
, RRR_R
, RRR_S
, RRR_T
);
2265 gen_compare(ole_s
, RRR_R
, RRR_S
, RRR_T
);
2269 gen_compare(ule_s
, RRR_R
, RRR_S
, RRR_T
);
2274 case 8: /*MOVEQZ.Sf*/
2275 case 9: /*MOVNEZ.Sf*/
2276 case 10: /*MOVLTZ.Sf*/
2277 case 11: /*MOVGEZ.Sf*/
2278 if (gen_window_check1(dc
, RRR_T
) &&
2279 gen_check_cpenable(dc
, 0)) {
2280 static const TCGCond cond
[] = {
2286 TCGv_i32 zero
= tcg_const_i32(0);
2288 tcg_gen_movcond_i32(cond
[OP2
- 8], cpu_FR
[RRR_R
],
2289 cpu_R
[RRR_T
], zero
, cpu_FR
[RRR_S
], cpu_FR
[RRR_R
]);
2290 tcg_temp_free(zero
);
2294 case 12: /*MOVF.Sf*/
2295 case 13: /*MOVT.Sf*/
2296 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
2297 if (gen_check_cpenable(dc
, 0)) {
2298 TCGv_i32 zero
= tcg_const_i32(0);
2299 TCGv_i32 tmp
= tcg_temp_new_i32();
2301 tcg_gen_andi_i32(tmp
, cpu_SR
[BR
], 1 << RRR_T
);
2302 tcg_gen_movcond_i32(OP2
& 1 ? TCG_COND_NE
: TCG_COND_EQ
,
2303 cpu_FR
[RRR_R
], tmp
, zero
,
2304 cpu_FR
[RRR_S
], cpu_FR
[RRR_R
]);
2307 tcg_temp_free(zero
);
2311 default: /*reserved*/
2317 default: /*reserved*/
2324 if (gen_window_check1(dc
, RRR_T
)) {
2325 TCGv_i32 tmp
= tcg_const_i32(
2326 ((dc
->tb
->flags
& XTENSA_TBFLAG_LITBASE
) ?
2327 0 : ((dc
->pc
+ 3) & ~3)) +
2328 (0xfffc0000 | (RI16_IMM16
<< 2)));
2330 if (dc
->tb
->flags
& XTENSA_TBFLAG_LITBASE
) {
2331 tcg_gen_add_i32(tmp
, tmp
, dc
->litbase
);
2333 tcg_gen_qemu_ld32u(cpu_R
[RRR_T
], tmp
, dc
->cring
);
2339 #define gen_load_store(type, shift) do { \
2340 if (gen_window_check2(dc, RRI8_S, RRI8_T)) { \
2341 TCGv_i32 addr = tcg_temp_new_i32(); \
2343 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << shift); \
2345 gen_load_store_alignment(dc, shift, addr, false); \
2347 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
2348 tcg_temp_free(addr); \
2354 gen_load_store(ld8u
, 0);
2358 gen_load_store(ld16u
, 1);
2362 gen_load_store(ld32u
, 2);
2366 gen_load_store(st8
, 0);
2370 gen_load_store(st16
, 1);
2374 gen_load_store(st32
, 2);
2377 #define gen_dcache_hit_test(w, shift) do { \
2378 if (gen_window_check1(dc, RRI##w##_S)) { \
2379 TCGv_i32 addr = tcg_temp_new_i32(); \
2380 TCGv_i32 res = tcg_temp_new_i32(); \
2381 tcg_gen_addi_i32(addr, cpu_R[RRI##w##_S], \
2382 RRI##w##_IMM##w << shift); \
2383 tcg_gen_qemu_ld8u(res, addr, dc->cring); \
2384 tcg_temp_free(addr); \
2385 tcg_temp_free(res); \
2389 #define gen_dcache_hit_test4() gen_dcache_hit_test(4, 4)
2390 #define gen_dcache_hit_test8() gen_dcache_hit_test(8, 2)
2394 HAS_OPTION(XTENSA_OPTION_DCACHE
);
2399 gen_window_check1(dc
, RRI8_S
);
2403 gen_window_check1(dc
, RRI8_S
);
2407 gen_window_check1(dc
, RRI8_S
);
2411 gen_window_check1(dc
, RRI8_S
);
2415 gen_dcache_hit_test8();
2419 gen_dcache_hit_test8();
2423 if (gen_check_privilege(dc
)) {
2424 gen_dcache_hit_test8();
2429 if (gen_check_privilege(dc
)) {
2430 gen_window_check1(dc
, RRI8_S
);
2437 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK
);
2438 if (gen_check_privilege(dc
)) {
2439 gen_dcache_hit_test4();
2444 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK
);
2445 if (gen_check_privilege(dc
)) {
2446 gen_dcache_hit_test4();
2451 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK
);
2452 if (gen_check_privilege(dc
)) {
2453 gen_window_check1(dc
, RRI4_S
);
2458 HAS_OPTION(XTENSA_OPTION_DCACHE
);
2459 if (gen_check_privilege(dc
)) {
2460 gen_window_check1(dc
, RRI4_S
);
2465 HAS_OPTION(XTENSA_OPTION_DCACHE
);
2466 if (gen_check_privilege(dc
)) {
2467 gen_window_check1(dc
, RRI4_S
);
2471 default: /*reserved*/
2478 #undef gen_dcache_hit_test
2479 #undef gen_dcache_hit_test4
2480 #undef gen_dcache_hit_test8
2482 #define gen_icache_hit_test(w, shift) do { \
2483 if (gen_window_check1(dc, RRI##w##_S)) { \
2484 TCGv_i32 addr = tcg_temp_new_i32(); \
2485 tcg_gen_movi_i32(cpu_pc, dc->pc); \
2486 tcg_gen_addi_i32(addr, cpu_R[RRI##w##_S], \
2487 RRI##w##_IMM##w << shift); \
2488 gen_helper_itlb_hit_test(cpu_env, addr); \
2489 tcg_temp_free(addr); \
2493 #define gen_icache_hit_test4() gen_icache_hit_test(4, 4)
2494 #define gen_icache_hit_test8() gen_icache_hit_test(8, 2)
2497 HAS_OPTION(XTENSA_OPTION_ICACHE
);
2498 gen_window_check1(dc
, RRI8_S
);
2504 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK
);
2505 if (gen_check_privilege(dc
)) {
2506 gen_icache_hit_test4();
2511 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK
);
2512 if (gen_check_privilege(dc
)) {
2513 gen_icache_hit_test4();
2518 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK
);
2519 if (gen_check_privilege(dc
)) {
2520 gen_window_check1(dc
, RRI4_S
);
2524 default: /*reserved*/
2531 HAS_OPTION(XTENSA_OPTION_ICACHE
);
2532 gen_icache_hit_test8();
2536 HAS_OPTION(XTENSA_OPTION_ICACHE
);
2537 if (gen_check_privilege(dc
)) {
2538 gen_window_check1(dc
, RRI8_S
);
2542 default: /*reserved*/
2548 #undef gen_icache_hit_test
2549 #undef gen_icache_hit_test4
2550 #undef gen_icache_hit_test8
2553 gen_load_store(ld16s
, 1);
2555 #undef gen_load_store
2558 if (gen_window_check1(dc
, RRI8_T
)) {
2559 tcg_gen_movi_i32(cpu_R
[RRI8_T
],
2560 RRI8_IMM8
| (RRI8_S
<< 8) |
2561 ((RRI8_S
& 0x8) ? 0xfffff000 : 0));
2565 #define gen_load_store_no_hw_align(type) do { \
2566 if (gen_window_check2(dc, RRI8_S, RRI8_T)) { \
2567 TCGv_i32 addr = tcg_temp_local_new_i32(); \
2568 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2); \
2569 gen_load_store_alignment(dc, 2, addr, true); \
2570 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
2571 tcg_temp_free(addr); \
2576 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO
);
2577 gen_load_store_no_hw_align(ld32u
); /*TODO acquire?*/
2581 if (gen_window_check2(dc
, RRI8_S
, RRI8_T
)) {
2582 tcg_gen_addi_i32(cpu_R
[RRI8_T
], cpu_R
[RRI8_S
], RRI8_IMM8_SE
);
2587 if (gen_window_check2(dc
, RRI8_S
, RRI8_T
)) {
2588 tcg_gen_addi_i32(cpu_R
[RRI8_T
], cpu_R
[RRI8_S
],
2593 case 14: /*S32C1Iy*/
2594 HAS_OPTION(XTENSA_OPTION_CONDITIONAL_STORE
);
2595 if (gen_window_check2(dc
, RRI8_S
, RRI8_T
)) {
2596 TCGLabel
*label
= gen_new_label();
2597 TCGv_i32 tmp
= tcg_temp_local_new_i32();
2598 TCGv_i32 addr
= tcg_temp_local_new_i32();
2601 tcg_gen_mov_i32(tmp
, cpu_R
[RRI8_T
]);
2602 tcg_gen_addi_i32(addr
, cpu_R
[RRI8_S
], RRI8_IMM8
<< 2);
2603 gen_load_store_alignment(dc
, 2, addr
, true);
2605 tpc
= tcg_const_i32(dc
->pc
);
2606 gen_helper_check_atomctl(cpu_env
, tpc
, addr
);
2607 tcg_gen_qemu_ld32u(cpu_R
[RRI8_T
], addr
, dc
->cring
);
2608 tcg_gen_brcond_i32(TCG_COND_NE
, cpu_R
[RRI8_T
],
2609 cpu_SR
[SCOMPARE1
], label
);
2611 tcg_gen_qemu_st32(tmp
, addr
, dc
->cring
);
2613 gen_set_label(label
);
2615 tcg_temp_free(addr
);
2621 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO
);
2622 gen_load_store_no_hw_align(st32
); /*TODO release?*/
2624 #undef gen_load_store_no_hw_align
2626 default: /*reserved*/
2638 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR
);
2639 if (gen_window_check1(dc
, RRI8_S
) &&
2640 gen_check_cpenable(dc
, 0)) {
2641 TCGv_i32 addr
= tcg_temp_new_i32();
2642 tcg_gen_addi_i32(addr
, cpu_R
[RRI8_S
], RRI8_IMM8
<< 2);
2643 gen_load_store_alignment(dc
, 2, addr
, false);
2645 tcg_gen_qemu_st32(cpu_FR
[RRI8_T
], addr
, dc
->cring
);
2647 tcg_gen_qemu_ld32u(cpu_FR
[RRI8_T
], addr
, dc
->cring
);
2650 tcg_gen_mov_i32(cpu_R
[RRI8_S
], addr
);
2652 tcg_temp_free(addr
);
2656 default: /*reserved*/
2663 HAS_OPTION(XTENSA_OPTION_MAC16
);
2672 bool is_m1_sr
= (OP2
& 0x3) == 2;
2673 bool is_m2_sr
= (OP2
& 0xc) == 0;
2674 uint32_t ld_offset
= 0;
2681 case 0: /*MACI?/MACC?*/
2683 ld_offset
= (OP2
& 1) ? -4 : 4;
2685 if (OP2
>= 8) { /*MACI/MACC*/
2686 if (OP1
== 0) { /*LDINC/LDDEC*/
2691 } else if (op
!= MAC16_MULA
) { /*MULA.*.*.LDINC/LDDEC*/
2696 case 2: /*MACD?/MACA?*/
2697 if (op
== MAC16_UMUL
&& OP2
!= 7) { /*UMUL only in MACAA*/
2703 if (op
!= MAC16_NONE
) {
2704 if (!is_m1_sr
&& !gen_window_check1(dc
, RRR_S
)) {
2707 if (!is_m2_sr
&& !gen_window_check1(dc
, RRR_T
)) {
2712 if (ld_offset
&& !gen_window_check1(dc
, RRR_S
)) {
2717 TCGv_i32 vaddr
= tcg_temp_new_i32();
2718 TCGv_i32 mem32
= tcg_temp_new_i32();
2721 tcg_gen_addi_i32(vaddr
, cpu_R
[RRR_S
], ld_offset
);
2722 gen_load_store_alignment(dc
, 2, vaddr
, false);
2723 tcg_gen_qemu_ld32u(mem32
, vaddr
, dc
->cring
);
2725 if (op
!= MAC16_NONE
) {
2726 TCGv_i32 m1
= gen_mac16_m(
2727 is_m1_sr
? cpu_SR
[MR
+ RRR_X
] : cpu_R
[RRR_S
],
2728 OP1
& 1, op
== MAC16_UMUL
);
2729 TCGv_i32 m2
= gen_mac16_m(
2730 is_m2_sr
? cpu_SR
[MR
+ 2 + RRR_Y
] : cpu_R
[RRR_T
],
2731 OP1
& 2, op
== MAC16_UMUL
);
2733 if (op
== MAC16_MUL
|| op
== MAC16_UMUL
) {
2734 tcg_gen_mul_i32(cpu_SR
[ACCLO
], m1
, m2
);
2735 if (op
== MAC16_UMUL
) {
2736 tcg_gen_movi_i32(cpu_SR
[ACCHI
], 0);
2738 tcg_gen_sari_i32(cpu_SR
[ACCHI
], cpu_SR
[ACCLO
], 31);
2741 TCGv_i32 lo
= tcg_temp_new_i32();
2742 TCGv_i32 hi
= tcg_temp_new_i32();
2744 tcg_gen_mul_i32(lo
, m1
, m2
);
2745 tcg_gen_sari_i32(hi
, lo
, 31);
2746 if (op
== MAC16_MULA
) {
2747 tcg_gen_add2_i32(cpu_SR
[ACCLO
], cpu_SR
[ACCHI
],
2748 cpu_SR
[ACCLO
], cpu_SR
[ACCHI
],
2751 tcg_gen_sub2_i32(cpu_SR
[ACCLO
], cpu_SR
[ACCHI
],
2752 cpu_SR
[ACCLO
], cpu_SR
[ACCHI
],
2755 tcg_gen_ext8s_i32(cpu_SR
[ACCHI
], cpu_SR
[ACCHI
]);
2757 tcg_temp_free_i32(lo
);
2758 tcg_temp_free_i32(hi
);
2764 tcg_gen_mov_i32(cpu_R
[RRR_S
], vaddr
);
2765 tcg_gen_mov_i32(cpu_SR
[MR
+ RRR_W
], mem32
);
2767 tcg_temp_free(vaddr
);
2768 tcg_temp_free(mem32
);
2776 tcg_gen_movi_i32(cpu_R
[0], dc
->next_pc
);
2777 gen_jumpi(dc
, (dc
->pc
& ~3) + (CALL_OFFSET_SE
<< 2) + 4, 0);
2783 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
2784 if (gen_window_check1(dc
, CALL_N
<< 2)) {
2785 gen_callwi(dc
, CALL_N
,
2786 (dc
->pc
& ~3) + (CALL_OFFSET_SE
<< 2) + 4, 0);
2795 gen_jumpi(dc
, dc
->pc
+ 4 + CALL_OFFSET_SE
, 0);
2799 if (gen_window_check1(dc
, BRI12_S
)) {
2800 static const TCGCond cond
[] = {
2801 TCG_COND_EQ
, /*BEQZ*/
2802 TCG_COND_NE
, /*BNEZ*/
2803 TCG_COND_LT
, /*BLTZ*/
2804 TCG_COND_GE
, /*BGEZ*/
2807 gen_brcondi(dc
, cond
[BRI12_M
& 3], cpu_R
[BRI12_S
], 0,
2808 4 + BRI12_IMM12_SE
);
2813 if (gen_window_check1(dc
, BRI8_S
)) {
2814 static const TCGCond cond
[] = {
2815 TCG_COND_EQ
, /*BEQI*/
2816 TCG_COND_NE
, /*BNEI*/
2817 TCG_COND_LT
, /*BLTI*/
2818 TCG_COND_GE
, /*BGEI*/
2821 gen_brcondi(dc
, cond
[BRI8_M
& 3],
2822 cpu_R
[BRI8_S
], B4CONST
[BRI8_R
], 4 + BRI8_IMM8_SE
);
2829 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
2831 TCGv_i32 pc
= tcg_const_i32(dc
->pc
);
2832 TCGv_i32 s
= tcg_const_i32(BRI12_S
);
2833 TCGv_i32 imm
= tcg_const_i32(BRI12_IMM12
);
2834 gen_helper_entry(cpu_env
, pc
, s
, imm
);
2838 /* This can change tb->flags, so exit tb */
2839 gen_jumpi_check_loop_end(dc
, -1);
2847 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
2849 TCGv_i32 tmp
= tcg_temp_new_i32();
2850 tcg_gen_andi_i32(tmp
, cpu_SR
[BR
], 1 << RRI8_S
);
2852 BRI8_R
== 1 ? TCG_COND_NE
: TCG_COND_EQ
,
2853 tmp
, 0, 4 + RRI8_IMM8_SE
);
2860 case 10: /*LOOPGTZ*/
2861 HAS_OPTION(XTENSA_OPTION_LOOP
);
2862 if (gen_window_check1(dc
, RRI8_S
)) {
2863 uint32_t lend
= dc
->pc
+ RRI8_IMM8
+ 4;
2864 TCGv_i32 tmp
= tcg_const_i32(lend
);
2866 tcg_gen_subi_i32(cpu_SR
[LCOUNT
], cpu_R
[RRI8_S
], 1);
2867 tcg_gen_movi_i32(cpu_SR
[LBEG
], dc
->next_pc
);
2868 gen_helper_wsr_lend(cpu_env
, tmp
);
2872 TCGLabel
*label
= gen_new_label();
2873 tcg_gen_brcondi_i32(
2874 BRI8_R
== 9 ? TCG_COND_NE
: TCG_COND_GT
,
2875 cpu_R
[RRI8_S
], 0, label
);
2876 gen_jumpi(dc
, lend
, 1);
2877 gen_set_label(label
);
2880 gen_jumpi(dc
, dc
->next_pc
, 0);
2884 default: /*reserved*/
2893 if (gen_window_check1(dc
, BRI8_S
)) {
2894 gen_brcondi(dc
, BRI8_M
== 2 ? TCG_COND_LTU
: TCG_COND_GEU
,
2895 cpu_R
[BRI8_S
], B4CONSTU
[BRI8_R
],
2907 TCGCond eq_ne
= (RRI8_R
& 8) ? TCG_COND_NE
: TCG_COND_EQ
;
2909 switch (RRI8_R
& 7) {
2910 case 0: /*BNONE*/ /*BANY*/
2911 if (gen_window_check2(dc
, RRI8_S
, RRI8_T
)) {
2912 TCGv_i32 tmp
= tcg_temp_new_i32();
2913 tcg_gen_and_i32(tmp
, cpu_R
[RRI8_S
], cpu_R
[RRI8_T
]);
2914 gen_brcondi(dc
, eq_ne
, tmp
, 0, 4 + RRI8_IMM8_SE
);
2919 case 1: /*BEQ*/ /*BNE*/
2920 case 2: /*BLT*/ /*BGE*/
2921 case 3: /*BLTU*/ /*BGEU*/
2922 if (gen_window_check2(dc
, RRI8_S
, RRI8_T
)) {
2923 static const TCGCond cond
[] = {
2929 [11] = TCG_COND_GEU
,
2931 gen_brcond(dc
, cond
[RRI8_R
], cpu_R
[RRI8_S
], cpu_R
[RRI8_T
],
2936 case 4: /*BALL*/ /*BNALL*/
2937 if (gen_window_check2(dc
, RRI8_S
, RRI8_T
)) {
2938 TCGv_i32 tmp
= tcg_temp_new_i32();
2939 tcg_gen_and_i32(tmp
, cpu_R
[RRI8_S
], cpu_R
[RRI8_T
]);
2940 gen_brcond(dc
, eq_ne
, tmp
, cpu_R
[RRI8_T
],
2946 case 5: /*BBC*/ /*BBS*/
2947 if (gen_window_check2(dc
, RRI8_S
, RRI8_T
)) {
2948 #ifdef TARGET_WORDS_BIGENDIAN
2949 TCGv_i32 bit
= tcg_const_i32(0x80000000);
2951 TCGv_i32 bit
= tcg_const_i32(0x00000001);
2953 TCGv_i32 tmp
= tcg_temp_new_i32();
2954 tcg_gen_andi_i32(tmp
, cpu_R
[RRI8_T
], 0x1f);
2955 #ifdef TARGET_WORDS_BIGENDIAN
2956 tcg_gen_shr_i32(bit
, bit
, tmp
);
2958 tcg_gen_shl_i32(bit
, bit
, tmp
);
2960 tcg_gen_and_i32(tmp
, cpu_R
[RRI8_S
], bit
);
2961 gen_brcondi(dc
, eq_ne
, tmp
, 0, 4 + RRI8_IMM8_SE
);
2967 case 6: /*BBCI*/ /*BBSI*/
2969 if (gen_window_check1(dc
, RRI8_S
)) {
2970 TCGv_i32 tmp
= tcg_temp_new_i32();
2971 tcg_gen_andi_i32(tmp
, cpu_R
[RRI8_S
],
2972 #ifdef TARGET_WORDS_BIGENDIAN
2973 0x80000000 >> (((RRI8_R
& 1) << 4) | RRI8_T
));
2975 0x00000001 << (((RRI8_R
& 1) << 4) | RRI8_T
));
2977 gen_brcondi(dc
, eq_ne
, tmp
, 0, 4 + RRI8_IMM8_SE
);
2986 #define gen_narrow_load_store(type) do { \
2987 if (gen_window_check2(dc, RRRN_S, RRRN_T)) { \
2988 TCGv_i32 addr = tcg_temp_new_i32(); \
2989 tcg_gen_addi_i32(addr, cpu_R[RRRN_S], RRRN_R << 2); \
2990 gen_load_store_alignment(dc, 2, addr, false); \
2991 tcg_gen_qemu_##type(cpu_R[RRRN_T], addr, dc->cring); \
2992 tcg_temp_free(addr); \
2997 gen_narrow_load_store(ld32u
);
3001 gen_narrow_load_store(st32
);
3003 #undef gen_narrow_load_store
3006 if (gen_window_check3(dc
, RRRN_R
, RRRN_S
, RRRN_T
)) {
3007 tcg_gen_add_i32(cpu_R
[RRRN_R
], cpu_R
[RRRN_S
], cpu_R
[RRRN_T
]);
3011 case 11: /*ADDI.Nn*/
3012 if (gen_window_check2(dc
, RRRN_R
, RRRN_S
)) {
3013 tcg_gen_addi_i32(cpu_R
[RRRN_R
], cpu_R
[RRRN_S
],
3014 RRRN_T
? RRRN_T
: -1);
3019 if (!gen_window_check1(dc
, RRRN_S
)) {
3022 if (RRRN_T
< 8) { /*MOVI.Nn*/
3023 tcg_gen_movi_i32(cpu_R
[RRRN_S
],
3024 RRRN_R
| (RRRN_T
<< 4) |
3025 ((RRRN_T
& 6) == 6 ? 0xffffff80 : 0));
3026 } else { /*BEQZ.Nn*/ /*BNEZ.Nn*/
3027 TCGCond eq_ne
= (RRRN_T
& 4) ? TCG_COND_NE
: TCG_COND_EQ
;
3029 gen_brcondi(dc
, eq_ne
, cpu_R
[RRRN_S
], 0,
3030 4 + (RRRN_R
| ((RRRN_T
& 3) << 4)));
3037 if (gen_window_check2(dc
, RRRN_S
, RRRN_T
)) {
3038 tcg_gen_mov_i32(cpu_R
[RRRN_T
], cpu_R
[RRRN_S
]);
3045 gen_jump(dc
, cpu_R
[0]);
3049 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
3051 TCGv_i32 tmp
= tcg_const_i32(dc
->pc
);
3052 gen_helper_retw(tmp
, cpu_env
, tmp
);
3058 case 2: /*BREAK.Nn*/
3059 HAS_OPTION(XTENSA_OPTION_DEBUG
);
3061 gen_debug_exception(dc
, DEBUGCAUSE_BN
);
3069 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
3072 default: /*reserved*/
3078 default: /*reserved*/
3084 default: /*reserved*/
3089 if (dc
->is_jmp
== DISAS_NEXT
) {
3090 gen_check_loop_end(dc
, 0);
3092 dc
->pc
= dc
->next_pc
;
3097 qemu_log_mask(LOG_GUEST_ERROR
, "INVALID(pc = %08x)\n", dc
->pc
);
3098 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
3102 static inline unsigned xtensa_insn_len(CPUXtensaState
*env
, DisasContext
*dc
)
3104 uint8_t b0
= cpu_ldub_code(env
, dc
->pc
);
3105 return xtensa_op0_insn_len(OP0
);
3108 static void gen_ibreak_check(CPUXtensaState
*env
, DisasContext
*dc
)
3112 for (i
= 0; i
< dc
->config
->nibreak
; ++i
) {
3113 if ((env
->sregs
[IBREAKENABLE
] & (1 << i
)) &&
3114 env
->sregs
[IBREAKA
+ i
] == dc
->pc
) {
3115 gen_debug_exception(dc
, DEBUGCAUSE_IB
);
3121 void gen_intermediate_code(CPUState
*cs
, TranslationBlock
*tb
)
3123 CPUXtensaState
*env
= cs
->env_ptr
;
3126 int max_insns
= tb_cflags(tb
) & CF_COUNT_MASK
;
3127 uint32_t pc_start
= tb
->pc
;
3128 uint32_t next_page_start
=
3129 (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
3131 if (max_insns
== 0) {
3132 max_insns
= CF_COUNT_MASK
;
3134 if (max_insns
> TCG_MAX_INSNS
) {
3135 max_insns
= TCG_MAX_INSNS
;
3138 dc
.config
= env
->config
;
3139 dc
.singlestep_enabled
= cs
->singlestep_enabled
;
3142 dc
.ring
= tb
->flags
& XTENSA_TBFLAG_RING_MASK
;
3143 dc
.cring
= (tb
->flags
& XTENSA_TBFLAG_EXCM
) ? 0 : dc
.ring
;
3144 dc
.lbeg
= env
->sregs
[LBEG
];
3145 dc
.lend
= env
->sregs
[LEND
];
3146 dc
.is_jmp
= DISAS_NEXT
;
3147 dc
.debug
= tb
->flags
& XTENSA_TBFLAG_DEBUG
;
3148 dc
.icount
= tb
->flags
& XTENSA_TBFLAG_ICOUNT
;
3149 dc
.cpenable
= (tb
->flags
& XTENSA_TBFLAG_CPENABLE_MASK
) >>
3150 XTENSA_TBFLAG_CPENABLE_SHIFT
;
3151 dc
.window
= ((tb
->flags
& XTENSA_TBFLAG_WINDOW_MASK
) >>
3152 XTENSA_TBFLAG_WINDOW_SHIFT
);
3155 init_sar_tracker(&dc
);
3157 dc
.next_icount
= tcg_temp_local_new_i32();
3162 if ((tb_cflags(tb
) & CF_USE_ICOUNT
) &&
3163 (tb
->flags
& XTENSA_TBFLAG_YIELD
)) {
3164 tcg_gen_insn_start(dc
.pc
);
3166 gen_exception(&dc
, EXCP_YIELD
);
3167 dc
.is_jmp
= DISAS_UPDATE
;
3170 if (tb
->flags
& XTENSA_TBFLAG_EXCEPTION
) {
3171 tcg_gen_insn_start(dc
.pc
);
3173 gen_exception(&dc
, EXCP_DEBUG
);
3174 dc
.is_jmp
= DISAS_UPDATE
;
3179 tcg_gen_insn_start(dc
.pc
);
3182 if (unlikely(cpu_breakpoint_test(cs
, dc
.pc
, BP_ANY
))) {
3183 tcg_gen_movi_i32(cpu_pc
, dc
.pc
);
3184 gen_exception(&dc
, EXCP_DEBUG
);
3185 dc
.is_jmp
= DISAS_UPDATE
;
3186 /* The address covered by the breakpoint must be included in
3187 [tb->pc, tb->pc + tb->size) in order to for it to be
3188 properly cleared -- thus we increment the PC here so that
3189 the logic setting tb->size below does the right thing. */
3194 if (insn_count
== max_insns
&& (tb_cflags(tb
) & CF_LAST_IO
)) {
3199 TCGLabel
*label
= gen_new_label();
3201 tcg_gen_addi_i32(dc
.next_icount
, cpu_SR
[ICOUNT
], 1);
3202 tcg_gen_brcondi_i32(TCG_COND_NE
, dc
.next_icount
, 0, label
);
3203 tcg_gen_mov_i32(dc
.next_icount
, cpu_SR
[ICOUNT
]);
3205 gen_debug_exception(&dc
, DEBUGCAUSE_IC
);
3207 gen_set_label(label
);
3211 gen_ibreak_check(env
, &dc
);
3214 disas_xtensa_insn(env
, &dc
);
3216 tcg_gen_mov_i32(cpu_SR
[ICOUNT
], dc
.next_icount
);
3218 if (cs
->singlestep_enabled
) {
3219 tcg_gen_movi_i32(cpu_pc
, dc
.pc
);
3220 gen_exception(&dc
, EXCP_DEBUG
);
3223 } while (dc
.is_jmp
== DISAS_NEXT
&&
3224 insn_count
< max_insns
&&
3225 dc
.pc
< next_page_start
&&
3226 dc
.pc
+ xtensa_insn_len(env
, &dc
) <= next_page_start
&&
3227 !tcg_op_buf_full());
3230 reset_sar_tracker(&dc
);
3232 tcg_temp_free(dc
.next_icount
);
3235 if (tb_cflags(tb
) & CF_LAST_IO
) {
3239 if (dc
.is_jmp
== DISAS_NEXT
) {
3240 gen_jumpi(&dc
, dc
.pc
, 0);
3242 gen_tb_end(tb
, insn_count
);
3245 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)
3246 && qemu_log_in_addr_range(pc_start
)) {
3248 qemu_log("----------------\n");
3249 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
3250 log_target_disas(cs
, pc_start
, dc
.pc
- pc_start
);
3255 tb
->size
= dc
.pc
- pc_start
;
3256 tb
->icount
= insn_count
;
3259 void xtensa_cpu_dump_state(CPUState
*cs
, FILE *f
,
3260 fprintf_function cpu_fprintf
, int flags
)
3262 XtensaCPU
*cpu
= XTENSA_CPU(cs
);
3263 CPUXtensaState
*env
= &cpu
->env
;
3266 cpu_fprintf(f
, "PC=%08x\n\n", env
->pc
);
3268 for (i
= j
= 0; i
< 256; ++i
) {
3269 if (xtensa_option_bits_enabled(env
->config
, sregnames
[i
].opt_bits
)) {
3270 cpu_fprintf(f
, "%12s=%08x%c", sregnames
[i
].name
, env
->sregs
[i
],
3271 (j
++ % 4) == 3 ? '\n' : ' ');
3275 cpu_fprintf(f
, (j
% 4) == 0 ? "\n" : "\n\n");
3277 for (i
= j
= 0; i
< 256; ++i
) {
3278 if (xtensa_option_bits_enabled(env
->config
, uregnames
[i
].opt_bits
)) {
3279 cpu_fprintf(f
, "%s=%08x%c", uregnames
[i
].name
, env
->uregs
[i
],
3280 (j
++ % 4) == 3 ? '\n' : ' ');
3284 cpu_fprintf(f
, (j
% 4) == 0 ? "\n" : "\n\n");
3286 for (i
= 0; i
< 16; ++i
) {
3287 cpu_fprintf(f
, " A%02d=%08x%c", i
, env
->regs
[i
],
3288 (i
% 4) == 3 ? '\n' : ' ');
3291 cpu_fprintf(f
, "\n");
3293 for (i
= 0; i
< env
->config
->nareg
; ++i
) {
3294 cpu_fprintf(f
, "AR%02d=%08x%c", i
, env
->phys_regs
[i
],
3295 (i
% 4) == 3 ? '\n' : ' ');
3298 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_FP_COPROCESSOR
)) {
3299 cpu_fprintf(f
, "\n");
3301 for (i
= 0; i
< 16; ++i
) {
3302 cpu_fprintf(f
, "F%02d=%08x (%+10.8e)%c", i
,
3303 float32_val(env
->fregs
[i
].f32
[FP_F32_LOW
]),
3304 *(float *)(env
->fregs
[i
].f32
+ FP_F32_LOW
),
3305 (i
% 2) == 1 ? '\n' : ' ');
3310 void restore_state_to_opc(CPUXtensaState
*env
, TranslationBlock
*tb
,