tests/libqos/ahci.h

   1 #ifndef __libqos_ahci_h
   2 #define __libqos_ahci_h
   3
   4 /*
   5  * AHCI qtest library functions and definitions
   6  *
   7  * Copyright (c) 2014 John Snow <jsnow@redhat.com>
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a copy
  10  * of this software and associated documentation files (the "Software"), to deal
  11  * in the Software without restriction, including without limitation the rights
  12  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  13  * copies of the Software, and to permit persons to whom the Software is
  14  * furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice shall be included in
  17  * all copies or substantial portions of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  24  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  25  * THE SOFTWARE.
  26  */
  27
  28 #include <stdint.h>
  29 #include <stdlib.h>
  30 #include <stdbool.h>
  31 #include "libqos/libqos.h"
  32 #include "libqos/pci.h"
  33 #include "libqos/malloc-pc.h"
  34
  35 /*** Supplementary PCI Config Space IDs & Masks ***/
  36 #define PCI_DEVICE_ID_INTEL_Q35_AHCI   (0x2922)
  37 #define PCI_MSI_FLAGS_RESERVED         (0xFF00)
  38 #define PCI_PM_CTRL_RESERVED             (0xFC)
  39 #define PCI_BCC(REG32)          ((REG32) >> 24)
  40 #define PCI_PI(REG32)   (((REG32) >> 8) & 0xFF)
  41 #define PCI_SCC(REG32) (((REG32) >> 16) & 0xFF)
  42
  43 /*** Recognized AHCI Device Types ***/
  44 #define AHCI_INTEL_ICH9 (PCI_DEVICE_ID_INTEL_Q35_AHCI << 16 | \
  45                          PCI_VENDOR_ID_INTEL)
  46
  47 /*** AHCI/HBA Register Offsets and Bitmasks ***/
  48 #define AHCI_CAP                          (0)
  49 #define AHCI_CAP_NP                    (0x1F)
  50 #define AHCI_CAP_SXS                   (0x20)
  51 #define AHCI_CAP_EMS                   (0x40)
  52 #define AHCI_CAP_CCCS                  (0x80)
  53 #define AHCI_CAP_NCS                 (0x1F00)
  54 #define AHCI_CAP_PSC                 (0x2000)
  55 #define AHCI_CAP_SSC                 (0x4000)
  56 #define AHCI_CAP_PMD                 (0x8000)
  57 #define AHCI_CAP_FBSS               (0x10000)
  58 #define AHCI_CAP_SPM                (0x20000)
  59 #define AHCI_CAP_SAM                (0x40000)
  60 #define AHCI_CAP_RESERVED           (0x80000)
  61 #define AHCI_CAP_ISS               (0xF00000)
  62 #define AHCI_CAP_SCLO             (0x1000000)
  63 #define AHCI_CAP_SAL              (0x2000000)
  64 #define AHCI_CAP_SALP             (0x4000000)
  65 #define AHCI_CAP_SSS              (0x8000000)
  66 #define AHCI_CAP_SMPS            (0x10000000)
  67 #define AHCI_CAP_SSNTF           (0x20000000)
  68 #define AHCI_CAP_SNCQ            (0x40000000)
  69 #define AHCI_CAP_S64A            (0x80000000)
  70
  71 #define AHCI_GHC                          (1)
  72 #define AHCI_GHC_HR                    (0x01)
  73 #define AHCI_GHC_IE                    (0x02)
  74 #define AHCI_GHC_MRSM                  (0x04)
  75 #define AHCI_GHC_RESERVED        (0x7FFFFFF8)
  76 #define AHCI_GHC_AE              (0x80000000)
  77
  78 #define AHCI_IS                           (2)
  79 #define AHCI_PI                           (3)
  80 #define AHCI_VS                           (4)
  81
  82 #define AHCI_CCCCTL                       (5)
  83 #define AHCI_CCCCTL_EN                 (0x01)
  84 #define AHCI_CCCCTL_RESERVED           (0x06)
  85 #define AHCI_CCCCTL_CC               (0xFF00)
  86 #define AHCI_CCCCTL_TV           (0xFFFF0000)
  87
  88 #define AHCI_CCCPORTS                     (6)
  89 #define AHCI_EMLOC                        (7)
  90
  91 #define AHCI_EMCTL                        (8)
  92 #define AHCI_EMCTL_STSMR               (0x01)
  93 #define AHCI_EMCTL_CTLTM              (0x100)
  94 #define AHCI_EMCTL_CTLRST             (0x200)
  95 #define AHCI_EMCTL_RESERVED      (0xF0F0FCFE)
  96
  97 #define AHCI_CAP2                         (9)
  98 #define AHCI_CAP2_BOH                  (0x01)
  99 #define AHCI_CAP2_NVMP                 (0x02)
 100 #define AHCI_CAP2_APST                 (0x04)
 101 #define AHCI_CAP2_RESERVED       (0xFFFFFFF8)
 102
 103 #define AHCI_BOHC                        (10)
 104 #define AHCI_RESERVED                    (11)
 105 #define AHCI_NVMHCI                      (24)
 106 #define AHCI_VENDOR                      (40)
 107 #define AHCI_PORTS                       (64)
 108
 109 /*** Port Memory Offsets & Bitmasks ***/
 110 #define AHCI_PX_CLB                       (0)
 111 #define AHCI_PX_CLB_RESERVED          (0x1FF)
 112
 113 #define AHCI_PX_CLBU                      (1)
 114
 115 #define AHCI_PX_FB                        (2)
 116 #define AHCI_PX_FB_RESERVED            (0xFF)
 117
 118 #define AHCI_PX_FBU                       (3)
 119
 120 #define AHCI_PX_IS                        (4)
 121 #define AHCI_PX_IS_DHRS                 (0x1)
 122 #define AHCI_PX_IS_PSS                  (0x2)
 123 #define AHCI_PX_IS_DSS                  (0x4)
 124 #define AHCI_PX_IS_SDBS                 (0x8)
 125 #define AHCI_PX_IS_UFS                 (0x10)
 126 #define AHCI_PX_IS_DPS                 (0x20)
 127 #define AHCI_PX_IS_PCS                 (0x40)
 128 #define AHCI_PX_IS_DMPS                (0x80)
 129 #define AHCI_PX_IS_RESERVED       (0x23FFF00)
 130 #define AHCI_PX_IS_PRCS            (0x400000)
 131 #define AHCI_PX_IS_IPMS            (0x800000)
 132 #define AHCI_PX_IS_OFS            (0x1000000)
 133 #define AHCI_PX_IS_INFS           (0x4000000)
 134 #define AHCI_PX_IS_IFS            (0x8000000)
 135 #define AHCI_PX_IS_HBDS          (0x10000000)
 136 #define AHCI_PX_IS_HBFS          (0x20000000)
 137 #define AHCI_PX_IS_TFES          (0x40000000)
 138 #define AHCI_PX_IS_CPDS          (0x80000000)
 139
 140 #define AHCI_PX_IE                        (5)
 141 #define AHCI_PX_IE_DHRE                 (0x1)
 142 #define AHCI_PX_IE_PSE                  (0x2)
 143 #define AHCI_PX_IE_DSE                  (0x4)
 144 #define AHCI_PX_IE_SDBE                 (0x8)
 145 #define AHCI_PX_IE_UFE                 (0x10)
 146 #define AHCI_PX_IE_DPE                 (0x20)
 147 #define AHCI_PX_IE_PCE                 (0x40)
 148 #define AHCI_PX_IE_DMPE                (0x80)
 149 #define AHCI_PX_IE_RESERVED       (0x23FFF00)
 150 #define AHCI_PX_IE_PRCE            (0x400000)
 151 #define AHCI_PX_IE_IPME            (0x800000)
 152 #define AHCI_PX_IE_OFE            (0x1000000)
 153 #define AHCI_PX_IE_INFE           (0x4000000)
 154 #define AHCI_PX_IE_IFE            (0x8000000)
 155 #define AHCI_PX_IE_HBDE          (0x10000000)
 156 #define AHCI_PX_IE_HBFE          (0x20000000)
 157 #define AHCI_PX_IE_TFEE          (0x40000000)
 158 #define AHCI_PX_IE_CPDE          (0x80000000)
 159
 160 #define AHCI_PX_CMD                       (6)
 161 #define AHCI_PX_CMD_ST                  (0x1)
 162 #define AHCI_PX_CMD_SUD                 (0x2)
 163 #define AHCI_PX_CMD_POD                 (0x4)
 164 #define AHCI_PX_CMD_CLO                 (0x8)
 165 #define AHCI_PX_CMD_FRE                (0x10)
 166 #define AHCI_PX_CMD_RESERVED           (0xE0)
 167 #define AHCI_PX_CMD_CCS              (0x1F00)
 168 #define AHCI_PX_CMD_MPSS             (0x2000)
 169 #define AHCI_PX_CMD_FR               (0x4000)
 170 #define AHCI_PX_CMD_CR               (0x8000)
 171 #define AHCI_PX_CMD_CPS             (0x10000)
 172 #define AHCI_PX_CMD_PMA             (0x20000)
 173 #define AHCI_PX_CMD_HPCP            (0x40000)
 174 #define AHCI_PX_CMD_MPSP            (0x80000)
 175 #define AHCI_PX_CMD_CPD            (0x100000)
 176 #define AHCI_PX_CMD_ESP            (0x200000)
 177 #define AHCI_PX_CMD_FBSCP          (0x400000)
 178 #define AHCI_PX_CMD_APSTE          (0x800000)
 179 #define AHCI_PX_CMD_ATAPI         (0x1000000)
 180 #define AHCI_PX_CMD_DLAE          (0x2000000)
 181 #define AHCI_PX_CMD_ALPE          (0x4000000)
 182 #define AHCI_PX_CMD_ASP           (0x8000000)
 183 #define AHCI_PX_CMD_ICC          (0xF0000000)
 184
 185 #define AHCI_PX_RES1                      (7)
 186
 187 #define AHCI_PX_TFD                       (8)
 188 #define AHCI_PX_TFD_STS                (0xFF)
 189 #define AHCI_PX_TFD_STS_ERR            (0x01)
 190 #define AHCI_PX_TFD_STS_CS1            (0x06)
 191 #define AHCI_PX_TFD_STS_DRQ            (0x08)
 192 #define AHCI_PX_TFD_STS_CS2            (0x70)
 193 #define AHCI_PX_TFD_STS_BSY            (0x80)
 194 #define AHCI_PX_TFD_ERR              (0xFF00)
 195 #define AHCI_PX_TFD_RESERVED     (0xFFFF0000)
 196
 197 #define AHCI_PX_SIG                       (9)
 198 #define AHCI_PX_SIG_SECTOR_COUNT       (0xFF)
 199 #define AHCI_PX_SIG_LBA_LOW          (0xFF00)
 200 #define AHCI_PX_SIG_LBA_MID        (0xFF0000)
 201 #define AHCI_PX_SIG_LBA_HIGH     (0xFF000000)
 202
 203 #define AHCI_PX_SSTS                     (10)
 204 #define AHCI_PX_SSTS_DET               (0x0F)
 205 #define AHCI_PX_SSTS_SPD               (0xF0)
 206 #define AHCI_PX_SSTS_IPM              (0xF00)
 207 #define AHCI_PX_SSTS_RESERVED    (0xFFFFF000)
 208 #define SSTS_DET_NO_DEVICE             (0x00)
 209 #define SSTS_DET_PRESENT               (0x01)
 210 #define SSTS_DET_ESTABLISHED           (0x03)
 211 #define SSTS_DET_OFFLINE               (0x04)
 212
 213 #define AHCI_PX_SCTL                     (11)
 214
 215 #define AHCI_PX_SERR                     (12)
 216 #define AHCI_PX_SERR_ERR             (0xFFFF)
 217 #define AHCI_PX_SERR_DIAG        (0xFFFF0000)
 218 #define AHCI_PX_SERR_DIAG_X      (0x04000000)
 219
 220 #define AHCI_PX_SACT                     (13)
 221 #define AHCI_PX_CI                       (14)
 222 #define AHCI_PX_SNTF                     (15)
 223
 224 #define AHCI_PX_FBS                      (16)
 225 #define AHCI_PX_FBS_EN                  (0x1)
 226 #define AHCI_PX_FBS_DEC                 (0x2)
 227 #define AHCI_PX_FBS_SDE                 (0x4)
 228 #define AHCI_PX_FBS_DEV               (0xF00)
 229 #define AHCI_PX_FBS_ADO              (0xF000)
 230 #define AHCI_PX_FBS_DWE             (0xF0000)
 231 #define AHCI_PX_FBS_RESERVED     (0xFFF000F8)
 232
 233 #define AHCI_PX_RES2                     (17)
 234 #define AHCI_PX_VS                       (28)
 235
 236 #define HBA_DATA_REGION_SIZE            (256)
 237 #define HBA_PORT_DATA_SIZE              (128)
 238 #define HBA_PORT_NUM_REG (HBA_PORT_DATA_SIZE/4)
 239
 240 #define AHCI_VERSION_0_95        (0x00000905)
 241 #define AHCI_VERSION_1_0         (0x00010000)
 242 #define AHCI_VERSION_1_1         (0x00010100)
 243 #define AHCI_VERSION_1_2         (0x00010200)
 244 #define AHCI_VERSION_1_3         (0x00010300)
 245
 246 #define AHCI_SECTOR_SIZE                (512)
 247
 248 /* FIS types */
 249 enum {
 250     REG_H2D_FIS = 0x27,
 251     REG_D2H_FIS = 0x34,
 252     DMA_ACTIVATE_FIS = 0x39,
 253     DMA_SETUP_FIS = 0x41,
 254     DATA_FIS = 0x46,
 255     BIST_ACTIVATE_FIS = 0x58,
 256     PIO_SETUP_FIS = 0x5F,
 257     SDB_FIS = 0xA1
 258 };
 259
 260 /* FIS flags */
 261 #define REG_H2D_FIS_CMD  0x80
 262
 263 /* ATA Commands */
 264 enum {
 265     /* DMA */
 266     CMD_READ_DMA      = 0xC8,
 267     CMD_READ_DMA_EXT  = 0x25,
 268     CMD_WRITE_DMA     = 0xCA,
 269     CMD_WRITE_DMA_EXT = 0x35,
 270     /* PIO */
 271     CMD_READ_PIO      = 0x20,
 272     CMD_READ_PIO_EXT  = 0x24,
 273     CMD_WRITE_PIO     = 0x30,
 274     CMD_WRITE_PIO_EXT = 0x34,
 275     /* Misc */
 276     CMD_READ_MAX      = 0xF8,
 277     CMD_READ_MAX_EXT  = 0x27,
 278     CMD_FLUSH_CACHE   = 0xE7,
 279     CMD_IDENTIFY      = 0xEC
 280 };
 281
 282 /* AHCI Command Header Flags & Masks*/
 283 #define CMDH_CFL        (0x1F)
 284 #define CMDH_ATAPI      (0x20)
 285 #define CMDH_WRITE      (0x40)
 286 #define CMDH_PREFETCH   (0x80)
 287 #define CMDH_RESET     (0x100)
 288 #define CMDH_BIST      (0x200)
 289 #define CMDH_CLR_BSY   (0x400)
 290 #define CMDH_RES       (0x800)
 291 #define CMDH_PMP      (0xF000)
 292
 293 /* ATA device register masks */
 294 #define ATA_DEVICE_MAGIC 0xA0
 295 #define ATA_DEVICE_LBA   0x40
 296 #define ATA_DEVICE_DRIVE 0x10
 297 #define ATA_DEVICE_HEAD  0x0F
 298
 299 /*** Structures ***/
 300
 301 typedef struct AHCIPortQState {
 302     uint64_t fb;
 303     uint64_t clb;
 304     uint64_t ctba[32];
 305     uint16_t prdtl[32];
 306     uint8_t next; /** Next Command Slot to Use **/
 307 } AHCIPortQState;
 308
 309 typedef struct AHCIQState {
 310     QOSState *parent;
 311     QPCIDevice *dev;
 312     void *hba_base;
 313     uint64_t barsize;
 314     uint32_t fingerprint;
 315     uint32_t cap;
 316     uint32_t cap2;
 317     AHCIPortQState port[32];
 318 } AHCIQState;
 319
 320 /**
 321  * Generic FIS structure.
 322  */
 323 typedef struct FIS {
 324     uint8_t fis_type;
 325     uint8_t flags;
 326     char data[0];
 327 } __attribute__((__packed__)) FIS;
 328
 329 /**
 330  * Register device-to-host FIS structure.
 331  */
 332 typedef struct RegD2HFIS {
 333     /* DW0 */
 334     uint8_t fis_type;
 335     uint8_t flags;
 336     uint8_t status;
 337     uint8_t error;
 338     /* DW1 */
 339     uint8_t lba_lo[3];
 340     uint8_t device;
 341     /* DW2 */
 342     uint8_t lba_hi[3];
 343     uint8_t res0;
 344     /* DW3 */
 345     uint16_t count;
 346     uint16_t res1;
 347     /* DW4 */
 348     uint32_t res2;
 349 } __attribute__((__packed__)) RegD2HFIS;
 350
 351 /**
 352  * Register device-to-host FIS structure;
 353  * PIO Setup variety.
 354  */
 355 typedef struct PIOSetupFIS {
 356     /* DW0 */
 357     uint8_t fis_type;
 358     uint8_t flags;
 359     uint8_t status;
 360     uint8_t error;
 361     /* DW1 */
 362     uint8_t lba_lo[3];
 363     uint8_t device;
 364     /* DW2 */
 365     uint8_t lba_hi[3];
 366     uint8_t res0;
 367     /* DW3 */
 368     uint16_t count;
 369     uint8_t res1;
 370     uint8_t e_status;
 371     /* DW4 */
 372     uint16_t tx_count;
 373     uint16_t res2;
 374 } __attribute__((__packed__)) PIOSetupFIS;
 375
 376 /**
 377  * Register host-to-device FIS structure.
 378  */
 379 typedef struct RegH2DFIS {
 380     /* DW0 */
 381     uint8_t fis_type;
 382     uint8_t flags;
 383     uint8_t command;
 384     uint8_t feature_low;
 385     /* DW1 */
 386     uint8_t lba_lo[3];
 387     uint8_t device;
 388     /* DW2 */
 389     uint8_t lba_hi[3];
 390     uint8_t feature_high;
 391     /* DW3 */
 392     uint16_t count;
 393     uint8_t icc;
 394     uint8_t control;
 395     /* DW4 */
 396     uint8_t aux[4];
 397 } __attribute__((__packed__)) RegH2DFIS;
 398
 399 /**
 400  * Command List entry structure.
 401  * The command list contains between 1-32 of these structures.
 402  */
 403 typedef struct AHCICommandHeader {
 404     uint16_t flags; /* Cmd-Fis-Len, PMP#, and flags. */
 405     uint16_t prdtl; /* Phys Region Desc. Table Length */
 406     uint32_t prdbc; /* Phys Region Desc. Byte Count */
 407     uint64_t ctba;  /* Command Table Descriptor Base Address */
 408     uint32_t res[4];
 409 } __attribute__((__packed__)) AHCICommandHeader;
 410
 411 /**
 412  * Physical Region Descriptor; pointed to by the Command List Header,
 413  * struct ahci_command.
 414  */
 415 typedef struct PRD {
 416     uint64_t dba;  /* Data Base Address */
 417     uint32_t res;  /* Reserved */
 418     uint32_t dbc;  /* Data Byte Count (0-indexed) & Interrupt Flag (bit 2^31) */
 419 } __attribute__((__packed__)) PRD;
 420
 421 /* Opaque, defined within ahci.c */
 422 typedef struct AHCICommand AHCICommand;
 423
 424 /*** Macro Utilities ***/
 425 #define BITANY(data, mask) (((data) & (mask)) != 0)
 426 #define BITSET(data, mask) (((data) & (mask)) == (mask))
 427 #define BITCLR(data, mask) (((data) & (mask)) == 0)
 428 #define ASSERT_BIT_SET(data, mask) g_assert_cmphex((data) & (mask), ==, (mask))
 429 #define ASSERT_BIT_CLEAR(data, mask) g_assert_cmphex((data) & (mask), ==, 0)
 430
 431 /* For calculating how big the PRD table needs to be: */
 432 #define CMD_TBL_SIZ(n) ((0x80 + ((n) * sizeof(PRD)) + 0x7F) & ~0x7F)
 433
 434 /* Helpers for reading/writing AHCI HBA register values */
 435
 436 static inline uint32_t ahci_mread(AHCIQState *ahci, size_t offset)
 437 {
 438     return qpci_io_readl(ahci->dev, ahci->hba_base + offset);
 439 }
 440
 441 static inline void ahci_mwrite(AHCIQState *ahci, size_t offset, uint32_t value)
 442 {
 443     qpci_io_writel(ahci->dev, ahci->hba_base + offset, value);
 444 }
 445
 446 static inline uint32_t ahci_rreg(AHCIQState *ahci, uint32_t reg_num)
 447 {
 448     return ahci_mread(ahci, 4 * reg_num);
 449 }
 450
 451 static inline void ahci_wreg(AHCIQState *ahci, uint32_t reg_num, uint32_t value)
 452 {
 453     ahci_mwrite(ahci, 4 * reg_num, value);
 454 }
 455
 456 static inline void ahci_set(AHCIQState *ahci, uint32_t reg_num, uint32_t mask)
 457 {
 458     ahci_wreg(ahci, reg_num, ahci_rreg(ahci, reg_num) | mask);
 459 }
 460
 461 static inline void ahci_clr(AHCIQState *ahci, uint32_t reg_num, uint32_t mask)
 462 {
 463     ahci_wreg(ahci, reg_num, ahci_rreg(ahci, reg_num) & ~mask);
 464 }
 465
 466 static inline size_t ahci_px_offset(uint8_t port, uint32_t reg_num)
 467 {
 468     return AHCI_PORTS + (HBA_PORT_NUM_REG * port) + reg_num;
 469 }
 470
 471 static inline uint32_t ahci_px_rreg(AHCIQState *ahci, uint8_t port,
 472                                     uint32_t reg_num)
 473 {
 474     return ahci_rreg(ahci, ahci_px_offset(port, reg_num));
 475 }
 476
 477 static inline void ahci_px_wreg(AHCIQState *ahci, uint8_t port,
 478                                 uint32_t reg_num, uint32_t value)
 479 {
 480     ahci_wreg(ahci, ahci_px_offset(port, reg_num), value);
 481 }
 482
 483 static inline void ahci_px_set(AHCIQState *ahci, uint8_t port,
 484                                uint32_t reg_num, uint32_t mask)
 485 {
 486     ahci_px_wreg(ahci, port, reg_num,
 487                  ahci_px_rreg(ahci, port, reg_num) | mask);
 488 }
 489
 490 static inline void ahci_px_clr(AHCIQState *ahci, uint8_t port,
 491                                uint32_t reg_num, uint32_t mask)
 492 {
 493     ahci_px_wreg(ahci, port, reg_num,
 494                  ahci_px_rreg(ahci, port, reg_num) & ~mask);
 495 }
 496
 497 /*** Prototypes ***/
 498 uint64_t ahci_alloc(AHCIQState *ahci, size_t bytes);
 499 void ahci_free(AHCIQState *ahci, uint64_t addr);
 500 QPCIDevice *get_ahci_device(uint32_t *fingerprint);
 501 void free_ahci_device(QPCIDevice *dev);
 502 void ahci_clean_mem(AHCIQState *ahci);
 503 void ahci_pci_enable(AHCIQState *ahci);
 504 void start_ahci_device(AHCIQState *ahci);
 505 void ahci_hba_enable(AHCIQState *ahci);
 506 unsigned ahci_port_select(AHCIQState *ahci);
 507 void ahci_port_clear(AHCIQState *ahci, uint8_t port);
 508 void ahci_port_check_error(AHCIQState *ahci, uint8_t port);
 509 void ahci_port_check_interrupts(AHCIQState *ahci, uint8_t port,
 510                                 uint32_t intr_mask);
 511 void ahci_port_check_nonbusy(AHCIQState *ahci, uint8_t port, uint8_t slot);
 512 void ahci_port_check_d2h_sanity(AHCIQState *ahci, uint8_t port, uint8_t slot);
 513 void ahci_port_check_pio_sanity(AHCIQState *ahci, uint8_t port,
 514                                 uint8_t slot, size_t buffsize);
 515 void ahci_port_check_cmd_sanity(AHCIQState *ahci, uint8_t port,
 516                                 uint8_t slot, size_t buffsize);
 517 void ahci_get_command_header(AHCIQState *ahci, uint8_t port,
 518                              uint8_t slot, AHCICommandHeader *cmd);
 519 void ahci_set_command_header(AHCIQState *ahci, uint8_t port,
 520                              uint8_t slot, AHCICommandHeader *cmd);
 521 void ahci_destroy_command(AHCIQState *ahci, uint8_t port, uint8_t slot);
 522 void ahci_write_fis(AHCIQState *ahci, RegH2DFIS *fis, uint64_t addr);
 523 unsigned ahci_pick_cmd(AHCIQState *ahci, uint8_t port);
 524 unsigned size_to_prdtl(unsigned bytes, unsigned bytes_per_prd);
 525 void ahci_guest_io(AHCIQState *ahci, uint8_t port, uint8_t ide_cmd,
 526                    uint64_t gbuffer, size_t size, uint64_t sector);
 527 AHCICommand *ahci_guest_io_halt(AHCIQState *ahci, uint8_t port, uint8_t ide_cmd,
 528                                 uint64_t gbuffer, size_t size, uint64_t sector);
 529 void ahci_guest_io_resume(AHCIQState *ahci, AHCICommand *cmd);
 530 void ahci_io(AHCIQState *ahci, uint8_t port, uint8_t ide_cmd,
 531              void *buffer, size_t bufsize, uint64_t sector);
 532
 533 /* Command Lifecycle */
 534 AHCICommand *ahci_command_create(uint8_t command_name);
 535 void ahci_command_commit(AHCIQState *ahci, AHCICommand *cmd, uint8_t port);
 536 void ahci_command_issue(AHCIQState *ahci, AHCICommand *cmd);
 537 void ahci_command_issue_async(AHCIQState *ahci, AHCICommand *cmd);
 538 void ahci_command_wait(AHCIQState *ahci, AHCICommand *cmd);
 539 void ahci_command_verify(AHCIQState *ahci, AHCICommand *cmd);
 540 void ahci_command_free(AHCICommand *cmd);
 541
 542 /* Command adjustments */
 543 void ahci_command_set_flags(AHCICommand *cmd, uint16_t cmdh_flags);
 544 void ahci_command_clr_flags(AHCICommand *cmd, uint16_t cmdh_flags);
 545 void ahci_command_set_offset(AHCICommand *cmd, uint64_t lba_sect);
 546 void ahci_command_set_buffer(AHCICommand *cmd, uint64_t buffer);
 547 void ahci_command_set_size(AHCICommand *cmd, uint64_t xbytes);
 548 void ahci_command_set_prd_size(AHCICommand *cmd, unsigned prd_size);
 549 void ahci_command_set_sizes(AHCICommand *cmd, uint64_t xbytes,
 550                             unsigned prd_size);
 551 void ahci_command_adjust(AHCICommand *cmd, uint64_t lba_sect, uint64_t gbuffer,
 552                          uint64_t xbytes, unsigned prd_size);
 553
 554 /* Command Misc */
 555 uint8_t ahci_command_slot(AHCICommand *cmd);
 556
 557 #endif