target-arm/internals.h

   1 /*
   2  * QEMU ARM CPU -- internal functions and types
   3  *
   4  * Copyright (c) 2014 Linaro Ltd
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  *
  20  * This header defines functions, types, etc which need to be shared
  21  * between different source files within target-arm/ but which are
  22  * private to it and not required by the rest of QEMU.
  23  */
  24
  25 #ifndef TARGET_ARM_INTERNALS_H
  26 #define TARGET_ARM_INTERNALS_H
  27
  28 static inline bool excp_is_internal(int excp)
  29 {
  30     /* Return true if this exception number represents a QEMU-internal
  31      * exception that will not be passed to the guest.
  32      */
  33     return excp == EXCP_INTERRUPT
  34         || excp == EXCP_HLT
  35         || excp == EXCP_DEBUG
  36         || excp == EXCP_HALTED
  37         || excp == EXCP_EXCEPTION_EXIT
  38         || excp == EXCP_KERNEL_TRAP
  39         || excp == EXCP_STREX;
  40 }
  41
  42 /* Exception names for debug logging; note that not all of these
  43  * precisely correspond to architectural exceptions.
  44  */
  45 static const char * const excnames[] = {
  46     [EXCP_UDEF] = "Undefined Instruction",
  47     [EXCP_SWI] = "SVC",
  48     [EXCP_PREFETCH_ABORT] = "Prefetch Abort",
  49     [EXCP_DATA_ABORT] = "Data Abort",
  50     [EXCP_IRQ] = "IRQ",
  51     [EXCP_FIQ] = "FIQ",
  52     [EXCP_BKPT] = "Breakpoint",
  53     [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit",
  54     [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage",
  55     [EXCP_STREX] = "QEMU intercept of STREX",
  56     [EXCP_HVC] = "Hypervisor Call",
  57     [EXCP_HYP_TRAP] = "Hypervisor Trap",
  58     [EXCP_SMC] = "Secure Monitor Call",
  59     [EXCP_VIRQ] = "Virtual IRQ",
  60     [EXCP_VFIQ] = "Virtual FIQ",
  61 };
  62
  63 static inline void arm_log_exception(int idx)
  64 {
  65     if (qemu_loglevel_mask(CPU_LOG_INT)) {
  66         const char *exc = NULL;
  67
  68         if (idx >= 0 && idx < ARRAY_SIZE(excnames)) {
  69             exc = excnames[idx];
  70         }
  71         if (!exc) {
  72             exc = "unknown";
  73         }
  74         qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s]\n", idx, exc);
  75     }
  76 }
  77
  78 /* Scale factor for generic timers, ie number of ns per tick.
  79  * This gives a 62.5MHz timer.
  80  */
  81 #define GTIMER_SCALE 16
  82
  83 /*
  84  * For AArch64, map a given EL to an index in the banked_spsr array.
  85  * Note that this mapping and the AArch32 mapping defined in bank_number()
  86  * must agree such that the AArch64<->AArch32 SPSRs have the architecturally
  87  * mandated mapping between each other.
  88  */
  89 static inline unsigned int aarch64_banked_spsr_index(unsigned int el)
  90 {
  91     static const unsigned int map[4] = {
  92         [1] = 1, /* EL1.  */
  93         [2] = 6, /* EL2.  */
  94         [3] = 7, /* EL3.  */
  95     };
  96     assert(el >= 1 && el <= 3);
  97     return map[el];
  98 }
  99
 100 int bank_number(int mode);
 101 void switch_mode(CPUARMState *, int);
 102 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu);
 103 void arm_translate_init(void);
 104
 105 enum arm_fprounding {
 106     FPROUNDING_TIEEVEN,
 107     FPROUNDING_POSINF,
 108     FPROUNDING_NEGINF,
 109     FPROUNDING_ZERO,
 110     FPROUNDING_TIEAWAY,
 111     FPROUNDING_ODD
 112 };
 113
 114 int arm_rmode_to_sf(int rmode);
 115
 116 static inline void aarch64_save_sp(CPUARMState *env, int el)
 117 {
 118     if (env->pstate & PSTATE_SP) {
 119         env->sp_el[el] = env->xregs[31];
 120     } else {
 121         env->sp_el[0] = env->xregs[31];
 122     }
 123 }
 124
 125 static inline void aarch64_restore_sp(CPUARMState *env, int el)
 126 {
 127     if (env->pstate & PSTATE_SP) {
 128         env->xregs[31] = env->sp_el[el];
 129     } else {
 130         env->xregs[31] = env->sp_el[0];
 131     }
 132 }
 133
 134 static inline void update_spsel(CPUARMState *env, uint32_t imm)
 135 {
 136     unsigned int cur_el = arm_current_el(env);
 137     /* Update PSTATE SPSel bit; this requires us to update the
 138      * working stack pointer in xregs[31].
 139      */
 140     if (!((imm ^ env->pstate) & PSTATE_SP)) {
 141         return;
 142     }
 143     aarch64_save_sp(env, cur_el);
 144     env->pstate = deposit32(env->pstate, 0, 1, imm);
 145
 146     /* We rely on illegal updates to SPsel from EL0 to get trapped
 147      * at translation time.
 148      */
 149     assert(cur_el >= 1 && cur_el <= 3);
 150     aarch64_restore_sp(env, cur_el);
 151 }
 152
 153 /* Return true if extended addresses are enabled.
 154  * This is always the case if our translation regime is 64 bit,
 155  * but depends on TTBCR.EAE for 32 bit.
 156  */
 157 static inline bool extended_addresses_enabled(CPUARMState *env)
 158 {
 159     TCR *tcr = &env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1];
 160     return arm_el_is_aa64(env, 1) ||
 161            (arm_feature(env, ARM_FEATURE_LPAE) && (tcr->raw_tcr & TTBCR_EAE));
 162 }
 163
 164 /* Valid Syndrome Register EC field values */
 165 enum arm_exception_class {
 166     EC_UNCATEGORIZED          = 0x00,
 167     EC_WFX_TRAP               = 0x01,
 168     EC_CP15RTTRAP             = 0x03,
 169     EC_CP15RRTTRAP            = 0x04,
 170     EC_CP14RTTRAP             = 0x05,
 171     EC_CP14DTTRAP             = 0x06,
 172     EC_ADVSIMDFPACCESSTRAP    = 0x07,
 173     EC_FPIDTRAP               = 0x08,
 174     EC_CP14RRTTRAP            = 0x0c,
 175     EC_ILLEGALSTATE           = 0x0e,
 176     EC_AA32_SVC               = 0x11,
 177     EC_AA32_HVC               = 0x12,
 178     EC_AA32_SMC               = 0x13,
 179     EC_AA64_SVC               = 0x15,
 180     EC_AA64_HVC               = 0x16,
 181     EC_AA64_SMC               = 0x17,
 182     EC_SYSTEMREGISTERTRAP     = 0x18,
 183     EC_INSNABORT              = 0x20,
 184     EC_INSNABORT_SAME_EL      = 0x21,
 185     EC_PCALIGNMENT            = 0x22,
 186     EC_DATAABORT              = 0x24,
 187     EC_DATAABORT_SAME_EL      = 0x25,
 188     EC_SPALIGNMENT            = 0x26,
 189     EC_AA32_FPTRAP            = 0x28,
 190     EC_AA64_FPTRAP            = 0x2c,
 191     EC_SERROR                 = 0x2f,
 192     EC_BREAKPOINT             = 0x30,
 193     EC_BREAKPOINT_SAME_EL     = 0x31,
 194     EC_SOFTWARESTEP           = 0x32,
 195     EC_SOFTWARESTEP_SAME_EL   = 0x33,
 196     EC_WATCHPOINT             = 0x34,
 197     EC_WATCHPOINT_SAME_EL     = 0x35,
 198     EC_AA32_BKPT              = 0x38,
 199     EC_VECTORCATCH            = 0x3a,
 200     EC_AA64_BKPT              = 0x3c,
 201 };
 202
 203 #define ARM_EL_EC_SHIFT 26
 204 #define ARM_EL_IL_SHIFT 25
 205 #define ARM_EL_IL (1 << ARM_EL_IL_SHIFT)
 206
 207 /* Utility functions for constructing various kinds of syndrome value.
 208  * Note that in general we follow the AArch64 syndrome values; in a
 209  * few cases the value in HSR for exceptions taken to AArch32 Hyp
 210  * mode differs slightly, so if we ever implemented Hyp mode then the
 211  * syndrome value would need some massaging on exception entry.
 212  * (One example of this is that AArch64 defaults to IL bit set for
 213  * exceptions which don't specifically indicate information about the
 214  * trapping instruction, whereas AArch32 defaults to IL bit clear.)
 215  */
 216 static inline uint32_t syn_uncategorized(void)
 217 {
 218     return (EC_UNCATEGORIZED << ARM_EL_EC_SHIFT) | ARM_EL_IL;
 219 }
 220
 221 static inline uint32_t syn_aa64_svc(uint32_t imm16)
 222 {
 223     return (EC_AA64_SVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
 224 }
 225
 226 static inline uint32_t syn_aa64_hvc(uint32_t imm16)
 227 {
 228     return (EC_AA64_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
 229 }
 230
 231 static inline uint32_t syn_aa64_smc(uint32_t imm16)
 232 {
 233     return (EC_AA64_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
 234 }
 235
 236 static inline uint32_t syn_aa32_svc(uint32_t imm16, bool is_thumb)
 237 {
 238     return (EC_AA32_SVC << ARM_EL_EC_SHIFT) | (imm16 & 0xffff)
 239         | (is_thumb ? 0 : ARM_EL_IL);
 240 }
 241
 242 static inline uint32_t syn_aa32_hvc(uint32_t imm16)
 243 {
 244     return (EC_AA32_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
 245 }
 246
 247 static inline uint32_t syn_aa32_smc(void)
 248 {
 249     return (EC_AA32_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL;
 250 }
 251
 252 static inline uint32_t syn_aa64_bkpt(uint32_t imm16)
 253 {
 254     return (EC_AA64_BKPT << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
 255 }
 256
 257 static inline uint32_t syn_aa32_bkpt(uint32_t imm16, bool is_thumb)
 258 {
 259     return (EC_AA32_BKPT << ARM_EL_EC_SHIFT) | (imm16 & 0xffff)
 260         | (is_thumb ? 0 : ARM_EL_IL);
 261 }
 262
 263 static inline uint32_t syn_aa64_sysregtrap(int op0, int op1, int op2,
 264                                            int crn, int crm, int rt,
 265                                            int isread)
 266 {
 267     return (EC_SYSTEMREGISTERTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL
 268         | (op0 << 20) | (op2 << 17) | (op1 << 14) | (crn << 10) | (rt << 5)
 269         | (crm << 1) | isread;
 270 }
 271
 272 static inline uint32_t syn_cp14_rt_trap(int cv, int cond, int opc1, int opc2,
 273                                         int crn, int crm, int rt, int isread,
 274                                         bool is_thumb)
 275 {
 276     return (EC_CP14RTTRAP << ARM_EL_EC_SHIFT)
 277         | (is_thumb ? 0 : ARM_EL_IL)
 278         | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14)
 279         | (crn << 10) | (rt << 5) | (crm << 1) | isread;
 280 }
 281
 282 static inline uint32_t syn_cp15_rt_trap(int cv, int cond, int opc1, int opc2,
 283                                         int crn, int crm, int rt, int isread,
 284                                         bool is_thumb)
 285 {
 286     return (EC_CP15RTTRAP << ARM_EL_EC_SHIFT)
 287         | (is_thumb ? 0 : ARM_EL_IL)
 288         | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14)
 289         | (crn << 10) | (rt << 5) | (crm << 1) | isread;
 290 }
 291
 292 static inline uint32_t syn_cp14_rrt_trap(int cv, int cond, int opc1, int crm,
 293                                          int rt, int rt2, int isread,
 294                                          bool is_thumb)
 295 {
 296     return (EC_CP14RRTTRAP << ARM_EL_EC_SHIFT)
 297         | (is_thumb ? 0 : ARM_EL_IL)
 298         | (cv << 24) | (cond << 20) | (opc1 << 16)
 299         | (rt2 << 10) | (rt << 5) | (crm << 1) | isread;
 300 }
 301
 302 static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int crm,
 303                                          int rt, int rt2, int isread,
 304                                          bool is_thumb)
 305 {
 306     return (EC_CP15RRTTRAP << ARM_EL_EC_SHIFT)
 307         | (is_thumb ? 0 : ARM_EL_IL)
 308         | (cv << 24) | (cond << 20) | (opc1 << 16)
 309         | (rt2 << 10) | (rt << 5) | (crm << 1) | isread;
 310 }
 311
 312 static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_thumb)
 313 {
 314     return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT)
 315         | (is_thumb ? 0 : ARM_EL_IL)
 316         | (cv << 24) | (cond << 20);
 317 }
 318
 319 static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc)
 320 {
 321     return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
 322         | (ea << 9) | (s1ptw << 7) | fsc;
 323 }
 324
 325 static inline uint32_t syn_data_abort(int same_el, int ea, int cm, int s1ptw,
 326                                       int wnr, int fsc)
 327 {
 328     return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
 329         | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc;
 330 }
 331
 332 static inline uint32_t syn_swstep(int same_el, int isv, int ex)
 333 {
 334     return (EC_SOFTWARESTEP << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
 335         | (isv << 24) | (ex << 6) | 0x22;
 336 }
 337
 338 static inline uint32_t syn_watchpoint(int same_el, int cm, int wnr)
 339 {
 340     return (EC_WATCHPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
 341         | (cm << 8) | (wnr << 6) | 0x22;
 342 }
 343
 344 static inline uint32_t syn_breakpoint(int same_el)
 345 {
 346     return (EC_BREAKPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
 347         | ARM_EL_IL | 0x22;
 348 }
 349
 350 static inline uint32_t syn_wfx(int cv, int cond, int ti)
 351 {
 352     return (EC_WFX_TRAP << ARM_EL_EC_SHIFT) |
 353            (cv << 24) | (cond << 20) | ti;
 354 }
 355
 356 /* Update a QEMU watchpoint based on the information the guest has set in the
 357  * DBGWCR<n>_EL1 and DBGWVR<n>_EL1 registers.
 358  */
 359 void hw_watchpoint_update(ARMCPU *cpu, int n);
 360 /* Update the QEMU watchpoints for every guest watchpoint. This does a
 361  * complete delete-and-reinstate of the QEMU watchpoint list and so is
 362  * suitable for use after migration or on reset.
 363  */
 364 void hw_watchpoint_update_all(ARMCPU *cpu);
 365 /* Update a QEMU breakpoint based on the information the guest has set in the
 366  * DBGBCR<n>_EL1 and DBGBVR<n>_EL1 registers.
 367  */
 368 void hw_breakpoint_update(ARMCPU *cpu, int n);
 369 /* Update the QEMU breakpoints for every guest breakpoint. This does a
 370  * complete delete-and-reinstate of the QEMU breakpoint list and so is
 371  * suitable for use after migration or on reset.
 372  */
 373 void hw_breakpoint_update_all(ARMCPU *cpu);
 374
 375 /* Callback function for when a watchpoint or breakpoint triggers. */
 376 void arm_debug_excp_handler(CPUState *cs);
 377
 378 #ifdef CONFIG_USER_ONLY
 379 static inline bool arm_is_psci_call(ARMCPU *cpu, int excp_type)
 380 {
 381     return false;
 382 }
 383 #else
 384 /* Return true if the r0/x0 value indicates that this SMC/HVC is a PSCI call. */
 385 bool arm_is_psci_call(ARMCPU *cpu, int excp_type);
 386 /* Actually handle a PSCI call */
 387 void arm_handle_psci_call(ARMCPU *cpu);
 388 #endif
 389
 390 /* Do a page table walk and add page to TLB if possible */
 391 int arm_tlb_fill(CPUState *cpu, vaddr address, int rw, int mmu_idx);
 392
 393 #endif