2 * PPC4xx I2C controller emulation
4 * Copyright (c) 2007 Jocelyn Mayer
5 * Copyright (c) 2012 François Revol
6 * Copyright (c) 2016 BALATON Zoltan
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 #include "qemu/osdep.h"
28 #include "qemu-common.h"
32 #include "hw/i2c/ppc4xx_i2c.h"
34 #define PPC4xx_I2C_MEM_SIZE 18
36 #define IIC_CNTL_PT (1 << 0)
37 #define IIC_CNTL_READ (1 << 1)
38 #define IIC_CNTL_CHT (1 << 2)
39 #define IIC_CNTL_RPST (1 << 3)
41 #define IIC_STS_PT (1 << 0)
42 #define IIC_STS_ERR (1 << 2)
43 #define IIC_STS_MDBS (1 << 5)
45 #define IIC_EXTSTS_XFRA (1 << 0)
47 #define IIC_XTCNTLSS_SRST (1 << 0)
49 static void ppc4xx_i2c_reset(DeviceState
*s
)
51 PPC4xxI2CState
*i2c
= PPC4xx_I2C(s
);
53 /* FIXME: Should also reset bus?
54 *if (s->address != ADDR_RESET) {
55 * i2c_end_transfer(s->bus);
73 i2c
->directcntl
= 0xf;
77 static inline bool ppc4xx_i2c_is_master(PPC4xxI2CState
*i2c
)
82 static uint64_t ppc4xx_i2c_readb(void *opaque
, hwaddr addr
, unsigned int size
)
84 PPC4xxI2CState
*i2c
= PPC4xx_I2C(opaque
);
90 if (ppc4xx_i2c_is_master(i2c
)) {
93 if (!(i2c
->sts
& IIC_STS_MDBS
)) {
94 qemu_log_mask(LOG_GUEST_ERROR
, "[%s]%s: Trying to read "
95 "without starting transfer\n",
96 TYPE_PPC4xx_I2C
, __func__
);
98 int pending
= (i2c
->cntl
>> 4) & 3;
100 /* get the next byte */
101 int byte
= i2c_recv(i2c
->bus
);
104 qemu_log_mask(LOG_GUEST_ERROR
, "[%s]%s: read failed "
105 "for device 0x%02x\n", TYPE_PPC4xx_I2C
,
106 __func__
, i2c
->lmadr
);
110 /* Raise interrupt if enabled */
111 /*ppc4xx_i2c_raise_interrupt(i2c)*/;
115 i2c
->sts
&= ~IIC_STS_MDBS
;
116 /*i2c_end_transfer(i2c->bus);*/
117 /*} else if (i2c->cntl & (IIC_CNTL_RPST | IIC_CNTL_CHT)) {*/
118 } else if (pending
) {
119 /* current smbus implementation doesn't like
120 multibyte xfer repeated start */
121 i2c_end_transfer(i2c
->bus
);
122 if (i2c_start_transfer(i2c
->bus
, i2c
->lmadr
>> 1, 1)) {
123 /* if non zero is returned, the adress is not valid */
124 i2c
->sts
&= ~IIC_STS_PT
;
125 i2c
->sts
|= IIC_STS_ERR
;
126 i2c
->extsts
|= IIC_EXTSTS_XFRA
;
128 /*i2c->sts |= IIC_STS_PT;*/
129 i2c
->sts
|= IIC_STS_MDBS
;
130 i2c
->sts
&= ~IIC_STS_ERR
;
135 i2c
->cntl
= (i2c
->cntl
& 0xcf) | (pending
<< 4);
138 qemu_log_mask(LOG_UNIMP
, "[%s]%s: slave mode not implemented\n",
139 TYPE_PPC4xx_I2C
, __func__
);
182 ret
= i2c
->directcntl
;
188 if (addr
< PPC4xx_I2C_MEM_SIZE
) {
189 qemu_log_mask(LOG_UNIMP
, "%s: Unimplemented register 0x%"
190 HWADDR_PRIx
"\n", __func__
, addr
);
192 qemu_log_mask(LOG_GUEST_ERROR
, "%s: Bad address 0x%"
193 HWADDR_PRIx
"\n", __func__
, addr
);
201 static void ppc4xx_i2c_writeb(void *opaque
, hwaddr addr
, uint64_t value
,
204 PPC4xxI2CState
*i2c
= opaque
;
209 if (!i2c_bus_busy(i2c
->bus
)) {
210 /* assume we start a write transfer */
211 if (i2c_start_transfer(i2c
->bus
, i2c
->lmadr
>> 1, 0)) {
212 /* if non zero is returned, the adress is not valid */
213 i2c
->sts
&= ~IIC_STS_PT
;
214 i2c
->sts
|= IIC_STS_ERR
;
215 i2c
->extsts
|= IIC_EXTSTS_XFRA
;
217 i2c
->sts
|= IIC_STS_PT
;
218 i2c
->sts
&= ~IIC_STS_ERR
;
222 if (i2c_bus_busy(i2c
->bus
)) {
223 if (i2c_send(i2c
->bus
, i2c
->mdata
)) {
224 /* if the target return non zero then end the transfer */
225 i2c
->sts
&= ~IIC_STS_PT
;
226 i2c
->sts
|= IIC_STS_ERR
;
227 i2c
->extsts
|= IIC_EXTSTS_XFRA
;
228 i2c_end_transfer(i2c
->bus
);
237 if (i2c_bus_busy(i2c
->bus
)) {
238 i2c_end_transfer(i2c
->bus
);
246 if (i2c
->cntl
& IIC_CNTL_PT
) {
247 if (i2c
->cntl
& IIC_CNTL_READ
) {
248 if (i2c_bus_busy(i2c
->bus
)) {
249 /* end previous transfer */
250 i2c
->sts
&= ~IIC_STS_PT
;
251 i2c_end_transfer(i2c
->bus
);
253 if (i2c_start_transfer(i2c
->bus
, i2c
->lmadr
>> 1, 1)) {
254 /* if non zero is returned, the adress is not valid */
255 i2c
->sts
&= ~IIC_STS_PT
;
256 i2c
->sts
|= IIC_STS_ERR
;
257 i2c
->extsts
|= IIC_EXTSTS_XFRA
;
259 /*i2c->sts |= IIC_STS_PT;*/
260 i2c
->sts
|= IIC_STS_MDBS
;
261 i2c
->sts
&= ~IIC_STS_ERR
;
265 /* we actually already did the write transfer... */
266 i2c
->sts
&= ~IIC_STS_PT
;
271 i2c
->mdcntl
= value
& 0xdf;
274 i2c
->sts
&= ~(value
& 0xa);
277 i2c
->extsts
&= ~(value
& 0x8f);
289 i2c
->intrmsk
= value
;
292 i2c
->xfrcnt
= value
& 0x77;
295 if (value
& IIC_XTCNTLSS_SRST
) {
296 /* Is it actually a full reset? U-Boot sets some regs before */
297 ppc4xx_i2c_reset(DEVICE(i2c
));
300 i2c
->xtcntlss
= value
;
303 i2c
->directcntl
= value
& 0x7;
309 if (addr
< PPC4xx_I2C_MEM_SIZE
) {
310 qemu_log_mask(LOG_UNIMP
, "%s: Unimplemented register 0x%"
311 HWADDR_PRIx
"\n", __func__
, addr
);
313 qemu_log_mask(LOG_GUEST_ERROR
, "%s: Bad address 0x%"
314 HWADDR_PRIx
"\n", __func__
, addr
);
320 static const MemoryRegionOps ppc4xx_i2c_ops
= {
321 .read
= ppc4xx_i2c_readb
,
322 .write
= ppc4xx_i2c_writeb
,
323 .valid
.min_access_size
= 1,
324 .valid
.max_access_size
= 4,
325 .impl
.min_access_size
= 1,
326 .impl
.max_access_size
= 1,
327 .endianness
= DEVICE_NATIVE_ENDIAN
,
330 static void ppc4xx_i2c_init(Object
*o
)
332 PPC4xxI2CState
*s
= PPC4xx_I2C(o
);
334 memory_region_init_io(&s
->iomem
, OBJECT(s
), &ppc4xx_i2c_ops
, s
,
335 TYPE_PPC4xx_I2C
, PPC4xx_I2C_MEM_SIZE
);
336 sysbus_init_mmio(SYS_BUS_DEVICE(s
), &s
->iomem
);
337 sysbus_init_irq(SYS_BUS_DEVICE(s
), &s
->irq
);
338 s
->bus
= i2c_init_bus(DEVICE(s
), "i2c");
341 static void ppc4xx_i2c_class_init(ObjectClass
*klass
, void *data
)
343 DeviceClass
*dc
= DEVICE_CLASS(klass
);
345 dc
->reset
= ppc4xx_i2c_reset
;
348 static const TypeInfo ppc4xx_i2c_type_info
= {
349 .name
= TYPE_PPC4xx_I2C
,
350 .parent
= TYPE_SYS_BUS_DEVICE
,
351 .instance_size
= sizeof(PPC4xxI2CState
),
352 .instance_init
= ppc4xx_i2c_init
,
353 .class_init
= ppc4xx_i2c_class_init
,
356 static void ppc4xx_i2c_register_types(void)
358 type_register_static(&ppc4xx_i2c_type_info
);
361 type_init(ppc4xx_i2c_register_types
)