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target-tilegx: Handle nofault prefetch instructions
[qemu.git] / target-tilegx / translate.c
blob6ab66f9b07721d9ca6068c5406b6422de57178c1
1 /*
2 * QEMU TILE-Gx CPU
3 *
4 * Copyright (c) 2015 Chen Gang
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see
18 * <http://www.gnu.org/licenses/lgpl-2.1.html>
19 */
20
21 #include "cpu.h"
22 #include "qemu/log.h"
23 #include "disas/disas.h"
24 #include "tcg-op.h"
25 #include "exec/cpu_ldst.h"
26 #include "linux-user/syscall_defs.h"
27
28 #include "opcode_tilegx.h"
29 #include "spr_def_64.h"
30
31 #define FMT64X "%016" PRIx64
32
33 static TCGv_ptr cpu_env;
34 static TCGv cpu_pc;
35 static TCGv cpu_regs[TILEGX_R_COUNT];
36
37 static const char * const reg_names[64] = {
38 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
39 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
40 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
41 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
42 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
43 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
44 "r48", "r49", "r50", "r51", "bp", "tp", "sp", "lr",
45 "sn", "idn0", "idn1", "udn0", "udn1", "udn2", "udn2", "zero"
46 };
47
48 /* Modified registers are cached in temporaries until the end of the bundle. */
49 typedef struct {
50 unsigned reg;
51 TCGv val;
52 } DisasContextTemp;
53
54 #define MAX_WRITEBACK 4
55
56 /* This is the state at translation time. */
57 typedef struct {
58 uint64_t pc; /* Current pc */
59
60 TCGv zero; /* For zero register */
61
62 DisasContextTemp wb[MAX_WRITEBACK];
63 int num_wb;
64 int mmuidx;
65 bool exit_tb;
66 TileExcp atomic_excp;
67
68 struct {
69 TCGCond cond; /* branch condition */
70 TCGv dest; /* branch destination */
71 TCGv val1; /* value to be compared against zero, for cond */
72 } jmp; /* Jump object, only once in each TB block */
73 } DisasContext;
74
75 #include "exec/gen-icount.h"
76
77 /* Differentiate the various pipe encodings. */
78 #define TY_X0 0
79 #define TY_X1 1
80 #define TY_Y0 2
81 #define TY_Y1 3
82
83 /* Remerge the base opcode and extension fields for switching.
84 The X opcode fields are 3 bits; Y0/Y1 opcode fields are 4 bits;
85 Y2 opcode field is 2 bits. */
86 #define OE(OP, EXT, XY) (TY_##XY + OP * 4 + EXT * 64)
87
88 /* Similar, but for Y2 only. */
89 #define OEY2(OP, MODE) (OP + MODE * 4)
90
91 /* Similar, but make sure opcode names match up. */
92 #define OE_RR_X0(E) OE(RRR_0_OPCODE_X0, E##_UNARY_OPCODE_X0, X0)
93 #define OE_RR_X1(E) OE(RRR_0_OPCODE_X1, E##_UNARY_OPCODE_X1, X1)
94 #define OE_RR_Y0(E) OE(RRR_1_OPCODE_Y0, E##_UNARY_OPCODE_Y0, Y0)
95 #define OE_RR_Y1(E) OE(RRR_1_OPCODE_Y1, E##_UNARY_OPCODE_Y1, Y1)
96 #define OE_RRR(E,N,XY) OE(RRR_##N##_OPCODE_##XY, E##_RRR_##N##_OPCODE_##XY, XY)
97 #define OE_IM(E,XY) OE(IMM8_OPCODE_##XY, E##_IMM8_OPCODE_##XY, XY)
98 #define OE_SH(E,XY) OE(SHIFT_OPCODE_##XY, E##_SHIFT_OPCODE_##XY, XY)
99
100 #define V1_IMM(X) (((X) & 0xff) * 0x0101010101010101ull)
101 #define V2_IMM(X) (((X) & 0xffff) * 0x0001000100010001ull)
102
103
104 static void gen_exception(DisasContext *dc, TileExcp num)
105 {
106 TCGv_i32 tmp;
107
108 tcg_gen_movi_tl(cpu_pc, dc->pc + TILEGX_BUNDLE_SIZE_IN_BYTES);
109
110 tmp = tcg_const_i32(num);
111 gen_helper_exception(cpu_env, tmp);
112 tcg_temp_free_i32(tmp);
113 dc->exit_tb = true;
114 }
115
116 static bool check_gr(DisasContext *dc, uint8_t reg)
117 {
118 if (likely(reg < TILEGX_R_COUNT)) {
119 return true;
120 }
121
122 switch (reg) {
123 case TILEGX_R_SN:
124 case TILEGX_R_ZERO:
125 break;
126 case TILEGX_R_IDN0:
127 case TILEGX_R_IDN1:
128 gen_exception(dc, TILEGX_EXCP_REG_IDN_ACCESS);
129 break;
130 case TILEGX_R_UDN0:
131 case TILEGX_R_UDN1:
132 case TILEGX_R_UDN2:
133 case TILEGX_R_UDN3:
134 gen_exception(dc, TILEGX_EXCP_REG_UDN_ACCESS);
135 break;
136 default:
137 g_assert_not_reached();
138 }
139 return false;
140 }
141
142 static TCGv load_zero(DisasContext *dc)
143 {
144 if (TCGV_IS_UNUSED_I64(dc->zero)) {
145 dc->zero = tcg_const_i64(0);
146 }
147 return dc->zero;
148 }
149
150 static TCGv load_gr(DisasContext *dc, unsigned reg)
151 {
152 if (check_gr(dc, reg)) {
153 return cpu_regs[reg];
154 }
155 return load_zero(dc);
156 }
157
158 static TCGv dest_gr(DisasContext *dc, unsigned reg)
159 {
160 int n;
161
162 /* Skip the result, mark the exception if necessary, and continue */
163 check_gr(dc, reg);
164
165 n = dc->num_wb++;
166 dc->wb[n].reg = reg;
167 return dc->wb[n].val = tcg_temp_new_i64();
168 }
169
170 static void gen_saturate_op(TCGv tdest, TCGv tsrca, TCGv tsrcb,
171 void (*operate)(TCGv, TCGv, TCGv))
172 {
173 TCGv t0 = tcg_temp_new();
174
175 tcg_gen_ext32s_tl(tdest, tsrca);
176 tcg_gen_ext32s_tl(t0, tsrcb);
177 operate(tdest, tdest, t0);
178
179 tcg_gen_movi_tl(t0, 0x7fffffff);
180 tcg_gen_movcond_tl(TCG_COND_GT, tdest, tdest, t0, t0, tdest);
181 tcg_gen_movi_tl(t0, -0x80000000LL);
182 tcg_gen_movcond_tl(TCG_COND_LT, tdest, tdest, t0, t0, tdest);
183
184 tcg_temp_free(t0);
185 }
186
187 static void gen_atomic_excp(DisasContext *dc, unsigned dest, TCGv tdest,
188 TCGv tsrca, TCGv tsrcb, TileExcp excp)
189 {
190 #ifdef CONFIG_USER_ONLY
191 TCGv_i32 t;
192
193 tcg_gen_st_tl(tsrca, cpu_env, offsetof(CPUTLGState, atomic_srca));
194 tcg_gen_st_tl(tsrcb, cpu_env, offsetof(CPUTLGState, atomic_srcb));
195 t = tcg_const_i32(dest);
196 tcg_gen_st_i32(t, cpu_env, offsetof(CPUTLGState, atomic_dstr));
197 tcg_temp_free_i32(t);
198
199 /* We're going to write the real result in the exception. But in
200 the meantime we've already created a writeback register, and
201 we don't want that to remain uninitialized. */
202 tcg_gen_movi_tl(tdest, 0);
203
204 /* Note that we need to delay issuing the exception that implements
205 the atomic operation until after writing back the results of the
206 instruction occupying the X0 pipe. */
207 dc->atomic_excp = excp;
208 #else
209 gen_exception(dc, TILEGX_EXCP_OPCODE_UNIMPLEMENTED);
210 #endif
211 }
212
213 /* Shift the 128-bit value TSRCA:TSRCD right by the number of bytes
214 specified by the bottom 3 bits of TSRCB, and set TDEST to the
215 low 64 bits of the resulting value. */
216 static void gen_dblalign(TCGv tdest, TCGv tsrcd, TCGv tsrca, TCGv tsrcb)
217 {
218 TCGv t0 = tcg_temp_new();
219
220 tcg_gen_andi_tl(t0, tsrcb, 7);
221 tcg_gen_shli_tl(t0, t0, 3);
222 tcg_gen_shr_tl(tdest, tsrcd, t0);
223
224 /* We want to do "t0 = tsrca << (64 - t0)". Two's complement
225 arithmetic on a 6-bit field tells us that 64 - t0 is equal
226 to (t0 ^ 63) + 1. So we can do the shift in two parts,
227 neither of which will be an invalid shift by 64. */
228 tcg_gen_xori_tl(t0, t0, 63);
229 tcg_gen_shl_tl(t0, tsrca, t0);
230 tcg_gen_shli_tl(t0, t0, 1);
231 tcg_gen_or_tl(tdest, tdest, t0);
232
233 tcg_temp_free(t0);
234 }
235
236 /* Similarly, except that the 128-bit value is TSRCA:TSRCB, and the
237 right shift is an immediate. */
238 static void gen_dblaligni(TCGv tdest, TCGv tsrca, TCGv tsrcb, int shr)
239 {
240 TCGv t0 = tcg_temp_new();
241
242 tcg_gen_shri_tl(t0, tsrcb, shr);
243 tcg_gen_shli_tl(tdest, tsrca, 64 - shr);
244 tcg_gen_or_tl(tdest, tdest, t0);
245
246 tcg_temp_free(t0);
247 }
248
249 typedef enum {
250 LU, LS, HU, HS
251 } MulHalf;
252
253 static void gen_ext_half(TCGv d, TCGv s, MulHalf h)
254 {
255 switch (h) {
256 case LU:
257 tcg_gen_ext32u_tl(d, s);
258 break;
259 case LS:
260 tcg_gen_ext32s_tl(d, s);
261 break;
262 case HU:
263 tcg_gen_shri_tl(d, s, 32);
264 break;
265 case HS:
266 tcg_gen_sari_tl(d, s, 32);
267 break;
268 }
269 }
270
271 static void gen_mul_half(TCGv tdest, TCGv tsrca, TCGv tsrcb,
272 MulHalf ha, MulHalf hb)
273 {
274 TCGv t = tcg_temp_new();
275 gen_ext_half(t, tsrca, ha);
276 gen_ext_half(tdest, tsrcb, hb);
277 tcg_gen_mul_tl(tdest, tdest, t);
278 tcg_temp_free(t);
279 }
280
281 static void gen_cmul2(TCGv tdest, TCGv tsrca, TCGv tsrcb, int sh, int rd)
282 {
283 TCGv_i32 tsh = tcg_const_i32(sh);
284 TCGv_i32 trd = tcg_const_i32(rd);
285 gen_helper_cmul2(tdest, tsrca, tsrcb, tsh, trd);
286 tcg_temp_free_i32(tsh);
287 tcg_temp_free_i32(trd);
288 }
289
290 static TileExcp gen_st_opcode(DisasContext *dc, unsigned dest, unsigned srca,
291 unsigned srcb, TCGMemOp memop, const char *name)
292 {
293 if (dest) {
294 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
295 }
296
297 tcg_gen_qemu_st_tl(load_gr(dc, srcb), load_gr(dc, srca),
298 dc->mmuidx, memop);
299
300 qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s", name,
301 reg_names[srca], reg_names[srcb]);
302 return TILEGX_EXCP_NONE;
303 }
304
305 static TileExcp gen_st_add_opcode(DisasContext *dc, unsigned srca, unsigned srcb,
306 int imm, TCGMemOp memop, const char *name)
307 {
308 TCGv tsrca = load_gr(dc, srca);
309 TCGv tsrcb = load_gr(dc, srcb);
310
311 tcg_gen_qemu_st_tl(tsrcb, tsrca, dc->mmuidx, memop);
312 tcg_gen_addi_tl(dest_gr(dc, srca), tsrca, imm);
313
314 qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s, %d", name,
315 reg_names[srca], reg_names[srcb], imm);
316 return TILEGX_EXCP_NONE;
317 }
318
319 /* Equality comparison with zero can be done quickly and efficiently. */
320 static void gen_v1cmpeq0(TCGv v)
321 {
322 TCGv m = tcg_const_tl(V1_IMM(0x7f));
323 TCGv c = tcg_temp_new();
324
325 /* ~(((v & m) + m) | m | v). Sets the msb for each byte == 0. */
326 tcg_gen_and_tl(c, v, m);
327 tcg_gen_add_tl(c, c, m);
328 tcg_gen_or_tl(c, c, m);
329 tcg_gen_nor_tl(c, c, v);
330 tcg_temp_free(m);
331
332 /* Shift the msb down to form the lsb boolean result. */
333 tcg_gen_shri_tl(v, c, 7);
334 tcg_temp_free(c);
335 }
336
337 static void gen_v1cmpne0(TCGv v)
338 {
339 TCGv m = tcg_const_tl(V1_IMM(0x7f));
340 TCGv c = tcg_temp_new();
341
342 /* (((v & m) + m) | v) & ~m. Sets the msb for each byte != 0. */
343 tcg_gen_and_tl(c, v, m);
344 tcg_gen_add_tl(c, c, m);
345 tcg_gen_or_tl(c, c, v);
346 tcg_gen_andc_tl(c, c, m);
347 tcg_temp_free(m);
348
349 /* Shift the msb down to form the lsb boolean result. */
350 tcg_gen_shri_tl(v, c, 7);
351 tcg_temp_free(c);
352 }
353
354 /* Vector addition can be performed via arithmetic plus masking. It is
355 efficient this way only for 4 or more elements. */
356 static void gen_v12add(TCGv tdest, TCGv tsrca, TCGv tsrcb, uint64_t sign)
357 {
358 TCGv tmask = tcg_const_tl(~sign);
359 TCGv t0 = tcg_temp_new();
360 TCGv t1 = tcg_temp_new();
361
362 /* ((a & ~sign) + (b & ~sign)) ^ ((a ^ b) & sign). */
363 tcg_gen_and_tl(t0, tsrca, tmask);
364 tcg_gen_and_tl(t1, tsrcb, tmask);
365 tcg_gen_add_tl(tdest, t0, t1);
366 tcg_gen_xor_tl(t0, tsrca, tsrcb);
367 tcg_gen_andc_tl(t0, t0, tmask);
368 tcg_gen_xor_tl(tdest, tdest, t0);
369
370 tcg_temp_free(t1);
371 tcg_temp_free(t0);
372 tcg_temp_free(tmask);
373 }
374
375 /* Similarly for vector subtraction. */
376 static void gen_v12sub(TCGv tdest, TCGv tsrca, TCGv tsrcb, uint64_t sign)
377 {
378 TCGv tsign = tcg_const_tl(sign);
379 TCGv t0 = tcg_temp_new();
380 TCGv t1 = tcg_temp_new();
381
382 /* ((a | sign) - (b & ~sign)) ^ ((a ^ ~b) & sign). */
383 tcg_gen_or_tl(t0, tsrca, tsign);
384 tcg_gen_andc_tl(t1, tsrcb, tsign);
385 tcg_gen_sub_tl(tdest, t0, t1);
386 tcg_gen_eqv_tl(t0, tsrca, tsrcb);
387 tcg_gen_and_tl(t0, t0, tsign);
388 tcg_gen_xor_tl(tdest, tdest, t0);
389
390 tcg_temp_free(t1);
391 tcg_temp_free(t0);
392 tcg_temp_free(tsign);
393 }
394
395 static void gen_v4sh(TCGv d64, TCGv a64, TCGv b64,
396 void (*generate)(TCGv_i32, TCGv_i32, TCGv_i32))
397 {
398 TCGv_i32 al = tcg_temp_new_i32();
399 TCGv_i32 ah = tcg_temp_new_i32();
400 TCGv_i32 bl = tcg_temp_new_i32();
401
402 tcg_gen_extr_i64_i32(al, ah, a64);
403 tcg_gen_extrl_i64_i32(bl, b64);
404 tcg_gen_andi_i32(bl, bl, 31);
405 generate(al, al, bl);
406 generate(ah, ah, bl);
407 tcg_gen_concat_i32_i64(d64, al, ah);
408
409 tcg_temp_free_i32(al);
410 tcg_temp_free_i32(ah);
411 tcg_temp_free_i32(bl);
412 }
413
414 static void gen_v4op(TCGv d64, TCGv a64, TCGv b64,
415 void (*generate)(TCGv_i32, TCGv_i32, TCGv_i32))
416 {
417 TCGv_i32 al = tcg_temp_new_i32();
418 TCGv_i32 ah = tcg_temp_new_i32();
419 TCGv_i32 bl = tcg_temp_new_i32();
420 TCGv_i32 bh = tcg_temp_new_i32();
421
422 tcg_gen_extr_i64_i32(al, ah, a64);
423 tcg_gen_extr_i64_i32(bl, bh, b64);
424 generate(al, al, bl);
425 generate(ah, ah, bh);
426 tcg_gen_concat_i32_i64(d64, al, ah);
427
428 tcg_temp_free_i32(al);
429 tcg_temp_free_i32(ah);
430 tcg_temp_free_i32(bl);
431 tcg_temp_free_i32(bh);
432 }
433
434 static TileExcp gen_signal(DisasContext *dc, int signo, int sigcode,
435 const char *mnemonic)
436 {
437 TCGv_i32 t0 = tcg_const_i32(signo);
438 TCGv_i32 t1 = tcg_const_i32(sigcode);
439
440 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUTLGState, signo));
441 tcg_gen_st_i32(t1, cpu_env, offsetof(CPUTLGState, sigcode));
442
443 tcg_temp_free_i32(t1);
444 tcg_temp_free_i32(t0);
445
446 qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s", mnemonic);
447 return TILEGX_EXCP_SIGNAL;
448 }
449
450 static bool parse_from_addli(uint64_t bundle, int *signo, int *sigcode)
451 {
452 int imm;
453
454 if ((get_Opcode_X0(bundle) != ADDLI_OPCODE_X0)
455 || (get_Dest_X0(bundle) != TILEGX_R_ZERO)
456 || (get_SrcA_X0(bundle) != TILEGX_R_ZERO)) {
457 return false;
458 }
459
460 imm = get_Imm16_X0(bundle);
461 *signo = imm & 0x3f;
462 *sigcode = (imm >> 6) & 0xf;
463
464 /* ??? The linux kernel validates both signo and the sigcode vs the
465 known max for each signal. Don't bother here. */
466 return true;
467 }
468
469 static TileExcp gen_specill(DisasContext *dc, unsigned dest, unsigned srca,
470 uint64_t bundle)
471 {
472 const char *mnemonic;
473 int signo;
474 int sigcode;
475
476 if (dest == 0x1c && srca == 0x25) {
477 signo = TARGET_SIGTRAP;
478 sigcode = TARGET_TRAP_BRKPT;
479 mnemonic = "bpt";
480 } else if (dest == 0x1d && srca == 0x25
481 && parse_from_addli(bundle, &signo, &sigcode)) {
482 mnemonic = "raise";
483 } else {
484 signo = TARGET_SIGILL;
485 sigcode = TARGET_ILL_ILLOPC;
486 mnemonic = "ill";
487 }
488
489 return gen_signal(dc, signo, sigcode, mnemonic);
490 }
491
492 static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
493 unsigned dest, unsigned srca, uint64_t bundle)
494 {
495 TCGv tdest, tsrca;
496 const char *mnemonic;
497 TCGMemOp memop;
498 TileExcp ret = TILEGX_EXCP_NONE;
499 bool prefetch_nofault = false;
500
501 /* Eliminate instructions with no output before doing anything else. */
502 switch (opext) {
503 case OE_RR_Y0(NOP):
504 case OE_RR_Y1(NOP):
505 case OE_RR_X0(NOP):
506 case OE_RR_X1(NOP):
507 mnemonic = "nop";
508 goto done0;
509 case OE_RR_Y0(FNOP):
510 case OE_RR_Y1(FNOP):
511 case OE_RR_X0(FNOP):
512 case OE_RR_X1(FNOP):
513 mnemonic = "fnop";
514 goto done0;
515 case OE_RR_X1(DRAIN):
516 mnemonic = "drain";
517 goto done0;
518 case OE_RR_X1(FLUSHWB):
519 mnemonic = "flushwb";
520 goto done0;
521 case OE_RR_X1(ILL):
522 return gen_specill(dc, dest, srca, bundle);
523 case OE_RR_Y1(ILL):
524 return gen_signal(dc, TARGET_SIGILL, TARGET_ILL_ILLOPC, "ill");
525 case OE_RR_X1(MF):
526 mnemonic = "mf";
527 goto done0;
528 case OE_RR_X1(NAP):
529 /* ??? This should yield, especially in system mode. */
530 mnemonic = "nap";
531 goto done0;
532 case OE_RR_X1(SWINT0):
533 case OE_RR_X1(SWINT2):
534 case OE_RR_X1(SWINT3):
535 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
536 case OE_RR_X1(SWINT1):
537 ret = TILEGX_EXCP_SYSCALL;
538 mnemonic = "swint1";
539 done0:
540 if (srca || dest) {
541 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
542 }
543 qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s", mnemonic);
544 return ret;
545
546 case OE_RR_X1(DTLBPR):
547 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
548 case OE_RR_X1(FINV):
549 mnemonic = "finv";
550 goto done1;
551 case OE_RR_X1(FLUSH):
552 mnemonic = "flush";
553 goto done1;
554 case OE_RR_X1(ICOH):
555 mnemonic = "icoh";
556 goto done1;
557 case OE_RR_X1(INV):
558 mnemonic = "inv";
559 goto done1;
560 case OE_RR_X1(WH64):
561 mnemonic = "wh64";
562 goto done1;
563 case OE_RR_X1(JRP):
564 case OE_RR_Y1(JRP):
565 mnemonic = "jrp";
566 goto do_jr;
567 case OE_RR_X1(JR):
568 case OE_RR_Y1(JR):
569 mnemonic = "jr";
570 goto do_jr;
571 case OE_RR_X1(JALRP):
572 case OE_RR_Y1(JALRP):
573 mnemonic = "jalrp";
574 goto do_jalr;
575 case OE_RR_X1(JALR):
576 case OE_RR_Y1(JALR):
577 mnemonic = "jalr";
578 do_jalr:
579 tcg_gen_movi_tl(dest_gr(dc, TILEGX_R_LR),
580 dc->pc + TILEGX_BUNDLE_SIZE_IN_BYTES);
581 do_jr:
582 dc->jmp.cond = TCG_COND_ALWAYS;
583 dc->jmp.dest = tcg_temp_new();
584 tcg_gen_andi_tl(dc->jmp.dest, load_gr(dc, srca), ~7);
585 done1:
586 if (dest) {
587 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
588 }
589 qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s", mnemonic, reg_names[srca]);
590 return ret;
591 }
592
593 tdest = dest_gr(dc, dest);
594 tsrca = load_gr(dc, srca);
595
596 switch (opext) {
597 case OE_RR_X0(CNTLZ):
598 case OE_RR_Y0(CNTLZ):
599 gen_helper_cntlz(tdest, tsrca);
600 mnemonic = "cntlz";
601 break;
602 case OE_RR_X0(CNTTZ):
603 case OE_RR_Y0(CNTTZ):
604 gen_helper_cnttz(tdest, tsrca);
605 mnemonic = "cnttz";
606 break;
607 case OE_RR_X0(FSINGLE_PACK1):
608 case OE_RR_Y0(FSINGLE_PACK1):
609 case OE_RR_X1(IRET):
610 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
611 case OE_RR_X1(LD1S):
612 memop = MO_SB;
613 mnemonic = "ld1s"; /* prefetch_l1_fault */
614 goto do_load;
615 case OE_RR_X1(LD1U):
616 memop = MO_UB;
617 mnemonic = "ld1u"; /* prefetch, prefetch_l1 */
618 prefetch_nofault = (dest == TILEGX_R_ZERO);
619 goto do_load;
620 case OE_RR_X1(LD2S):
621 memop = MO_TESW;
622 mnemonic = "ld2s"; /* prefetch_l2_fault */
623 goto do_load;
624 case OE_RR_X1(LD2U):
625 memop = MO_TEUW;
626 mnemonic = "ld2u"; /* prefetch_l2 */
627 prefetch_nofault = (dest == TILEGX_R_ZERO);
628 goto do_load;
629 case OE_RR_X1(LD4S):
630 memop = MO_TESL;
631 mnemonic = "ld4s"; /* prefetch_l3_fault */
632 goto do_load;
633 case OE_RR_X1(LD4U):
634 memop = MO_TEUL;
635 mnemonic = "ld4u"; /* prefetch_l3 */
636 prefetch_nofault = (dest == TILEGX_R_ZERO);
637 goto do_load;
638 case OE_RR_X1(LDNT1S):
639 memop = MO_SB;
640 mnemonic = "ldnt1s";
641 goto do_load;
642 case OE_RR_X1(LDNT1U):
643 memop = MO_UB;
644 mnemonic = "ldnt1u";
645 goto do_load;
646 case OE_RR_X1(LDNT2S):
647 memop = MO_TESW;
648 mnemonic = "ldnt2s";
649 goto do_load;
650 case OE_RR_X1(LDNT2U):
651 memop = MO_TEUW;
652 mnemonic = "ldnt2u";
653 goto do_load;
654 case OE_RR_X1(LDNT4S):
655 memop = MO_TESL;
656 mnemonic = "ldnt4s";
657 goto do_load;
658 case OE_RR_X1(LDNT4U):
659 memop = MO_TEUL;
660 mnemonic = "ldnt4u";
661 goto do_load;
662 case OE_RR_X1(LDNT):
663 memop = MO_TEQ;
664 mnemonic = "ldnt";
665 goto do_load;
666 case OE_RR_X1(LD):
667 memop = MO_TEQ;
668 mnemonic = "ld";
669 do_load:
670 if (!prefetch_nofault) {
671 tcg_gen_qemu_ld_tl(tdest, tsrca, dc->mmuidx, memop);
672 }
673 break;
674 case OE_RR_X1(LDNA):
675 tcg_gen_andi_tl(tdest, tsrca, ~7);
676 tcg_gen_qemu_ld_tl(tdest, tdest, dc->mmuidx, MO_TEQ);
677 mnemonic = "ldna";
678 break;
679 case OE_RR_X1(LNK):
680 case OE_RR_Y1(LNK):
681 if (srca) {
682 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
683 }
684 tcg_gen_movi_tl(tdest, dc->pc + TILEGX_BUNDLE_SIZE_IN_BYTES);
685 mnemonic = "lnk";
686 break;
687 case OE_RR_X0(PCNT):
688 case OE_RR_Y0(PCNT):
689 gen_helper_pcnt(tdest, tsrca);
690 mnemonic = "pcnt";
691 break;
692 case OE_RR_X0(REVBITS):
693 case OE_RR_Y0(REVBITS):
694 gen_helper_revbits(tdest, tsrca);
695 mnemonic = "revbits";
696 break;
697 case OE_RR_X0(REVBYTES):
698 case OE_RR_Y0(REVBYTES):
699 tcg_gen_bswap64_tl(tdest, tsrca);
700 mnemonic = "revbytes";
701 break;
702 case OE_RR_X0(TBLIDXB0):
703 case OE_RR_Y0(TBLIDXB0):
704 tcg_gen_deposit_tl(tdest, load_gr(dc, dest), tsrca, 2, 8);
705 mnemonic = "tblidxb0";
706 break;
707 case OE_RR_X0(TBLIDXB1):
708 case OE_RR_Y0(TBLIDXB1):
709 tcg_gen_shri_tl(tdest, tsrca, 8);
710 tcg_gen_deposit_tl(tdest, load_gr(dc, dest), tdest, 2, 8);
711 mnemonic = "tblidxb1";
712 break;
713 case OE_RR_X0(TBLIDXB2):
714 case OE_RR_Y0(TBLIDXB2):
715 tcg_gen_shri_tl(tdest, tsrca, 16);
716 tcg_gen_deposit_tl(tdest, load_gr(dc, dest), tdest, 2, 8);
717 mnemonic = "tblidxb2";
718 break;
719 case OE_RR_X0(TBLIDXB3):
720 case OE_RR_Y0(TBLIDXB3):
721 tcg_gen_shri_tl(tdest, tsrca, 24);
722 tcg_gen_deposit_tl(tdest, load_gr(dc, dest), tdest, 2, 8);
723 mnemonic = "tblidxb3";
724 break;
725 default:
726 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
727 }
728
729 qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s", mnemonic,
730 reg_names[dest], reg_names[srca]);
731 return ret;
732 }
733
734 static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
735 unsigned dest, unsigned srca, unsigned srcb)
736 {
737 TCGv tdest = dest_gr(dc, dest);
738 TCGv tsrca = load_gr(dc, srca);
739 TCGv tsrcb = load_gr(dc, srcb);
740 TCGv t0;
741 const char *mnemonic;
742
743 switch (opext) {
744 case OE_RRR(ADDXSC, 0, X0):
745 case OE_RRR(ADDXSC, 0, X1):
746 gen_saturate_op(tdest, tsrca, tsrcb, tcg_gen_add_tl);
747 mnemonic = "addxsc";
748 break;
749 case OE_RRR(ADDX, 0, X0):
750 case OE_RRR(ADDX, 0, X1):
751 case OE_RRR(ADDX, 0, Y0):
752 case OE_RRR(ADDX, 0, Y1):
753 tcg_gen_add_tl(tdest, tsrca, tsrcb);
754 tcg_gen_ext32s_tl(tdest, tdest);
755 mnemonic = "addx";
756 break;
757 case OE_RRR(ADD, 0, X0):
758 case OE_RRR(ADD, 0, X1):
759 case OE_RRR(ADD, 0, Y0):
760 case OE_RRR(ADD, 0, Y1):
761 tcg_gen_add_tl(tdest, tsrca, tsrcb);
762 mnemonic = "add";
763 break;
764 case OE_RRR(AND, 0, X0):
765 case OE_RRR(AND, 0, X1):
766 case OE_RRR(AND, 5, Y0):
767 case OE_RRR(AND, 5, Y1):
768 tcg_gen_and_tl(tdest, tsrca, tsrcb);
769 mnemonic = "and";
770 break;
771 case OE_RRR(CMOVEQZ, 0, X0):
772 case OE_RRR(CMOVEQZ, 4, Y0):
773 tcg_gen_movcond_tl(TCG_COND_EQ, tdest, tsrca, load_zero(dc),
774 tsrcb, load_gr(dc, dest));
775 mnemonic = "cmoveqz";
776 break;
777 case OE_RRR(CMOVNEZ, 0, X0):
778 case OE_RRR(CMOVNEZ, 4, Y0):
779 tcg_gen_movcond_tl(TCG_COND_NE, tdest, tsrca, load_zero(dc),
780 tsrcb, load_gr(dc, dest));
781 mnemonic = "cmovnez";
782 break;
783 case OE_RRR(CMPEQ, 0, X0):
784 case OE_RRR(CMPEQ, 0, X1):
785 case OE_RRR(CMPEQ, 3, Y0):
786 case OE_RRR(CMPEQ, 3, Y1):
787 tcg_gen_setcond_tl(TCG_COND_EQ, tdest, tsrca, tsrcb);
788 mnemonic = "cmpeq";
789 break;
790 case OE_RRR(CMPEXCH4, 0, X1):
791 gen_atomic_excp(dc, dest, tdest, tsrca, tsrcb,
792 TILEGX_EXCP_OPCODE_CMPEXCH4);
793 mnemonic = "cmpexch4";
794 break;
795 case OE_RRR(CMPEXCH, 0, X1):
796 gen_atomic_excp(dc, dest, tdest, tsrca, tsrcb,
797 TILEGX_EXCP_OPCODE_CMPEXCH);
798 mnemonic = "cmpexch";
799 break;
800 case OE_RRR(CMPLES, 0, X0):
801 case OE_RRR(CMPLES, 0, X1):
802 case OE_RRR(CMPLES, 2, Y0):
803 case OE_RRR(CMPLES, 2, Y1):
804 tcg_gen_setcond_tl(TCG_COND_LE, tdest, tsrca, tsrcb);
805 mnemonic = "cmples";
806 break;
807 case OE_RRR(CMPLEU, 0, X0):
808 case OE_RRR(CMPLEU, 0, X1):
809 case OE_RRR(CMPLEU, 2, Y0):
810 case OE_RRR(CMPLEU, 2, Y1):
811 tcg_gen_setcond_tl(TCG_COND_LEU, tdest, tsrca, tsrcb);
812 mnemonic = "cmpleu";
813 break;
814 case OE_RRR(CMPLTS, 0, X0):
815 case OE_RRR(CMPLTS, 0, X1):
816 case OE_RRR(CMPLTS, 2, Y0):
817 case OE_RRR(CMPLTS, 2, Y1):
818 tcg_gen_setcond_tl(TCG_COND_LT, tdest, tsrca, tsrcb);
819 mnemonic = "cmplts";
820 break;
821 case OE_RRR(CMPLTU, 0, X0):
822 case OE_RRR(CMPLTU, 0, X1):
823 case OE_RRR(CMPLTU, 2, Y0):
824 case OE_RRR(CMPLTU, 2, Y1):
825 tcg_gen_setcond_tl(TCG_COND_LTU, tdest, tsrca, tsrcb);
826 mnemonic = "cmpltu";
827 break;
828 case OE_RRR(CMPNE, 0, X0):
829 case OE_RRR(CMPNE, 0, X1):
830 case OE_RRR(CMPNE, 3, Y0):
831 case OE_RRR(CMPNE, 3, Y1):
832 tcg_gen_setcond_tl(TCG_COND_NE, tdest, tsrca, tsrcb);
833 mnemonic = "cmpne";
834 break;
835 case OE_RRR(CMULAF, 0, X0):
836 gen_helper_cmulaf(tdest, load_gr(dc, dest), tsrca, tsrcb);
837 mnemonic = "cmulaf";
838 break;
839 case OE_RRR(CMULA, 0, X0):
840 gen_helper_cmula(tdest, load_gr(dc, dest), tsrca, tsrcb);
841 mnemonic = "cmula";
842 break;
843 case OE_RRR(CMULFR, 0, X0):
844 gen_cmul2(tdest, tsrca, tsrcb, 15, 1 << 14);
845 mnemonic = "cmulfr";
846 break;
847 case OE_RRR(CMULF, 0, X0):
848 gen_cmul2(tdest, tsrca, tsrcb, 15, 0);
849 mnemonic = "cmulf";
850 break;
851 case OE_RRR(CMULHR, 0, X0):
852 gen_cmul2(tdest, tsrca, tsrcb, 16, 1 << 15);
853 mnemonic = "cmulhr";
854 break;
855 case OE_RRR(CMULH, 0, X0):
856 gen_cmul2(tdest, tsrca, tsrcb, 16, 0);
857 mnemonic = "cmulh";
858 break;
859 case OE_RRR(CMUL, 0, X0):
860 gen_helper_cmula(tdest, load_zero(dc), tsrca, tsrcb);
861 mnemonic = "cmul";
862 break;
863 case OE_RRR(CRC32_32, 0, X0):
864 gen_helper_crc32_32(tdest, tsrca, tsrcb);
865 mnemonic = "crc32_32";
866 break;
867 case OE_RRR(CRC32_8, 0, X0):
868 gen_helper_crc32_8(tdest, tsrca, tsrcb);
869 mnemonic = "crc32_8";
870 break;
871 case OE_RRR(DBLALIGN2, 0, X0):
872 case OE_RRR(DBLALIGN2, 0, X1):
873 gen_dblaligni(tdest, tsrca, tsrcb, 16);
874 mnemonic = "dblalign2";
875 break;
876 case OE_RRR(DBLALIGN4, 0, X0):
877 case OE_RRR(DBLALIGN4, 0, X1):
878 gen_dblaligni(tdest, tsrca, tsrcb, 32);
879 mnemonic = "dblalign4";
880 break;
881 case OE_RRR(DBLALIGN6, 0, X0):
882 case OE_RRR(DBLALIGN6, 0, X1):
883 gen_dblaligni(tdest, tsrca, tsrcb, 48);
884 mnemonic = "dblalign6";
885 break;
886 case OE_RRR(DBLALIGN, 0, X0):
887 gen_dblalign(tdest, load_gr(dc, dest), tsrca, tsrcb);
888 mnemonic = "dblalign";
889 break;
890 case OE_RRR(EXCH4, 0, X1):
891 gen_atomic_excp(dc, dest, tdest, tsrca, tsrcb,
892 TILEGX_EXCP_OPCODE_EXCH4);
893 mnemonic = "exch4";
894 break;
895 case OE_RRR(EXCH, 0, X1):
896 gen_atomic_excp(dc, dest, tdest, tsrca, tsrcb,
897 TILEGX_EXCP_OPCODE_EXCH);
898 mnemonic = "exch";
899 break;
900 case OE_RRR(FDOUBLE_ADDSUB, 0, X0):
901 case OE_RRR(FDOUBLE_ADD_FLAGS, 0, X0):
902 case OE_RRR(FDOUBLE_MUL_FLAGS, 0, X0):
903 case OE_RRR(FDOUBLE_PACK1, 0, X0):
904 case OE_RRR(FDOUBLE_PACK2, 0, X0):
905 case OE_RRR(FDOUBLE_SUB_FLAGS, 0, X0):
906 case OE_RRR(FDOUBLE_UNPACK_MAX, 0, X0):
907 case OE_RRR(FDOUBLE_UNPACK_MIN, 0, X0):
908 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
909 case OE_RRR(FETCHADD4, 0, X1):
910 gen_atomic_excp(dc, dest, tdest, tsrca, tsrcb,
911 TILEGX_EXCP_OPCODE_FETCHADD4);
912 mnemonic = "fetchadd4";
913 break;
914 case OE_RRR(FETCHADDGEZ4, 0, X1):
915 gen_atomic_excp(dc, dest, tdest, tsrca, tsrcb,
916 TILEGX_EXCP_OPCODE_FETCHADDGEZ4);
917 mnemonic = "fetchaddgez4";
918 break;
919 case OE_RRR(FETCHADDGEZ, 0, X1):
920 gen_atomic_excp(dc, dest, tdest, tsrca, tsrcb,
921 TILEGX_EXCP_OPCODE_FETCHADDGEZ);
922 mnemonic = "fetchaddgez";
923 break;
924 case OE_RRR(FETCHADD, 0, X1):
925 gen_atomic_excp(dc, dest, tdest, tsrca, tsrcb,
926 TILEGX_EXCP_OPCODE_FETCHADD);
927 mnemonic = "fetchadd";
928 break;
929 case OE_RRR(FETCHAND4, 0, X1):
930 gen_atomic_excp(dc, dest, tdest, tsrca, tsrcb,
931 TILEGX_EXCP_OPCODE_FETCHAND4);
932 mnemonic = "fetchand4";
933 break;
934 case OE_RRR(FETCHAND, 0, X1):
935 gen_atomic_excp(dc, dest, tdest, tsrca, tsrcb,
936 TILEGX_EXCP_OPCODE_FETCHAND);
937 mnemonic = "fetchand";
938 break;
939 case OE_RRR(FETCHOR4, 0, X1):
940 gen_atomic_excp(dc, dest, tdest, tsrca, tsrcb,
941 TILEGX_EXCP_OPCODE_FETCHOR4);
942 mnemonic = "fetchor4";
943 break;
944 case OE_RRR(FETCHOR, 0, X1):
945 gen_atomic_excp(dc, dest, tdest, tsrca, tsrcb,
946 TILEGX_EXCP_OPCODE_FETCHOR);
947 mnemonic = "fetchor";
948 break;
949 case OE_RRR(FSINGLE_ADD1, 0, X0):
950 case OE_RRR(FSINGLE_ADDSUB2, 0, X0):
951 case OE_RRR(FSINGLE_MUL1, 0, X0):
952 case OE_RRR(FSINGLE_MUL2, 0, X0):
953 case OE_RRR(FSINGLE_PACK2, 0, X0):
954 case OE_RRR(FSINGLE_SUB1, 0, X0):
955 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
956 case OE_RRR(MNZ, 0, X0):
957 case OE_RRR(MNZ, 0, X1):
958 case OE_RRR(MNZ, 4, Y0):
959 case OE_RRR(MNZ, 4, Y1):
960 t0 = load_zero(dc);
961 tcg_gen_movcond_tl(TCG_COND_NE, tdest, tsrca, t0, tsrcb, t0);
962 mnemonic = "mnz";
963 break;
964 case OE_RRR(MULAX, 0, X0):
965 case OE_RRR(MULAX, 3, Y0):
966 tcg_gen_mul_tl(tdest, tsrca, tsrcb);
967 tcg_gen_add_tl(tdest, tdest, load_gr(dc, dest));
968 tcg_gen_ext32s_tl(tdest, tdest);
969 mnemonic = "mulax";
970 break;
971 case OE_RRR(MULA_HS_HS, 0, X0):
972 case OE_RRR(MULA_HS_HS, 9, Y0):
973 gen_mul_half(tdest, tsrca, tsrcb, HS, HS);
974 tcg_gen_add_tl(tdest, tdest, load_gr(dc, dest));
975 mnemonic = "mula_hs_hs";
976 break;
977 case OE_RRR(MULA_HS_HU, 0, X0):
978 gen_mul_half(tdest, tsrca, tsrcb, HS, HU);
979 tcg_gen_add_tl(tdest, tdest, load_gr(dc, dest));
980 mnemonic = "mula_hs_hu";
981 break;
982 case OE_RRR(MULA_HS_LS, 0, X0):
983 gen_mul_half(tdest, tsrca, tsrcb, HS, LS);
984 tcg_gen_add_tl(tdest, tdest, load_gr(dc, dest));
985 mnemonic = "mula_hs_ls";
986 break;
987 case OE_RRR(MULA_HS_LU, 0, X0):
988 gen_mul_half(tdest, tsrca, tsrcb, HS, LU);
989 tcg_gen_add_tl(tdest, tdest, load_gr(dc, dest));
990 mnemonic = "mula_hs_lu";
991 break;
992 case OE_RRR(MULA_HU_HU, 0, X0):
993 case OE_RRR(MULA_HU_HU, 9, Y0):
994 gen_mul_half(tdest, tsrca, tsrcb, HU, HU);
995 tcg_gen_add_tl(tdest, tdest, load_gr(dc, dest));
996 mnemonic = "mula_hu_hu";
997 break;
998 case OE_RRR(MULA_HU_LS, 0, X0):
999 gen_mul_half(tdest, tsrca, tsrcb, HU, LS);
1000 tcg_gen_add_tl(tdest, tdest, load_gr(dc, dest));
1001 mnemonic = "mula_hu_ls";
1002 break;
1003 case OE_RRR(MULA_HU_LU, 0, X0):
1004 gen_mul_half(tdest, tsrca, tsrcb, HU, LU);
1005 tcg_gen_add_tl(tdest, tdest, load_gr(dc, dest));
1006 mnemonic = "mula_hu_lu";
1007 break;
1008 case OE_RRR(MULA_LS_LS, 0, X0):
1009 case OE_RRR(MULA_LS_LS, 9, Y0):
1010 gen_mul_half(tdest, tsrca, tsrcb, LS, LS);
1011 tcg_gen_add_tl(tdest, tdest, load_gr(dc, dest));
1012 mnemonic = "mula_ls_ls";
1013 break;
1014 case OE_RRR(MULA_LS_LU, 0, X0):
1015 gen_mul_half(tdest, tsrca, tsrcb, LS, LU);
1016 tcg_gen_add_tl(tdest, tdest, load_gr(dc, dest));
1017 mnemonic = "mula_ls_lu";
1018 break;
1019 case OE_RRR(MULA_LU_LU, 0, X0):
1020 case OE_RRR(MULA_LU_LU, 9, Y0):
1021 gen_mul_half(tdest, tsrca, tsrcb, LU, LU);
1022 tcg_gen_add_tl(tdest, tdest, load_gr(dc, dest));
1023 mnemonic = "mula_lu_lu";
1024 break;
1025 case OE_RRR(MULX, 0, X0):
1026 case OE_RRR(MULX, 3, Y0):
1027 tcg_gen_mul_tl(tdest, tsrca, tsrcb);
1028 tcg_gen_ext32s_tl(tdest, tdest);
1029 mnemonic = "mulx";
1030 break;
1031 case OE_RRR(MUL_HS_HS, 0, X0):
1032 case OE_RRR(MUL_HS_HS, 8, Y0):
1033 gen_mul_half(tdest, tsrca, tsrcb, HS, HS);
1034 mnemonic = "mul_hs_hs";
1035 break;
1036 case OE_RRR(MUL_HS_HU, 0, X0):
1037 gen_mul_half(tdest, tsrca, tsrcb, HS, HU);
1038 mnemonic = "mul_hs_hu";
1039 break;
1040 case OE_RRR(MUL_HS_LS, 0, X0):
1041 gen_mul_half(tdest, tsrca, tsrcb, HS, LS);
1042 mnemonic = "mul_hs_ls";
1043 break;
1044 case OE_RRR(MUL_HS_LU, 0, X0):
1045 gen_mul_half(tdest, tsrca, tsrcb, HS, LU);
1046 mnemonic = "mul_hs_lu";
1047 break;
1048 case OE_RRR(MUL_HU_HU, 0, X0):
1049 case OE_RRR(MUL_HU_HU, 8, Y0):
1050 gen_mul_half(tdest, tsrca, tsrcb, HU, HU);
1051 mnemonic = "mul_hu_hu";
1052 break;
1053 case OE_RRR(MUL_HU_LS, 0, X0):
1054 gen_mul_half(tdest, tsrca, tsrcb, HU, LS);
1055 mnemonic = "mul_hu_ls";
1056 break;
1057 case OE_RRR(MUL_HU_LU, 0, X0):
1058 gen_mul_half(tdest, tsrca, tsrcb, HU, LU);
1059 mnemonic = "mul_hu_lu";
1060 break;
1061 case OE_RRR(MUL_LS_LS, 0, X0):
1062 case OE_RRR(MUL_LS_LS, 8, Y0):
1063 gen_mul_half(tdest, tsrca, tsrcb, LS, LS);
1064 mnemonic = "mul_ls_ls";
1065 break;
1066 case OE_RRR(MUL_LS_LU, 0, X0):
1067 gen_mul_half(tdest, tsrca, tsrcb, LS, LU);
1068 mnemonic = "mul_ls_lu";
1069 break;
1070 case OE_RRR(MUL_LU_LU, 0, X0):
1071 case OE_RRR(MUL_LU_LU, 8, Y0):
1072 gen_mul_half(tdest, tsrca, tsrcb, LU, LU);
1073 mnemonic = "mul_lu_lu";
1074 break;
1075 case OE_RRR(MZ, 0, X0):
1076 case OE_RRR(MZ, 0, X1):
1077 case OE_RRR(MZ, 4, Y0):
1078 case OE_RRR(MZ, 4, Y1):
1079 t0 = load_zero(dc);
1080 tcg_gen_movcond_tl(TCG_COND_EQ, tdest, tsrca, t0, tsrcb, t0);
1081 mnemonic = "mz";
1082 break;
1083 case OE_RRR(NOR, 0, X0):
1084 case OE_RRR(NOR, 0, X1):
1085 case OE_RRR(NOR, 5, Y0):
1086 case OE_RRR(NOR, 5, Y1):
1087 tcg_gen_nor_tl(tdest, tsrca, tsrcb);
1088 mnemonic = "nor";
1089 break;
1090 case OE_RRR(OR, 0, X0):
1091 case OE_RRR(OR, 0, X1):
1092 case OE_RRR(OR, 5, Y0):
1093 case OE_RRR(OR, 5, Y1):
1094 tcg_gen_or_tl(tdest, tsrca, tsrcb);
1095 mnemonic = "or";
1096 break;
1097 case OE_RRR(ROTL, 0, X0):
1098 case OE_RRR(ROTL, 0, X1):
1099 case OE_RRR(ROTL, 6, Y0):
1100 case OE_RRR(ROTL, 6, Y1):
1101 tcg_gen_andi_tl(tdest, tsrcb, 63);
1102 tcg_gen_rotl_tl(tdest, tsrca, tdest);
1103 mnemonic = "rotl";
1104 break;
1105 case OE_RRR(SHL1ADDX, 0, X0):
1106 case OE_RRR(SHL1ADDX, 0, X1):
1107 case OE_RRR(SHL1ADDX, 7, Y0):
1108 case OE_RRR(SHL1ADDX, 7, Y1):
1109 tcg_gen_shli_tl(tdest, tsrca, 1);
1110 tcg_gen_add_tl(tdest, tdest, tsrcb);
1111 tcg_gen_ext32s_tl(tdest, tdest);
1112 mnemonic = "shl1addx";
1113 break;
1114 case OE_RRR(SHL1ADD, 0, X0):
1115 case OE_RRR(SHL1ADD, 0, X1):
1116 case OE_RRR(SHL1ADD, 1, Y0):
1117 case OE_RRR(SHL1ADD, 1, Y1):
1118 tcg_gen_shli_tl(tdest, tsrca, 1);
1119 tcg_gen_add_tl(tdest, tdest, tsrcb);
1120 mnemonic = "shl1add";
1121 break;
1122 case OE_RRR(SHL2ADDX, 0, X0):
1123 case OE_RRR(SHL2ADDX, 0, X1):
1124 case OE_RRR(SHL2ADDX, 7, Y0):
1125 case OE_RRR(SHL2ADDX, 7, Y1):
1126 tcg_gen_shli_tl(tdest, tsrca, 2);
1127 tcg_gen_add_tl(tdest, tdest, tsrcb);
1128 tcg_gen_ext32s_tl(tdest, tdest);
1129 mnemonic = "shl2addx";
1130 break;
1131 case OE_RRR(SHL2ADD, 0, X0):
1132 case OE_RRR(SHL2ADD, 0, X1):
1133 case OE_RRR(SHL2ADD, 1, Y0):
1134 case OE_RRR(SHL2ADD, 1, Y1):
1135 tcg_gen_shli_tl(tdest, tsrca, 2);
1136 tcg_gen_add_tl(tdest, tdest, tsrcb);
1137 mnemonic = "shl2add";
1138 break;
1139 case OE_RRR(SHL3ADDX, 0, X0):
1140 case OE_RRR(SHL3ADDX, 0, X1):
1141 case OE_RRR(SHL3ADDX, 7, Y0):
1142 case OE_RRR(SHL3ADDX, 7, Y1):
1143 tcg_gen_shli_tl(tdest, tsrca, 3);
1144 tcg_gen_add_tl(tdest, tdest, tsrcb);
1145 tcg_gen_ext32s_tl(tdest, tdest);
1146 mnemonic = "shl3addx";
1147 break;
1148 case OE_RRR(SHL3ADD, 0, X0):
1149 case OE_RRR(SHL3ADD, 0, X1):
1150 case OE_RRR(SHL3ADD, 1, Y0):
1151 case OE_RRR(SHL3ADD, 1, Y1):
1152 tcg_gen_shli_tl(tdest, tsrca, 3);
1153 tcg_gen_add_tl(tdest, tdest, tsrcb);
1154 mnemonic = "shl3add";
1155 break;
1156 case OE_RRR(SHLX, 0, X0):
1157 case OE_RRR(SHLX, 0, X1):
1158 tcg_gen_andi_tl(tdest, tsrcb, 31);
1159 tcg_gen_shl_tl(tdest, tsrca, tdest);
1160 tcg_gen_ext32s_tl(tdest, tdest);
1161 mnemonic = "shlx";
1162 break;
1163 case OE_RRR(SHL, 0, X0):
1164 case OE_RRR(SHL, 0, X1):
1165 case OE_RRR(SHL, 6, Y0):
1166 case OE_RRR(SHL, 6, Y1):
1167 tcg_gen_andi_tl(tdest, tsrcb, 63);
1168 tcg_gen_shl_tl(tdest, tsrca, tdest);
1169 mnemonic = "shl";
1170 break;
1171 case OE_RRR(SHRS, 0, X0):
1172 case OE_RRR(SHRS, 0, X1):
1173 case OE_RRR(SHRS, 6, Y0):
1174 case OE_RRR(SHRS, 6, Y1):
1175 tcg_gen_andi_tl(tdest, tsrcb, 63);
1176 tcg_gen_sar_tl(tdest, tsrca, tdest);
1177 mnemonic = "shrs";
1178 break;
1179 case OE_RRR(SHRUX, 0, X0):
1180 case OE_RRR(SHRUX, 0, X1):
1181 t0 = tcg_temp_new();
1182 tcg_gen_andi_tl(t0, tsrcb, 31);
1183 tcg_gen_ext32u_tl(tdest, tsrca);
1184 tcg_gen_shr_tl(tdest, tdest, t0);
1185 tcg_gen_ext32s_tl(tdest, tdest);
1186 tcg_temp_free(t0);
1187 mnemonic = "shrux";
1188 break;
1189 case OE_RRR(SHRU, 0, X0):
1190 case OE_RRR(SHRU, 0, X1):
1191 case OE_RRR(SHRU, 6, Y0):
1192 case OE_RRR(SHRU, 6, Y1):
1193 tcg_gen_andi_tl(tdest, tsrcb, 63);
1194 tcg_gen_shr_tl(tdest, tsrca, tdest);
1195 mnemonic = "shru";
1196 break;
1197 case OE_RRR(SHUFFLEBYTES, 0, X0):
1198 gen_helper_shufflebytes(tdest, load_gr(dc, dest), tsrca, tsrca);
1199 mnemonic = "shufflebytes";
1200 break;
1201 case OE_RRR(SUBXSC, 0, X0):
1202 case OE_RRR(SUBXSC, 0, X1):
1203 gen_saturate_op(tdest, tsrca, tsrcb, tcg_gen_sub_tl);
1204 mnemonic = "subxsc";
1205 break;
1206 case OE_RRR(SUBX, 0, X0):
1207 case OE_RRR(SUBX, 0, X1):
1208 case OE_RRR(SUBX, 0, Y0):
1209 case OE_RRR(SUBX, 0, Y1):
1210 tcg_gen_sub_tl(tdest, tsrca, tsrcb);
1211 tcg_gen_ext32s_tl(tdest, tdest);
1212 mnemonic = "subx";
1213 break;
1214 case OE_RRR(SUB, 0, X0):
1215 case OE_RRR(SUB, 0, X1):
1216 case OE_RRR(SUB, 0, Y0):
1217 case OE_RRR(SUB, 0, Y1):
1218 tcg_gen_sub_tl(tdest, tsrca, tsrcb);
1219 mnemonic = "sub";
1220 break;
1221 case OE_RRR(V1ADDUC, 0, X0):
1222 case OE_RRR(V1ADDUC, 0, X1):
1223 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1224 case OE_RRR(V1ADD, 0, X0):
1225 case OE_RRR(V1ADD, 0, X1):
1226 gen_v12add(tdest, tsrca, tsrcb, V1_IMM(0x80));
1227 mnemonic = "v1add";
1228 break;
1229 case OE_RRR(V1ADIFFU, 0, X0):
1230 case OE_RRR(V1AVGU, 0, X0):
1231 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1232 case OE_RRR(V1CMPEQ, 0, X0):
1233 case OE_RRR(V1CMPEQ, 0, X1):
1234 tcg_gen_xor_tl(tdest, tsrca, tsrcb);
1235 gen_v1cmpeq0(tdest);
1236 mnemonic = "v1cmpeq";
1237 break;
1238 case OE_RRR(V1CMPLES, 0, X0):
1239 case OE_RRR(V1CMPLES, 0, X1):
1240 case OE_RRR(V1CMPLEU, 0, X0):
1241 case OE_RRR(V1CMPLEU, 0, X1):
1242 case OE_RRR(V1CMPLTS, 0, X0):
1243 case OE_RRR(V1CMPLTS, 0, X1):
1244 case OE_RRR(V1CMPLTU, 0, X0):
1245 case OE_RRR(V1CMPLTU, 0, X1):
1246 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1247 case OE_RRR(V1CMPNE, 0, X0):
1248 case OE_RRR(V1CMPNE, 0, X1):
1249 tcg_gen_xor_tl(tdest, tsrca, tsrcb);
1250 gen_v1cmpne0(tdest);
1251 mnemonic = "v1cmpne";
1252 break;
1253 case OE_RRR(V1DDOTPUA, 0, X0):
1254 case OE_RRR(V1DDOTPUSA, 0, X0):
1255 case OE_RRR(V1DDOTPUS, 0, X0):
1256 case OE_RRR(V1DDOTPU, 0, X0):
1257 case OE_RRR(V1DOTPA, 0, X0):
1258 case OE_RRR(V1DOTPUA, 0, X0):
1259 case OE_RRR(V1DOTPUSA, 0, X0):
1260 case OE_RRR(V1DOTPUS, 0, X0):
1261 case OE_RRR(V1DOTPU, 0, X0):
1262 case OE_RRR(V1DOTP, 0, X0):
1263 case OE_RRR(V1INT_H, 0, X0):
1264 case OE_RRR(V1INT_H, 0, X1):
1265 case OE_RRR(V1INT_L, 0, X0):
1266 case OE_RRR(V1INT_L, 0, X1):
1267 case OE_RRR(V1MAXU, 0, X0):
1268 case OE_RRR(V1MAXU, 0, X1):
1269 case OE_RRR(V1MINU, 0, X0):
1270 case OE_RRR(V1MINU, 0, X1):
1271 case OE_RRR(V1MNZ, 0, X0):
1272 case OE_RRR(V1MNZ, 0, X1):
1273 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1274 case OE_RRR(V1MULTU, 0, X0):
1275 gen_helper_v1multu(tdest, tsrca, tsrcb);
1276 mnemonic = "v1multu";
1277 break;
1278 case OE_RRR(V1MULUS, 0, X0):
1279 case OE_RRR(V1MULU, 0, X0):
1280 case OE_RRR(V1MZ, 0, X0):
1281 case OE_RRR(V1MZ, 0, X1):
1282 case OE_RRR(V1SADAU, 0, X0):
1283 case OE_RRR(V1SADU, 0, X0):
1284 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1285 case OE_RRR(V1SHL, 0, X0):
1286 case OE_RRR(V1SHL, 0, X1):
1287 gen_helper_v1shl(tdest, tsrca, tsrcb);
1288 mnemonic = "v1shl";
1289 break;
1290 case OE_RRR(V1SHRS, 0, X0):
1291 case OE_RRR(V1SHRS, 0, X1):
1292 gen_helper_v1shrs(tdest, tsrca, tsrcb);
1293 mnemonic = "v1shrs";
1294 break;
1295 case OE_RRR(V1SHRU, 0, X0):
1296 case OE_RRR(V1SHRU, 0, X1):
1297 gen_helper_v1shru(tdest, tsrca, tsrcb);
1298 mnemonic = "v1shru";
1299 break;
1300 case OE_RRR(V1SUBUC, 0, X0):
1301 case OE_RRR(V1SUBUC, 0, X1):
1302 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1303 case OE_RRR(V1SUB, 0, X0):
1304 case OE_RRR(V1SUB, 0, X1):
1305 gen_v12sub(tdest, tsrca, tsrcb, V1_IMM(0x80));
1306 mnemonic = "v1sub";
1307 break;
1308 case OE_RRR(V2ADDSC, 0, X0):
1309 case OE_RRR(V2ADDSC, 0, X1):
1310 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1311 case OE_RRR(V2ADD, 0, X0):
1312 case OE_RRR(V2ADD, 0, X1):
1313 gen_v12add(tdest, tsrca, tsrcb, V2_IMM(0x8000));
1314 mnemonic = "v2add";
1315 break;
1316 case OE_RRR(V2ADIFFS, 0, X0):
1317 case OE_RRR(V2AVGS, 0, X0):
1318 case OE_RRR(V2CMPEQ, 0, X0):
1319 case OE_RRR(V2CMPEQ, 0, X1):
1320 case OE_RRR(V2CMPLES, 0, X0):
1321 case OE_RRR(V2CMPLES, 0, X1):
1322 case OE_RRR(V2CMPLEU, 0, X0):
1323 case OE_RRR(V2CMPLEU, 0, X1):
1324 case OE_RRR(V2CMPLTS, 0, X0):
1325 case OE_RRR(V2CMPLTS, 0, X1):
1326 case OE_RRR(V2CMPLTU, 0, X0):
1327 case OE_RRR(V2CMPLTU, 0, X1):
1328 case OE_RRR(V2CMPNE, 0, X0):
1329 case OE_RRR(V2CMPNE, 0, X1):
1330 case OE_RRR(V2DOTPA, 0, X0):
1331 case OE_RRR(V2DOTP, 0, X0):
1332 case OE_RRR(V2INT_H, 0, X0):
1333 case OE_RRR(V2INT_H, 0, X1):
1334 case OE_RRR(V2INT_L, 0, X0):
1335 case OE_RRR(V2INT_L, 0, X1):
1336 case OE_RRR(V2MAXS, 0, X0):
1337 case OE_RRR(V2MAXS, 0, X1):
1338 case OE_RRR(V2MINS, 0, X0):
1339 case OE_RRR(V2MINS, 0, X1):
1340 case OE_RRR(V2MNZ, 0, X0):
1341 case OE_RRR(V2MNZ, 0, X1):
1342 case OE_RRR(V2MULFSC, 0, X0):
1343 case OE_RRR(V2MULS, 0, X0):
1344 case OE_RRR(V2MULTS, 0, X0):
1345 case OE_RRR(V2MZ, 0, X0):
1346 case OE_RRR(V2MZ, 0, X1):
1347 case OE_RRR(V2PACKH, 0, X0):
1348 case OE_RRR(V2PACKH, 0, X1):
1349 case OE_RRR(V2PACKL, 0, X0):
1350 case OE_RRR(V2PACKL, 0, X1):
1351 case OE_RRR(V2PACKUC, 0, X0):
1352 case OE_RRR(V2PACKUC, 0, X1):
1353 case OE_RRR(V2SADAS, 0, X0):
1354 case OE_RRR(V2SADAU, 0, X0):
1355 case OE_RRR(V2SADS, 0, X0):
1356 case OE_RRR(V2SADU, 0, X0):
1357 case OE_RRR(V2SHLSC, 0, X0):
1358 case OE_RRR(V2SHLSC, 0, X1):
1359 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1360 case OE_RRR(V2SHL, 0, X0):
1361 case OE_RRR(V2SHL, 0, X1):
1362 gen_helper_v2shl(tdest, tsrca, tsrcb);
1363 mnemonic = "v2shl";
1364 break;
1365 case OE_RRR(V2SHRS, 0, X0):
1366 case OE_RRR(V2SHRS, 0, X1):
1367 gen_helper_v2shrs(tdest, tsrca, tsrcb);
1368 mnemonic = "v2shrs";
1369 break;
1370 case OE_RRR(V2SHRU, 0, X0):
1371 case OE_RRR(V2SHRU, 0, X1):
1372 gen_helper_v2shru(tdest, tsrca, tsrcb);
1373 mnemonic = "v2shru";
1374 break;
1375 case OE_RRR(V2SUBSC, 0, X0):
1376 case OE_RRR(V2SUBSC, 0, X1):
1377 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1378 case OE_RRR(V2SUB, 0, X0):
1379 case OE_RRR(V2SUB, 0, X1):
1380 gen_v12sub(tdest, tsrca, tsrcb, V2_IMM(0x8000));
1381 mnemonic = "v2sub";
1382 break;
1383 case OE_RRR(V4ADDSC, 0, X0):
1384 case OE_RRR(V4ADDSC, 0, X1):
1385 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1386 case OE_RRR(V4ADD, 0, X0):
1387 case OE_RRR(V4ADD, 0, X1):
1388 gen_v4op(tdest, tsrca, tsrcb, tcg_gen_add_i32);
1389 mnemonic = "v4add";
1390 break;
1391 case OE_RRR(V4INT_H, 0, X0):
1392 case OE_RRR(V4INT_H, 0, X1):
1393 tcg_gen_shri_tl(tdest, tsrcb, 32);
1394 tcg_gen_deposit_tl(tdest, tsrca, tdest, 0, 32);
1395 mnemonic = "v4int_h";
1396 break;
1397 case OE_RRR(V4INT_L, 0, X0):
1398 case OE_RRR(V4INT_L, 0, X1):
1399 tcg_gen_deposit_tl(tdest, tsrcb, tsrca, 32, 32);
1400 mnemonic = "v4int_l";
1401 break;
1402 case OE_RRR(V4PACKSC, 0, X0):
1403 case OE_RRR(V4PACKSC, 0, X1):
1404 case OE_RRR(V4SHLSC, 0, X0):
1405 case OE_RRR(V4SHLSC, 0, X1):
1406 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1407 case OE_RRR(V4SHL, 0, X0):
1408 case OE_RRR(V4SHL, 0, X1):
1409 gen_v4sh(tdest, tsrca, tsrcb, tcg_gen_shl_i32);
1410 mnemonic = "v4shl";
1411 break;
1412 case OE_RRR(V4SHRS, 0, X0):
1413 case OE_RRR(V4SHRS, 0, X1):
1414 gen_v4sh(tdest, tsrca, tsrcb, tcg_gen_sar_i32);
1415 mnemonic = "v4shrs";
1416 break;
1417 case OE_RRR(V4SHRU, 0, X0):
1418 case OE_RRR(V4SHRU, 0, X1):
1419 gen_v4sh(tdest, tsrca, tsrcb, tcg_gen_shr_i32);
1420 mnemonic = "v4shru";
1421 break;
1422 case OE_RRR(V4SUBSC, 0, X0):
1423 case OE_RRR(V4SUBSC, 0, X1):
1424 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1425 case OE_RRR(V4SUB, 0, X0):
1426 case OE_RRR(V4SUB, 0, X1):
1427 gen_v4op(tdest, tsrca, tsrcb, tcg_gen_sub_i32);
1428 mnemonic = "v2sub";
1429 break;
1430 case OE_RRR(XOR, 0, X0):
1431 case OE_RRR(XOR, 0, X1):
1432 case OE_RRR(XOR, 5, Y0):
1433 case OE_RRR(XOR, 5, Y1):
1434 tcg_gen_xor_tl(tdest, tsrca, tsrcb);
1435 mnemonic = "xor";
1436 break;
1437 default:
1438 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1439 }
1440
1441 qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s, %s", mnemonic,
1442 reg_names[dest], reg_names[srca], reg_names[srcb]);
1443 return TILEGX_EXCP_NONE;
1444 }
1445
1446 static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext,
1447 unsigned dest, unsigned srca, int imm)
1448 {
1449 TCGv tdest = dest_gr(dc, dest);
1450 TCGv tsrca = load_gr(dc, srca);
1451 bool prefetch_nofault = false;
1452 const char *mnemonic;
1453 TCGMemOp memop;
1454 int i2, i3;
1455 TCGv t0;
1456
1457 switch (opext) {
1458 case OE(ADDI_OPCODE_Y0, 0, Y0):
1459 case OE(ADDI_OPCODE_Y1, 0, Y1):
1460 case OE_IM(ADDI, X0):
1461 case OE_IM(ADDI, X1):
1462 tcg_gen_addi_tl(tdest, tsrca, imm);
1463 mnemonic = "addi";
1464 break;
1465 case OE(ADDXI_OPCODE_Y0, 0, Y0):
1466 case OE(ADDXI_OPCODE_Y1, 0, Y1):
1467 case OE_IM(ADDXI, X0):
1468 case OE_IM(ADDXI, X1):
1469 tcg_gen_addi_tl(tdest, tsrca, imm);
1470 tcg_gen_ext32s_tl(tdest, tdest);
1471 mnemonic = "addxi";
1472 break;
1473 case OE(ANDI_OPCODE_Y0, 0, Y0):
1474 case OE(ANDI_OPCODE_Y1, 0, Y1):
1475 case OE_IM(ANDI, X0):
1476 case OE_IM(ANDI, X1):
1477 tcg_gen_andi_tl(tdest, tsrca, imm);
1478 mnemonic = "andi";
1479 break;
1480 case OE(CMPEQI_OPCODE_Y0, 0, Y0):
1481 case OE(CMPEQI_OPCODE_Y1, 0, Y1):
1482 case OE_IM(CMPEQI, X0):
1483 case OE_IM(CMPEQI, X1):
1484 tcg_gen_setcondi_tl(TCG_COND_EQ, tdest, tsrca, imm);
1485 mnemonic = "cmpeqi";
1486 break;
1487 case OE(CMPLTSI_OPCODE_Y0, 0, Y0):
1488 case OE(CMPLTSI_OPCODE_Y1, 0, Y1):
1489 case OE_IM(CMPLTSI, X0):
1490 case OE_IM(CMPLTSI, X1):
1491 tcg_gen_setcondi_tl(TCG_COND_LT, tdest, tsrca, imm);
1492 mnemonic = "cmpltsi";
1493 break;
1494 case OE_IM(CMPLTUI, X0):
1495 case OE_IM(CMPLTUI, X1):
1496 tcg_gen_setcondi_tl(TCG_COND_LTU, tdest, tsrca, imm);
1497 mnemonic = "cmpltui";
1498 break;
1499 case OE_IM(LD1S_ADD, X1):
1500 memop = MO_SB;
1501 mnemonic = "ld1s_add"; /* prefetch_add_l1_fault */
1502 goto do_load_add;
1503 case OE_IM(LD1U_ADD, X1):
1504 memop = MO_UB;
1505 mnemonic = "ld1u_add"; /* prefetch_add_l1 */
1506 prefetch_nofault = (dest == TILEGX_R_ZERO);
1507 goto do_load_add;
1508 case OE_IM(LD2S_ADD, X1):
1509 memop = MO_TESW;
1510 mnemonic = "ld2s_add"; /* prefetch_add_l2_fault */
1511 goto do_load_add;
1512 case OE_IM(LD2U_ADD, X1):
1513 memop = MO_TEUW;
1514 mnemonic = "ld2u_add"; /* prefetch_add_l2 */
1515 prefetch_nofault = (dest == TILEGX_R_ZERO);
1516 goto do_load_add;
1517 case OE_IM(LD4S_ADD, X1):
1518 memop = MO_TESL;
1519 mnemonic = "ld4s_add"; /* prefetch_add_l3_fault */
1520 goto do_load_add;
1521 case OE_IM(LD4U_ADD, X1):
1522 memop = MO_TEUL;
1523 mnemonic = "ld4u_add"; /* prefetch_add_l3 */
1524 prefetch_nofault = (dest == TILEGX_R_ZERO);
1525 goto do_load_add;
1526 case OE_IM(LDNT1S_ADD, X1):
1527 memop = MO_SB;
1528 mnemonic = "ldnt1s_add";
1529 goto do_load_add;
1530 case OE_IM(LDNT1U_ADD, X1):
1531 memop = MO_UB;
1532 mnemonic = "ldnt1u_add";
1533 goto do_load_add;
1534 case OE_IM(LDNT2S_ADD, X1):
1535 memop = MO_TESW;
1536 mnemonic = "ldnt2s_add";
1537 goto do_load_add;
1538 case OE_IM(LDNT2U_ADD, X1):
1539 memop = MO_TEUW;
1540 mnemonic = "ldnt2u_add";
1541 goto do_load_add;
1542 case OE_IM(LDNT4S_ADD, X1):
1543 memop = MO_TESL;
1544 mnemonic = "ldnt4s_add";
1545 goto do_load_add;
1546 case OE_IM(LDNT4U_ADD, X1):
1547 memop = MO_TEUL;
1548 mnemonic = "ldnt4u_add";
1549 goto do_load_add;
1550 case OE_IM(LDNT_ADD, X1):
1551 memop = MO_TEQ;
1552 mnemonic = "ldnt_add";
1553 goto do_load_add;
1554 case OE_IM(LD_ADD, X1):
1555 memop = MO_TEQ;
1556 mnemonic = "ld_add";
1557 do_load_add:
1558 if (!prefetch_nofault) {
1559 tcg_gen_qemu_ld_tl(tdest, tsrca, dc->mmuidx, memop);
1560 }
1561 tcg_gen_addi_tl(dest_gr(dc, srca), tsrca, imm);
1562 break;
1563 case OE_IM(LDNA_ADD, X1):
1564 tcg_gen_andi_tl(tdest, tsrca, ~7);
1565 tcg_gen_qemu_ld_tl(tdest, tdest, dc->mmuidx, MO_TEQ);
1566 tcg_gen_addi_tl(dest_gr(dc, srca), tsrca, imm);
1567 mnemonic = "ldna_add";
1568 break;
1569 case OE_IM(ORI, X0):
1570 case OE_IM(ORI, X1):
1571 tcg_gen_ori_tl(tdest, tsrca, imm);
1572 mnemonic = "ori";
1573 break;
1574 case OE_IM(V1ADDI, X0):
1575 case OE_IM(V1ADDI, X1):
1576 t0 = tcg_const_tl(V1_IMM(imm));
1577 gen_v12add(tdest, tsrca, t0, V1_IMM(0x80));
1578 tcg_temp_free(t0);
1579 mnemonic = "v1addi";
1580 break;
1581 case OE_IM(V1CMPEQI, X0):
1582 case OE_IM(V1CMPEQI, X1):
1583 tcg_gen_xori_tl(tdest, tsrca, V1_IMM(imm));
1584 gen_v1cmpeq0(tdest);
1585 mnemonic = "v1cmpeqi";
1586 break;
1587 case OE_IM(V1CMPLTSI, X0):
1588 case OE_IM(V1CMPLTSI, X1):
1589 case OE_IM(V1CMPLTUI, X0):
1590 case OE_IM(V1CMPLTUI, X1):
1591 case OE_IM(V1MAXUI, X0):
1592 case OE_IM(V1MAXUI, X1):
1593 case OE_IM(V1MINUI, X0):
1594 case OE_IM(V1MINUI, X1):
1595 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1596 case OE_IM(V2ADDI, X0):
1597 case OE_IM(V2ADDI, X1):
1598 t0 = tcg_const_tl(V2_IMM(imm));
1599 gen_v12add(tdest, tsrca, t0, V2_IMM(0x8000));
1600 tcg_temp_free(t0);
1601 mnemonic = "v2addi";
1602 break;
1603 case OE_IM(V2CMPEQI, X0):
1604 case OE_IM(V2CMPEQI, X1):
1605 case OE_IM(V2CMPLTSI, X0):
1606 case OE_IM(V2CMPLTSI, X1):
1607 case OE_IM(V2CMPLTUI, X0):
1608 case OE_IM(V2CMPLTUI, X1):
1609 case OE_IM(V2MAXSI, X0):
1610 case OE_IM(V2MAXSI, X1):
1611 case OE_IM(V2MINSI, X0):
1612 case OE_IM(V2MINSI, X1):
1613 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1614 case OE_IM(XORI, X0):
1615 case OE_IM(XORI, X1):
1616 tcg_gen_xori_tl(tdest, tsrca, imm);
1617 mnemonic = "xori";
1618 break;
1619
1620 case OE_SH(ROTLI, X0):
1621 case OE_SH(ROTLI, X1):
1622 case OE_SH(ROTLI, Y0):
1623 case OE_SH(ROTLI, Y1):
1624 tcg_gen_rotli_tl(tdest, tsrca, imm);
1625 mnemonic = "rotli";
1626 break;
1627 case OE_SH(SHLI, X0):
1628 case OE_SH(SHLI, X1):
1629 case OE_SH(SHLI, Y0):
1630 case OE_SH(SHLI, Y1):
1631 tcg_gen_shli_tl(tdest, tsrca, imm);
1632 mnemonic = "shli";
1633 break;
1634 case OE_SH(SHLXI, X0):
1635 case OE_SH(SHLXI, X1):
1636 tcg_gen_shli_tl(tdest, tsrca, imm & 31);
1637 tcg_gen_ext32s_tl(tdest, tdest);
1638 mnemonic = "shlxi";
1639 break;
1640 case OE_SH(SHRSI, X0):
1641 case OE_SH(SHRSI, X1):
1642 case OE_SH(SHRSI, Y0):
1643 case OE_SH(SHRSI, Y1):
1644 tcg_gen_sari_tl(tdest, tsrca, imm);
1645 mnemonic = "shrsi";
1646 break;
1647 case OE_SH(SHRUI, X0):
1648 case OE_SH(SHRUI, X1):
1649 case OE_SH(SHRUI, Y0):
1650 case OE_SH(SHRUI, Y1):
1651 tcg_gen_shri_tl(tdest, tsrca, imm);
1652 mnemonic = "shrui";
1653 break;
1654 case OE_SH(SHRUXI, X0):
1655 case OE_SH(SHRUXI, X1):
1656 if ((imm & 31) == 0) {
1657 tcg_gen_ext32s_tl(tdest, tsrca);
1658 } else {
1659 tcg_gen_ext32u_tl(tdest, tsrca);
1660 tcg_gen_shri_tl(tdest, tdest, imm & 31);
1661 }
1662 mnemonic = "shlxi";
1663 break;
1664 case OE_SH(V1SHLI, X0):
1665 case OE_SH(V1SHLI, X1):
1666 i2 = imm & 7;
1667 i3 = 0xff >> i2;
1668 tcg_gen_andi_tl(tdest, tsrca, V1_IMM(i3));
1669 tcg_gen_shli_tl(tdest, tdest, i2);
1670 mnemonic = "v1shli";
1671 break;
1672 case OE_SH(V1SHRSI, X0):
1673 case OE_SH(V1SHRSI, X1):
1674 t0 = tcg_const_tl(imm & 7);
1675 gen_helper_v1shrs(tdest, tsrca, t0);
1676 tcg_temp_free(t0);
1677 mnemonic = "v1shrsi";
1678 break;
1679 case OE_SH(V1SHRUI, X0):
1680 case OE_SH(V1SHRUI, X1):
1681 i2 = imm & 7;
1682 i3 = (0xff << i2) & 0xff;
1683 tcg_gen_andi_tl(tdest, tsrca, V1_IMM(i3));
1684 tcg_gen_shri_tl(tdest, tdest, i2);
1685 mnemonic = "v1shrui";
1686 break;
1687 case OE_SH(V2SHLI, X0):
1688 case OE_SH(V2SHLI, X1):
1689 case OE_SH(V2SHRSI, X0):
1690 case OE_SH(V2SHRSI, X1):
1691 case OE_SH(V2SHRUI, X0):
1692 case OE_SH(V2SHRUI, X1):
1693 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1694
1695 case OE(ADDLI_OPCODE_X0, 0, X0):
1696 case OE(ADDLI_OPCODE_X1, 0, X1):
1697 tcg_gen_addi_tl(tdest, tsrca, imm);
1698 mnemonic = "addli";
1699 break;
1700 case OE(ADDXLI_OPCODE_X0, 0, X0):
1701 case OE(ADDXLI_OPCODE_X1, 0, X1):
1702 tcg_gen_addi_tl(tdest, tsrca, imm);
1703 tcg_gen_ext32s_tl(tdest, tdest);
1704 mnemonic = "addxli";
1705 break;
1706 case OE(SHL16INSLI_OPCODE_X0, 0, X0):
1707 case OE(SHL16INSLI_OPCODE_X1, 0, X1):
1708 tcg_gen_shli_tl(tdest, tsrca, 16);
1709 tcg_gen_ori_tl(tdest, tdest, imm & 0xffff);
1710 mnemonic = "shl16insli";
1711 break;
1712
1713 default:
1714 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1715 }
1716
1717 qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s, %d", mnemonic,
1718 reg_names[dest], reg_names[srca], imm);
1719 return TILEGX_EXCP_NONE;
1720 }
1721
1722 static TileExcp gen_bf_opcode_x0(DisasContext *dc, unsigned ext,
1723 unsigned dest, unsigned srca,
1724 unsigned bfs, unsigned bfe)
1725 {
1726 TCGv tdest = dest_gr(dc, dest);
1727 TCGv tsrca = load_gr(dc, srca);
1728 TCGv tsrcd;
1729 int len;
1730 const char *mnemonic;
1731
1732 /* The bitfield is either between E and S inclusive,
1733 or up from S and down from E inclusive. */
1734 if (bfs <= bfe) {
1735 len = bfe - bfs + 1;
1736 } else {
1737 len = (64 - bfs) + (bfe + 1);
1738 }
1739
1740 switch (ext) {
1741 case BFEXTU_BF_OPCODE_X0:
1742 if (bfs == 0 && bfe == 7) {
1743 tcg_gen_ext8u_tl(tdest, tsrca);
1744 } else if (bfs == 0 && bfe == 15) {
1745 tcg_gen_ext16u_tl(tdest, tsrca);
1746 } else if (bfs == 0 && bfe == 31) {
1747 tcg_gen_ext32u_tl(tdest, tsrca);
1748 } else {
1749 int rol = 63 - bfe;
1750 if (bfs <= bfe) {
1751 tcg_gen_shli_tl(tdest, tsrca, rol);
1752 } else {
1753 tcg_gen_rotli_tl(tdest, tsrca, rol);
1754 }
1755 tcg_gen_shri_tl(tdest, tdest, (bfs + rol) & 63);
1756 }
1757 mnemonic = "bfextu";
1758 break;
1759
1760 case BFEXTS_BF_OPCODE_X0:
1761 if (bfs == 0 && bfe == 7) {
1762 tcg_gen_ext8s_tl(tdest, tsrca);
1763 } else if (bfs == 0 && bfe == 15) {
1764 tcg_gen_ext16s_tl(tdest, tsrca);
1765 } else if (bfs == 0 && bfe == 31) {
1766 tcg_gen_ext32s_tl(tdest, tsrca);
1767 } else {
1768 int rol = 63 - bfe;
1769 if (bfs <= bfe) {
1770 tcg_gen_shli_tl(tdest, tsrca, rol);
1771 } else {
1772 tcg_gen_rotli_tl(tdest, tsrca, rol);
1773 }
1774 tcg_gen_sari_tl(tdest, tdest, (bfs + rol) & 63);
1775 }
1776 mnemonic = "bfexts";
1777 break;
1778
1779 case BFINS_BF_OPCODE_X0:
1780 tsrcd = load_gr(dc, dest);
1781 if (bfs <= bfe) {
1782 tcg_gen_deposit_tl(tdest, tsrcd, tsrca, bfs, len);
1783 } else {
1784 tcg_gen_rotri_tl(tdest, tsrcd, bfs);
1785 tcg_gen_deposit_tl(tdest, tdest, tsrca, 0, len);
1786 tcg_gen_rotli_tl(tdest, tdest, bfs);
1787 }
1788 mnemonic = "bfins";
1789 break;
1790
1791 case MM_BF_OPCODE_X0:
1792 tsrcd = load_gr(dc, dest);
1793 if (bfs == 0) {
1794 tcg_gen_deposit_tl(tdest, tsrca, tsrcd, 0, len);
1795 } else {
1796 uint64_t mask = len == 64 ? -1 : rol64((1ULL << len) - 1, bfs);
1797 TCGv tmp = tcg_const_tl(mask);
1798
1799 tcg_gen_and_tl(tdest, tsrcd, tmp);
1800 tcg_gen_andc_tl(tmp, tsrca, tmp);
1801 tcg_gen_or_tl(tdest, tdest, tmp);
1802 tcg_temp_free(tmp);
1803 }
1804 mnemonic = "mm";
1805 break;
1806
1807 default:
1808 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1809 }
1810
1811 qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s, %u, %u", mnemonic,
1812 reg_names[dest], reg_names[srca], bfs, bfe);
1813 return TILEGX_EXCP_NONE;
1814 }
1815
1816 static TileExcp gen_branch_opcode_x1(DisasContext *dc, unsigned ext,
1817 unsigned srca, int off)
1818 {
1819 target_ulong tgt = dc->pc + off * TILEGX_BUNDLE_SIZE_IN_BYTES;
1820 const char *mnemonic;
1821
1822 dc->jmp.dest = tcg_const_tl(tgt);
1823 dc->jmp.val1 = tcg_temp_new();
1824 tcg_gen_mov_tl(dc->jmp.val1, load_gr(dc, srca));
1825
1826 /* Note that the "predict taken" opcodes have bit 0 clear.
1827 Therefore, fold the two cases together by setting bit 0. */
1828 switch (ext | 1) {
1829 case BEQZ_BRANCH_OPCODE_X1:
1830 dc->jmp.cond = TCG_COND_EQ;
1831 mnemonic = "beqz";
1832 break;
1833 case BNEZ_BRANCH_OPCODE_X1:
1834 dc->jmp.cond = TCG_COND_NE;
1835 mnemonic = "bnez";
1836 break;
1837 case BGEZ_BRANCH_OPCODE_X1:
1838 dc->jmp.cond = TCG_COND_GE;
1839 mnemonic = "bgez";
1840 break;
1841 case BGTZ_BRANCH_OPCODE_X1:
1842 dc->jmp.cond = TCG_COND_GT;
1843 mnemonic = "bgtz";
1844 break;
1845 case BLEZ_BRANCH_OPCODE_X1:
1846 dc->jmp.cond = TCG_COND_LE;
1847 mnemonic = "blez";
1848 break;
1849 case BLTZ_BRANCH_OPCODE_X1:
1850 dc->jmp.cond = TCG_COND_LT;
1851 mnemonic = "bltz";
1852 break;
1853 case BLBC_BRANCH_OPCODE_X1:
1854 dc->jmp.cond = TCG_COND_EQ;
1855 tcg_gen_andi_tl(dc->jmp.val1, dc->jmp.val1, 1);
1856 mnemonic = "blbc";
1857 break;
1858 case BLBS_BRANCH_OPCODE_X1:
1859 dc->jmp.cond = TCG_COND_NE;
1860 tcg_gen_andi_tl(dc->jmp.val1, dc->jmp.val1, 1);
1861 mnemonic = "blbs";
1862 break;
1863 default:
1864 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1865 }
1866
1867 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1868 qemu_log("%s%s %s, " TARGET_FMT_lx " <%s>",
1869 mnemonic, ext & 1 ? "" : "t",
1870 reg_names[srca], tgt, lookup_symbol(tgt));
1871 }
1872 return TILEGX_EXCP_NONE;
1873 }
1874
1875 static TileExcp gen_jump_opcode_x1(DisasContext *dc, unsigned ext, int off)
1876 {
1877 target_ulong tgt = dc->pc + off * TILEGX_BUNDLE_SIZE_IN_BYTES;
1878 const char *mnemonic = "j";
1879
1880 /* The extension field is 1 bit, therefore we only have JAL and J. */
1881 if (ext == JAL_JUMP_OPCODE_X1) {
1882 tcg_gen_movi_tl(dest_gr(dc, TILEGX_R_LR),
1883 dc->pc + TILEGX_BUNDLE_SIZE_IN_BYTES);
1884 mnemonic = "jal";
1885 }
1886 dc->jmp.cond = TCG_COND_ALWAYS;
1887 dc->jmp.dest = tcg_const_tl(tgt);
1888
1889 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1890 qemu_log("%s " TARGET_FMT_lx " <%s>",
1891 mnemonic, tgt, lookup_symbol(tgt));
1892 }
1893 return TILEGX_EXCP_NONE;
1894 }
1895
1896 typedef struct {
1897 const char *name;
1898 intptr_t offset;
1899 void (*get)(TCGv, TCGv_ptr);
1900 void (*put)(TCGv_ptr, TCGv);
1901 } TileSPR;
1902
1903 static const TileSPR *find_spr(unsigned spr)
1904 {
1905 /* Allow the compiler to construct the binary search tree. */
1906 #define D(N, O, G, P) \
1907 case SPR_##N: { static const TileSPR x = { #N, O, G, P }; return &x; }
1908
1909 switch (spr) {
1910 D(CMPEXCH_VALUE,
1911 offsetof(CPUTLGState, spregs[TILEGX_SPR_CMPEXCH]), 0, 0)
1912 D(INTERRUPT_CRITICAL_SECTION,
1913 offsetof(CPUTLGState, spregs[TILEGX_SPR_CRITICAL_SEC]), 0, 0)
1914 D(SIM_CONTROL,
1915 offsetof(CPUTLGState, spregs[TILEGX_SPR_SIM_CONTROL]), 0, 0)
1916 }
1917
1918 #undef D
1919
1920 qemu_log_mask(LOG_UNIMP, "UNIMP SPR %u\n", spr);
1921 return NULL;
1922 }
1923
1924 static TileExcp gen_mtspr_x1(DisasContext *dc, unsigned spr, unsigned srca)
1925 {
1926 const TileSPR *def = find_spr(spr);
1927 TCGv tsrca;
1928
1929 if (def == NULL) {
1930 qemu_log_mask(CPU_LOG_TB_IN_ASM, "mtspr spr[%u], %s", spr, reg_names[srca]);
1931 return TILEGX_EXCP_OPCODE_UNKNOWN;
1932 }
1933
1934 tsrca = load_gr(dc, srca);
1935 if (def->put) {
1936 def->put(cpu_env, tsrca);
1937 } else {
1938 tcg_gen_st_tl(tsrca, cpu_env, def->offset);
1939 }
1940 qemu_log_mask(CPU_LOG_TB_IN_ASM, "mtspr %s, %s", def->name, reg_names[srca]);
1941 return TILEGX_EXCP_NONE;
1942 }
1943
1944 static TileExcp gen_mfspr_x1(DisasContext *dc, unsigned dest, unsigned spr)
1945 {
1946 const TileSPR *def = find_spr(spr);
1947 TCGv tdest;
1948
1949 if (def == NULL) {
1950 qemu_log_mask(CPU_LOG_TB_IN_ASM, "mtspr %s, spr[%u]", reg_names[dest], spr);
1951 return TILEGX_EXCP_OPCODE_UNKNOWN;
1952 }
1953
1954 tdest = dest_gr(dc, dest);
1955 if (def->get) {
1956 def->get(tdest, cpu_env);
1957 } else {
1958 tcg_gen_ld_tl(tdest, cpu_env, def->offset);
1959 }
1960 qemu_log_mask(CPU_LOG_TB_IN_ASM, "mfspr %s, %s", reg_names[dest], def->name);
1961 return TILEGX_EXCP_NONE;
1962 }
1963
1964 static TileExcp decode_y0(DisasContext *dc, tilegx_bundle_bits bundle)
1965 {
1966 unsigned opc = get_Opcode_Y0(bundle);
1967 unsigned ext = get_RRROpcodeExtension_Y0(bundle);
1968 unsigned dest = get_Dest_Y0(bundle);
1969 unsigned srca = get_SrcA_Y0(bundle);
1970 unsigned srcb;
1971 int imm;
1972
1973 switch (opc) {
1974 case RRR_1_OPCODE_Y0:
1975 if (ext == UNARY_RRR_1_OPCODE_Y0) {
1976 ext = get_UnaryOpcodeExtension_Y0(bundle);
1977 return gen_rr_opcode(dc, OE(opc, ext, Y0), dest, srca, bundle);
1978 }
1979 /* fallthru */
1980 case RRR_0_OPCODE_Y0:
1981 case RRR_2_OPCODE_Y0:
1982 case RRR_3_OPCODE_Y0:
1983 case RRR_4_OPCODE_Y0:
1984 case RRR_5_OPCODE_Y0:
1985 case RRR_6_OPCODE_Y0:
1986 case RRR_7_OPCODE_Y0:
1987 case RRR_8_OPCODE_Y0:
1988 case RRR_9_OPCODE_Y0:
1989 srcb = get_SrcB_Y0(bundle);
1990 return gen_rrr_opcode(dc, OE(opc, ext, Y0), dest, srca, srcb);
1991
1992 case SHIFT_OPCODE_Y0:
1993 ext = get_ShiftOpcodeExtension_Y0(bundle);
1994 imm = get_ShAmt_Y0(bundle);
1995 return gen_rri_opcode(dc, OE(opc, ext, Y0), dest, srca, imm);
1996
1997 case ADDI_OPCODE_Y0:
1998 case ADDXI_OPCODE_Y0:
1999 case ANDI_OPCODE_Y0:
2000 case CMPEQI_OPCODE_Y0:
2001 case CMPLTSI_OPCODE_Y0:
2002 imm = (int8_t)get_Imm8_Y0(bundle);
2003 return gen_rri_opcode(dc, OE(opc, 0, Y0), dest, srca, imm);
2004
2005 default:
2006 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
2007 }
2008 }
2009
2010 static TileExcp decode_y1(DisasContext *dc, tilegx_bundle_bits bundle)
2011 {
2012 unsigned opc = get_Opcode_Y1(bundle);
2013 unsigned ext = get_RRROpcodeExtension_Y1(bundle);
2014 unsigned dest = get_Dest_Y1(bundle);
2015 unsigned srca = get_SrcA_Y1(bundle);
2016 unsigned srcb;
2017 int imm;
2018
2019 switch (get_Opcode_Y1(bundle)) {
2020 case RRR_1_OPCODE_Y1:
2021 if (ext == UNARY_RRR_1_OPCODE_Y0) {
2022 ext = get_UnaryOpcodeExtension_Y1(bundle);
2023 return gen_rr_opcode(dc, OE(opc, ext, Y1), dest, srca, bundle);
2024 }
2025 /* fallthru */
2026 case RRR_0_OPCODE_Y1:
2027 case RRR_2_OPCODE_Y1:
2028 case RRR_3_OPCODE_Y1:
2029 case RRR_4_OPCODE_Y1:
2030 case RRR_5_OPCODE_Y1:
2031 case RRR_6_OPCODE_Y1:
2032 case RRR_7_OPCODE_Y1:
2033 srcb = get_SrcB_Y1(bundle);
2034 return gen_rrr_opcode(dc, OE(opc, ext, Y1), dest, srca, srcb);
2035
2036 case SHIFT_OPCODE_Y1:
2037 ext = get_ShiftOpcodeExtension_Y1(bundle);
2038 imm = get_ShAmt_Y1(bundle);
2039 return gen_rri_opcode(dc, OE(opc, ext, Y1), dest, srca, imm);
2040
2041 case ADDI_OPCODE_Y1:
2042 case ADDXI_OPCODE_Y1:
2043 case ANDI_OPCODE_Y1:
2044 case CMPEQI_OPCODE_Y1:
2045 case CMPLTSI_OPCODE_Y1:
2046 imm = (int8_t)get_Imm8_Y1(bundle);
2047 return gen_rri_opcode(dc, OE(opc, 0, Y1), dest, srca, imm);
2048
2049 default:
2050 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
2051 }
2052 }
2053
2054 static TileExcp decode_y2(DisasContext *dc, tilegx_bundle_bits bundle)
2055 {
2056 unsigned mode = get_Mode(bundle);
2057 unsigned opc = get_Opcode_Y2(bundle);
2058 unsigned srca = get_SrcA_Y2(bundle);
2059 unsigned srcbdest = get_SrcBDest_Y2(bundle);
2060 const char *mnemonic;
2061 TCGMemOp memop;
2062
2063 switch (OEY2(opc, mode)) {
2064 case OEY2(LD1S_OPCODE_Y2, MODE_OPCODE_YA2):
2065 memop = MO_SB;
2066 mnemonic = "ld1s";
2067 goto do_load;
2068 case OEY2(LD1U_OPCODE_Y2, MODE_OPCODE_YA2):
2069 memop = MO_UB;
2070 mnemonic = "ld1u";
2071 goto do_load;
2072 case OEY2(LD2S_OPCODE_Y2, MODE_OPCODE_YA2):
2073 memop = MO_TESW;
2074 mnemonic = "ld2s";
2075 goto do_load;
2076 case OEY2(LD2U_OPCODE_Y2, MODE_OPCODE_YA2):
2077 memop = MO_TEUW;
2078 mnemonic = "ld2u";
2079 goto do_load;
2080 case OEY2(LD4S_OPCODE_Y2, MODE_OPCODE_YB2):
2081 memop = MO_TESL;
2082 mnemonic = "ld4s";
2083 goto do_load;
2084 case OEY2(LD4U_OPCODE_Y2, MODE_OPCODE_YB2):
2085 memop = MO_TEUL;
2086 mnemonic = "ld4u";
2087 goto do_load;
2088 case OEY2(LD_OPCODE_Y2, MODE_OPCODE_YB2):
2089 memop = MO_TEQ;
2090 mnemonic = "ld";
2091 do_load:
2092 tcg_gen_qemu_ld_tl(dest_gr(dc, srcbdest), load_gr(dc, srca),
2093 dc->mmuidx, memop);
2094 qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s", mnemonic,
2095 reg_names[srcbdest], reg_names[srca]);
2096 return TILEGX_EXCP_NONE;
2097
2098 case OEY2(ST1_OPCODE_Y2, MODE_OPCODE_YC2):
2099 return gen_st_opcode(dc, 0, srca, srcbdest, MO_UB, "st1");
2100 case OEY2(ST2_OPCODE_Y2, MODE_OPCODE_YC2):
2101 return gen_st_opcode(dc, 0, srca, srcbdest, MO_TEUW, "st2");
2102 case OEY2(ST4_OPCODE_Y2, MODE_OPCODE_YC2):
2103 return gen_st_opcode(dc, 0, srca, srcbdest, MO_TEUL, "st4");
2104 case OEY2(ST_OPCODE_Y2, MODE_OPCODE_YC2):
2105 return gen_st_opcode(dc, 0, srca, srcbdest, MO_TEQ, "st");
2106
2107 default:
2108 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
2109 }
2110 }
2111
2112 static TileExcp decode_x0(DisasContext *dc, tilegx_bundle_bits bundle)
2113 {
2114 unsigned opc = get_Opcode_X0(bundle);
2115 unsigned dest = get_Dest_X0(bundle);
2116 unsigned srca = get_SrcA_X0(bundle);
2117 unsigned ext, srcb, bfs, bfe;
2118 int imm;
2119
2120 switch (opc) {
2121 case RRR_0_OPCODE_X0:
2122 ext = get_RRROpcodeExtension_X0(bundle);
2123 if (ext == UNARY_RRR_0_OPCODE_X0) {
2124 ext = get_UnaryOpcodeExtension_X0(bundle);
2125 return gen_rr_opcode(dc, OE(opc, ext, X0), dest, srca, bundle);
2126 }
2127 srcb = get_SrcB_X0(bundle);
2128 return gen_rrr_opcode(dc, OE(opc, ext, X0), dest, srca, srcb);
2129
2130 case SHIFT_OPCODE_X0:
2131 ext = get_ShiftOpcodeExtension_X0(bundle);
2132 imm = get_ShAmt_X0(bundle);
2133 return gen_rri_opcode(dc, OE(opc, ext, X0), dest, srca, imm);
2134
2135 case IMM8_OPCODE_X0:
2136 ext = get_Imm8OpcodeExtension_X0(bundle);
2137 imm = (int8_t)get_Imm8_X0(bundle);
2138 return gen_rri_opcode(dc, OE(opc, ext, X0), dest, srca, imm);
2139
2140 case BF_OPCODE_X0:
2141 ext = get_BFOpcodeExtension_X0(bundle);
2142 bfs = get_BFStart_X0(bundle);
2143 bfe = get_BFEnd_X0(bundle);
2144 return gen_bf_opcode_x0(dc, ext, dest, srca, bfs, bfe);
2145
2146 case ADDLI_OPCODE_X0:
2147 case SHL16INSLI_OPCODE_X0:
2148 case ADDXLI_OPCODE_X0:
2149 imm = (int16_t)get_Imm16_X0(bundle);
2150 return gen_rri_opcode(dc, OE(opc, 0, X0), dest, srca, imm);
2151
2152 default:
2153 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
2154 }
2155 }
2156
2157 static TileExcp decode_x1(DisasContext *dc, tilegx_bundle_bits bundle)
2158 {
2159 unsigned opc = get_Opcode_X1(bundle);
2160 unsigned dest = get_Dest_X1(bundle);
2161 unsigned srca = get_SrcA_X1(bundle);
2162 unsigned ext, srcb;
2163 int imm;
2164
2165 switch (opc) {
2166 case RRR_0_OPCODE_X1:
2167 ext = get_RRROpcodeExtension_X1(bundle);
2168 srcb = get_SrcB_X1(bundle);
2169 switch (ext) {
2170 case UNARY_RRR_0_OPCODE_X1:
2171 ext = get_UnaryOpcodeExtension_X1(bundle);
2172 return gen_rr_opcode(dc, OE(opc, ext, X1), dest, srca, bundle);
2173 case ST1_RRR_0_OPCODE_X1:
2174 return gen_st_opcode(dc, dest, srca, srcb, MO_UB, "st1");
2175 case ST2_RRR_0_OPCODE_X1:
2176 return gen_st_opcode(dc, dest, srca, srcb, MO_TEUW, "st2");
2177 case ST4_RRR_0_OPCODE_X1:
2178 return gen_st_opcode(dc, dest, srca, srcb, MO_TEUL, "st4");
2179 case STNT1_RRR_0_OPCODE_X1:
2180 return gen_st_opcode(dc, dest, srca, srcb, MO_UB, "stnt1");
2181 case STNT2_RRR_0_OPCODE_X1:
2182 return gen_st_opcode(dc, dest, srca, srcb, MO_TEUW, "stnt2");
2183 case STNT4_RRR_0_OPCODE_X1:
2184 return gen_st_opcode(dc, dest, srca, srcb, MO_TEUL, "stnt4");
2185 case STNT_RRR_0_OPCODE_X1:
2186 return gen_st_opcode(dc, dest, srca, srcb, MO_TEQ, "stnt");
2187 case ST_RRR_0_OPCODE_X1:
2188 return gen_st_opcode(dc, dest, srca, srcb, MO_TEQ, "st");
2189 }
2190 return gen_rrr_opcode(dc, OE(opc, ext, X1), dest, srca, srcb);
2191
2192 case SHIFT_OPCODE_X1:
2193 ext = get_ShiftOpcodeExtension_X1(bundle);
2194 imm = get_ShAmt_X1(bundle);
2195 return gen_rri_opcode(dc, OE(opc, ext, X1), dest, srca, imm);
2196
2197 case IMM8_OPCODE_X1:
2198 ext = get_Imm8OpcodeExtension_X1(bundle);
2199 imm = (int8_t)get_Dest_Imm8_X1(bundle);
2200 srcb = get_SrcB_X1(bundle);
2201 switch (ext) {
2202 case ST1_ADD_IMM8_OPCODE_X1:
2203 return gen_st_add_opcode(dc, srca, srcb, imm, MO_UB, "st1_add");
2204 case ST2_ADD_IMM8_OPCODE_X1:
2205 return gen_st_add_opcode(dc, srca, srcb, imm, MO_TEUW, "st2_add");
2206 case ST4_ADD_IMM8_OPCODE_X1:
2207 return gen_st_add_opcode(dc, srca, srcb, imm, MO_TEUL, "st4_add");
2208 case STNT1_ADD_IMM8_OPCODE_X1:
2209 return gen_st_add_opcode(dc, srca, srcb, imm, MO_UB, "stnt1_add");
2210 case STNT2_ADD_IMM8_OPCODE_X1:
2211 return gen_st_add_opcode(dc, srca, srcb, imm, MO_TEUW, "stnt2_add");
2212 case STNT4_ADD_IMM8_OPCODE_X1:
2213 return gen_st_add_opcode(dc, srca, srcb, imm, MO_TEUL, "stnt4_add");
2214 case STNT_ADD_IMM8_OPCODE_X1:
2215 return gen_st_add_opcode(dc, srca, srcb, imm, MO_TEQ, "stnt_add");
2216 case ST_ADD_IMM8_OPCODE_X1:
2217 return gen_st_add_opcode(dc, srca, srcb, imm, MO_TEQ, "st_add");
2218 case MFSPR_IMM8_OPCODE_X1:
2219 return gen_mfspr_x1(dc, dest, get_MF_Imm14_X1(bundle));
2220 case MTSPR_IMM8_OPCODE_X1:
2221 return gen_mtspr_x1(dc, get_MT_Imm14_X1(bundle), srca);
2222 }
2223 imm = (int8_t)get_Imm8_X1(bundle);
2224 return gen_rri_opcode(dc, OE(opc, ext, X1), dest, srca, imm);
2225
2226 case BRANCH_OPCODE_X1:
2227 ext = get_BrType_X1(bundle);
2228 imm = sextract32(get_BrOff_X1(bundle), 0, 17);
2229 return gen_branch_opcode_x1(dc, ext, srca, imm);
2230
2231 case JUMP_OPCODE_X1:
2232 ext = get_JumpOpcodeExtension_X1(bundle);
2233 imm = sextract32(get_JumpOff_X1(bundle), 0, 27);
2234 return gen_jump_opcode_x1(dc, ext, imm);
2235
2236 case ADDLI_OPCODE_X1:
2237 case SHL16INSLI_OPCODE_X1:
2238 case ADDXLI_OPCODE_X1:
2239 imm = (int16_t)get_Imm16_X1(bundle);
2240 return gen_rri_opcode(dc, OE(opc, 0, X1), dest, srca, imm);
2241
2242 default:
2243 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
2244 }
2245 }
2246
2247 static void notice_excp(DisasContext *dc, uint64_t bundle,
2248 const char *type, TileExcp excp)
2249 {
2250 if (likely(excp == TILEGX_EXCP_NONE)) {
2251 return;
2252 }
2253 gen_exception(dc, excp);
2254 if (excp == TILEGX_EXCP_OPCODE_UNIMPLEMENTED) {
2255 qemu_log_mask(LOG_UNIMP, "UNIMP %s, [" FMT64X "]\n", type, bundle);
2256 }
2257 }
2258
2259 static void translate_one_bundle(DisasContext *dc, uint64_t bundle)
2260 {
2261 int i;
2262
2263 for (i = 0; i < ARRAY_SIZE(dc->wb); i++) {
2264 DisasContextTemp *wb = &dc->wb[i];
2265 wb->reg = TILEGX_R_NOREG;
2266 TCGV_UNUSED_I64(wb->val);
2267 }
2268 dc->num_wb = 0;
2269
2270 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
2271 tcg_gen_debug_insn_start(dc->pc);
2272 }
2273
2274 qemu_log_mask(CPU_LOG_TB_IN_ASM, " %" PRIx64 ": { ", dc->pc);
2275 if (get_Mode(bundle)) {
2276 notice_excp(dc, bundle, "y0", decode_y0(dc, bundle));
2277 qemu_log_mask(CPU_LOG_TB_IN_ASM, " ; ");
2278 notice_excp(dc, bundle, "y1", decode_y1(dc, bundle));
2279 qemu_log_mask(CPU_LOG_TB_IN_ASM, " ; ");
2280 notice_excp(dc, bundle, "y2", decode_y2(dc, bundle));
2281 } else {
2282 notice_excp(dc, bundle, "x0", decode_x0(dc, bundle));
2283 qemu_log_mask(CPU_LOG_TB_IN_ASM, " ; ");
2284 notice_excp(dc, bundle, "x1", decode_x1(dc, bundle));
2285 }
2286 qemu_log_mask(CPU_LOG_TB_IN_ASM, " }\n");
2287
2288 for (i = dc->num_wb - 1; i >= 0; --i) {
2289 DisasContextTemp *wb = &dc->wb[i];
2290 if (wb->reg < TILEGX_R_COUNT) {
2291 tcg_gen_mov_i64(cpu_regs[wb->reg], wb->val);
2292 }
2293 tcg_temp_free_i64(wb->val);
2294 }
2295
2296 if (dc->jmp.cond != TCG_COND_NEVER) {
2297 if (dc->jmp.cond == TCG_COND_ALWAYS) {
2298 tcg_gen_mov_i64(cpu_pc, dc->jmp.dest);
2299 } else {
2300 TCGv next = tcg_const_i64(dc->pc + TILEGX_BUNDLE_SIZE_IN_BYTES);
2301 tcg_gen_movcond_i64(dc->jmp.cond, cpu_pc,
2302 dc->jmp.val1, load_zero(dc),
2303 dc->jmp.dest, next);
2304 tcg_temp_free_i64(dc->jmp.val1);
2305 tcg_temp_free_i64(next);
2306 }
2307 tcg_temp_free_i64(dc->jmp.dest);
2308 tcg_gen_exit_tb(0);
2309 dc->exit_tb = true;
2310 } else if (dc->atomic_excp != TILEGX_EXCP_NONE) {
2311 gen_exception(dc, dc->atomic_excp);
2312 }
2313 }
2314
2315 static inline void gen_intermediate_code_internal(TileGXCPU *cpu,
2316 TranslationBlock *tb,
2317 bool search_pc)
2318 {
2319 DisasContext ctx;
2320 DisasContext *dc = &ctx;
2321 CPUState *cs = CPU(cpu);
2322 CPUTLGState *env = &cpu->env;
2323 uint64_t pc_start = tb->pc;
2324 uint64_t next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
2325 int j, lj = -1;
2326 int num_insns = 0;
2327 int max_insns = tb->cflags & CF_COUNT_MASK;
2328
2329 dc->pc = pc_start;
2330 dc->mmuidx = 0;
2331 dc->exit_tb = false;
2332 dc->atomic_excp = TILEGX_EXCP_NONE;
2333 dc->jmp.cond = TCG_COND_NEVER;
2334 TCGV_UNUSED_I64(dc->jmp.dest);
2335 TCGV_UNUSED_I64(dc->jmp.val1);
2336 TCGV_UNUSED_I64(dc->zero);
2337
2338 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
2339 qemu_log("IN: %s\n", lookup_symbol(pc_start));
2340 }
2341 if (!max_insns) {
2342 max_insns = CF_COUNT_MASK;
2343 }
2344 if (cs->singlestep_enabled || singlestep) {
2345 max_insns = 1;
2346 }
2347 gen_tb_start(tb);
2348
2349 while (1) {
2350 if (search_pc) {
2351 j = tcg_op_buf_count();
2352 if (lj < j) {
2353 lj++;
2354 while (lj < j) {
2355 tcg_ctx.gen_opc_instr_start[lj++] = 0;
2356 }
2357 }
2358 tcg_ctx.gen_opc_pc[lj] = dc->pc;
2359 tcg_ctx.gen_opc_instr_start[lj] = 1;
2360 tcg_ctx.gen_opc_icount[lj] = num_insns;
2361 }
2362 translate_one_bundle(dc, cpu_ldq_data(env, dc->pc));
2363
2364 if (dc->exit_tb) {
2365 /* PC updated and EXIT_TB/GOTO_TB/exception emitted. */
2366 break;
2367 }
2368 dc->pc += TILEGX_BUNDLE_SIZE_IN_BYTES;
2369 if (++num_insns >= max_insns
2370 || dc->pc >= next_page_start
2371 || tcg_op_buf_full()) {
2372 /* Ending the TB due to TB size or page boundary. Set PC. */
2373 tcg_gen_movi_tl(cpu_pc, dc->pc);
2374 tcg_gen_exit_tb(0);
2375 break;
2376 }
2377 }
2378
2379 gen_tb_end(tb, num_insns);
2380 if (search_pc) {
2381 j = tcg_op_buf_count();
2382 lj++;
2383 while (lj <= j) {
2384 tcg_ctx.gen_opc_instr_start[lj++] = 0;
2385 }
2386 } else {
2387 tb->size = dc->pc - pc_start;
2388 tb->icount = num_insns;
2389 }
2390
2391 qemu_log_mask(CPU_LOG_TB_IN_ASM, "\n");
2392 }
2393
2394 void gen_intermediate_code(CPUTLGState *env, struct TranslationBlock *tb)
2395 {
2396 gen_intermediate_code_internal(tilegx_env_get_cpu(env), tb, false);
2397 }
2398
2399 void gen_intermediate_code_pc(CPUTLGState *env, struct TranslationBlock *tb)
2400 {
2401 gen_intermediate_code_internal(tilegx_env_get_cpu(env), tb, true);
2402 }
2403
2404 void restore_state_to_opc(CPUTLGState *env, TranslationBlock *tb, int pc_pos)
2405 {
2406 env->pc = tcg_ctx.gen_opc_pc[pc_pos];
2407 }
2408
2409 void tilegx_tcg_init(void)
2410 {
2411 int i;
2412
2413 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
2414 cpu_pc = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUTLGState, pc), "pc");
2415 for (i = 0; i < TILEGX_R_COUNT; i++) {
2416 cpu_regs[i] = tcg_global_mem_new_i64(TCG_AREG0,
2417 offsetof(CPUTLGState, regs[i]),
2418 reg_names[i]);
2419 }
2420 }
QEmu