8 #include "qemu-common.h"
9 #include "host-utils.h"
10 #if !defined(CONFIG_USER_ONLY)
11 #include "hw/loader.h"
15 static uint32_t cortexa15_cp15_c0_c1
[8] = {
16 0x00001131, 0x00011011, 0x02010555, 0x00000000,
17 0x10201105, 0x20000000, 0x01240000, 0x02102211
20 static uint32_t cortexa15_cp15_c0_c2
[8] = {
21 0x02101110, 0x13112111, 0x21232041, 0x11112131, 0x10011142, 0, 0, 0
24 static uint32_t cortexa9_cp15_c0_c1
[8] =
25 { 0x1031, 0x11, 0x000, 0, 0x00100103, 0x20000000, 0x01230000, 0x00002111 };
27 static uint32_t cortexa9_cp15_c0_c2
[8] =
28 { 0x00101111, 0x13112111, 0x21232041, 0x11112131, 0x00111142, 0, 0, 0 };
30 static uint32_t cortexa8_cp15_c0_c1
[8] =
31 { 0x1031, 0x11, 0x400, 0, 0x31100003, 0x20000000, 0x01202000, 0x11 };
33 static uint32_t cortexa8_cp15_c0_c2
[8] =
34 { 0x00101111, 0x12112111, 0x21232031, 0x11112131, 0x00111142, 0, 0, 0 };
36 static uint32_t mpcore_cp15_c0_c1
[8] =
37 { 0x111, 0x1, 0, 0x2, 0x01100103, 0x10020302, 0x01222000, 0 };
39 static uint32_t mpcore_cp15_c0_c2
[8] =
40 { 0x00100011, 0x12002111, 0x11221011, 0x01102131, 0x141, 0, 0, 0 };
42 static uint32_t arm1136_cp15_c0_c1
[8] =
43 { 0x111, 0x1, 0x2, 0x3, 0x01130003, 0x10030302, 0x01222110, 0 };
45 static uint32_t arm1136_cp15_c0_c2
[8] =
46 { 0x00140011, 0x12002111, 0x11231111, 0x01102131, 0x141, 0, 0, 0 };
48 static uint32_t arm1176_cp15_c0_c1
[8] =
49 { 0x111, 0x11, 0x33, 0, 0x01130003, 0x10030302, 0x01222100, 0 };
51 static uint32_t arm1176_cp15_c0_c2
[8] =
52 { 0x0140011, 0x12002111, 0x11231121, 0x01102131, 0x01141, 0, 0, 0 };
54 static uint32_t cpu_arm_find_by_name(const char *name
);
56 static inline void set_feature(CPUARMState
*env
, int feature
)
58 env
->features
|= 1u << feature
;
61 static void cpu_reset_model_id(CPUARMState
*env
, uint32_t id
)
63 env
->cp15
.c0_cpuid
= id
;
65 case ARM_CPUID_ARM926
:
66 set_feature(env
, ARM_FEATURE_V5
);
67 set_feature(env
, ARM_FEATURE_VFP
);
68 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x41011090;
69 env
->cp15
.c0_cachetype
= 0x1dd20d2;
70 env
->cp15
.c1_sys
= 0x00090078;
72 case ARM_CPUID_ARM946
:
73 set_feature(env
, ARM_FEATURE_V5
);
74 set_feature(env
, ARM_FEATURE_MPU
);
75 env
->cp15
.c0_cachetype
= 0x0f004006;
76 env
->cp15
.c1_sys
= 0x00000078;
78 case ARM_CPUID_ARM1026
:
79 set_feature(env
, ARM_FEATURE_V5
);
80 set_feature(env
, ARM_FEATURE_VFP
);
81 set_feature(env
, ARM_FEATURE_AUXCR
);
82 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x410110a0;
83 env
->cp15
.c0_cachetype
= 0x1dd20d2;
84 env
->cp15
.c1_sys
= 0x00090078;
86 case ARM_CPUID_ARM1136
:
87 /* This is the 1136 r1, which is a v6K core */
88 set_feature(env
, ARM_FEATURE_V6K
);
90 case ARM_CPUID_ARM1136_R2
:
91 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
92 * older core than plain "arm1136". In particular this does not
93 * have the v6K features.
95 set_feature(env
, ARM_FEATURE_V6
);
96 set_feature(env
, ARM_FEATURE_VFP
);
97 /* These ID register values are correct for 1136 but may be wrong
98 * for 1136_r2 (in particular r0p2 does not actually implement most
99 * of the ID registers).
101 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x410120b4;
102 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = 0x11111111;
103 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = 0x00000000;
104 memcpy(env
->cp15
.c0_c1
, arm1136_cp15_c0_c1
, 8 * sizeof(uint32_t));
105 memcpy(env
->cp15
.c0_c2
, arm1136_cp15_c0_c2
, 8 * sizeof(uint32_t));
106 env
->cp15
.c0_cachetype
= 0x1dd20d2;
107 env
->cp15
.c1_sys
= 0x00050078;
109 case ARM_CPUID_ARM1176
:
110 set_feature(env
, ARM_FEATURE_V6K
);
111 set_feature(env
, ARM_FEATURE_VFP
);
112 set_feature(env
, ARM_FEATURE_VAPA
);
113 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x410120b5;
114 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = 0x11111111;
115 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = 0x00000000;
116 memcpy(env
->cp15
.c0_c1
, arm1176_cp15_c0_c1
, 8 * sizeof(uint32_t));
117 memcpy(env
->cp15
.c0_c2
, arm1176_cp15_c0_c2
, 8 * sizeof(uint32_t));
118 env
->cp15
.c0_cachetype
= 0x1dd20d2;
119 env
->cp15
.c1_sys
= 0x00050078;
121 case ARM_CPUID_ARM11MPCORE
:
122 set_feature(env
, ARM_FEATURE_V6K
);
123 set_feature(env
, ARM_FEATURE_VFP
);
124 set_feature(env
, ARM_FEATURE_VAPA
);
125 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x410120b4;
126 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = 0x11111111;
127 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = 0x00000000;
128 memcpy(env
->cp15
.c0_c1
, mpcore_cp15_c0_c1
, 8 * sizeof(uint32_t));
129 memcpy(env
->cp15
.c0_c2
, mpcore_cp15_c0_c2
, 8 * sizeof(uint32_t));
130 env
->cp15
.c0_cachetype
= 0x1dd20d2;
132 case ARM_CPUID_CORTEXA8
:
133 set_feature(env
, ARM_FEATURE_V7
);
134 set_feature(env
, ARM_FEATURE_VFP3
);
135 set_feature(env
, ARM_FEATURE_NEON
);
136 set_feature(env
, ARM_FEATURE_THUMB2EE
);
137 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x410330c0;
138 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = 0x11110222;
139 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = 0x00011100;
140 memcpy(env
->cp15
.c0_c1
, cortexa8_cp15_c0_c1
, 8 * sizeof(uint32_t));
141 memcpy(env
->cp15
.c0_c2
, cortexa8_cp15_c0_c2
, 8 * sizeof(uint32_t));
142 env
->cp15
.c0_cachetype
= 0x82048004;
143 env
->cp15
.c0_clid
= (1 << 27) | (2 << 24) | 3;
144 env
->cp15
.c0_ccsid
[0] = 0xe007e01a; /* 16k L1 dcache. */
145 env
->cp15
.c0_ccsid
[1] = 0x2007e01a; /* 16k L1 icache. */
146 env
->cp15
.c0_ccsid
[2] = 0xf0000000; /* No L2 icache. */
147 env
->cp15
.c1_sys
= 0x00c50078;
149 case ARM_CPUID_CORTEXA9
:
150 set_feature(env
, ARM_FEATURE_V7
);
151 set_feature(env
, ARM_FEATURE_VFP3
);
152 set_feature(env
, ARM_FEATURE_VFP_FP16
);
153 set_feature(env
, ARM_FEATURE_NEON
);
154 set_feature(env
, ARM_FEATURE_THUMB2EE
);
155 /* Note that A9 supports the MP extensions even for
156 * A9UP and single-core A9MP (which are both different
157 * and valid configurations; we don't model A9UP).
159 set_feature(env
, ARM_FEATURE_V7MP
);
160 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x41033090;
161 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = 0x11110222;
162 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = 0x01111111;
163 memcpy(env
->cp15
.c0_c1
, cortexa9_cp15_c0_c1
, 8 * sizeof(uint32_t));
164 memcpy(env
->cp15
.c0_c2
, cortexa9_cp15_c0_c2
, 8 * sizeof(uint32_t));
165 env
->cp15
.c0_cachetype
= 0x80038003;
166 env
->cp15
.c0_clid
= (1 << 27) | (1 << 24) | 3;
167 env
->cp15
.c0_ccsid
[0] = 0xe00fe015; /* 16k L1 dcache. */
168 env
->cp15
.c0_ccsid
[1] = 0x200fe015; /* 16k L1 icache. */
169 env
->cp15
.c1_sys
= 0x00c50078;
171 case ARM_CPUID_CORTEXA15
:
172 set_feature(env
, ARM_FEATURE_V7
);
173 set_feature(env
, ARM_FEATURE_VFP4
);
174 set_feature(env
, ARM_FEATURE_VFP_FP16
);
175 set_feature(env
, ARM_FEATURE_NEON
);
176 set_feature(env
, ARM_FEATURE_THUMB2EE
);
177 set_feature(env
, ARM_FEATURE_ARM_DIV
);
178 set_feature(env
, ARM_FEATURE_V7MP
);
179 set_feature(env
, ARM_FEATURE_GENERIC_TIMER
);
180 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x410430f0;
181 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = 0x10110222;
182 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = 0x11111111;
183 memcpy(env
->cp15
.c0_c1
, cortexa15_cp15_c0_c1
, 8 * sizeof(uint32_t));
184 memcpy(env
->cp15
.c0_c2
, cortexa15_cp15_c0_c2
, 8 * sizeof(uint32_t));
185 env
->cp15
.c0_cachetype
= 0x8444c004;
186 env
->cp15
.c0_clid
= 0x0a200023;
187 env
->cp15
.c0_ccsid
[0] = 0x701fe00a; /* 32K L1 dcache */
188 env
->cp15
.c0_ccsid
[1] = 0x201fe00a; /* 32K L1 icache */
189 env
->cp15
.c0_ccsid
[2] = 0x711fe07a; /* 4096K L2 unified cache */
190 env
->cp15
.c1_sys
= 0x00c50078;
192 case ARM_CPUID_CORTEXM3
:
193 set_feature(env
, ARM_FEATURE_V7
);
194 set_feature(env
, ARM_FEATURE_M
);
196 case ARM_CPUID_ANY
: /* For userspace emulation. */
197 set_feature(env
, ARM_FEATURE_V7
);
198 set_feature(env
, ARM_FEATURE_VFP4
);
199 set_feature(env
, ARM_FEATURE_VFP_FP16
);
200 set_feature(env
, ARM_FEATURE_NEON
);
201 set_feature(env
, ARM_FEATURE_THUMB2EE
);
202 set_feature(env
, ARM_FEATURE_ARM_DIV
);
203 set_feature(env
, ARM_FEATURE_V7MP
);
205 case ARM_CPUID_TI915T
:
206 case ARM_CPUID_TI925T
:
207 set_feature(env
, ARM_FEATURE_V4T
);
208 set_feature(env
, ARM_FEATURE_OMAPCP
);
209 env
->cp15
.c0_cpuid
= ARM_CPUID_TI925T
; /* Depends on wiring. */
210 env
->cp15
.c0_cachetype
= 0x5109149;
211 env
->cp15
.c1_sys
= 0x00000070;
212 env
->cp15
.c15_i_max
= 0x000;
213 env
->cp15
.c15_i_min
= 0xff0;
215 case ARM_CPUID_PXA250
:
216 case ARM_CPUID_PXA255
:
217 case ARM_CPUID_PXA260
:
218 case ARM_CPUID_PXA261
:
219 case ARM_CPUID_PXA262
:
220 set_feature(env
, ARM_FEATURE_V5
);
221 set_feature(env
, ARM_FEATURE_XSCALE
);
222 /* JTAG_ID is ((id << 28) | 0x09265013) */
223 env
->cp15
.c0_cachetype
= 0xd172172;
224 env
->cp15
.c1_sys
= 0x00000078;
226 case ARM_CPUID_PXA270_A0
:
227 case ARM_CPUID_PXA270_A1
:
228 case ARM_CPUID_PXA270_B0
:
229 case ARM_CPUID_PXA270_B1
:
230 case ARM_CPUID_PXA270_C0
:
231 case ARM_CPUID_PXA270_C5
:
232 set_feature(env
, ARM_FEATURE_V5
);
233 set_feature(env
, ARM_FEATURE_XSCALE
);
234 /* JTAG_ID is ((id << 28) | 0x09265013) */
235 set_feature(env
, ARM_FEATURE_IWMMXT
);
236 env
->iwmmxt
.cregs
[ARM_IWMMXT_wCID
] = 0x69051000 | 'Q';
237 env
->cp15
.c0_cachetype
= 0xd172172;
238 env
->cp15
.c1_sys
= 0x00000078;
240 case ARM_CPUID_SA1100
:
241 case ARM_CPUID_SA1110
:
242 set_feature(env
, ARM_FEATURE_STRONGARM
);
243 env
->cp15
.c1_sys
= 0x00000070;
246 cpu_abort(env
, "Bad CPU ID: %x\n", id
);
250 /* Some features automatically imply others: */
251 if (arm_feature(env
, ARM_FEATURE_V7
)) {
252 set_feature(env
, ARM_FEATURE_VAPA
);
253 set_feature(env
, ARM_FEATURE_THUMB2
);
254 if (!arm_feature(env
, ARM_FEATURE_M
)) {
255 set_feature(env
, ARM_FEATURE_V6K
);
257 set_feature(env
, ARM_FEATURE_V6
);
260 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
261 set_feature(env
, ARM_FEATURE_V6
);
263 if (arm_feature(env
, ARM_FEATURE_V6
)) {
264 set_feature(env
, ARM_FEATURE_V5
);
265 if (!arm_feature(env
, ARM_FEATURE_M
)) {
266 set_feature(env
, ARM_FEATURE_AUXCR
);
269 if (arm_feature(env
, ARM_FEATURE_V5
)) {
270 set_feature(env
, ARM_FEATURE_V4T
);
272 if (arm_feature(env
, ARM_FEATURE_M
)) {
273 set_feature(env
, ARM_FEATURE_THUMB_DIV
);
275 if (arm_feature(env
, ARM_FEATURE_ARM_DIV
)) {
276 set_feature(env
, ARM_FEATURE_THUMB_DIV
);
278 if (arm_feature(env
, ARM_FEATURE_VFP4
)) {
279 set_feature(env
, ARM_FEATURE_VFP3
);
281 if (arm_feature(env
, ARM_FEATURE_VFP3
)) {
282 set_feature(env
, ARM_FEATURE_VFP
);
286 void cpu_reset(CPUARMState
*env
)
291 if (qemu_loglevel_mask(CPU_LOG_RESET
)) {
292 qemu_log("CPU Reset (CPU %d)\n", env
->cpu_index
);
293 log_cpu_state(env
, 0);
296 id
= env
->cp15
.c0_cpuid
;
297 tmp
= env
->cp15
.c15_config_base_address
;
298 memset(env
, 0, offsetof(CPUARMState
, breakpoints
));
300 cpu_reset_model_id(env
, id
);
301 env
->cp15
.c15_config_base_address
= tmp
;
302 #if defined (CONFIG_USER_ONLY)
303 env
->uncached_cpsr
= ARM_CPU_MODE_USR
;
304 /* For user mode we must enable access to coprocessors */
305 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 1 << 30;
306 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
307 env
->cp15
.c15_cpar
= 3;
308 } else if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
309 env
->cp15
.c15_cpar
= 1;
312 /* SVC mode with interrupts disabled. */
313 env
->uncached_cpsr
= ARM_CPU_MODE_SVC
| CPSR_A
| CPSR_F
| CPSR_I
;
314 /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
315 clear at reset. Initial SP and PC are loaded from ROM. */
319 env
->uncached_cpsr
&= ~CPSR_I
;
322 /* We should really use ldl_phys here, in case the guest
323 modified flash and reset itself. However images
324 loaded via -kernel have not been copied yet, so load the
325 values directly from there. */
326 env
->regs
[13] = ldl_p(rom
);
329 env
->regs
[15] = pc
& ~1;
332 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 0;
333 env
->cp15
.c2_base_mask
= 0xffffc000u
;
334 /* v7 performance monitor control register: same implementor
335 * field as main ID register, and we implement no event counters.
337 env
->cp15
.c9_pmcr
= (id
& 0xff000000);
339 set_flush_to_zero(1, &env
->vfp
.standard_fp_status
);
340 set_flush_inputs_to_zero(1, &env
->vfp
.standard_fp_status
);
341 set_default_nan_mode(1, &env
->vfp
.standard_fp_status
);
342 set_float_detect_tininess(float_tininess_before_rounding
,
343 &env
->vfp
.fp_status
);
344 set_float_detect_tininess(float_tininess_before_rounding
,
345 &env
->vfp
.standard_fp_status
);
347 /* Reset is a state change for some CPUState fields which we
348 * bake assumptions about into translated code, so we need to
354 static int vfp_gdb_get_reg(CPUState
*env
, uint8_t *buf
, int reg
)
358 /* VFP data registers are always little-endian. */
359 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
361 stfq_le_p(buf
, env
->vfp
.regs
[reg
]);
364 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
365 /* Aliases for Q regs. */
368 stfq_le_p(buf
, env
->vfp
.regs
[(reg
- 32) * 2]);
369 stfq_le_p(buf
+ 8, env
->vfp
.regs
[(reg
- 32) * 2 + 1]);
373 switch (reg
- nregs
) {
374 case 0: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSID
]); return 4;
375 case 1: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSCR
]); return 4;
376 case 2: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPEXC
]); return 4;
381 static int vfp_gdb_set_reg(CPUState
*env
, uint8_t *buf
, int reg
)
385 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
387 env
->vfp
.regs
[reg
] = ldfq_le_p(buf
);
390 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
393 env
->vfp
.regs
[(reg
- 32) * 2] = ldfq_le_p(buf
);
394 env
->vfp
.regs
[(reg
- 32) * 2 + 1] = ldfq_le_p(buf
+ 8);
398 switch (reg
- nregs
) {
399 case 0: env
->vfp
.xregs
[ARM_VFP_FPSID
] = ldl_p(buf
); return 4;
400 case 1: env
->vfp
.xregs
[ARM_VFP_FPSCR
] = ldl_p(buf
); return 4;
401 case 2: env
->vfp
.xregs
[ARM_VFP_FPEXC
] = ldl_p(buf
) & (1 << 30); return 4;
406 CPUARMState
*cpu_arm_init(const char *cpu_model
)
410 static int inited
= 0;
412 id
= cpu_arm_find_by_name(cpu_model
);
415 env
= g_malloc0(sizeof(CPUARMState
));
417 if (tcg_enabled() && !inited
) {
419 arm_translate_init();
422 env
->cpu_model_str
= cpu_model
;
423 env
->cp15
.c0_cpuid
= id
;
425 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
426 gdb_register_coprocessor(env
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
427 51, "arm-neon.xml", 0);
428 } else if (arm_feature(env
, ARM_FEATURE_VFP3
)) {
429 gdb_register_coprocessor(env
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
430 35, "arm-vfp3.xml", 0);
431 } else if (arm_feature(env
, ARM_FEATURE_VFP
)) {
432 gdb_register_coprocessor(env
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
433 19, "arm-vfp.xml", 0);
444 static const struct arm_cpu_t arm_cpu_names
[] = {
445 { ARM_CPUID_ARM926
, "arm926"},
446 { ARM_CPUID_ARM946
, "arm946"},
447 { ARM_CPUID_ARM1026
, "arm1026"},
448 { ARM_CPUID_ARM1136
, "arm1136"},
449 { ARM_CPUID_ARM1136_R2
, "arm1136-r2"},
450 { ARM_CPUID_ARM1176
, "arm1176"},
451 { ARM_CPUID_ARM11MPCORE
, "arm11mpcore"},
452 { ARM_CPUID_CORTEXM3
, "cortex-m3"},
453 { ARM_CPUID_CORTEXA8
, "cortex-a8"},
454 { ARM_CPUID_CORTEXA9
, "cortex-a9"},
455 { ARM_CPUID_CORTEXA15
, "cortex-a15" },
456 { ARM_CPUID_TI925T
, "ti925t" },
457 { ARM_CPUID_PXA250
, "pxa250" },
458 { ARM_CPUID_SA1100
, "sa1100" },
459 { ARM_CPUID_SA1110
, "sa1110" },
460 { ARM_CPUID_PXA255
, "pxa255" },
461 { ARM_CPUID_PXA260
, "pxa260" },
462 { ARM_CPUID_PXA261
, "pxa261" },
463 { ARM_CPUID_PXA262
, "pxa262" },
464 { ARM_CPUID_PXA270
, "pxa270" },
465 { ARM_CPUID_PXA270_A0
, "pxa270-a0" },
466 { ARM_CPUID_PXA270_A1
, "pxa270-a1" },
467 { ARM_CPUID_PXA270_B0
, "pxa270-b0" },
468 { ARM_CPUID_PXA270_B1
, "pxa270-b1" },
469 { ARM_CPUID_PXA270_C0
, "pxa270-c0" },
470 { ARM_CPUID_PXA270_C5
, "pxa270-c5" },
471 { ARM_CPUID_ANY
, "any"},
475 void arm_cpu_list(FILE *f
, fprintf_function cpu_fprintf
)
479 (*cpu_fprintf
)(f
, "Available CPUs:\n");
480 for (i
= 0; arm_cpu_names
[i
].name
; i
++) {
481 (*cpu_fprintf
)(f
, " %s\n", arm_cpu_names
[i
].name
);
485 /* return 0 if not found */
486 static uint32_t cpu_arm_find_by_name(const char *name
)
492 for (i
= 0; arm_cpu_names
[i
].name
; i
++) {
493 if (strcmp(name
, arm_cpu_names
[i
].name
) == 0) {
494 id
= arm_cpu_names
[i
].id
;
501 void cpu_arm_close(CPUARMState
*env
)
506 static int bad_mode_switch(CPUState
*env
, int mode
)
508 /* Return true if it is not valid for us to switch to
509 * this CPU mode (ie all the UNPREDICTABLE cases in
510 * the ARM ARM CPSRWriteByInstr pseudocode).
513 case ARM_CPU_MODE_USR
:
514 case ARM_CPU_MODE_SYS
:
515 case ARM_CPU_MODE_SVC
:
516 case ARM_CPU_MODE_ABT
:
517 case ARM_CPU_MODE_UND
:
518 case ARM_CPU_MODE_IRQ
:
519 case ARM_CPU_MODE_FIQ
:
526 uint32_t cpsr_read(CPUARMState
*env
)
530 return env
->uncached_cpsr
| (env
->NF
& 0x80000000) | (ZF
<< 30) |
531 (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
532 | (env
->thumb
<< 5) | ((env
->condexec_bits
& 3) << 25)
533 | ((env
->condexec_bits
& 0xfc) << 8)
537 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
)
539 if (mask
& CPSR_NZCV
) {
540 env
->ZF
= (~val
) & CPSR_Z
;
542 env
->CF
= (val
>> 29) & 1;
543 env
->VF
= (val
<< 3) & 0x80000000;
546 env
->QF
= ((val
& CPSR_Q
) != 0);
548 env
->thumb
= ((val
& CPSR_T
) != 0);
549 if (mask
& CPSR_IT_0_1
) {
550 env
->condexec_bits
&= ~3;
551 env
->condexec_bits
|= (val
>> 25) & 3;
553 if (mask
& CPSR_IT_2_7
) {
554 env
->condexec_bits
&= 3;
555 env
->condexec_bits
|= (val
>> 8) & 0xfc;
557 if (mask
& CPSR_GE
) {
558 env
->GE
= (val
>> 16) & 0xf;
561 if ((env
->uncached_cpsr
^ val
) & mask
& CPSR_M
) {
562 if (bad_mode_switch(env
, val
& CPSR_M
)) {
563 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
564 * We choose to ignore the attempt and leave the CPSR M field
569 switch_mode(env
, val
& CPSR_M
);
572 mask
&= ~CACHED_CPSR_BITS
;
573 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~mask
) | (val
& mask
);
576 /* Sign/zero extend */
577 uint32_t HELPER(sxtb16
)(uint32_t x
)
580 res
= (uint16_t)(int8_t)x
;
581 res
|= (uint32_t)(int8_t)(x
>> 16) << 16;
585 uint32_t HELPER(uxtb16
)(uint32_t x
)
588 res
= (uint16_t)(uint8_t)x
;
589 res
|= (uint32_t)(uint8_t)(x
>> 16) << 16;
593 uint32_t HELPER(clz
)(uint32_t x
)
598 int32_t HELPER(sdiv
)(int32_t num
, int32_t den
)
602 if (num
== INT_MIN
&& den
== -1)
607 uint32_t HELPER(udiv
)(uint32_t num
, uint32_t den
)
614 uint32_t HELPER(rbit
)(uint32_t x
)
616 x
= ((x
& 0xff000000) >> 24)
617 | ((x
& 0x00ff0000) >> 8)
618 | ((x
& 0x0000ff00) << 8)
619 | ((x
& 0x000000ff) << 24);
620 x
= ((x
& 0xf0f0f0f0) >> 4)
621 | ((x
& 0x0f0f0f0f) << 4);
622 x
= ((x
& 0x88888888) >> 3)
623 | ((x
& 0x44444444) >> 1)
624 | ((x
& 0x22222222) << 1)
625 | ((x
& 0x11111111) << 3);
629 uint32_t HELPER(abs
)(uint32_t x
)
631 return ((int32_t)x
< 0) ? -x
: x
;
634 #if defined(CONFIG_USER_ONLY)
636 void do_interrupt (CPUState
*env
)
638 env
->exception_index
= -1;
641 int cpu_arm_handle_mmu_fault (CPUState
*env
, target_ulong address
, int rw
,
645 env
->exception_index
= EXCP_PREFETCH_ABORT
;
646 env
->cp15
.c6_insn
= address
;
648 env
->exception_index
= EXCP_DATA_ABORT
;
649 env
->cp15
.c6_data
= address
;
654 /* These should probably raise undefined insn exceptions. */
655 void HELPER(set_cp
)(CPUState
*env
, uint32_t insn
, uint32_t val
)
657 int op1
= (insn
>> 8) & 0xf;
658 cpu_abort(env
, "cp%i insn %08x\n", op1
, insn
);
662 uint32_t HELPER(get_cp
)(CPUState
*env
, uint32_t insn
)
664 int op1
= (insn
>> 8) & 0xf;
665 cpu_abort(env
, "cp%i insn %08x\n", op1
, insn
);
669 void HELPER(set_cp15
)(CPUState
*env
, uint32_t insn
, uint32_t val
)
671 cpu_abort(env
, "cp15 insn %08x\n", insn
);
674 uint32_t HELPER(get_cp15
)(CPUState
*env
, uint32_t insn
)
676 cpu_abort(env
, "cp15 insn %08x\n", insn
);
679 /* These should probably raise undefined insn exceptions. */
680 void HELPER(v7m_msr
)(CPUState
*env
, uint32_t reg
, uint32_t val
)
682 cpu_abort(env
, "v7m_mrs %d\n", reg
);
685 uint32_t HELPER(v7m_mrs
)(CPUState
*env
, uint32_t reg
)
687 cpu_abort(env
, "v7m_mrs %d\n", reg
);
691 void switch_mode(CPUState
*env
, int mode
)
693 if (mode
!= ARM_CPU_MODE_USR
)
694 cpu_abort(env
, "Tried to switch out of user mode\n");
697 void HELPER(set_r13_banked
)(CPUState
*env
, uint32_t mode
, uint32_t val
)
699 cpu_abort(env
, "banked r13 write\n");
702 uint32_t HELPER(get_r13_banked
)(CPUState
*env
, uint32_t mode
)
704 cpu_abort(env
, "banked r13 read\n");
710 /* Map CPU modes onto saved register banks. */
711 static inline int bank_number(CPUState
*env
, int mode
)
714 case ARM_CPU_MODE_USR
:
715 case ARM_CPU_MODE_SYS
:
717 case ARM_CPU_MODE_SVC
:
719 case ARM_CPU_MODE_ABT
:
721 case ARM_CPU_MODE_UND
:
723 case ARM_CPU_MODE_IRQ
:
725 case ARM_CPU_MODE_FIQ
:
728 cpu_abort(env
, "Bad mode %x\n", mode
);
732 void switch_mode(CPUState
*env
, int mode
)
737 old_mode
= env
->uncached_cpsr
& CPSR_M
;
738 if (mode
== old_mode
)
741 if (old_mode
== ARM_CPU_MODE_FIQ
) {
742 memcpy (env
->fiq_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
743 memcpy (env
->regs
+ 8, env
->usr_regs
, 5 * sizeof(uint32_t));
744 } else if (mode
== ARM_CPU_MODE_FIQ
) {
745 memcpy (env
->usr_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
746 memcpy (env
->regs
+ 8, env
->fiq_regs
, 5 * sizeof(uint32_t));
749 i
= bank_number(env
, old_mode
);
750 env
->banked_r13
[i
] = env
->regs
[13];
751 env
->banked_r14
[i
] = env
->regs
[14];
752 env
->banked_spsr
[i
] = env
->spsr
;
754 i
= bank_number(env
, mode
);
755 env
->regs
[13] = env
->banked_r13
[i
];
756 env
->regs
[14] = env
->banked_r14
[i
];
757 env
->spsr
= env
->banked_spsr
[i
];
760 static void v7m_push(CPUARMState
*env
, uint32_t val
)
763 stl_phys(env
->regs
[13], val
);
766 static uint32_t v7m_pop(CPUARMState
*env
)
769 val
= ldl_phys(env
->regs
[13]);
774 /* Switch to V7M main or process stack pointer. */
775 static void switch_v7m_sp(CPUARMState
*env
, int process
)
778 if (env
->v7m
.current_sp
!= process
) {
779 tmp
= env
->v7m
.other_sp
;
780 env
->v7m
.other_sp
= env
->regs
[13];
782 env
->v7m
.current_sp
= process
;
786 static void do_v7m_exception_exit(CPUARMState
*env
)
791 type
= env
->regs
[15];
792 if (env
->v7m
.exception
!= 0)
793 armv7m_nvic_complete_irq(env
->nvic
, env
->v7m
.exception
);
795 /* Switch to the target stack. */
796 switch_v7m_sp(env
, (type
& 4) != 0);
798 env
->regs
[0] = v7m_pop(env
);
799 env
->regs
[1] = v7m_pop(env
);
800 env
->regs
[2] = v7m_pop(env
);
801 env
->regs
[3] = v7m_pop(env
);
802 env
->regs
[12] = v7m_pop(env
);
803 env
->regs
[14] = v7m_pop(env
);
804 env
->regs
[15] = v7m_pop(env
);
806 xpsr_write(env
, xpsr
, 0xfffffdff);
807 /* Undo stack alignment. */
810 /* ??? The exception return type specifies Thread/Handler mode. However
811 this is also implied by the xPSR value. Not sure what to do
812 if there is a mismatch. */
813 /* ??? Likewise for mismatches between the CONTROL register and the stack
817 static void do_interrupt_v7m(CPUARMState
*env
)
819 uint32_t xpsr
= xpsr_read(env
);
824 if (env
->v7m
.current_sp
)
826 if (env
->v7m
.exception
== 0)
829 /* For exceptions we just mark as pending on the NVIC, and let that
831 /* TODO: Need to escalate if the current priority is higher than the
832 one we're raising. */
833 switch (env
->exception_index
) {
835 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
);
839 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SVC
);
841 case EXCP_PREFETCH_ABORT
:
842 case EXCP_DATA_ABORT
:
843 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_MEM
);
846 if (semihosting_enabled
) {
848 nr
= lduw_code(env
->regs
[15]) & 0xff;
851 env
->regs
[0] = do_arm_semihosting(env
);
855 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_DEBUG
);
858 env
->v7m
.exception
= armv7m_nvic_acknowledge_irq(env
->nvic
);
860 case EXCP_EXCEPTION_EXIT
:
861 do_v7m_exception_exit(env
);
864 cpu_abort(env
, "Unhandled exception 0x%x\n", env
->exception_index
);
865 return; /* Never happens. Keep compiler happy. */
868 /* Align stack pointer. */
869 /* ??? Should only do this if Configuration Control Register
870 STACKALIGN bit is set. */
871 if (env
->regs
[13] & 4) {
875 /* Switch to the handler mode. */
877 v7m_push(env
, env
->regs
[15]);
878 v7m_push(env
, env
->regs
[14]);
879 v7m_push(env
, env
->regs
[12]);
880 v7m_push(env
, env
->regs
[3]);
881 v7m_push(env
, env
->regs
[2]);
882 v7m_push(env
, env
->regs
[1]);
883 v7m_push(env
, env
->regs
[0]);
884 switch_v7m_sp(env
, 0);
885 env
->uncached_cpsr
&= ~CPSR_IT
;
887 addr
= ldl_phys(env
->v7m
.vecbase
+ env
->v7m
.exception
* 4);
888 env
->regs
[15] = addr
& 0xfffffffe;
889 env
->thumb
= addr
& 1;
892 /* Handle a CPU exception. */
893 void do_interrupt(CPUARMState
*env
)
901 do_interrupt_v7m(env
);
904 /* TODO: Vectored interrupt controller. */
905 switch (env
->exception_index
) {
907 new_mode
= ARM_CPU_MODE_UND
;
916 if (semihosting_enabled
) {
917 /* Check for semihosting interrupt. */
919 mask
= lduw_code(env
->regs
[15] - 2) & 0xff;
921 mask
= ldl_code(env
->regs
[15] - 4) & 0xffffff;
923 /* Only intercept calls from privileged modes, to provide some
924 semblance of security. */
925 if (((mask
== 0x123456 && !env
->thumb
)
926 || (mask
== 0xab && env
->thumb
))
927 && (env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
) {
928 env
->regs
[0] = do_arm_semihosting(env
);
932 new_mode
= ARM_CPU_MODE_SVC
;
935 /* The PC already points to the next instruction. */
939 /* See if this is a semihosting syscall. */
940 if (env
->thumb
&& semihosting_enabled
) {
941 mask
= lduw_code(env
->regs
[15]) & 0xff;
943 && (env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
) {
945 env
->regs
[0] = do_arm_semihosting(env
);
949 env
->cp15
.c5_insn
= 2;
950 /* Fall through to prefetch abort. */
951 case EXCP_PREFETCH_ABORT
:
952 new_mode
= ARM_CPU_MODE_ABT
;
954 mask
= CPSR_A
| CPSR_I
;
957 case EXCP_DATA_ABORT
:
958 new_mode
= ARM_CPU_MODE_ABT
;
960 mask
= CPSR_A
| CPSR_I
;
964 new_mode
= ARM_CPU_MODE_IRQ
;
966 /* Disable IRQ and imprecise data aborts. */
967 mask
= CPSR_A
| CPSR_I
;
971 new_mode
= ARM_CPU_MODE_FIQ
;
973 /* Disable FIQ, IRQ and imprecise data aborts. */
974 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
978 cpu_abort(env
, "Unhandled exception 0x%x\n", env
->exception_index
);
979 return; /* Never happens. Keep compiler happy. */
982 if (env
->cp15
.c1_sys
& (1 << 13)) {
985 switch_mode (env
, new_mode
);
986 env
->spsr
= cpsr_read(env
);
988 env
->condexec_bits
= 0;
989 /* Switch to the new mode, and to the correct instruction set. */
990 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~CPSR_M
) | new_mode
;
991 env
->uncached_cpsr
|= mask
;
992 /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
993 * and we should just guard the thumb mode on V4 */
994 if (arm_feature(env
, ARM_FEATURE_V4T
)) {
995 env
->thumb
= (env
->cp15
.c1_sys
& (1 << 30)) != 0;
997 env
->regs
[14] = env
->regs
[15] + offset
;
998 env
->regs
[15] = addr
;
999 env
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
1002 /* Check section/page access permissions.
1003 Returns the page protection flags, or zero if the access is not
1005 static inline int check_ap(CPUState
*env
, int ap
, int domain_prot
,
1006 int access_type
, int is_user
)
1010 if (domain_prot
== 3) {
1011 return PAGE_READ
| PAGE_WRITE
;
1014 if (access_type
== 1)
1017 prot_ro
= PAGE_READ
;
1021 if (access_type
== 1)
1023 switch ((env
->cp15
.c1_sys
>> 8) & 3) {
1025 return is_user
? 0 : PAGE_READ
;
1032 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
1037 return PAGE_READ
| PAGE_WRITE
;
1039 return PAGE_READ
| PAGE_WRITE
;
1040 case 4: /* Reserved. */
1043 return is_user
? 0 : prot_ro
;
1047 if (!arm_feature (env
, ARM_FEATURE_V6K
))
1055 static uint32_t get_level1_table_address(CPUState
*env
, uint32_t address
)
1059 if (address
& env
->cp15
.c2_mask
)
1060 table
= env
->cp15
.c2_base1
& 0xffffc000;
1062 table
= env
->cp15
.c2_base0
& env
->cp15
.c2_base_mask
;
1064 table
|= (address
>> 18) & 0x3ffc;
1068 static int get_phys_addr_v5(CPUState
*env
, uint32_t address
, int access_type
,
1069 int is_user
, uint32_t *phys_ptr
, int *prot
,
1070 target_ulong
*page_size
)
1081 /* Pagetable walk. */
1082 /* Lookup l1 descriptor. */
1083 table
= get_level1_table_address(env
, address
);
1084 desc
= ldl_phys(table
);
1086 domain
= (desc
>> 5) & 0x0f;
1087 domain_prot
= (env
->cp15
.c3
>> (domain
* 2)) & 3;
1089 /* Section translation fault. */
1093 if (domain_prot
== 0 || domain_prot
== 2) {
1095 code
= 9; /* Section domain fault. */
1097 code
= 11; /* Page domain fault. */
1102 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
1103 ap
= (desc
>> 10) & 3;
1105 *page_size
= 1024 * 1024;
1107 /* Lookup l2 entry. */
1109 /* Coarse pagetable. */
1110 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
1112 /* Fine pagetable. */
1113 table
= (desc
& 0xfffff000) | ((address
>> 8) & 0xffc);
1115 desc
= ldl_phys(table
);
1117 case 0: /* Page translation fault. */
1120 case 1: /* 64k page. */
1121 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
1122 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
1123 *page_size
= 0x10000;
1125 case 2: /* 4k page. */
1126 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
1127 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
1128 *page_size
= 0x1000;
1130 case 3: /* 1k page. */
1132 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
1133 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
1135 /* Page translation fault. */
1140 phys_addr
= (desc
& 0xfffffc00) | (address
& 0x3ff);
1142 ap
= (desc
>> 4) & 3;
1146 /* Never happens, but compiler isn't smart enough to tell. */
1151 *prot
= check_ap(env
, ap
, domain_prot
, access_type
, is_user
);
1153 /* Access permission fault. */
1157 *phys_ptr
= phys_addr
;
1160 return code
| (domain
<< 4);
1163 static int get_phys_addr_v6(CPUState
*env
, uint32_t address
, int access_type
,
1164 int is_user
, uint32_t *phys_ptr
, int *prot
,
1165 target_ulong
*page_size
)
1177 /* Pagetable walk. */
1178 /* Lookup l1 descriptor. */
1179 table
= get_level1_table_address(env
, address
);
1180 desc
= ldl_phys(table
);
1183 /* Section translation fault. */
1187 } else if (type
== 2 && (desc
& (1 << 18))) {
1191 /* Section or page. */
1192 domain
= (desc
>> 5) & 0x0f;
1194 domain_prot
= (env
->cp15
.c3
>> (domain
* 2)) & 3;
1195 if (domain_prot
== 0 || domain_prot
== 2) {
1197 code
= 9; /* Section domain fault. */
1199 code
= 11; /* Page domain fault. */
1203 if (desc
& (1 << 18)) {
1205 phys_addr
= (desc
& 0xff000000) | (address
& 0x00ffffff);
1206 *page_size
= 0x1000000;
1209 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
1210 *page_size
= 0x100000;
1212 ap
= ((desc
>> 10) & 3) | ((desc
>> 13) & 4);
1213 xn
= desc
& (1 << 4);
1216 /* Lookup l2 entry. */
1217 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
1218 desc
= ldl_phys(table
);
1219 ap
= ((desc
>> 4) & 3) | ((desc
>> 7) & 4);
1221 case 0: /* Page translation fault. */
1224 case 1: /* 64k page. */
1225 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
1226 xn
= desc
& (1 << 15);
1227 *page_size
= 0x10000;
1229 case 2: case 3: /* 4k page. */
1230 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
1232 *page_size
= 0x1000;
1235 /* Never happens, but compiler isn't smart enough to tell. */
1240 if (domain_prot
== 3) {
1241 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
1243 if (xn
&& access_type
== 2)
1246 /* The simplified model uses AP[0] as an access control bit. */
1247 if ((env
->cp15
.c1_sys
& (1 << 29)) && (ap
& 1) == 0) {
1248 /* Access flag fault. */
1249 code
= (code
== 15) ? 6 : 3;
1252 *prot
= check_ap(env
, ap
, domain_prot
, access_type
, is_user
);
1254 /* Access permission fault. */
1261 *phys_ptr
= phys_addr
;
1264 return code
| (domain
<< 4);
1267 static int get_phys_addr_mpu(CPUState
*env
, uint32_t address
, int access_type
,
1268 int is_user
, uint32_t *phys_ptr
, int *prot
)
1274 *phys_ptr
= address
;
1275 for (n
= 7; n
>= 0; n
--) {
1276 base
= env
->cp15
.c6_region
[n
];
1277 if ((base
& 1) == 0)
1279 mask
= 1 << ((base
>> 1) & 0x1f);
1280 /* Keep this shift separate from the above to avoid an
1281 (undefined) << 32. */
1282 mask
= (mask
<< 1) - 1;
1283 if (((base
^ address
) & ~mask
) == 0)
1289 if (access_type
== 2) {
1290 mask
= env
->cp15
.c5_insn
;
1292 mask
= env
->cp15
.c5_data
;
1294 mask
= (mask
>> (n
* 4)) & 0xf;
1301 *prot
= PAGE_READ
| PAGE_WRITE
;
1306 *prot
|= PAGE_WRITE
;
1309 *prot
= PAGE_READ
| PAGE_WRITE
;
1320 /* Bad permission. */
1327 static inline int get_phys_addr(CPUState
*env
, uint32_t address
,
1328 int access_type
, int is_user
,
1329 uint32_t *phys_ptr
, int *prot
,
1330 target_ulong
*page_size
)
1332 /* Fast Context Switch Extension. */
1333 if (address
< 0x02000000)
1334 address
+= env
->cp15
.c13_fcse
;
1336 if ((env
->cp15
.c1_sys
& 1) == 0) {
1337 /* MMU/MPU disabled. */
1338 *phys_ptr
= address
;
1339 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
1340 *page_size
= TARGET_PAGE_SIZE
;
1342 } else if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1343 *page_size
= TARGET_PAGE_SIZE
;
1344 return get_phys_addr_mpu(env
, address
, access_type
, is_user
, phys_ptr
,
1346 } else if (env
->cp15
.c1_sys
& (1 << 23)) {
1347 return get_phys_addr_v6(env
, address
, access_type
, is_user
, phys_ptr
,
1350 return get_phys_addr_v5(env
, address
, access_type
, is_user
, phys_ptr
,
1355 int cpu_arm_handle_mmu_fault (CPUState
*env
, target_ulong address
,
1356 int access_type
, int mmu_idx
)
1359 target_ulong page_size
;
1363 is_user
= mmu_idx
== MMU_USER_IDX
;
1364 ret
= get_phys_addr(env
, address
, access_type
, is_user
, &phys_addr
, &prot
,
1367 /* Map a single [sub]page. */
1368 phys_addr
&= ~(uint32_t)0x3ff;
1369 address
&= ~(uint32_t)0x3ff;
1370 tlb_set_page (env
, address
, phys_addr
, prot
, mmu_idx
, page_size
);
1374 if (access_type
== 2) {
1375 env
->cp15
.c5_insn
= ret
;
1376 env
->cp15
.c6_insn
= address
;
1377 env
->exception_index
= EXCP_PREFETCH_ABORT
;
1379 env
->cp15
.c5_data
= ret
;
1380 if (access_type
== 1 && arm_feature(env
, ARM_FEATURE_V6
))
1381 env
->cp15
.c5_data
|= (1 << 11);
1382 env
->cp15
.c6_data
= address
;
1383 env
->exception_index
= EXCP_DATA_ABORT
;
1388 target_phys_addr_t
cpu_get_phys_page_debug(CPUState
*env
, target_ulong addr
)
1391 target_ulong page_size
;
1395 ret
= get_phys_addr(env
, addr
, 0, 0, &phys_addr
, &prot
, &page_size
);
1403 void HELPER(set_cp
)(CPUState
*env
, uint32_t insn
, uint32_t val
)
1405 int cp_num
= (insn
>> 8) & 0xf;
1406 int cp_info
= (insn
>> 5) & 7;
1407 int src
= (insn
>> 16) & 0xf;
1408 int operand
= insn
& 0xf;
1410 if (env
->cp
[cp_num
].cp_write
)
1411 env
->cp
[cp_num
].cp_write(env
->cp
[cp_num
].opaque
,
1412 cp_info
, src
, operand
, val
);
1415 uint32_t HELPER(get_cp
)(CPUState
*env
, uint32_t insn
)
1417 int cp_num
= (insn
>> 8) & 0xf;
1418 int cp_info
= (insn
>> 5) & 7;
1419 int dest
= (insn
>> 16) & 0xf;
1420 int operand
= insn
& 0xf;
1422 if (env
->cp
[cp_num
].cp_read
)
1423 return env
->cp
[cp_num
].cp_read(env
->cp
[cp_num
].opaque
,
1424 cp_info
, dest
, operand
);
1428 /* Return basic MPU access permission bits. */
1429 static uint32_t simple_mpu_ap_bits(uint32_t val
)
1436 for (i
= 0; i
< 16; i
+= 2) {
1437 ret
|= (val
>> i
) & mask
;
1443 /* Pad basic MPU access permission bits to extended format. */
1444 static uint32_t extended_mpu_ap_bits(uint32_t val
)
1451 for (i
= 0; i
< 16; i
+= 2) {
1452 ret
|= (val
& mask
) << i
;
1458 void HELPER(set_cp15
)(CPUState
*env
, uint32_t insn
, uint32_t val
)
1464 op1
= (insn
>> 21) & 7;
1465 op2
= (insn
>> 5) & 7;
1467 switch ((insn
>> 16) & 0xf) {
1470 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1472 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1474 if (arm_feature(env
, ARM_FEATURE_V7
)
1475 && op1
== 2 && crm
== 0 && op2
== 0) {
1476 env
->cp15
.c0_cssel
= val
& 0xf;
1480 case 1: /* System configuration. */
1481 if (arm_feature(env
, ARM_FEATURE_V7
)
1482 && op1
== 0 && crm
== 1 && op2
== 0) {
1483 env
->cp15
.c1_scr
= val
;
1486 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1490 if (!arm_feature(env
, ARM_FEATURE_XSCALE
) || crm
== 0)
1491 env
->cp15
.c1_sys
= val
;
1492 /* ??? Lots of these bits are not implemented. */
1493 /* This may enable/disable the MMU, so do a TLB flush. */
1496 case 1: /* Auxiliary control register. */
1497 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
1498 env
->cp15
.c1_xscaleauxcr
= val
;
1501 /* Not implemented. */
1504 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1506 if (env
->cp15
.c1_coproc
!= val
) {
1507 env
->cp15
.c1_coproc
= val
;
1508 /* ??? Is this safe when called from within a TB? */
1516 case 2: /* MMU Page table control / MPU cache control. */
1517 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1520 env
->cp15
.c2_data
= val
;
1523 env
->cp15
.c2_insn
= val
;
1531 env
->cp15
.c2_base0
= val
;
1534 env
->cp15
.c2_base1
= val
;
1538 env
->cp15
.c2_control
= val
;
1539 env
->cp15
.c2_mask
= ~(((uint32_t)0xffffffffu
) >> val
);
1540 env
->cp15
.c2_base_mask
= ~((uint32_t)0x3fffu
>> val
);
1547 case 3: /* MMU Domain access control / MPU write buffer control. */
1549 tlb_flush(env
, 1); /* Flush TLB as domain not tracked in TLB */
1551 case 4: /* Reserved. */
1553 case 5: /* MMU Fault status / MPU access permission. */
1554 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1558 if (arm_feature(env
, ARM_FEATURE_MPU
))
1559 val
= extended_mpu_ap_bits(val
);
1560 env
->cp15
.c5_data
= val
;
1563 if (arm_feature(env
, ARM_FEATURE_MPU
))
1564 val
= extended_mpu_ap_bits(val
);
1565 env
->cp15
.c5_insn
= val
;
1568 if (!arm_feature(env
, ARM_FEATURE_MPU
))
1570 env
->cp15
.c5_data
= val
;
1573 if (!arm_feature(env
, ARM_FEATURE_MPU
))
1575 env
->cp15
.c5_insn
= val
;
1581 case 6: /* MMU Fault address / MPU base/size. */
1582 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1585 env
->cp15
.c6_region
[crm
] = val
;
1587 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1591 env
->cp15
.c6_data
= val
;
1593 case 1: /* ??? This is WFAR on armv6 */
1595 env
->cp15
.c6_insn
= val
;
1602 case 7: /* Cache control. */
1603 env
->cp15
.c15_i_max
= 0x000;
1604 env
->cp15
.c15_i_min
= 0xff0;
1608 /* No cache, so nothing to do except VA->PA translations. */
1609 if (arm_feature(env
, ARM_FEATURE_VAPA
)) {
1612 if (arm_feature(env
, ARM_FEATURE_V7
)) {
1613 env
->cp15
.c7_par
= val
& 0xfffff6ff;
1615 env
->cp15
.c7_par
= val
& 0xfffff1ff;
1620 target_ulong page_size
;
1622 int ret
, is_user
= op2
& 2;
1623 int access_type
= op2
& 1;
1626 /* Other states are only available with TrustZone */
1629 ret
= get_phys_addr(env
, val
, access_type
, is_user
,
1630 &phys_addr
, &prot
, &page_size
);
1632 /* We do not set any attribute bits in the PAR */
1633 if (page_size
== (1 << 24)
1634 && arm_feature(env
, ARM_FEATURE_V7
)) {
1635 env
->cp15
.c7_par
= (phys_addr
& 0xff000000) | 1 << 1;
1637 env
->cp15
.c7_par
= phys_addr
& 0xfffff000;
1640 env
->cp15
.c7_par
= ((ret
& (10 << 1)) >> 5) |
1641 ((ret
& (12 << 1)) >> 6) |
1642 ((ret
& 0xf) << 1) | 1;
1649 case 8: /* MMU TLB control. */
1651 case 0: /* Invalidate all (TLBIALL) */
1654 case 1: /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
1655 tlb_flush_page(env
, val
& TARGET_PAGE_MASK
);
1657 case 2: /* Invalidate by ASID (TLBIASID) */
1658 tlb_flush(env
, val
== 0);
1660 case 3: /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
1661 tlb_flush_page(env
, val
& TARGET_PAGE_MASK
);
1668 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1670 if (arm_feature(env
, ARM_FEATURE_STRONGARM
))
1671 break; /* Ignore ReadBuffer access */
1673 case 0: /* Cache lockdown. */
1675 case 0: /* L1 cache. */
1678 env
->cp15
.c9_data
= val
;
1681 env
->cp15
.c9_insn
= val
;
1687 case 1: /* L2 cache. */
1688 /* Ignore writes to L2 lockdown/auxiliary registers. */
1694 case 1: /* TCM memory region registers. */
1695 /* Not implemented. */
1697 case 12: /* Performance monitor control */
1698 /* Performance monitors are implementation defined in v7,
1699 * but with an ARM recommended set of registers, which we
1700 * follow (although we don't actually implement any counters)
1702 if (!arm_feature(env
, ARM_FEATURE_V7
)) {
1706 case 0: /* performance monitor control register */
1707 /* only the DP, X, D and E bits are writable */
1708 env
->cp15
.c9_pmcr
&= ~0x39;
1709 env
->cp15
.c9_pmcr
|= (val
& 0x39);
1711 case 1: /* Count enable set register */
1713 env
->cp15
.c9_pmcnten
|= val
;
1715 case 2: /* Count enable clear */
1717 env
->cp15
.c9_pmcnten
&= ~val
;
1719 case 3: /* Overflow flag status */
1720 env
->cp15
.c9_pmovsr
&= ~val
;
1722 case 4: /* Software increment */
1723 /* RAZ/WI since we don't implement the software-count event */
1725 case 5: /* Event counter selection register */
1726 /* Since we don't implement any events, writing to this register
1727 * is actually UNPREDICTABLE. So we choose to RAZ/WI.
1734 case 13: /* Performance counters */
1735 if (!arm_feature(env
, ARM_FEATURE_V7
)) {
1739 case 0: /* Cycle count register: not implemented, so RAZ/WI */
1741 case 1: /* Event type select */
1742 env
->cp15
.c9_pmxevtyper
= val
& 0xff;
1744 case 2: /* Event count register */
1745 /* Unimplemented (we have no events), RAZ/WI */
1751 case 14: /* Performance monitor control */
1752 if (!arm_feature(env
, ARM_FEATURE_V7
)) {
1756 case 0: /* user enable */
1757 env
->cp15
.c9_pmuserenr
= val
& 1;
1758 /* changes access rights for cp registers, so flush tbs */
1761 case 1: /* interrupt enable set */
1762 /* We have no event counters so only the C bit can be changed */
1764 env
->cp15
.c9_pminten
|= val
;
1766 case 2: /* interrupt enable clear */
1768 env
->cp15
.c9_pminten
&= ~val
;
1776 case 10: /* MMU TLB lockdown. */
1777 /* ??? TLB lockdown not implemented. */
1779 case 12: /* Reserved. */
1781 case 13: /* Process ID. */
1784 /* Unlike real hardware the qemu TLB uses virtual addresses,
1785 not modified virtual addresses, so this causes a TLB flush.
1787 if (env
->cp15
.c13_fcse
!= val
)
1789 env
->cp15
.c13_fcse
= val
;
1792 /* This changes the ASID, so do a TLB flush. */
1793 if (env
->cp15
.c13_context
!= val
1794 && !arm_feature(env
, ARM_FEATURE_MPU
))
1796 env
->cp15
.c13_context
= val
;
1802 case 14: /* Generic timer */
1803 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
1804 /* Dummy implementation: RAZ/WI for all */
1808 case 15: /* Implementation specific. */
1809 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
1810 if (op2
== 0 && crm
== 1) {
1811 if (env
->cp15
.c15_cpar
!= (val
& 0x3fff)) {
1812 /* Changes cp0 to cp13 behavior, so needs a TB flush. */
1814 env
->cp15
.c15_cpar
= val
& 0x3fff;
1820 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
1824 case 1: /* Set TI925T configuration. */
1825 env
->cp15
.c15_ticonfig
= val
& 0xe7;
1826 env
->cp15
.c0_cpuid
= (val
& (1 << 5)) ? /* OS_TYPE bit */
1827 ARM_CPUID_TI915T
: ARM_CPUID_TI925T
;
1829 case 2: /* Set I_max. */
1830 env
->cp15
.c15_i_max
= val
;
1832 case 3: /* Set I_min. */
1833 env
->cp15
.c15_i_min
= val
;
1835 case 4: /* Set thread-ID. */
1836 env
->cp15
.c15_threadid
= val
& 0xffff;
1838 case 8: /* Wait-for-interrupt (deprecated). */
1839 cpu_interrupt(env
, CPU_INTERRUPT_HALT
);
1845 if (ARM_CPUID(env
) == ARM_CPUID_CORTEXA9
) {
1848 if ((op1
== 0) && (op2
== 0)) {
1849 env
->cp15
.c15_power_control
= val
;
1850 } else if ((op1
== 0) && (op2
== 1)) {
1851 env
->cp15
.c15_diagnostic
= val
;
1852 } else if ((op1
== 0) && (op2
== 2)) {
1853 env
->cp15
.c15_power_diagnostic
= val
;
1863 /* ??? For debugging only. Should raise illegal instruction exception. */
1864 cpu_abort(env
, "Unimplemented cp15 register write (c%d, c%d, {%d, %d})\n",
1865 (insn
>> 16) & 0xf, crm
, op1
, op2
);
1868 uint32_t HELPER(get_cp15
)(CPUState
*env
, uint32_t insn
)
1874 op1
= (insn
>> 21) & 7;
1875 op2
= (insn
>> 5) & 7;
1877 switch ((insn
>> 16) & 0xf) {
1878 case 0: /* ID codes. */
1884 case 0: /* Device ID. */
1885 return env
->cp15
.c0_cpuid
;
1886 case 1: /* Cache Type. */
1887 return env
->cp15
.c0_cachetype
;
1888 case 2: /* TCM status. */
1890 case 3: /* TLB type register. */
1891 return 0; /* No lockable TLB entries. */
1893 /* The MPIDR was standardised in v7; prior to
1894 * this it was implemented only in the 11MPCore.
1895 * For all other pre-v7 cores it does not exist.
1897 if (arm_feature(env
, ARM_FEATURE_V7
) ||
1898 ARM_CPUID(env
) == ARM_CPUID_ARM11MPCORE
) {
1899 int mpidr
= env
->cpu_index
;
1900 /* We don't support setting cluster ID ([8..11])
1901 * so these bits always RAZ.
1903 if (arm_feature(env
, ARM_FEATURE_V7MP
)) {
1905 /* Cores which are uniprocessor (non-coherent)
1906 * but still implement the MP extensions set
1907 * bit 30. (For instance, A9UP.) However we do
1908 * not currently model any of those cores.
1913 /* otherwise fall through to the unimplemented-reg case */
1918 if (!arm_feature(env
, ARM_FEATURE_V6
))
1920 return env
->cp15
.c0_c1
[op2
];
1922 if (!arm_feature(env
, ARM_FEATURE_V6
))
1924 return env
->cp15
.c0_c2
[op2
];
1925 case 3: case 4: case 5: case 6: case 7:
1931 /* These registers aren't documented on arm11 cores. However
1932 Linux looks at them anyway. */
1933 if (!arm_feature(env
, ARM_FEATURE_V6
))
1937 if (!arm_feature(env
, ARM_FEATURE_V7
))
1942 return env
->cp15
.c0_ccsid
[env
->cp15
.c0_cssel
];
1944 return env
->cp15
.c0_clid
;
1950 if (op2
!= 0 || crm
!= 0)
1952 return env
->cp15
.c0_cssel
;
1956 case 1: /* System configuration. */
1957 if (arm_feature(env
, ARM_FEATURE_V7
)
1958 && op1
== 0 && crm
== 1 && op2
== 0) {
1959 return env
->cp15
.c1_scr
;
1961 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1964 case 0: /* Control register. */
1965 return env
->cp15
.c1_sys
;
1966 case 1: /* Auxiliary control register. */
1967 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1968 return env
->cp15
.c1_xscaleauxcr
;
1969 if (!arm_feature(env
, ARM_FEATURE_AUXCR
))
1971 switch (ARM_CPUID(env
)) {
1972 case ARM_CPUID_ARM1026
:
1974 case ARM_CPUID_ARM1136
:
1975 case ARM_CPUID_ARM1136_R2
:
1976 case ARM_CPUID_ARM1176
:
1978 case ARM_CPUID_ARM11MPCORE
:
1980 case ARM_CPUID_CORTEXA8
:
1982 case ARM_CPUID_CORTEXA9
:
1983 case ARM_CPUID_CORTEXA15
:
1988 case 2: /* Coprocessor access register. */
1989 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1991 return env
->cp15
.c1_coproc
;
1995 case 2: /* MMU Page table control / MPU cache control. */
1996 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1999 return env
->cp15
.c2_data
;
2002 return env
->cp15
.c2_insn
;
2010 return env
->cp15
.c2_base0
;
2012 return env
->cp15
.c2_base1
;
2014 return env
->cp15
.c2_control
;
2019 case 3: /* MMU Domain access control / MPU write buffer control. */
2020 return env
->cp15
.c3
;
2021 case 4: /* Reserved. */
2023 case 5: /* MMU Fault status / MPU access permission. */
2024 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
2028 if (arm_feature(env
, ARM_FEATURE_MPU
))
2029 return simple_mpu_ap_bits(env
->cp15
.c5_data
);
2030 return env
->cp15
.c5_data
;
2032 if (arm_feature(env
, ARM_FEATURE_MPU
))
2033 return simple_mpu_ap_bits(env
->cp15
.c5_data
);
2034 return env
->cp15
.c5_insn
;
2036 if (!arm_feature(env
, ARM_FEATURE_MPU
))
2038 return env
->cp15
.c5_data
;
2040 if (!arm_feature(env
, ARM_FEATURE_MPU
))
2042 return env
->cp15
.c5_insn
;
2046 case 6: /* MMU Fault address. */
2047 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
2050 return env
->cp15
.c6_region
[crm
];
2052 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
2056 return env
->cp15
.c6_data
;
2058 if (arm_feature(env
, ARM_FEATURE_V6
)) {
2059 /* Watchpoint Fault Adrress. */
2060 return 0; /* Not implemented. */
2062 /* Instruction Fault Adrress. */
2063 /* Arm9 doesn't have an IFAR, but implementing it anyway
2064 shouldn't do any harm. */
2065 return env
->cp15
.c6_insn
;
2068 if (arm_feature(env
, ARM_FEATURE_V6
)) {
2069 /* Instruction Fault Adrress. */
2070 return env
->cp15
.c6_insn
;
2078 case 7: /* Cache control. */
2079 if (crm
== 4 && op1
== 0 && op2
== 0) {
2080 return env
->cp15
.c7_par
;
2082 /* FIXME: Should only clear Z flag if destination is r15. */
2085 case 8: /* MMU TLB control. */
2089 case 0: /* Cache lockdown */
2091 case 0: /* L1 cache. */
2092 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
2097 return env
->cp15
.c9_data
;
2099 return env
->cp15
.c9_insn
;
2103 case 1: /* L2 cache */
2104 /* L2 Lockdown and Auxiliary control. */
2107 /* L2 cache lockdown (A8 only) */
2110 /* L2 cache auxiliary control (A8) or control (A15) */
2111 if (ARM_CPUID(env
) == ARM_CPUID_CORTEXA15
) {
2112 /* Linux wants the number of processors from here.
2113 * Might as well set the interrupt-controller bit too.
2115 return ((smp_cpus
- 1) << 24) | (1 << 23);
2119 /* L2 cache extended control (A15) */
2128 case 12: /* Performance monitor control */
2129 if (!arm_feature(env
, ARM_FEATURE_V7
)) {
2133 case 0: /* performance monitor control register */
2134 return env
->cp15
.c9_pmcr
;
2135 case 1: /* count enable set */
2136 case 2: /* count enable clear */
2137 return env
->cp15
.c9_pmcnten
;
2138 case 3: /* overflow flag status */
2139 return env
->cp15
.c9_pmovsr
;
2140 case 4: /* software increment */
2141 case 5: /* event counter selection register */
2142 return 0; /* Unimplemented, RAZ/WI */
2146 case 13: /* Performance counters */
2147 if (!arm_feature(env
, ARM_FEATURE_V7
)) {
2151 case 1: /* Event type select */
2152 return env
->cp15
.c9_pmxevtyper
;
2153 case 0: /* Cycle count register */
2154 case 2: /* Event count register */
2155 /* Unimplemented, so RAZ/WI */
2160 case 14: /* Performance monitor control */
2161 if (!arm_feature(env
, ARM_FEATURE_V7
)) {
2165 case 0: /* user enable */
2166 return env
->cp15
.c9_pmuserenr
;
2167 case 1: /* interrupt enable set */
2168 case 2: /* interrupt enable clear */
2169 return env
->cp15
.c9_pminten
;
2177 case 10: /* MMU TLB lockdown. */
2178 /* ??? TLB lockdown not implemented. */
2180 case 11: /* TCM DMA control. */
2181 case 12: /* Reserved. */
2183 case 13: /* Process ID. */
2186 return env
->cp15
.c13_fcse
;
2188 return env
->cp15
.c13_context
;
2192 case 14: /* Generic timer */
2193 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
2194 /* Dummy implementation: RAZ/WI for all */
2198 case 15: /* Implementation specific. */
2199 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
2200 if (op2
== 0 && crm
== 1)
2201 return env
->cp15
.c15_cpar
;
2205 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
2209 case 1: /* Read TI925T configuration. */
2210 return env
->cp15
.c15_ticonfig
;
2211 case 2: /* Read I_max. */
2212 return env
->cp15
.c15_i_max
;
2213 case 3: /* Read I_min. */
2214 return env
->cp15
.c15_i_min
;
2215 case 4: /* Read thread-ID. */
2216 return env
->cp15
.c15_threadid
;
2217 case 8: /* TI925T_status */
2220 /* TODO: Peripheral port remap register:
2221 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt
2222 * controller base address at $rn & ~0xfff and map size of
2223 * 0x200 << ($rn & 0xfff), when MMU is off. */
2226 if (ARM_CPUID(env
) == ARM_CPUID_CORTEXA9
) {
2229 if ((op1
== 4) && (op2
== 0)) {
2230 /* The config_base_address should hold the value of
2231 * the peripheral base. ARM should get this from a CPU
2232 * object property, but that support isn't available in
2233 * December 2011. Default to 0 for now and board models
2234 * that care can set it by a private hook */
2235 return env
->cp15
.c15_config_base_address
;
2236 } else if ((op1
== 0) && (op2
== 0)) {
2237 /* power_control should be set to maximum latency. Again,
2238 default to 0 and set by private hook */
2239 return env
->cp15
.c15_power_control
;
2240 } else if ((op1
== 0) && (op2
== 1)) {
2241 return env
->cp15
.c15_diagnostic
;
2242 } else if ((op1
== 0) && (op2
== 2)) {
2243 return env
->cp15
.c15_power_diagnostic
;
2246 case 1: /* NEON Busy */
2248 case 5: /* tlb lockdown */
2251 if ((op1
== 5) && (op2
== 2)) {
2263 /* ??? For debugging only. Should raise illegal instruction exception. */
2264 cpu_abort(env
, "Unimplemented cp15 register read (c%d, c%d, {%d, %d})\n",
2265 (insn
>> 16) & 0xf, crm
, op1
, op2
);
2269 void HELPER(set_r13_banked
)(CPUState
*env
, uint32_t mode
, uint32_t val
)
2271 if ((env
->uncached_cpsr
& CPSR_M
) == mode
) {
2272 env
->regs
[13] = val
;
2274 env
->banked_r13
[bank_number(env
, mode
)] = val
;
2278 uint32_t HELPER(get_r13_banked
)(CPUState
*env
, uint32_t mode
)
2280 if ((env
->uncached_cpsr
& CPSR_M
) == mode
) {
2281 return env
->regs
[13];
2283 return env
->banked_r13
[bank_number(env
, mode
)];
2287 uint32_t HELPER(v7m_mrs
)(CPUState
*env
, uint32_t reg
)
2291 return xpsr_read(env
) & 0xf8000000;
2293 return xpsr_read(env
) & 0xf80001ff;
2295 return xpsr_read(env
) & 0xff00fc00;
2297 return xpsr_read(env
) & 0xff00fdff;
2299 return xpsr_read(env
) & 0x000001ff;
2301 return xpsr_read(env
) & 0x0700fc00;
2303 return xpsr_read(env
) & 0x0700edff;
2305 return env
->v7m
.current_sp
? env
->v7m
.other_sp
: env
->regs
[13];
2307 return env
->v7m
.current_sp
? env
->regs
[13] : env
->v7m
.other_sp
;
2308 case 16: /* PRIMASK */
2309 return (env
->uncached_cpsr
& CPSR_I
) != 0;
2310 case 17: /* BASEPRI */
2311 case 18: /* BASEPRI_MAX */
2312 return env
->v7m
.basepri
;
2313 case 19: /* FAULTMASK */
2314 return (env
->uncached_cpsr
& CPSR_F
) != 0;
2315 case 20: /* CONTROL */
2316 return env
->v7m
.control
;
2318 /* ??? For debugging only. */
2319 cpu_abort(env
, "Unimplemented system register read (%d)\n", reg
);
2324 void HELPER(v7m_msr
)(CPUState
*env
, uint32_t reg
, uint32_t val
)
2328 xpsr_write(env
, val
, 0xf8000000);
2331 xpsr_write(env
, val
, 0xf8000000);
2334 xpsr_write(env
, val
, 0xfe00fc00);
2337 xpsr_write(env
, val
, 0xfe00fc00);
2340 /* IPSR bits are readonly. */
2343 xpsr_write(env
, val
, 0x0600fc00);
2346 xpsr_write(env
, val
, 0x0600fc00);
2349 if (env
->v7m
.current_sp
)
2350 env
->v7m
.other_sp
= val
;
2352 env
->regs
[13] = val
;
2355 if (env
->v7m
.current_sp
)
2356 env
->regs
[13] = val
;
2358 env
->v7m
.other_sp
= val
;
2360 case 16: /* PRIMASK */
2362 env
->uncached_cpsr
|= CPSR_I
;
2364 env
->uncached_cpsr
&= ~CPSR_I
;
2366 case 17: /* BASEPRI */
2367 env
->v7m
.basepri
= val
& 0xff;
2369 case 18: /* BASEPRI_MAX */
2371 if (val
!= 0 && (val
< env
->v7m
.basepri
|| env
->v7m
.basepri
== 0))
2372 env
->v7m
.basepri
= val
;
2374 case 19: /* FAULTMASK */
2376 env
->uncached_cpsr
|= CPSR_F
;
2378 env
->uncached_cpsr
&= ~CPSR_F
;
2380 case 20: /* CONTROL */
2381 env
->v7m
.control
= val
& 3;
2382 switch_v7m_sp(env
, (val
& 2) != 0);
2385 /* ??? For debugging only. */
2386 cpu_abort(env
, "Unimplemented system register write (%d)\n", reg
);
2391 void cpu_arm_set_cp_io(CPUARMState
*env
, int cpnum
,
2392 ARMReadCPFunc
*cp_read
, ARMWriteCPFunc
*cp_write
,
2395 if (cpnum
< 0 || cpnum
> 14) {
2396 cpu_abort(env
, "Bad coprocessor number: %i\n", cpnum
);
2400 env
->cp
[cpnum
].cp_read
= cp_read
;
2401 env
->cp
[cpnum
].cp_write
= cp_write
;
2402 env
->cp
[cpnum
].opaque
= opaque
;
2407 /* Note that signed overflow is undefined in C. The following routines are
2408 careful to use unsigned types where modulo arithmetic is required.
2409 Failure to do so _will_ break on newer gcc. */
2411 /* Signed saturating arithmetic. */
2413 /* Perform 16-bit signed saturating addition. */
2414 static inline uint16_t add16_sat(uint16_t a
, uint16_t b
)
2419 if (((res
^ a
) & 0x8000) && !((a
^ b
) & 0x8000)) {
2428 /* Perform 8-bit signed saturating addition. */
2429 static inline uint8_t add8_sat(uint8_t a
, uint8_t b
)
2434 if (((res
^ a
) & 0x80) && !((a
^ b
) & 0x80)) {
2443 /* Perform 16-bit signed saturating subtraction. */
2444 static inline uint16_t sub16_sat(uint16_t a
, uint16_t b
)
2449 if (((res
^ a
) & 0x8000) && ((a
^ b
) & 0x8000)) {
2458 /* Perform 8-bit signed saturating subtraction. */
2459 static inline uint8_t sub8_sat(uint8_t a
, uint8_t b
)
2464 if (((res
^ a
) & 0x80) && ((a
^ b
) & 0x80)) {
2473 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
2474 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
2475 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
2476 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
2479 #include "op_addsub.h"
2481 /* Unsigned saturating arithmetic. */
2482 static inline uint16_t add16_usat(uint16_t a
, uint16_t b
)
2491 static inline uint16_t sub16_usat(uint16_t a
, uint16_t b
)
2499 static inline uint8_t add8_usat(uint8_t a
, uint8_t b
)
2508 static inline uint8_t sub8_usat(uint8_t a
, uint8_t b
)
2516 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
2517 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
2518 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
2519 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
2522 #include "op_addsub.h"
2524 /* Signed modulo arithmetic. */
2525 #define SARITH16(a, b, n, op) do { \
2527 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
2528 RESULT(sum, n, 16); \
2530 ge |= 3 << (n * 2); \
2533 #define SARITH8(a, b, n, op) do { \
2535 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
2536 RESULT(sum, n, 8); \
2542 #define ADD16(a, b, n) SARITH16(a, b, n, +)
2543 #define SUB16(a, b, n) SARITH16(a, b, n, -)
2544 #define ADD8(a, b, n) SARITH8(a, b, n, +)
2545 #define SUB8(a, b, n) SARITH8(a, b, n, -)
2549 #include "op_addsub.h"
2551 /* Unsigned modulo arithmetic. */
2552 #define ADD16(a, b, n) do { \
2554 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
2555 RESULT(sum, n, 16); \
2556 if ((sum >> 16) == 1) \
2557 ge |= 3 << (n * 2); \
2560 #define ADD8(a, b, n) do { \
2562 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
2563 RESULT(sum, n, 8); \
2564 if ((sum >> 8) == 1) \
2568 #define SUB16(a, b, n) do { \
2570 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
2571 RESULT(sum, n, 16); \
2572 if ((sum >> 16) == 0) \
2573 ge |= 3 << (n * 2); \
2576 #define SUB8(a, b, n) do { \
2578 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
2579 RESULT(sum, n, 8); \
2580 if ((sum >> 8) == 0) \
2587 #include "op_addsub.h"
2589 /* Halved signed arithmetic. */
2590 #define ADD16(a, b, n) \
2591 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
2592 #define SUB16(a, b, n) \
2593 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
2594 #define ADD8(a, b, n) \
2595 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
2596 #define SUB8(a, b, n) \
2597 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
2600 #include "op_addsub.h"
2602 /* Halved unsigned arithmetic. */
2603 #define ADD16(a, b, n) \
2604 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2605 #define SUB16(a, b, n) \
2606 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2607 #define ADD8(a, b, n) \
2608 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2609 #define SUB8(a, b, n) \
2610 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2613 #include "op_addsub.h"
2615 static inline uint8_t do_usad(uint8_t a
, uint8_t b
)
2623 /* Unsigned sum of absolute byte differences. */
2624 uint32_t HELPER(usad8
)(uint32_t a
, uint32_t b
)
2627 sum
= do_usad(a
, b
);
2628 sum
+= do_usad(a
>> 8, b
>> 8);
2629 sum
+= do_usad(a
>> 16, b
>>16);
2630 sum
+= do_usad(a
>> 24, b
>> 24);
2634 /* For ARMv6 SEL instruction. */
2635 uint32_t HELPER(sel_flags
)(uint32_t flags
, uint32_t a
, uint32_t b
)
2648 return (a
& mask
) | (b
& ~mask
);
2651 uint32_t HELPER(logicq_cc
)(uint64_t val
)
2653 return (val
>> 32) | (val
!= 0);
2656 /* VFP support. We follow the convention used for VFP instrunctions:
2657 Single precition routines have a "s" suffix, double precision a
2660 /* Convert host exception flags to vfp form. */
2661 static inline int vfp_exceptbits_from_host(int host_bits
)
2663 int target_bits
= 0;
2665 if (host_bits
& float_flag_invalid
)
2667 if (host_bits
& float_flag_divbyzero
)
2669 if (host_bits
& float_flag_overflow
)
2671 if (host_bits
& (float_flag_underflow
| float_flag_output_denormal
))
2673 if (host_bits
& float_flag_inexact
)
2674 target_bits
|= 0x10;
2675 if (host_bits
& float_flag_input_denormal
)
2676 target_bits
|= 0x80;
2680 uint32_t HELPER(vfp_get_fpscr
)(CPUState
*env
)
2685 fpscr
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & 0xffc8ffff)
2686 | (env
->vfp
.vec_len
<< 16)
2687 | (env
->vfp
.vec_stride
<< 20);
2688 i
= get_float_exception_flags(&env
->vfp
.fp_status
);
2689 i
|= get_float_exception_flags(&env
->vfp
.standard_fp_status
);
2690 fpscr
|= vfp_exceptbits_from_host(i
);
2694 uint32_t vfp_get_fpscr(CPUState
*env
)
2696 return HELPER(vfp_get_fpscr
)(env
);
2699 /* Convert vfp exception flags to target form. */
2700 static inline int vfp_exceptbits_to_host(int target_bits
)
2704 if (target_bits
& 1)
2705 host_bits
|= float_flag_invalid
;
2706 if (target_bits
& 2)
2707 host_bits
|= float_flag_divbyzero
;
2708 if (target_bits
& 4)
2709 host_bits
|= float_flag_overflow
;
2710 if (target_bits
& 8)
2711 host_bits
|= float_flag_underflow
;
2712 if (target_bits
& 0x10)
2713 host_bits
|= float_flag_inexact
;
2714 if (target_bits
& 0x80)
2715 host_bits
|= float_flag_input_denormal
;
2719 void HELPER(vfp_set_fpscr
)(CPUState
*env
, uint32_t val
)
2724 changed
= env
->vfp
.xregs
[ARM_VFP_FPSCR
];
2725 env
->vfp
.xregs
[ARM_VFP_FPSCR
] = (val
& 0xffc8ffff);
2726 env
->vfp
.vec_len
= (val
>> 16) & 7;
2727 env
->vfp
.vec_stride
= (val
>> 20) & 3;
2730 if (changed
& (3 << 22)) {
2731 i
= (val
>> 22) & 3;
2734 i
= float_round_nearest_even
;
2740 i
= float_round_down
;
2743 i
= float_round_to_zero
;
2746 set_float_rounding_mode(i
, &env
->vfp
.fp_status
);
2748 if (changed
& (1 << 24)) {
2749 set_flush_to_zero((val
& (1 << 24)) != 0, &env
->vfp
.fp_status
);
2750 set_flush_inputs_to_zero((val
& (1 << 24)) != 0, &env
->vfp
.fp_status
);
2752 if (changed
& (1 << 25))
2753 set_default_nan_mode((val
& (1 << 25)) != 0, &env
->vfp
.fp_status
);
2755 i
= vfp_exceptbits_to_host(val
);
2756 set_float_exception_flags(i
, &env
->vfp
.fp_status
);
2757 set_float_exception_flags(0, &env
->vfp
.standard_fp_status
);
2760 void vfp_set_fpscr(CPUState
*env
, uint32_t val
)
2762 HELPER(vfp_set_fpscr
)(env
, val
);
2765 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
2767 #define VFP_BINOP(name) \
2768 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
2770 float_status *fpst = fpstp; \
2771 return float32_ ## name(a, b, fpst); \
2773 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
2775 float_status *fpst = fpstp; \
2776 return float64_ ## name(a, b, fpst); \
2784 float32
VFP_HELPER(neg
, s
)(float32 a
)
2786 return float32_chs(a
);
2789 float64
VFP_HELPER(neg
, d
)(float64 a
)
2791 return float64_chs(a
);
2794 float32
VFP_HELPER(abs
, s
)(float32 a
)
2796 return float32_abs(a
);
2799 float64
VFP_HELPER(abs
, d
)(float64 a
)
2801 return float64_abs(a
);
2804 float32
VFP_HELPER(sqrt
, s
)(float32 a
, CPUState
*env
)
2806 return float32_sqrt(a
, &env
->vfp
.fp_status
);
2809 float64
VFP_HELPER(sqrt
, d
)(float64 a
, CPUState
*env
)
2811 return float64_sqrt(a
, &env
->vfp
.fp_status
);
2814 /* XXX: check quiet/signaling case */
2815 #define DO_VFP_cmp(p, type) \
2816 void VFP_HELPER(cmp, p)(type a, type b, CPUState *env) \
2819 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
2820 case 0: flags = 0x6; break; \
2821 case -1: flags = 0x8; break; \
2822 case 1: flags = 0x2; break; \
2823 default: case 2: flags = 0x3; break; \
2825 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2826 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2828 void VFP_HELPER(cmpe, p)(type a, type b, CPUState *env) \
2831 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
2832 case 0: flags = 0x6; break; \
2833 case -1: flags = 0x8; break; \
2834 case 1: flags = 0x2; break; \
2835 default: case 2: flags = 0x3; break; \
2837 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2838 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2840 DO_VFP_cmp(s
, float32
)
2841 DO_VFP_cmp(d
, float64
)
2844 /* Integer to float and float to integer conversions */
2846 #define CONV_ITOF(name, fsz, sign) \
2847 float##fsz HELPER(name)(uint32_t x, void *fpstp) \
2849 float_status *fpst = fpstp; \
2850 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
2853 #define CONV_FTOI(name, fsz, sign, round) \
2854 uint32_t HELPER(name)(float##fsz x, void *fpstp) \
2856 float_status *fpst = fpstp; \
2857 if (float##fsz##_is_any_nan(x)) { \
2858 float_raise(float_flag_invalid, fpst); \
2861 return float##fsz##_to_##sign##int32##round(x, fpst); \
2864 #define FLOAT_CONVS(name, p, fsz, sign) \
2865 CONV_ITOF(vfp_##name##to##p, fsz, sign) \
2866 CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
2867 CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
2869 FLOAT_CONVS(si
, s
, 32, )
2870 FLOAT_CONVS(si
, d
, 64, )
2871 FLOAT_CONVS(ui
, s
, 32, u
)
2872 FLOAT_CONVS(ui
, d
, 64, u
)
2878 /* floating point conversion */
2879 float64
VFP_HELPER(fcvtd
, s
)(float32 x
, CPUState
*env
)
2881 float64 r
= float32_to_float64(x
, &env
->vfp
.fp_status
);
2882 /* ARM requires that S<->D conversion of any kind of NaN generates
2883 * a quiet NaN by forcing the most significant frac bit to 1.
2885 return float64_maybe_silence_nan(r
);
2888 float32
VFP_HELPER(fcvts
, d
)(float64 x
, CPUState
*env
)
2890 float32 r
= float64_to_float32(x
, &env
->vfp
.fp_status
);
2891 /* ARM requires that S<->D conversion of any kind of NaN generates
2892 * a quiet NaN by forcing the most significant frac bit to 1.
2894 return float32_maybe_silence_nan(r
);
2897 /* VFP3 fixed point conversion. */
2898 #define VFP_CONV_FIX(name, p, fsz, itype, sign) \
2899 float##fsz HELPER(vfp_##name##to##p)(uint##fsz##_t x, uint32_t shift, \
2902 float_status *fpst = fpstp; \
2904 tmp = sign##int32_to_##float##fsz((itype##_t)x, fpst); \
2905 return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
2907 uint##fsz##_t HELPER(vfp_to##name##p)(float##fsz x, uint32_t shift, \
2910 float_status *fpst = fpstp; \
2912 if (float##fsz##_is_any_nan(x)) { \
2913 float_raise(float_flag_invalid, fpst); \
2916 tmp = float##fsz##_scalbn(x, shift, fpst); \
2917 return float##fsz##_to_##itype##_round_to_zero(tmp, fpst); \
2920 VFP_CONV_FIX(sh
, d
, 64, int16
, )
2921 VFP_CONV_FIX(sl
, d
, 64, int32
, )
2922 VFP_CONV_FIX(uh
, d
, 64, uint16
, u
)
2923 VFP_CONV_FIX(ul
, d
, 64, uint32
, u
)
2924 VFP_CONV_FIX(sh
, s
, 32, int16
, )
2925 VFP_CONV_FIX(sl
, s
, 32, int32
, )
2926 VFP_CONV_FIX(uh
, s
, 32, uint16
, u
)
2927 VFP_CONV_FIX(ul
, s
, 32, uint32
, u
)
2930 /* Half precision conversions. */
2931 static float32
do_fcvt_f16_to_f32(uint32_t a
, CPUState
*env
, float_status
*s
)
2933 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
2934 float32 r
= float16_to_float32(make_float16(a
), ieee
, s
);
2936 return float32_maybe_silence_nan(r
);
2941 static uint32_t do_fcvt_f32_to_f16(float32 a
, CPUState
*env
, float_status
*s
)
2943 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
2944 float16 r
= float32_to_float16(a
, ieee
, s
);
2946 r
= float16_maybe_silence_nan(r
);
2948 return float16_val(r
);
2951 float32
HELPER(neon_fcvt_f16_to_f32
)(uint32_t a
, CPUState
*env
)
2953 return do_fcvt_f16_to_f32(a
, env
, &env
->vfp
.standard_fp_status
);
2956 uint32_t HELPER(neon_fcvt_f32_to_f16
)(float32 a
, CPUState
*env
)
2958 return do_fcvt_f32_to_f16(a
, env
, &env
->vfp
.standard_fp_status
);
2961 float32
HELPER(vfp_fcvt_f16_to_f32
)(uint32_t a
, CPUState
*env
)
2963 return do_fcvt_f16_to_f32(a
, env
, &env
->vfp
.fp_status
);
2966 uint32_t HELPER(vfp_fcvt_f32_to_f16
)(float32 a
, CPUState
*env
)
2968 return do_fcvt_f32_to_f16(a
, env
, &env
->vfp
.fp_status
);
2971 #define float32_two make_float32(0x40000000)
2972 #define float32_three make_float32(0x40400000)
2973 #define float32_one_point_five make_float32(0x3fc00000)
2975 float32
HELPER(recps_f32
)(float32 a
, float32 b
, CPUState
*env
)
2977 float_status
*s
= &env
->vfp
.standard_fp_status
;
2978 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
2979 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
2980 if (!(float32_is_zero(a
) || float32_is_zero(b
))) {
2981 float_raise(float_flag_input_denormal
, s
);
2985 return float32_sub(float32_two
, float32_mul(a
, b
, s
), s
);
2988 float32
HELPER(rsqrts_f32
)(float32 a
, float32 b
, CPUState
*env
)
2990 float_status
*s
= &env
->vfp
.standard_fp_status
;
2992 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
2993 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
2994 if (!(float32_is_zero(a
) || float32_is_zero(b
))) {
2995 float_raise(float_flag_input_denormal
, s
);
2997 return float32_one_point_five
;
2999 product
= float32_mul(a
, b
, s
);
3000 return float32_div(float32_sub(float32_three
, product
, s
), float32_two
, s
);
3005 /* Constants 256 and 512 are used in some helpers; we avoid relying on
3006 * int->float conversions at run-time. */
3007 #define float64_256 make_float64(0x4070000000000000LL)
3008 #define float64_512 make_float64(0x4080000000000000LL)
3010 /* The algorithm that must be used to calculate the estimate
3011 * is specified by the ARM ARM.
3013 static float64
recip_estimate(float64 a
, CPUState
*env
)
3015 /* These calculations mustn't set any fp exception flags,
3016 * so we use a local copy of the fp_status.
3018 float_status dummy_status
= env
->vfp
.standard_fp_status
;
3019 float_status
*s
= &dummy_status
;
3020 /* q = (int)(a * 512.0) */
3021 float64 q
= float64_mul(float64_512
, a
, s
);
3022 int64_t q_int
= float64_to_int64_round_to_zero(q
, s
);
3024 /* r = 1.0 / (((double)q + 0.5) / 512.0) */
3025 q
= int64_to_float64(q_int
, s
);
3026 q
= float64_add(q
, float64_half
, s
);
3027 q
= float64_div(q
, float64_512
, s
);
3028 q
= float64_div(float64_one
, q
, s
);
3030 /* s = (int)(256.0 * r + 0.5) */
3031 q
= float64_mul(q
, float64_256
, s
);
3032 q
= float64_add(q
, float64_half
, s
);
3033 q_int
= float64_to_int64_round_to_zero(q
, s
);
3035 /* return (double)s / 256.0 */
3036 return float64_div(int64_to_float64(q_int
, s
), float64_256
, s
);
3039 float32
HELPER(recpe_f32
)(float32 a
, CPUState
*env
)
3041 float_status
*s
= &env
->vfp
.standard_fp_status
;
3043 uint32_t val32
= float32_val(a
);
3046 int a_exp
= (val32
& 0x7f800000) >> 23;
3047 int sign
= val32
& 0x80000000;
3049 if (float32_is_any_nan(a
)) {
3050 if (float32_is_signaling_nan(a
)) {
3051 float_raise(float_flag_invalid
, s
);
3053 return float32_default_nan
;
3054 } else if (float32_is_infinity(a
)) {
3055 return float32_set_sign(float32_zero
, float32_is_neg(a
));
3056 } else if (float32_is_zero_or_denormal(a
)) {
3057 if (!float32_is_zero(a
)) {
3058 float_raise(float_flag_input_denormal
, s
);
3060 float_raise(float_flag_divbyzero
, s
);
3061 return float32_set_sign(float32_infinity
, float32_is_neg(a
));
3062 } else if (a_exp
>= 253) {
3063 float_raise(float_flag_underflow
, s
);
3064 return float32_set_sign(float32_zero
, float32_is_neg(a
));
3067 f64
= make_float64((0x3feULL
<< 52)
3068 | ((int64_t)(val32
& 0x7fffff) << 29));
3070 result_exp
= 253 - a_exp
;
3072 f64
= recip_estimate(f64
, env
);
3075 | ((result_exp
& 0xff) << 23)
3076 | ((float64_val(f64
) >> 29) & 0x7fffff);
3077 return make_float32(val32
);
3080 /* The algorithm that must be used to calculate the estimate
3081 * is specified by the ARM ARM.
3083 static float64
recip_sqrt_estimate(float64 a
, CPUState
*env
)
3085 /* These calculations mustn't set any fp exception flags,
3086 * so we use a local copy of the fp_status.
3088 float_status dummy_status
= env
->vfp
.standard_fp_status
;
3089 float_status
*s
= &dummy_status
;
3093 if (float64_lt(a
, float64_half
, s
)) {
3094 /* range 0.25 <= a < 0.5 */
3096 /* a in units of 1/512 rounded down */
3097 /* q0 = (int)(a * 512.0); */
3098 q
= float64_mul(float64_512
, a
, s
);
3099 q_int
= float64_to_int64_round_to_zero(q
, s
);
3101 /* reciprocal root r */
3102 /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */
3103 q
= int64_to_float64(q_int
, s
);
3104 q
= float64_add(q
, float64_half
, s
);
3105 q
= float64_div(q
, float64_512
, s
);
3106 q
= float64_sqrt(q
, s
);
3107 q
= float64_div(float64_one
, q
, s
);
3109 /* range 0.5 <= a < 1.0 */
3111 /* a in units of 1/256 rounded down */
3112 /* q1 = (int)(a * 256.0); */
3113 q
= float64_mul(float64_256
, a
, s
);
3114 int64_t q_int
= float64_to_int64_round_to_zero(q
, s
);
3116 /* reciprocal root r */
3117 /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
3118 q
= int64_to_float64(q_int
, s
);
3119 q
= float64_add(q
, float64_half
, s
);
3120 q
= float64_div(q
, float64_256
, s
);
3121 q
= float64_sqrt(q
, s
);
3122 q
= float64_div(float64_one
, q
, s
);
3124 /* r in units of 1/256 rounded to nearest */
3125 /* s = (int)(256.0 * r + 0.5); */
3127 q
= float64_mul(q
, float64_256
,s
);
3128 q
= float64_add(q
, float64_half
, s
);
3129 q_int
= float64_to_int64_round_to_zero(q
, s
);
3131 /* return (double)s / 256.0;*/
3132 return float64_div(int64_to_float64(q_int
, s
), float64_256
, s
);
3135 float32
HELPER(rsqrte_f32
)(float32 a
, CPUState
*env
)
3137 float_status
*s
= &env
->vfp
.standard_fp_status
;
3143 val
= float32_val(a
);
3145 if (float32_is_any_nan(a
)) {
3146 if (float32_is_signaling_nan(a
)) {
3147 float_raise(float_flag_invalid
, s
);
3149 return float32_default_nan
;
3150 } else if (float32_is_zero_or_denormal(a
)) {
3151 if (!float32_is_zero(a
)) {
3152 float_raise(float_flag_input_denormal
, s
);
3154 float_raise(float_flag_divbyzero
, s
);
3155 return float32_set_sign(float32_infinity
, float32_is_neg(a
));
3156 } else if (float32_is_neg(a
)) {
3157 float_raise(float_flag_invalid
, s
);
3158 return float32_default_nan
;
3159 } else if (float32_is_infinity(a
)) {
3160 return float32_zero
;
3163 /* Normalize to a double-precision value between 0.25 and 1.0,
3164 * preserving the parity of the exponent. */
3165 if ((val
& 0x800000) == 0) {
3166 f64
= make_float64(((uint64_t)(val
& 0x80000000) << 32)
3168 | ((uint64_t)(val
& 0x7fffff) << 29));
3170 f64
= make_float64(((uint64_t)(val
& 0x80000000) << 32)
3172 | ((uint64_t)(val
& 0x7fffff) << 29));
3175 result_exp
= (380 - ((val
& 0x7f800000) >> 23)) / 2;
3177 f64
= recip_sqrt_estimate(f64
, env
);
3179 val64
= float64_val(f64
);
3181 val
= ((result_exp
& 0xff) << 23)
3182 | ((val64
>> 29) & 0x7fffff);
3183 return make_float32(val
);
3186 uint32_t HELPER(recpe_u32
)(uint32_t a
, CPUState
*env
)
3190 if ((a
& 0x80000000) == 0) {
3194 f64
= make_float64((0x3feULL
<< 52)
3195 | ((int64_t)(a
& 0x7fffffff) << 21));
3197 f64
= recip_estimate (f64
, env
);
3199 return 0x80000000 | ((float64_val(f64
) >> 21) & 0x7fffffff);
3202 uint32_t HELPER(rsqrte_u32
)(uint32_t a
, CPUState
*env
)
3206 if ((a
& 0xc0000000) == 0) {
3210 if (a
& 0x80000000) {
3211 f64
= make_float64((0x3feULL
<< 52)
3212 | ((uint64_t)(a
& 0x7fffffff) << 21));
3213 } else { /* bits 31-30 == '01' */
3214 f64
= make_float64((0x3fdULL
<< 52)
3215 | ((uint64_t)(a
& 0x3fffffff) << 22));
3218 f64
= recip_sqrt_estimate(f64
, env
);
3220 return 0x80000000 | ((float64_val(f64
) >> 21) & 0x7fffffff);
3223 /* VFPv4 fused multiply-accumulate */
3224 float32
VFP_HELPER(muladd
, s
)(float32 a
, float32 b
, float32 c
, void *fpstp
)
3226 float_status
*fpst
= fpstp
;
3227 return float32_muladd(a
, b
, c
, 0, fpst
);
3230 float64
VFP_HELPER(muladd
, d
)(float64 a
, float64 b
, float64 c
, void *fpstp
)
3232 float_status
*fpst
= fpstp
;
3233 return float64_muladd(a
, b
, c
, 0, fpst
);
3236 void HELPER(set_teecr
)(CPUState
*env
, uint32_t val
)
3239 if (env
->teecr
!= val
) {