2 * i386 CPUID helper functions
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
25 #include "sysemu/kvm.h"
26 #include "sysemu/cpus.h"
30 #include "qemu/option.h"
31 #include "qemu/config-file.h"
32 #include "qapi/qmp/qerror.h"
34 #include "qapi-types.h"
35 #include "qapi-visit.h"
36 #include "qapi/visitor.h"
37 #include "sysemu/arch_init.h"
40 #if defined(CONFIG_KVM)
41 #include <linux/kvm_para.h>
44 #include "sysemu/sysemu.h"
45 #include "hw/qdev-properties.h"
46 #include "hw/cpu/icc_bus.h"
47 #ifndef CONFIG_USER_ONLY
48 #include "hw/xen/xen.h"
49 #include "hw/i386/apic_internal.h"
53 /* Cache topology CPUID constants: */
55 /* CPUID Leaf 2 Descriptors */
57 #define CPUID_2_L1D_32KB_8WAY_64B 0x2c
58 #define CPUID_2_L1I_32KB_8WAY_64B 0x30
59 #define CPUID_2_L2_2MB_8WAY_64B 0x7d
62 /* CPUID Leaf 4 constants: */
65 #define CPUID_4_TYPE_DCACHE 1
66 #define CPUID_4_TYPE_ICACHE 2
67 #define CPUID_4_TYPE_UNIFIED 3
69 #define CPUID_4_LEVEL(l) ((l) << 5)
71 #define CPUID_4_SELF_INIT_LEVEL (1 << 8)
72 #define CPUID_4_FULLY_ASSOC (1 << 9)
75 #define CPUID_4_NO_INVD_SHARING (1 << 0)
76 #define CPUID_4_INCLUSIVE (1 << 1)
77 #define CPUID_4_COMPLEX_IDX (1 << 2)
79 #define ASSOC_FULL 0xFF
81 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */
82 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
92 a == ASSOC_FULL ? 0xF : \
93 0 /* invalid value */)
96 /* Definitions of the hardcoded cache entries we expose: */
99 #define L1D_LINE_SIZE 64
100 #define L1D_ASSOCIATIVITY 8
102 #define L1D_PARTITIONS 1
103 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
104 #define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
105 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
106 #define L1D_LINES_PER_TAG 1
107 #define L1D_SIZE_KB_AMD 64
108 #define L1D_ASSOCIATIVITY_AMD 2
110 /* L1 instruction cache: */
111 #define L1I_LINE_SIZE 64
112 #define L1I_ASSOCIATIVITY 8
114 #define L1I_PARTITIONS 1
115 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
116 #define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
117 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
118 #define L1I_LINES_PER_TAG 1
119 #define L1I_SIZE_KB_AMD 64
120 #define L1I_ASSOCIATIVITY_AMD 2
122 /* Level 2 unified cache: */
123 #define L2_LINE_SIZE 64
124 #define L2_ASSOCIATIVITY 16
126 #define L2_PARTITIONS 1
127 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
128 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
129 #define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
130 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
131 #define L2_LINES_PER_TAG 1
132 #define L2_SIZE_KB_AMD 512
135 #define L3_SIZE_KB 0 /* disabled */
136 #define L3_ASSOCIATIVITY 0 /* disabled */
137 #define L3_LINES_PER_TAG 0 /* disabled */
138 #define L3_LINE_SIZE 0 /* disabled */
140 /* TLB definitions: */
142 #define L1_DTLB_2M_ASSOC 1
143 #define L1_DTLB_2M_ENTRIES 255
144 #define L1_DTLB_4K_ASSOC 1
145 #define L1_DTLB_4K_ENTRIES 255
147 #define L1_ITLB_2M_ASSOC 1
148 #define L1_ITLB_2M_ENTRIES 255
149 #define L1_ITLB_4K_ASSOC 1
150 #define L1_ITLB_4K_ENTRIES 255
152 #define L2_DTLB_2M_ASSOC 0 /* disabled */
153 #define L2_DTLB_2M_ENTRIES 0 /* disabled */
154 #define L2_DTLB_4K_ASSOC 4
155 #define L2_DTLB_4K_ENTRIES 512
157 #define L2_ITLB_2M_ASSOC 0 /* disabled */
158 #define L2_ITLB_2M_ENTRIES 0 /* disabled */
159 #define L2_ITLB_4K_ASSOC 4
160 #define L2_ITLB_4K_ENTRIES 512
164 static void x86_cpu_vendor_words2str(char *dst
, uint32_t vendor1
,
165 uint32_t vendor2
, uint32_t vendor3
)
168 for (i
= 0; i
< 4; i
++) {
169 dst
[i
] = vendor1
>> (8 * i
);
170 dst
[i
+ 4] = vendor2
>> (8 * i
);
171 dst
[i
+ 8] = vendor3
>> (8 * i
);
173 dst
[CPUID_VENDOR_SZ
] = '\0';
176 /* feature flags taken from "Intel Processor Identification and the CPUID
177 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
178 * between feature naming conventions, aliases may be added.
180 static const char *feature_name
[] = {
181 "fpu", "vme", "de", "pse",
182 "tsc", "msr", "pae", "mce",
183 "cx8", "apic", NULL
, "sep",
184 "mtrr", "pge", "mca", "cmov",
185 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
186 NULL
, "ds" /* Intel dts */, "acpi", "mmx",
187 "fxsr", "sse", "sse2", "ss",
188 "ht" /* Intel htt */, "tm", "ia64", "pbe",
190 static const char *ext_feature_name
[] = {
191 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
192 "ds_cpl", "vmx", "smx", "est",
193 "tm2", "ssse3", "cid", NULL
,
194 "fma", "cx16", "xtpr", "pdcm",
195 NULL
, "pcid", "dca", "sse4.1|sse4_1",
196 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
197 "tsc-deadline", "aes", "xsave", "osxsave",
198 "avx", "f16c", "rdrand", "hypervisor",
200 /* Feature names that are already defined on feature_name[] but are set on
201 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
202 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
203 * if and only if CPU vendor is AMD.
205 static const char *ext2_feature_name
[] = {
206 NULL
/* fpu */, NULL
/* vme */, NULL
/* de */, NULL
/* pse */,
207 NULL
/* tsc */, NULL
/* msr */, NULL
/* pae */, NULL
/* mce */,
208 NULL
/* cx8 */ /* AMD CMPXCHG8B */, NULL
/* apic */, NULL
, "syscall",
209 NULL
/* mtrr */, NULL
/* pge */, NULL
/* mca */, NULL
/* cmov */,
210 NULL
/* pat */, NULL
/* pse36 */, NULL
, NULL
/* Linux mp */,
211 "nx|xd", NULL
, "mmxext", NULL
/* mmx */,
212 NULL
/* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
213 NULL
, "lm|i64", "3dnowext", "3dnow",
215 static const char *ext3_feature_name
[] = {
216 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
217 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
218 "3dnowprefetch", "osvw", "ibs", "xop",
219 "skinit", "wdt", NULL
, "lwp",
220 "fma4", "tce", NULL
, "nodeid_msr",
221 NULL
, "tbm", "topoext", "perfctr_core",
222 "perfctr_nb", NULL
, NULL
, NULL
,
223 NULL
, NULL
, NULL
, NULL
,
226 static const char *ext4_feature_name
[] = {
227 NULL
, NULL
, "xstore", "xstore-en",
228 NULL
, NULL
, "xcrypt", "xcrypt-en",
229 "ace2", "ace2-en", "phe", "phe-en",
230 "pmm", "pmm-en", NULL
, NULL
,
231 NULL
, NULL
, NULL
, NULL
,
232 NULL
, NULL
, NULL
, NULL
,
233 NULL
, NULL
, NULL
, NULL
,
234 NULL
, NULL
, NULL
, NULL
,
237 static const char *kvm_feature_name
[] = {
238 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
239 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", "kvm_pv_unhalt",
240 NULL
, NULL
, NULL
, NULL
,
241 NULL
, NULL
, NULL
, NULL
,
242 NULL
, NULL
, NULL
, NULL
,
243 NULL
, NULL
, NULL
, NULL
,
244 NULL
, NULL
, NULL
, NULL
,
245 NULL
, NULL
, NULL
, NULL
,
248 static const char *svm_feature_name
[] = {
249 "npt", "lbrv", "svm_lock", "nrip_save",
250 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
251 NULL
, NULL
, "pause_filter", NULL
,
252 "pfthreshold", NULL
, NULL
, NULL
,
253 NULL
, NULL
, NULL
, NULL
,
254 NULL
, NULL
, NULL
, NULL
,
255 NULL
, NULL
, NULL
, NULL
,
256 NULL
, NULL
, NULL
, NULL
,
259 static const char *cpuid_7_0_ebx_feature_name
[] = {
260 "fsgsbase", NULL
, NULL
, "bmi1", "hle", "avx2", NULL
, "smep",
261 "bmi2", "erms", "invpcid", "rtm", NULL
, NULL
, NULL
, NULL
,
262 NULL
, NULL
, "rdseed", "adx", "smap", NULL
, NULL
, NULL
,
263 NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
266 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
267 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
268 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
269 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
270 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
271 CPUID_PSE36 | CPUID_FXSR)
272 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
273 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
274 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
275 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
276 CPUID_PAE | CPUID_SEP | CPUID_APIC)
278 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
279 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
280 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
281 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
282 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
283 /* partly implemented:
284 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
286 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
287 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
288 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
289 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
290 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
292 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
293 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
294 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
295 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_XSAVE,
296 CPUID_EXT_OSXSAVE, CPUID_EXT_AVX, CPUID_EXT_F16C,
300 #define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
302 #define TCG_EXT2_X86_64_FEATURES 0
305 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
306 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
307 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
308 TCG_EXT2_X86_64_FEATURES)
309 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
310 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
311 #define TCG_EXT4_FEATURES 0
312 #define TCG_SVM_FEATURES 0
313 #define TCG_KVM_FEATURES 0
314 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
315 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX)
317 CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
318 CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
319 CPUID_7_0_EBX_RDSEED */
322 typedef struct FeatureWordInfo
{
323 const char **feat_names
;
324 uint32_t cpuid_eax
; /* Input EAX for CPUID */
325 bool cpuid_needs_ecx
; /* CPUID instruction uses ECX as input */
326 uint32_t cpuid_ecx
; /* Input ECX value for CPUID */
327 int cpuid_reg
; /* output register (R_* constant) */
328 uint32_t tcg_features
; /* Feature flags supported by TCG */
329 uint32_t unmigratable_flags
; /* Feature flags known to be unmigratable */
332 static FeatureWordInfo feature_word_info
[FEATURE_WORDS
] = {
334 .feat_names
= feature_name
,
335 .cpuid_eax
= 1, .cpuid_reg
= R_EDX
,
336 .tcg_features
= TCG_FEATURES
,
339 .feat_names
= ext_feature_name
,
340 .cpuid_eax
= 1, .cpuid_reg
= R_ECX
,
341 .tcg_features
= TCG_EXT_FEATURES
,
343 [FEAT_8000_0001_EDX
] = {
344 .feat_names
= ext2_feature_name
,
345 .cpuid_eax
= 0x80000001, .cpuid_reg
= R_EDX
,
346 .tcg_features
= TCG_EXT2_FEATURES
,
348 [FEAT_8000_0001_ECX
] = {
349 .feat_names
= ext3_feature_name
,
350 .cpuid_eax
= 0x80000001, .cpuid_reg
= R_ECX
,
351 .tcg_features
= TCG_EXT3_FEATURES
,
353 [FEAT_C000_0001_EDX
] = {
354 .feat_names
= ext4_feature_name
,
355 .cpuid_eax
= 0xC0000001, .cpuid_reg
= R_EDX
,
356 .tcg_features
= TCG_EXT4_FEATURES
,
359 .feat_names
= kvm_feature_name
,
360 .cpuid_eax
= KVM_CPUID_FEATURES
, .cpuid_reg
= R_EAX
,
361 .tcg_features
= TCG_KVM_FEATURES
,
364 .feat_names
= svm_feature_name
,
365 .cpuid_eax
= 0x8000000A, .cpuid_reg
= R_EDX
,
366 .tcg_features
= TCG_SVM_FEATURES
,
369 .feat_names
= cpuid_7_0_ebx_feature_name
,
371 .cpuid_needs_ecx
= true, .cpuid_ecx
= 0,
373 .tcg_features
= TCG_7_0_EBX_FEATURES
,
377 typedef struct X86RegisterInfo32
{
378 /* Name of register */
380 /* QAPI enum value register */
381 X86CPURegister32 qapi_enum
;
384 #define REGISTER(reg) \
385 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
386 static const X86RegisterInfo32 x86_reg_info_32
[CPU_NB_REGS32
] = {
398 typedef struct ExtSaveArea
{
399 uint32_t feature
, bits
;
400 uint32_t offset
, size
;
403 static const ExtSaveArea ext_save_areas
[] = {
404 [2] = { .feature
= FEAT_1_ECX
, .bits
= CPUID_EXT_AVX
,
405 .offset
= 0x240, .size
= 0x100 },
406 [3] = { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_MPX
,
407 .offset
= 0x3c0, .size
= 0x40 },
408 [4] = { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_MPX
,
409 .offset
= 0x400, .size
= 0x40 },
412 const char *get_register_name_32(unsigned int reg
)
414 if (reg
>= CPU_NB_REGS32
) {
417 return x86_reg_info_32
[reg
].name
;
420 /* collects per-function cpuid data
422 typedef struct model_features_t
{
423 uint32_t *guest_feat
;
425 FeatureWord feat_word
;
428 /* KVM-specific features that are automatically added to all CPU models
429 * when KVM is enabled.
431 static uint32_t kvm_default_features
[FEATURE_WORDS
] = {
432 [FEAT_KVM
] = (1 << KVM_FEATURE_CLOCKSOURCE
) |
433 (1 << KVM_FEATURE_NOP_IO_DELAY
) |
434 (1 << KVM_FEATURE_CLOCKSOURCE2
) |
435 (1 << KVM_FEATURE_ASYNC_PF
) |
436 (1 << KVM_FEATURE_STEAL_TIME
) |
437 (1 << KVM_FEATURE_PV_EOI
) |
438 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT
),
439 [FEAT_1_ECX
] = CPUID_EXT_X2APIC
,
442 /* Features that are not added by default to any CPU model when KVM is enabled.
444 static uint32_t kvm_default_unset_features
[FEATURE_WORDS
] = {
445 [FEAT_1_ECX
] = CPUID_EXT_MONITOR
,
448 void x86_cpu_compat_disable_kvm_features(FeatureWord w
, uint32_t features
)
450 kvm_default_features
[w
] &= ~features
;
454 * Returns the set of feature flags that are supported and migratable by
455 * QEMU, for a given FeatureWord.
457 static uint32_t x86_cpu_get_migratable_flags(FeatureWord w
)
459 FeatureWordInfo
*wi
= &feature_word_info
[w
];
463 for (i
= 0; i
< 32; i
++) {
464 uint32_t f
= 1U << i
;
465 /* If the feature name is unknown, it is not supported by QEMU yet */
466 if (!wi
->feat_names
[i
]) {
469 /* Skip features known to QEMU, but explicitly marked as unmigratable */
470 if (wi
->unmigratable_flags
& f
) {
478 void host_cpuid(uint32_t function
, uint32_t count
,
479 uint32_t *eax
, uint32_t *ebx
, uint32_t *ecx
, uint32_t *edx
)
485 : "=a"(vec
[0]), "=b"(vec
[1]),
486 "=c"(vec
[2]), "=d"(vec
[3])
487 : "0"(function
), "c"(count
) : "cc");
488 #elif defined(__i386__)
489 asm volatile("pusha \n\t"
491 "mov %%eax, 0(%2) \n\t"
492 "mov %%ebx, 4(%2) \n\t"
493 "mov %%ecx, 8(%2) \n\t"
494 "mov %%edx, 12(%2) \n\t"
496 : : "a"(function
), "c"(count
), "S"(vec
)
512 #define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
514 /* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
515 * a substring. ex if !NULL points to the first char after a substring,
516 * otherwise the string is assumed to sized by a terminating nul.
517 * Return lexical ordering of *s1:*s2.
519 static int sstrcmp(const char *s1
, const char *e1
, const char *s2
,
523 if (!*s1
|| !*s2
|| *s1
!= *s2
)
526 if (s1
== e1
&& s2
== e2
)
535 /* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
536 * '|' delimited (possibly empty) strings in which case search for a match
537 * within the alternatives proceeds left to right. Return 0 for success,
538 * non-zero otherwise.
540 static int altcmp(const char *s
, const char *e
, const char *altstr
)
544 for (q
= p
= altstr
; ; ) {
545 while (*p
&& *p
!= '|')
547 if ((q
== p
&& !*s
) || (q
!= p
&& !sstrcmp(s
, e
, q
, p
)))
556 /* search featureset for flag *[s..e), if found set corresponding bit in
557 * *pval and return true, otherwise return false
559 static bool lookup_feature(uint32_t *pval
, const char *s
, const char *e
,
560 const char **featureset
)
566 for (mask
= 1, ppc
= featureset
; mask
; mask
<<= 1, ++ppc
) {
567 if (*ppc
&& !altcmp(s
, e
, *ppc
)) {
575 static void add_flagname_to_bitmaps(const char *flagname
,
576 FeatureWordArray words
)
579 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
580 FeatureWordInfo
*wi
= &feature_word_info
[w
];
581 if (wi
->feat_names
&&
582 lookup_feature(&words
[w
], flagname
, NULL
, wi
->feat_names
)) {
586 if (w
== FEATURE_WORDS
) {
587 fprintf(stderr
, "CPU feature %s not found\n", flagname
);
591 /* CPU class name definitions: */
593 #define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
594 #define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
596 /* Return type name for a given CPU model name
597 * Caller is responsible for freeing the returned string.
599 static char *x86_cpu_type_name(const char *model_name
)
601 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name
);
604 static ObjectClass
*x86_cpu_class_by_name(const char *cpu_model
)
609 if (cpu_model
== NULL
) {
613 typename
= x86_cpu_type_name(cpu_model
);
614 oc
= object_class_by_name(typename
);
619 struct X86CPUDefinition
{
624 /* vendor is zero-terminated, 12 character ASCII string */
625 char vendor
[CPUID_VENDOR_SZ
+ 1];
629 FeatureWordArray features
;
631 bool cache_info_passthrough
;
634 static X86CPUDefinition builtin_x86_defs
[] = {
638 .vendor
= CPUID_VENDOR_AMD
,
642 .features
[FEAT_1_EDX
] =
644 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
646 .features
[FEAT_1_ECX
] =
647 CPUID_EXT_SSE3
| CPUID_EXT_CX16
| CPUID_EXT_POPCNT
,
648 .features
[FEAT_8000_0001_EDX
] =
649 (PPRO_FEATURES
& CPUID_EXT2_AMD_ALIASES
) |
650 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
651 .features
[FEAT_8000_0001_ECX
] =
652 CPUID_EXT3_LAHF_LM
| CPUID_EXT3_SVM
|
653 CPUID_EXT3_ABM
| CPUID_EXT3_SSE4A
,
654 .xlevel
= 0x8000000A,
659 .vendor
= CPUID_VENDOR_AMD
,
663 .features
[FEAT_1_EDX
] =
665 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
666 CPUID_PSE36
| CPUID_VME
| CPUID_HT
,
667 .features
[FEAT_1_ECX
] =
668 CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_CX16
|
670 .features
[FEAT_8000_0001_EDX
] =
671 (PPRO_FEATURES
& CPUID_EXT2_AMD_ALIASES
) |
672 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
|
673 CPUID_EXT2_3DNOW
| CPUID_EXT2_3DNOWEXT
| CPUID_EXT2_MMXEXT
|
674 CPUID_EXT2_FFXSR
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_RDTSCP
,
675 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
677 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
678 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
679 .features
[FEAT_8000_0001_ECX
] =
680 CPUID_EXT3_LAHF_LM
| CPUID_EXT3_SVM
|
681 CPUID_EXT3_ABM
| CPUID_EXT3_SSE4A
,
682 .features
[FEAT_SVM
] =
683 CPUID_SVM_NPT
| CPUID_SVM_LBRV
,
684 .xlevel
= 0x8000001A,
685 .model_id
= "AMD Phenom(tm) 9550 Quad-Core Processor"
690 .vendor
= CPUID_VENDOR_INTEL
,
694 .features
[FEAT_1_EDX
] =
696 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
697 CPUID_PSE36
| CPUID_VME
| CPUID_DTS
| CPUID_ACPI
| CPUID_SS
|
698 CPUID_HT
| CPUID_TM
| CPUID_PBE
,
699 .features
[FEAT_1_ECX
] =
700 CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_SSSE3
|
701 CPUID_EXT_DTES64
| CPUID_EXT_DSCPL
| CPUID_EXT_VMX
| CPUID_EXT_EST
|
702 CPUID_EXT_TM2
| CPUID_EXT_CX16
| CPUID_EXT_XTPR
| CPUID_EXT_PDCM
,
703 .features
[FEAT_8000_0001_EDX
] =
704 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
705 .features
[FEAT_8000_0001_ECX
] =
707 .xlevel
= 0x80000008,
708 .model_id
= "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
713 .vendor
= CPUID_VENDOR_INTEL
,
717 /* Missing: CPUID_VME, CPUID_HT */
718 .features
[FEAT_1_EDX
] =
720 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
722 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
723 .features
[FEAT_1_ECX
] =
724 CPUID_EXT_SSE3
| CPUID_EXT_CX16
,
725 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
726 .features
[FEAT_8000_0001_EDX
] =
727 (PPRO_FEATURES
& CPUID_EXT2_AMD_ALIASES
) |
728 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
729 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
730 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
731 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
732 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
733 .features
[FEAT_8000_0001_ECX
] =
735 .xlevel
= 0x80000008,
736 .model_id
= "Common KVM processor"
741 .vendor
= CPUID_VENDOR_INTEL
,
745 .features
[FEAT_1_EDX
] =
747 .features
[FEAT_1_ECX
] =
748 CPUID_EXT_SSE3
| CPUID_EXT_POPCNT
,
749 .xlevel
= 0x80000004,
754 .vendor
= CPUID_VENDOR_INTEL
,
758 .features
[FEAT_1_EDX
] =
760 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
| CPUID_PSE36
,
761 .features
[FEAT_1_ECX
] =
763 .features
[FEAT_8000_0001_EDX
] =
764 PPRO_FEATURES
& CPUID_EXT2_AMD_ALIASES
,
765 .features
[FEAT_8000_0001_ECX
] =
767 .xlevel
= 0x80000008,
768 .model_id
= "Common 32-bit KVM processor"
773 .vendor
= CPUID_VENDOR_INTEL
,
777 .features
[FEAT_1_EDX
] =
778 PPRO_FEATURES
| CPUID_VME
|
779 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
| CPUID_DTS
| CPUID_ACPI
|
780 CPUID_SS
| CPUID_HT
| CPUID_TM
| CPUID_PBE
,
781 .features
[FEAT_1_ECX
] =
782 CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_VMX
|
783 CPUID_EXT_EST
| CPUID_EXT_TM2
| CPUID_EXT_XTPR
| CPUID_EXT_PDCM
,
784 .features
[FEAT_8000_0001_EDX
] =
786 .xlevel
= 0x80000008,
787 .model_id
= "Genuine Intel(R) CPU T2600 @ 2.16GHz",
792 .vendor
= CPUID_VENDOR_INTEL
,
796 .features
[FEAT_1_EDX
] =
803 .vendor
= CPUID_VENDOR_INTEL
,
807 .features
[FEAT_1_EDX
] =
814 .vendor
= CPUID_VENDOR_INTEL
,
818 .features
[FEAT_1_EDX
] =
825 .vendor
= CPUID_VENDOR_INTEL
,
829 .features
[FEAT_1_EDX
] =
836 .vendor
= CPUID_VENDOR_AMD
,
840 .features
[FEAT_1_EDX
] =
841 PPRO_FEATURES
| CPUID_PSE36
| CPUID_VME
| CPUID_MTRR
|
843 .features
[FEAT_8000_0001_EDX
] =
844 (PPRO_FEATURES
& CPUID_EXT2_AMD_ALIASES
) |
845 CPUID_EXT2_MMXEXT
| CPUID_EXT2_3DNOW
| CPUID_EXT2_3DNOWEXT
,
846 .xlevel
= 0x80000008,
850 /* original is on level 10 */
852 .vendor
= CPUID_VENDOR_INTEL
,
856 .features
[FEAT_1_EDX
] =
858 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
| CPUID_VME
| CPUID_DTS
|
859 CPUID_ACPI
| CPUID_SS
| CPUID_HT
| CPUID_TM
| CPUID_PBE
,
860 /* Some CPUs got no CPUID_SEP */
861 .features
[FEAT_1_ECX
] =
862 CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_SSSE3
|
863 CPUID_EXT_DSCPL
| CPUID_EXT_EST
| CPUID_EXT_TM2
| CPUID_EXT_XTPR
|
865 .features
[FEAT_8000_0001_EDX
] =
866 (PPRO_FEATURES
& CPUID_EXT2_AMD_ALIASES
) |
868 .features
[FEAT_8000_0001_ECX
] =
870 .xlevel
= 0x8000000A,
871 .model_id
= "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
876 .vendor
= CPUID_VENDOR_INTEL
,
880 .features
[FEAT_1_EDX
] =
881 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
882 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
883 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
884 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
885 CPUID_DE
| CPUID_FP87
,
886 .features
[FEAT_1_ECX
] =
887 CPUID_EXT_SSSE3
| CPUID_EXT_SSE3
,
888 .features
[FEAT_8000_0001_EDX
] =
889 CPUID_EXT2_LM
| CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
890 .features
[FEAT_8000_0001_ECX
] =
892 .xlevel
= 0x8000000A,
893 .model_id
= "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
898 .vendor
= CPUID_VENDOR_INTEL
,
902 .features
[FEAT_1_EDX
] =
903 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
904 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
905 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
906 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
907 CPUID_DE
| CPUID_FP87
,
908 .features
[FEAT_1_ECX
] =
909 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
911 .features
[FEAT_8000_0001_EDX
] =
912 CPUID_EXT2_LM
| CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
913 .features
[FEAT_8000_0001_ECX
] =
915 .xlevel
= 0x8000000A,
916 .model_id
= "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
921 .vendor
= CPUID_VENDOR_INTEL
,
925 .features
[FEAT_1_EDX
] =
926 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
927 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
928 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
929 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
930 CPUID_DE
| CPUID_FP87
,
931 .features
[FEAT_1_ECX
] =
932 CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
933 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_SSE3
,
934 .features
[FEAT_8000_0001_EDX
] =
935 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
936 .features
[FEAT_8000_0001_ECX
] =
938 .xlevel
= 0x8000000A,
939 .model_id
= "Intel Core i7 9xx (Nehalem Class Core i7)",
944 .vendor
= CPUID_VENDOR_INTEL
,
948 .features
[FEAT_1_EDX
] =
949 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
950 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
951 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
952 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
953 CPUID_DE
| CPUID_FP87
,
954 .features
[FEAT_1_ECX
] =
955 CPUID_EXT_AES
| CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
|
956 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
957 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
,
958 .features
[FEAT_8000_0001_EDX
] =
959 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
960 .features
[FEAT_8000_0001_ECX
] =
962 .xlevel
= 0x8000000A,
963 .model_id
= "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
966 .name
= "SandyBridge",
968 .vendor
= CPUID_VENDOR_INTEL
,
972 .features
[FEAT_1_EDX
] =
973 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
974 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
975 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
976 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
977 CPUID_DE
| CPUID_FP87
,
978 .features
[FEAT_1_ECX
] =
979 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
980 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_POPCNT
|
981 CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
982 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
|
984 .features
[FEAT_8000_0001_EDX
] =
985 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
987 .features
[FEAT_8000_0001_ECX
] =
989 .xlevel
= 0x8000000A,
990 .model_id
= "Intel Xeon E312xx (Sandy Bridge)",
995 .vendor
= CPUID_VENDOR_INTEL
,
999 .features
[FEAT_1_EDX
] =
1000 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1001 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1002 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1003 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1004 CPUID_DE
| CPUID_FP87
,
1005 .features
[FEAT_1_ECX
] =
1006 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1007 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
1008 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1009 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
1010 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
1012 .features
[FEAT_8000_0001_EDX
] =
1013 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1015 .features
[FEAT_8000_0001_ECX
] =
1017 .features
[FEAT_7_0_EBX
] =
1018 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
1019 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
1020 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
1022 .xlevel
= 0x8000000A,
1023 .model_id
= "Intel Core Processor (Haswell)",
1026 .name
= "Opteron_G1",
1028 .vendor
= CPUID_VENDOR_AMD
,
1032 .features
[FEAT_1_EDX
] =
1033 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1034 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1035 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1036 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1037 CPUID_DE
| CPUID_FP87
,
1038 .features
[FEAT_1_ECX
] =
1040 .features
[FEAT_8000_0001_EDX
] =
1041 CPUID_EXT2_LM
| CPUID_EXT2_FXSR
| CPUID_EXT2_MMX
|
1042 CPUID_EXT2_NX
| CPUID_EXT2_PSE36
| CPUID_EXT2_PAT
|
1043 CPUID_EXT2_CMOV
| CPUID_EXT2_MCA
| CPUID_EXT2_PGE
|
1044 CPUID_EXT2_MTRR
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_APIC
|
1045 CPUID_EXT2_CX8
| CPUID_EXT2_MCE
| CPUID_EXT2_PAE
| CPUID_EXT2_MSR
|
1046 CPUID_EXT2_TSC
| CPUID_EXT2_PSE
| CPUID_EXT2_DE
| CPUID_EXT2_FPU
,
1047 .xlevel
= 0x80000008,
1048 .model_id
= "AMD Opteron 240 (Gen 1 Class Opteron)",
1051 .name
= "Opteron_G2",
1053 .vendor
= CPUID_VENDOR_AMD
,
1057 .features
[FEAT_1_EDX
] =
1058 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1059 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1060 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1061 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1062 CPUID_DE
| CPUID_FP87
,
1063 .features
[FEAT_1_ECX
] =
1064 CPUID_EXT_CX16
| CPUID_EXT_SSE3
,
1065 .features
[FEAT_8000_0001_EDX
] =
1066 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_FXSR
|
1067 CPUID_EXT2_MMX
| CPUID_EXT2_NX
| CPUID_EXT2_PSE36
|
1068 CPUID_EXT2_PAT
| CPUID_EXT2_CMOV
| CPUID_EXT2_MCA
|
1069 CPUID_EXT2_PGE
| CPUID_EXT2_MTRR
| CPUID_EXT2_SYSCALL
|
1070 CPUID_EXT2_APIC
| CPUID_EXT2_CX8
| CPUID_EXT2_MCE
|
1071 CPUID_EXT2_PAE
| CPUID_EXT2_MSR
| CPUID_EXT2_TSC
| CPUID_EXT2_PSE
|
1072 CPUID_EXT2_DE
| CPUID_EXT2_FPU
,
1073 .features
[FEAT_8000_0001_ECX
] =
1074 CPUID_EXT3_SVM
| CPUID_EXT3_LAHF_LM
,
1075 .xlevel
= 0x80000008,
1076 .model_id
= "AMD Opteron 22xx (Gen 2 Class Opteron)",
1079 .name
= "Opteron_G3",
1081 .vendor
= CPUID_VENDOR_AMD
,
1085 .features
[FEAT_1_EDX
] =
1086 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1087 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1088 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1089 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1090 CPUID_DE
| CPUID_FP87
,
1091 .features
[FEAT_1_ECX
] =
1092 CPUID_EXT_POPCNT
| CPUID_EXT_CX16
| CPUID_EXT_MONITOR
|
1094 .features
[FEAT_8000_0001_EDX
] =
1095 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_FXSR
|
1096 CPUID_EXT2_MMX
| CPUID_EXT2_NX
| CPUID_EXT2_PSE36
|
1097 CPUID_EXT2_PAT
| CPUID_EXT2_CMOV
| CPUID_EXT2_MCA
|
1098 CPUID_EXT2_PGE
| CPUID_EXT2_MTRR
| CPUID_EXT2_SYSCALL
|
1099 CPUID_EXT2_APIC
| CPUID_EXT2_CX8
| CPUID_EXT2_MCE
|
1100 CPUID_EXT2_PAE
| CPUID_EXT2_MSR
| CPUID_EXT2_TSC
| CPUID_EXT2_PSE
|
1101 CPUID_EXT2_DE
| CPUID_EXT2_FPU
,
1102 .features
[FEAT_8000_0001_ECX
] =
1103 CPUID_EXT3_MISALIGNSSE
| CPUID_EXT3_SSE4A
|
1104 CPUID_EXT3_ABM
| CPUID_EXT3_SVM
| CPUID_EXT3_LAHF_LM
,
1105 .xlevel
= 0x80000008,
1106 .model_id
= "AMD Opteron 23xx (Gen 3 Class Opteron)",
1109 .name
= "Opteron_G4",
1111 .vendor
= CPUID_VENDOR_AMD
,
1115 .features
[FEAT_1_EDX
] =
1116 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1117 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1118 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1119 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1120 CPUID_DE
| CPUID_FP87
,
1121 .features
[FEAT_1_ECX
] =
1122 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1123 CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
1124 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
|
1126 .features
[FEAT_8000_0001_EDX
] =
1127 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
|
1128 CPUID_EXT2_PDPE1GB
| CPUID_EXT2_FXSR
| CPUID_EXT2_MMX
|
1129 CPUID_EXT2_NX
| CPUID_EXT2_PSE36
| CPUID_EXT2_PAT
|
1130 CPUID_EXT2_CMOV
| CPUID_EXT2_MCA
| CPUID_EXT2_PGE
|
1131 CPUID_EXT2_MTRR
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_APIC
|
1132 CPUID_EXT2_CX8
| CPUID_EXT2_MCE
| CPUID_EXT2_PAE
| CPUID_EXT2_MSR
|
1133 CPUID_EXT2_TSC
| CPUID_EXT2_PSE
| CPUID_EXT2_DE
| CPUID_EXT2_FPU
,
1134 .features
[FEAT_8000_0001_ECX
] =
1135 CPUID_EXT3_FMA4
| CPUID_EXT3_XOP
|
1136 CPUID_EXT3_3DNOWPREFETCH
| CPUID_EXT3_MISALIGNSSE
|
1137 CPUID_EXT3_SSE4A
| CPUID_EXT3_ABM
| CPUID_EXT3_SVM
|
1139 .xlevel
= 0x8000001A,
1140 .model_id
= "AMD Opteron 62xx class CPU",
1143 .name
= "Opteron_G5",
1145 .vendor
= CPUID_VENDOR_AMD
,
1149 .features
[FEAT_1_EDX
] =
1150 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1151 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1152 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1153 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1154 CPUID_DE
| CPUID_FP87
,
1155 .features
[FEAT_1_ECX
] =
1156 CPUID_EXT_F16C
| CPUID_EXT_AVX
| CPUID_EXT_XSAVE
|
1157 CPUID_EXT_AES
| CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
|
1158 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_FMA
|
1159 CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
,
1160 .features
[FEAT_8000_0001_EDX
] =
1161 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
|
1162 CPUID_EXT2_PDPE1GB
| CPUID_EXT2_FXSR
| CPUID_EXT2_MMX
|
1163 CPUID_EXT2_NX
| CPUID_EXT2_PSE36
| CPUID_EXT2_PAT
|
1164 CPUID_EXT2_CMOV
| CPUID_EXT2_MCA
| CPUID_EXT2_PGE
|
1165 CPUID_EXT2_MTRR
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_APIC
|
1166 CPUID_EXT2_CX8
| CPUID_EXT2_MCE
| CPUID_EXT2_PAE
| CPUID_EXT2_MSR
|
1167 CPUID_EXT2_TSC
| CPUID_EXT2_PSE
| CPUID_EXT2_DE
| CPUID_EXT2_FPU
,
1168 .features
[FEAT_8000_0001_ECX
] =
1169 CPUID_EXT3_TBM
| CPUID_EXT3_FMA4
| CPUID_EXT3_XOP
|
1170 CPUID_EXT3_3DNOWPREFETCH
| CPUID_EXT3_MISALIGNSSE
|
1171 CPUID_EXT3_SSE4A
| CPUID_EXT3_ABM
| CPUID_EXT3_SVM
|
1173 .xlevel
= 0x8000001A,
1174 .model_id
= "AMD Opteron 63xx class CPU",
1179 * x86_cpu_compat_set_features:
1180 * @cpu_model: CPU model name to be changed. If NULL, all CPU models are changed
1181 * @w: Identifies the feature word to be changed.
1182 * @feat_add: Feature bits to be added to feature word
1183 * @feat_remove: Feature bits to be removed from feature word
1185 * Change CPU model feature bits for compatibility.
1187 * This function may be used by machine-type compatibility functions
1188 * to enable or disable feature bits on specific CPU models.
1190 void x86_cpu_compat_set_features(const char *cpu_model
, FeatureWord w
,
1191 uint32_t feat_add
, uint32_t feat_remove
)
1193 X86CPUDefinition
*def
;
1195 for (i
= 0; i
< ARRAY_SIZE(builtin_x86_defs
); i
++) {
1196 def
= &builtin_x86_defs
[i
];
1197 if (!cpu_model
|| !strcmp(cpu_model
, def
->name
)) {
1198 def
->features
[w
] |= feat_add
;
1199 def
->features
[w
] &= ~feat_remove
;
1206 static int cpu_x86_fill_model_id(char *str
)
1208 uint32_t eax
= 0, ebx
= 0, ecx
= 0, edx
= 0;
1211 for (i
= 0; i
< 3; i
++) {
1212 host_cpuid(0x80000002 + i
, 0, &eax
, &ebx
, &ecx
, &edx
);
1213 memcpy(str
+ i
* 16 + 0, &eax
, 4);
1214 memcpy(str
+ i
* 16 + 4, &ebx
, 4);
1215 memcpy(str
+ i
* 16 + 8, &ecx
, 4);
1216 memcpy(str
+ i
* 16 + 12, &edx
, 4);
1221 static X86CPUDefinition host_cpudef
;
1223 static Property host_x86_cpu_properties
[] = {
1224 DEFINE_PROP_BOOL("migratable", X86CPU
, migratable
, true),
1225 DEFINE_PROP_END_OF_LIST()
1228 /* class_init for the "host" CPU model
1230 * This function may be called before KVM is initialized.
1232 static void host_x86_cpu_class_init(ObjectClass
*oc
, void *data
)
1234 DeviceClass
*dc
= DEVICE_CLASS(oc
);
1235 X86CPUClass
*xcc
= X86_CPU_CLASS(oc
);
1236 uint32_t eax
= 0, ebx
= 0, ecx
= 0, edx
= 0;
1238 xcc
->kvm_required
= true;
1240 host_cpuid(0x0, 0, &eax
, &ebx
, &ecx
, &edx
);
1241 x86_cpu_vendor_words2str(host_cpudef
.vendor
, ebx
, edx
, ecx
);
1243 host_cpuid(0x1, 0, &eax
, &ebx
, &ecx
, &edx
);
1244 host_cpudef
.family
= ((eax
>> 8) & 0x0F) + ((eax
>> 20) & 0xFF);
1245 host_cpudef
.model
= ((eax
>> 4) & 0x0F) | ((eax
& 0xF0000) >> 12);
1246 host_cpudef
.stepping
= eax
& 0x0F;
1248 cpu_x86_fill_model_id(host_cpudef
.model_id
);
1250 xcc
->cpu_def
= &host_cpudef
;
1251 host_cpudef
.cache_info_passthrough
= true;
1253 /* level, xlevel, xlevel2, and the feature words are initialized on
1254 * instance_init, because they require KVM to be initialized.
1257 dc
->props
= host_x86_cpu_properties
;
1260 static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w
,
1261 bool migratable_only
);
1263 static void host_x86_cpu_initfn(Object
*obj
)
1265 X86CPU
*cpu
= X86_CPU(obj
);
1266 CPUX86State
*env
= &cpu
->env
;
1267 KVMState
*s
= kvm_state
;
1270 assert(kvm_enabled());
1272 env
->cpuid_level
= kvm_arch_get_supported_cpuid(s
, 0x0, 0, R_EAX
);
1273 env
->cpuid_xlevel
= kvm_arch_get_supported_cpuid(s
, 0x80000000, 0, R_EAX
);
1274 env
->cpuid_xlevel2
= kvm_arch_get_supported_cpuid(s
, 0xC0000000, 0, R_EAX
);
1276 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
1278 x86_cpu_get_supported_feature_word(w
, cpu
->migratable
);
1280 object_property_set_bool(OBJECT(cpu
), true, "pmu", &error_abort
);
1283 static const TypeInfo host_x86_cpu_type_info
= {
1284 .name
= X86_CPU_TYPE_NAME("host"),
1285 .parent
= TYPE_X86_CPU
,
1286 .instance_init
= host_x86_cpu_initfn
,
1287 .class_init
= host_x86_cpu_class_init
,
1292 static void report_unavailable_features(FeatureWord w
, uint32_t mask
)
1294 FeatureWordInfo
*f
= &feature_word_info
[w
];
1297 for (i
= 0; i
< 32; ++i
) {
1298 if (1 << i
& mask
) {
1299 const char *reg
= get_register_name_32(f
->cpuid_reg
);
1301 fprintf(stderr
, "warning: %s doesn't support requested feature: "
1302 "CPUID.%02XH:%s%s%s [bit %d]\n",
1303 kvm_enabled() ? "host" : "TCG",
1305 f
->feat_names
[i
] ? "." : "",
1306 f
->feat_names
[i
] ? f
->feat_names
[i
] : "", i
);
1311 static void x86_cpuid_version_get_family(Object
*obj
, Visitor
*v
, void *opaque
,
1312 const char *name
, Error
**errp
)
1314 X86CPU
*cpu
= X86_CPU(obj
);
1315 CPUX86State
*env
= &cpu
->env
;
1318 value
= (env
->cpuid_version
>> 8) & 0xf;
1320 value
+= (env
->cpuid_version
>> 20) & 0xff;
1322 visit_type_int(v
, &value
, name
, errp
);
1325 static void x86_cpuid_version_set_family(Object
*obj
, Visitor
*v
, void *opaque
,
1326 const char *name
, Error
**errp
)
1328 X86CPU
*cpu
= X86_CPU(obj
);
1329 CPUX86State
*env
= &cpu
->env
;
1330 const int64_t min
= 0;
1331 const int64_t max
= 0xff + 0xf;
1332 Error
*local_err
= NULL
;
1335 visit_type_int(v
, &value
, name
, &local_err
);
1337 error_propagate(errp
, local_err
);
1340 if (value
< min
|| value
> max
) {
1341 error_set(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
1342 name
? name
: "null", value
, min
, max
);
1346 env
->cpuid_version
&= ~0xff00f00;
1348 env
->cpuid_version
|= 0xf00 | ((value
- 0x0f) << 20);
1350 env
->cpuid_version
|= value
<< 8;
1354 static void x86_cpuid_version_get_model(Object
*obj
, Visitor
*v
, void *opaque
,
1355 const char *name
, Error
**errp
)
1357 X86CPU
*cpu
= X86_CPU(obj
);
1358 CPUX86State
*env
= &cpu
->env
;
1361 value
= (env
->cpuid_version
>> 4) & 0xf;
1362 value
|= ((env
->cpuid_version
>> 16) & 0xf) << 4;
1363 visit_type_int(v
, &value
, name
, errp
);
1366 static void x86_cpuid_version_set_model(Object
*obj
, Visitor
*v
, void *opaque
,
1367 const char *name
, Error
**errp
)
1369 X86CPU
*cpu
= X86_CPU(obj
);
1370 CPUX86State
*env
= &cpu
->env
;
1371 const int64_t min
= 0;
1372 const int64_t max
= 0xff;
1373 Error
*local_err
= NULL
;
1376 visit_type_int(v
, &value
, name
, &local_err
);
1378 error_propagate(errp
, local_err
);
1381 if (value
< min
|| value
> max
) {
1382 error_set(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
1383 name
? name
: "null", value
, min
, max
);
1387 env
->cpuid_version
&= ~0xf00f0;
1388 env
->cpuid_version
|= ((value
& 0xf) << 4) | ((value
>> 4) << 16);
1391 static void x86_cpuid_version_get_stepping(Object
*obj
, Visitor
*v
,
1392 void *opaque
, const char *name
,
1395 X86CPU
*cpu
= X86_CPU(obj
);
1396 CPUX86State
*env
= &cpu
->env
;
1399 value
= env
->cpuid_version
& 0xf;
1400 visit_type_int(v
, &value
, name
, errp
);
1403 static void x86_cpuid_version_set_stepping(Object
*obj
, Visitor
*v
,
1404 void *opaque
, const char *name
,
1407 X86CPU
*cpu
= X86_CPU(obj
);
1408 CPUX86State
*env
= &cpu
->env
;
1409 const int64_t min
= 0;
1410 const int64_t max
= 0xf;
1411 Error
*local_err
= NULL
;
1414 visit_type_int(v
, &value
, name
, &local_err
);
1416 error_propagate(errp
, local_err
);
1419 if (value
< min
|| value
> max
) {
1420 error_set(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
1421 name
? name
: "null", value
, min
, max
);
1425 env
->cpuid_version
&= ~0xf;
1426 env
->cpuid_version
|= value
& 0xf;
1429 static void x86_cpuid_get_level(Object
*obj
, Visitor
*v
, void *opaque
,
1430 const char *name
, Error
**errp
)
1432 X86CPU
*cpu
= X86_CPU(obj
);
1434 visit_type_uint32(v
, &cpu
->env
.cpuid_level
, name
, errp
);
1437 static void x86_cpuid_set_level(Object
*obj
, Visitor
*v
, void *opaque
,
1438 const char *name
, Error
**errp
)
1440 X86CPU
*cpu
= X86_CPU(obj
);
1442 visit_type_uint32(v
, &cpu
->env
.cpuid_level
, name
, errp
);
1445 static void x86_cpuid_get_xlevel(Object
*obj
, Visitor
*v
, void *opaque
,
1446 const char *name
, Error
**errp
)
1448 X86CPU
*cpu
= X86_CPU(obj
);
1450 visit_type_uint32(v
, &cpu
->env
.cpuid_xlevel
, name
, errp
);
1453 static void x86_cpuid_set_xlevel(Object
*obj
, Visitor
*v
, void *opaque
,
1454 const char *name
, Error
**errp
)
1456 X86CPU
*cpu
= X86_CPU(obj
);
1458 visit_type_uint32(v
, &cpu
->env
.cpuid_xlevel
, name
, errp
);
1461 static char *x86_cpuid_get_vendor(Object
*obj
, Error
**errp
)
1463 X86CPU
*cpu
= X86_CPU(obj
);
1464 CPUX86State
*env
= &cpu
->env
;
1467 value
= (char *)g_malloc(CPUID_VENDOR_SZ
+ 1);
1468 x86_cpu_vendor_words2str(value
, env
->cpuid_vendor1
, env
->cpuid_vendor2
,
1469 env
->cpuid_vendor3
);
1473 static void x86_cpuid_set_vendor(Object
*obj
, const char *value
,
1476 X86CPU
*cpu
= X86_CPU(obj
);
1477 CPUX86State
*env
= &cpu
->env
;
1480 if (strlen(value
) != CPUID_VENDOR_SZ
) {
1481 error_set(errp
, QERR_PROPERTY_VALUE_BAD
, "",
1486 env
->cpuid_vendor1
= 0;
1487 env
->cpuid_vendor2
= 0;
1488 env
->cpuid_vendor3
= 0;
1489 for (i
= 0; i
< 4; i
++) {
1490 env
->cpuid_vendor1
|= ((uint8_t)value
[i
]) << (8 * i
);
1491 env
->cpuid_vendor2
|= ((uint8_t)value
[i
+ 4]) << (8 * i
);
1492 env
->cpuid_vendor3
|= ((uint8_t)value
[i
+ 8]) << (8 * i
);
1496 static char *x86_cpuid_get_model_id(Object
*obj
, Error
**errp
)
1498 X86CPU
*cpu
= X86_CPU(obj
);
1499 CPUX86State
*env
= &cpu
->env
;
1503 value
= g_malloc(48 + 1);
1504 for (i
= 0; i
< 48; i
++) {
1505 value
[i
] = env
->cpuid_model
[i
>> 2] >> (8 * (i
& 3));
1511 static void x86_cpuid_set_model_id(Object
*obj
, const char *model_id
,
1514 X86CPU
*cpu
= X86_CPU(obj
);
1515 CPUX86State
*env
= &cpu
->env
;
1518 if (model_id
== NULL
) {
1521 len
= strlen(model_id
);
1522 memset(env
->cpuid_model
, 0, 48);
1523 for (i
= 0; i
< 48; i
++) {
1527 c
= (uint8_t)model_id
[i
];
1529 env
->cpuid_model
[i
>> 2] |= c
<< (8 * (i
& 3));
1533 static void x86_cpuid_get_tsc_freq(Object
*obj
, Visitor
*v
, void *opaque
,
1534 const char *name
, Error
**errp
)
1536 X86CPU
*cpu
= X86_CPU(obj
);
1539 value
= cpu
->env
.tsc_khz
* 1000;
1540 visit_type_int(v
, &value
, name
, errp
);
1543 static void x86_cpuid_set_tsc_freq(Object
*obj
, Visitor
*v
, void *opaque
,
1544 const char *name
, Error
**errp
)
1546 X86CPU
*cpu
= X86_CPU(obj
);
1547 const int64_t min
= 0;
1548 const int64_t max
= INT64_MAX
;
1549 Error
*local_err
= NULL
;
1552 visit_type_int(v
, &value
, name
, &local_err
);
1554 error_propagate(errp
, local_err
);
1557 if (value
< min
|| value
> max
) {
1558 error_set(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
1559 name
? name
: "null", value
, min
, max
);
1563 cpu
->env
.tsc_khz
= value
/ 1000;
1566 static void x86_cpuid_get_apic_id(Object
*obj
, Visitor
*v
, void *opaque
,
1567 const char *name
, Error
**errp
)
1569 X86CPU
*cpu
= X86_CPU(obj
);
1570 int64_t value
= cpu
->env
.cpuid_apic_id
;
1572 visit_type_int(v
, &value
, name
, errp
);
1575 static void x86_cpuid_set_apic_id(Object
*obj
, Visitor
*v
, void *opaque
,
1576 const char *name
, Error
**errp
)
1578 X86CPU
*cpu
= X86_CPU(obj
);
1579 DeviceState
*dev
= DEVICE(obj
);
1580 const int64_t min
= 0;
1581 const int64_t max
= UINT32_MAX
;
1582 Error
*error
= NULL
;
1585 if (dev
->realized
) {
1586 error_setg(errp
, "Attempt to set property '%s' on '%s' after "
1587 "it was realized", name
, object_get_typename(obj
));
1591 visit_type_int(v
, &value
, name
, &error
);
1593 error_propagate(errp
, error
);
1596 if (value
< min
|| value
> max
) {
1597 error_setg(errp
, "Property %s.%s doesn't take value %" PRId64
1598 " (minimum: %" PRId64
", maximum: %" PRId64
")" ,
1599 object_get_typename(obj
), name
, value
, min
, max
);
1603 if ((value
!= cpu
->env
.cpuid_apic_id
) && cpu_exists(value
)) {
1604 error_setg(errp
, "CPU with APIC ID %" PRIi64
" exists", value
);
1607 cpu
->env
.cpuid_apic_id
= value
;
1610 /* Generic getter for "feature-words" and "filtered-features" properties */
1611 static void x86_cpu_get_feature_words(Object
*obj
, Visitor
*v
, void *opaque
,
1612 const char *name
, Error
**errp
)
1614 uint32_t *array
= (uint32_t *)opaque
;
1617 X86CPUFeatureWordInfo word_infos
[FEATURE_WORDS
] = { };
1618 X86CPUFeatureWordInfoList list_entries
[FEATURE_WORDS
] = { };
1619 X86CPUFeatureWordInfoList
*list
= NULL
;
1621 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
1622 FeatureWordInfo
*wi
= &feature_word_info
[w
];
1623 X86CPUFeatureWordInfo
*qwi
= &word_infos
[w
];
1624 qwi
->cpuid_input_eax
= wi
->cpuid_eax
;
1625 qwi
->has_cpuid_input_ecx
= wi
->cpuid_needs_ecx
;
1626 qwi
->cpuid_input_ecx
= wi
->cpuid_ecx
;
1627 qwi
->cpuid_register
= x86_reg_info_32
[wi
->cpuid_reg
].qapi_enum
;
1628 qwi
->features
= array
[w
];
1630 /* List will be in reverse order, but order shouldn't matter */
1631 list_entries
[w
].next
= list
;
1632 list_entries
[w
].value
= &word_infos
[w
];
1633 list
= &list_entries
[w
];
1636 visit_type_X86CPUFeatureWordInfoList(v
, &list
, "feature-words", &err
);
1637 error_propagate(errp
, err
);
1640 static void x86_get_hv_spinlocks(Object
*obj
, Visitor
*v
, void *opaque
,
1641 const char *name
, Error
**errp
)
1643 X86CPU
*cpu
= X86_CPU(obj
);
1644 int64_t value
= cpu
->hyperv_spinlock_attempts
;
1646 visit_type_int(v
, &value
, name
, errp
);
1649 static void x86_set_hv_spinlocks(Object
*obj
, Visitor
*v
, void *opaque
,
1650 const char *name
, Error
**errp
)
1652 const int64_t min
= 0xFFF;
1653 const int64_t max
= UINT_MAX
;
1654 X86CPU
*cpu
= X86_CPU(obj
);
1658 visit_type_int(v
, &value
, name
, &err
);
1660 error_propagate(errp
, err
);
1664 if (value
< min
|| value
> max
) {
1665 error_setg(errp
, "Property %s.%s doesn't take value %" PRId64
1666 " (minimum: %" PRId64
", maximum: %" PRId64
")",
1667 object_get_typename(obj
), name
? name
: "null",
1671 cpu
->hyperv_spinlock_attempts
= value
;
1674 static PropertyInfo qdev_prop_spinlocks
= {
1676 .get
= x86_get_hv_spinlocks
,
1677 .set
= x86_set_hv_spinlocks
,
1680 /* Convert all '_' in a feature string option name to '-', to make feature
1681 * name conform to QOM property naming rule, which uses '-' instead of '_'.
1683 static inline void feat2prop(char *s
)
1685 while ((s
= strchr(s
, '_'))) {
1690 /* Parse "+feature,-feature,feature=foo" CPU feature string
1692 static void x86_cpu_parse_featurestr(CPUState
*cs
, char *features
,
1695 X86CPU
*cpu
= X86_CPU(cs
);
1696 char *featurestr
; /* Single 'key=value" string being parsed */
1698 /* Features to be added */
1699 FeatureWordArray plus_features
= { 0 };
1700 /* Features to be removed */
1701 FeatureWordArray minus_features
= { 0 };
1703 CPUX86State
*env
= &cpu
->env
;
1704 Error
*local_err
= NULL
;
1706 featurestr
= features
? strtok(features
, ",") : NULL
;
1708 while (featurestr
) {
1710 if (featurestr
[0] == '+') {
1711 add_flagname_to_bitmaps(featurestr
+ 1, plus_features
);
1712 } else if (featurestr
[0] == '-') {
1713 add_flagname_to_bitmaps(featurestr
+ 1, minus_features
);
1714 } else if ((val
= strchr(featurestr
, '='))) {
1716 feat2prop(featurestr
);
1717 if (!strcmp(featurestr
, "xlevel")) {
1721 numvalue
= strtoul(val
, &err
, 0);
1722 if (!*val
|| *err
) {
1723 error_setg(errp
, "bad numerical value %s", val
);
1726 if (numvalue
< 0x80000000) {
1727 error_report("xlevel value shall always be >= 0x80000000"
1728 ", fixup will be removed in future versions");
1729 numvalue
+= 0x80000000;
1731 snprintf(num
, sizeof(num
), "%" PRIu32
, numvalue
);
1732 object_property_parse(OBJECT(cpu
), num
, featurestr
, &local_err
);
1733 } else if (!strcmp(featurestr
, "tsc-freq")) {
1738 tsc_freq
= strtosz_suffix_unit(val
, &err
,
1739 STRTOSZ_DEFSUFFIX_B
, 1000);
1740 if (tsc_freq
< 0 || *err
) {
1741 error_setg(errp
, "bad numerical value %s", val
);
1744 snprintf(num
, sizeof(num
), "%" PRId64
, tsc_freq
);
1745 object_property_parse(OBJECT(cpu
), num
, "tsc-frequency",
1747 } else if (!strcmp(featurestr
, "hv-spinlocks")) {
1749 const int min
= 0xFFF;
1751 numvalue
= strtoul(val
, &err
, 0);
1752 if (!*val
|| *err
) {
1753 error_setg(errp
, "bad numerical value %s", val
);
1756 if (numvalue
< min
) {
1757 error_report("hv-spinlocks value shall always be >= 0x%x"
1758 ", fixup will be removed in future versions",
1762 snprintf(num
, sizeof(num
), "%" PRId32
, numvalue
);
1763 object_property_parse(OBJECT(cpu
), num
, featurestr
, &local_err
);
1765 object_property_parse(OBJECT(cpu
), val
, featurestr
, &local_err
);
1768 feat2prop(featurestr
);
1769 object_property_parse(OBJECT(cpu
), "on", featurestr
, &local_err
);
1772 error_propagate(errp
, local_err
);
1775 featurestr
= strtok(NULL
, ",");
1778 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
1779 env
->features
[w
] |= plus_features
[w
];
1780 env
->features
[w
] &= ~minus_features
[w
];
1784 /* generate a composite string into buf of all cpuid names in featureset
1785 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1786 * if flags, suppress names undefined in featureset.
1788 static void listflags(char *buf
, int bufsize
, uint32_t fbits
,
1789 const char **featureset
, uint32_t flags
)
1791 const char **p
= &featureset
[31];
1795 b
= 4 <= bufsize
? buf
+ (bufsize
-= 3) - 1 : NULL
;
1797 for (q
= buf
, bit
= 31; fbits
&& bufsize
; --p
, fbits
&= ~(1 << bit
), --bit
)
1798 if (fbits
& 1 << bit
&& (*p
|| !flags
)) {
1800 nc
= snprintf(q
, bufsize
, "%s%s", q
== buf
? "" : " ", *p
);
1802 nc
= snprintf(q
, bufsize
, "%s[%d]", q
== buf
? "" : " ", bit
);
1803 if (bufsize
<= nc
) {
1805 memcpy(b
, "...", sizeof("..."));
1814 /* generate CPU information. */
1815 void x86_cpu_list(FILE *f
, fprintf_function cpu_fprintf
)
1817 X86CPUDefinition
*def
;
1821 for (i
= 0; i
< ARRAY_SIZE(builtin_x86_defs
); i
++) {
1822 def
= &builtin_x86_defs
[i
];
1823 snprintf(buf
, sizeof(buf
), "%s", def
->name
);
1824 (*cpu_fprintf
)(f
, "x86 %16s %-48s\n", buf
, def
->model_id
);
1827 (*cpu_fprintf
)(f
, "x86 %16s %-48s\n", "host",
1828 "KVM processor with all supported host features "
1829 "(only available in KVM mode)");
1832 (*cpu_fprintf
)(f
, "\nRecognized CPUID flags:\n");
1833 for (i
= 0; i
< ARRAY_SIZE(feature_word_info
); i
++) {
1834 FeatureWordInfo
*fw
= &feature_word_info
[i
];
1836 listflags(buf
, sizeof(buf
), (uint32_t)~0, fw
->feat_names
, 1);
1837 (*cpu_fprintf
)(f
, " %s\n", buf
);
1841 CpuDefinitionInfoList
*arch_query_cpu_definitions(Error
**errp
)
1843 CpuDefinitionInfoList
*cpu_list
= NULL
;
1844 X86CPUDefinition
*def
;
1847 for (i
= 0; i
< ARRAY_SIZE(builtin_x86_defs
); i
++) {
1848 CpuDefinitionInfoList
*entry
;
1849 CpuDefinitionInfo
*info
;
1851 def
= &builtin_x86_defs
[i
];
1852 info
= g_malloc0(sizeof(*info
));
1853 info
->name
= g_strdup(def
->name
);
1855 entry
= g_malloc0(sizeof(*entry
));
1856 entry
->value
= info
;
1857 entry
->next
= cpu_list
;
1864 static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w
,
1865 bool migratable_only
)
1867 FeatureWordInfo
*wi
= &feature_word_info
[w
];
1870 if (kvm_enabled()) {
1871 r
= kvm_arch_get_supported_cpuid(kvm_state
, wi
->cpuid_eax
,
1874 } else if (tcg_enabled()) {
1875 r
= wi
->tcg_features
;
1879 if (migratable_only
) {
1880 r
&= x86_cpu_get_migratable_flags(w
);
1886 * Filters CPU feature words based on host availability of each feature.
1888 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
1890 static int x86_cpu_filter_features(X86CPU
*cpu
)
1892 CPUX86State
*env
= &cpu
->env
;
1896 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
1897 uint32_t host_feat
=
1898 x86_cpu_get_supported_feature_word(w
, cpu
->migratable
);
1899 uint32_t requested_features
= env
->features
[w
];
1900 env
->features
[w
] &= host_feat
;
1901 cpu
->filtered_features
[w
] = requested_features
& ~env
->features
[w
];
1902 if (cpu
->filtered_features
[w
]) {
1903 if (cpu
->check_cpuid
|| cpu
->enforce_cpuid
) {
1904 report_unavailable_features(w
, cpu
->filtered_features
[w
]);
1913 /* Load data from X86CPUDefinition
1915 static void x86_cpu_load_def(X86CPU
*cpu
, X86CPUDefinition
*def
, Error
**errp
)
1917 CPUX86State
*env
= &cpu
->env
;
1919 char host_vendor
[CPUID_VENDOR_SZ
+ 1];
1922 object_property_set_int(OBJECT(cpu
), def
->level
, "level", errp
);
1923 object_property_set_int(OBJECT(cpu
), def
->family
, "family", errp
);
1924 object_property_set_int(OBJECT(cpu
), def
->model
, "model", errp
);
1925 object_property_set_int(OBJECT(cpu
), def
->stepping
, "stepping", errp
);
1926 object_property_set_int(OBJECT(cpu
), def
->xlevel
, "xlevel", errp
);
1927 env
->cpuid_xlevel2
= def
->xlevel2
;
1928 cpu
->cache_info_passthrough
= def
->cache_info_passthrough
;
1929 object_property_set_str(OBJECT(cpu
), def
->model_id
, "model-id", errp
);
1930 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
1931 env
->features
[w
] = def
->features
[w
];
1934 /* Special cases not set in the X86CPUDefinition structs: */
1935 if (kvm_enabled()) {
1937 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
1938 env
->features
[w
] |= kvm_default_features
[w
];
1939 env
->features
[w
] &= ~kvm_default_unset_features
[w
];
1943 env
->features
[FEAT_1_ECX
] |= CPUID_EXT_HYPERVISOR
;
1945 /* sysenter isn't supported in compatibility mode on AMD,
1946 * syscall isn't supported in compatibility mode on Intel.
1947 * Normally we advertise the actual CPU vendor, but you can
1948 * override this using the 'vendor' property if you want to use
1949 * KVM's sysenter/syscall emulation in compatibility mode and
1950 * when doing cross vendor migration
1952 vendor
= def
->vendor
;
1953 if (kvm_enabled()) {
1954 uint32_t ebx
= 0, ecx
= 0, edx
= 0;
1955 host_cpuid(0, 0, NULL
, &ebx
, &ecx
, &edx
);
1956 x86_cpu_vendor_words2str(host_vendor
, ebx
, edx
, ecx
);
1957 vendor
= host_vendor
;
1960 object_property_set_str(OBJECT(cpu
), vendor
, "vendor", errp
);
1964 X86CPU
*cpu_x86_create(const char *cpu_model
, DeviceState
*icc_bridge
,
1970 gchar
**model_pieces
;
1971 char *name
, *features
;
1972 Error
*error
= NULL
;
1974 model_pieces
= g_strsplit(cpu_model
, ",", 2);
1975 if (!model_pieces
[0]) {
1976 error_setg(&error
, "Invalid/empty CPU model name");
1979 name
= model_pieces
[0];
1980 features
= model_pieces
[1];
1982 oc
= x86_cpu_class_by_name(name
);
1984 error_setg(&error
, "Unable to find CPU definition: %s", name
);
1987 xcc
= X86_CPU_CLASS(oc
);
1989 if (xcc
->kvm_required
&& !kvm_enabled()) {
1990 error_setg(&error
, "CPU model '%s' requires KVM", name
);
1994 cpu
= X86_CPU(object_new(object_class_get_name(oc
)));
1996 #ifndef CONFIG_USER_ONLY
1997 if (icc_bridge
== NULL
) {
1998 error_setg(&error
, "Invalid icc-bridge value");
2001 qdev_set_parent_bus(DEVICE(cpu
), qdev_get_child_bus(icc_bridge
, "icc"));
2002 object_unref(OBJECT(cpu
));
2005 x86_cpu_parse_featurestr(CPU(cpu
), features
, &error
);
2011 if (error
!= NULL
) {
2012 error_propagate(errp
, error
);
2014 object_unref(OBJECT(cpu
));
2018 g_strfreev(model_pieces
);
2022 X86CPU
*cpu_x86_init(const char *cpu_model
)
2024 Error
*error
= NULL
;
2027 cpu
= cpu_x86_create(cpu_model
, NULL
, &error
);
2032 object_property_set_bool(OBJECT(cpu
), true, "realized", &error
);
2036 error_report("%s", error_get_pretty(error
));
2039 object_unref(OBJECT(cpu
));
2046 static void x86_cpu_cpudef_class_init(ObjectClass
*oc
, void *data
)
2048 X86CPUDefinition
*cpudef
= data
;
2049 X86CPUClass
*xcc
= X86_CPU_CLASS(oc
);
2051 xcc
->cpu_def
= cpudef
;
2054 static void x86_register_cpudef_type(X86CPUDefinition
*def
)
2056 char *typename
= x86_cpu_type_name(def
->name
);
2059 .parent
= TYPE_X86_CPU
,
2060 .class_init
= x86_cpu_cpudef_class_init
,
2068 #if !defined(CONFIG_USER_ONLY)
2070 void cpu_clear_apic_feature(CPUX86State
*env
)
2072 env
->features
[FEAT_1_EDX
] &= ~CPUID_APIC
;
2075 #endif /* !CONFIG_USER_ONLY */
2077 /* Initialize list of CPU models, filling some non-static fields if necessary
2079 void x86_cpudef_setup(void)
2082 static const char *model_with_versions
[] = { "qemu32", "qemu64", "athlon" };
2084 for (i
= 0; i
< ARRAY_SIZE(builtin_x86_defs
); ++i
) {
2085 X86CPUDefinition
*def
= &builtin_x86_defs
[i
];
2087 /* Look for specific "cpudef" models that */
2088 /* have the QEMU version in .model_id */
2089 for (j
= 0; j
< ARRAY_SIZE(model_with_versions
); j
++) {
2090 if (strcmp(model_with_versions
[j
], def
->name
) == 0) {
2091 pstrcpy(def
->model_id
, sizeof(def
->model_id
),
2092 "QEMU Virtual CPU version ");
2093 pstrcat(def
->model_id
, sizeof(def
->model_id
),
2094 qemu_get_version());
2101 static void get_cpuid_vendor(CPUX86State
*env
, uint32_t *ebx
,
2102 uint32_t *ecx
, uint32_t *edx
)
2104 *ebx
= env
->cpuid_vendor1
;
2105 *edx
= env
->cpuid_vendor2
;
2106 *ecx
= env
->cpuid_vendor3
;
2109 void cpu_x86_cpuid(CPUX86State
*env
, uint32_t index
, uint32_t count
,
2110 uint32_t *eax
, uint32_t *ebx
,
2111 uint32_t *ecx
, uint32_t *edx
)
2113 X86CPU
*cpu
= x86_env_get_cpu(env
);
2114 CPUState
*cs
= CPU(cpu
);
2116 /* test if maximum index reached */
2117 if (index
& 0x80000000) {
2118 if (index
> env
->cpuid_xlevel
) {
2119 if (env
->cpuid_xlevel2
> 0) {
2120 /* Handle the Centaur's CPUID instruction. */
2121 if (index
> env
->cpuid_xlevel2
) {
2122 index
= env
->cpuid_xlevel2
;
2123 } else if (index
< 0xC0000000) {
2124 index
= env
->cpuid_xlevel
;
2127 /* Intel documentation states that invalid EAX input will
2128 * return the same information as EAX=cpuid_level
2129 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2131 index
= env
->cpuid_level
;
2135 if (index
> env
->cpuid_level
)
2136 index
= env
->cpuid_level
;
2141 *eax
= env
->cpuid_level
;
2142 get_cpuid_vendor(env
, ebx
, ecx
, edx
);
2145 *eax
= env
->cpuid_version
;
2146 *ebx
= (env
->cpuid_apic_id
<< 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
2147 *ecx
= env
->features
[FEAT_1_ECX
];
2148 *edx
= env
->features
[FEAT_1_EDX
];
2149 if (cs
->nr_cores
* cs
->nr_threads
> 1) {
2150 *ebx
|= (cs
->nr_cores
* cs
->nr_threads
) << 16;
2151 *edx
|= 1 << 28; /* HTT bit */
2155 /* cache info: needed for Pentium Pro compatibility */
2156 if (cpu
->cache_info_passthrough
) {
2157 host_cpuid(index
, 0, eax
, ebx
, ecx
, edx
);
2160 *eax
= 1; /* Number of CPUID[EAX=2] calls required */
2163 *edx
= (L1D_DESCRIPTOR
<< 16) | \
2164 (L1I_DESCRIPTOR
<< 8) | \
2168 /* cache info: needed for Core compatibility */
2169 if (cpu
->cache_info_passthrough
) {
2170 host_cpuid(index
, count
, eax
, ebx
, ecx
, edx
);
2171 *eax
&= ~0xFC000000;
2175 case 0: /* L1 dcache info */
2176 *eax
|= CPUID_4_TYPE_DCACHE
| \
2177 CPUID_4_LEVEL(1) | \
2178 CPUID_4_SELF_INIT_LEVEL
;
2179 *ebx
= (L1D_LINE_SIZE
- 1) | \
2180 ((L1D_PARTITIONS
- 1) << 12) | \
2181 ((L1D_ASSOCIATIVITY
- 1) << 22);
2182 *ecx
= L1D_SETS
- 1;
2183 *edx
= CPUID_4_NO_INVD_SHARING
;
2185 case 1: /* L1 icache info */
2186 *eax
|= CPUID_4_TYPE_ICACHE
| \
2187 CPUID_4_LEVEL(1) | \
2188 CPUID_4_SELF_INIT_LEVEL
;
2189 *ebx
= (L1I_LINE_SIZE
- 1) | \
2190 ((L1I_PARTITIONS
- 1) << 12) | \
2191 ((L1I_ASSOCIATIVITY
- 1) << 22);
2192 *ecx
= L1I_SETS
- 1;
2193 *edx
= CPUID_4_NO_INVD_SHARING
;
2195 case 2: /* L2 cache info */
2196 *eax
|= CPUID_4_TYPE_UNIFIED
| \
2197 CPUID_4_LEVEL(2) | \
2198 CPUID_4_SELF_INIT_LEVEL
;
2199 if (cs
->nr_threads
> 1) {
2200 *eax
|= (cs
->nr_threads
- 1) << 14;
2202 *ebx
= (L2_LINE_SIZE
- 1) | \
2203 ((L2_PARTITIONS
- 1) << 12) | \
2204 ((L2_ASSOCIATIVITY
- 1) << 22);
2206 *edx
= CPUID_4_NO_INVD_SHARING
;
2208 default: /* end of info */
2217 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
2218 if ((*eax
& 31) && cs
->nr_cores
> 1) {
2219 *eax
|= (cs
->nr_cores
- 1) << 26;
2223 /* mwait info: needed for Core compatibility */
2224 *eax
= 0; /* Smallest monitor-line size in bytes */
2225 *ebx
= 0; /* Largest monitor-line size in bytes */
2226 *ecx
= CPUID_MWAIT_EMX
| CPUID_MWAIT_IBE
;
2230 /* Thermal and Power Leaf */
2237 /* Structured Extended Feature Flags Enumeration Leaf */
2239 *eax
= 0; /* Maximum ECX value for sub-leaves */
2240 *ebx
= env
->features
[FEAT_7_0_EBX
]; /* Feature flags */
2241 *ecx
= 0; /* Reserved */
2242 *edx
= 0; /* Reserved */
2251 /* Direct Cache Access Information Leaf */
2252 *eax
= 0; /* Bits 0-31 in DCA_CAP MSR */
2258 /* Architectural Performance Monitoring Leaf */
2259 if (kvm_enabled() && cpu
->enable_pmu
) {
2260 KVMState
*s
= cs
->kvm_state
;
2262 *eax
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_EAX
);
2263 *ebx
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_EBX
);
2264 *ecx
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_ECX
);
2265 *edx
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_EDX
);
2274 KVMState
*s
= cs
->kvm_state
;
2278 /* Processor Extended State */
2283 if (!(env
->features
[FEAT_1_ECX
] & CPUID_EXT_XSAVE
) || !kvm_enabled()) {
2287 kvm_arch_get_supported_cpuid(s
, 0xd, 0, R_EAX
) |
2288 ((uint64_t)kvm_arch_get_supported_cpuid(s
, 0xd, 0, R_EDX
) << 32);
2292 for (i
= 2; i
< ARRAY_SIZE(ext_save_areas
); i
++) {
2293 const ExtSaveArea
*esa
= &ext_save_areas
[i
];
2294 if ((env
->features
[esa
->feature
] & esa
->bits
) == esa
->bits
&&
2295 (kvm_mask
& (1 << i
)) != 0) {
2299 *edx
|= 1 << (i
- 32);
2301 *ecx
= MAX(*ecx
, esa
->offset
+ esa
->size
);
2304 *eax
|= kvm_mask
& (XSTATE_FP
| XSTATE_SSE
);
2306 } else if (count
== 1) {
2307 *eax
= kvm_arch_get_supported_cpuid(s
, 0xd, 1, R_EAX
);
2308 } else if (count
< ARRAY_SIZE(ext_save_areas
)) {
2309 const ExtSaveArea
*esa
= &ext_save_areas
[count
];
2310 if ((env
->features
[esa
->feature
] & esa
->bits
) == esa
->bits
&&
2311 (kvm_mask
& (1 << count
)) != 0) {
2319 *eax
= env
->cpuid_xlevel
;
2320 *ebx
= env
->cpuid_vendor1
;
2321 *edx
= env
->cpuid_vendor2
;
2322 *ecx
= env
->cpuid_vendor3
;
2325 *eax
= env
->cpuid_version
;
2327 *ecx
= env
->features
[FEAT_8000_0001_ECX
];
2328 *edx
= env
->features
[FEAT_8000_0001_EDX
];
2330 /* The Linux kernel checks for the CMPLegacy bit and
2331 * discards multiple thread information if it is set.
2332 * So dont set it here for Intel to make Linux guests happy.
2334 if (cs
->nr_cores
* cs
->nr_threads
> 1) {
2335 uint32_t tebx
, tecx
, tedx
;
2336 get_cpuid_vendor(env
, &tebx
, &tecx
, &tedx
);
2337 if (tebx
!= CPUID_VENDOR_INTEL_1
||
2338 tedx
!= CPUID_VENDOR_INTEL_2
||
2339 tecx
!= CPUID_VENDOR_INTEL_3
) {
2340 *ecx
|= 1 << 1; /* CmpLegacy bit */
2347 *eax
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 0];
2348 *ebx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 1];
2349 *ecx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 2];
2350 *edx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 3];
2353 /* cache info (L1 cache) */
2354 if (cpu
->cache_info_passthrough
) {
2355 host_cpuid(index
, 0, eax
, ebx
, ecx
, edx
);
2358 *eax
= (L1_DTLB_2M_ASSOC
<< 24) | (L1_DTLB_2M_ENTRIES
<< 16) | \
2359 (L1_ITLB_2M_ASSOC
<< 8) | (L1_ITLB_2M_ENTRIES
);
2360 *ebx
= (L1_DTLB_4K_ASSOC
<< 24) | (L1_DTLB_4K_ENTRIES
<< 16) | \
2361 (L1_ITLB_4K_ASSOC
<< 8) | (L1_ITLB_4K_ENTRIES
);
2362 *ecx
= (L1D_SIZE_KB_AMD
<< 24) | (L1D_ASSOCIATIVITY_AMD
<< 16) | \
2363 (L1D_LINES_PER_TAG
<< 8) | (L1D_LINE_SIZE
);
2364 *edx
= (L1I_SIZE_KB_AMD
<< 24) | (L1I_ASSOCIATIVITY_AMD
<< 16) | \
2365 (L1I_LINES_PER_TAG
<< 8) | (L1I_LINE_SIZE
);
2368 /* cache info (L2 cache) */
2369 if (cpu
->cache_info_passthrough
) {
2370 host_cpuid(index
, 0, eax
, ebx
, ecx
, edx
);
2373 *eax
= (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC
) << 28) | \
2374 (L2_DTLB_2M_ENTRIES
<< 16) | \
2375 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC
) << 12) | \
2376 (L2_ITLB_2M_ENTRIES
);
2377 *ebx
= (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC
) << 28) | \
2378 (L2_DTLB_4K_ENTRIES
<< 16) | \
2379 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC
) << 12) | \
2380 (L2_ITLB_4K_ENTRIES
);
2381 *ecx
= (L2_SIZE_KB_AMD
<< 16) | \
2382 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY
) << 12) | \
2383 (L2_LINES_PER_TAG
<< 8) | (L2_LINE_SIZE
);
2384 *edx
= ((L3_SIZE_KB
/512) << 18) | \
2385 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY
) << 12) | \
2386 (L3_LINES_PER_TAG
<< 8) | (L3_LINE_SIZE
);
2389 /* virtual & phys address size in low 2 bytes. */
2390 /* XXX: This value must match the one used in the MMU code. */
2391 if (env
->features
[FEAT_8000_0001_EDX
] & CPUID_EXT2_LM
) {
2392 /* 64 bit processor */
2393 /* XXX: The physical address space is limited to 42 bits in exec.c. */
2394 *eax
= 0x00003028; /* 48 bits virtual, 40 bits physical */
2396 if (env
->features
[FEAT_1_EDX
] & CPUID_PSE36
) {
2397 *eax
= 0x00000024; /* 36 bits physical */
2399 *eax
= 0x00000020; /* 32 bits physical */
2405 if (cs
->nr_cores
* cs
->nr_threads
> 1) {
2406 *ecx
|= (cs
->nr_cores
* cs
->nr_threads
) - 1;
2410 if (env
->features
[FEAT_8000_0001_ECX
] & CPUID_EXT3_SVM
) {
2411 *eax
= 0x00000001; /* SVM Revision */
2412 *ebx
= 0x00000010; /* nr of ASIDs */
2414 *edx
= env
->features
[FEAT_SVM
]; /* optional features */
2423 *eax
= env
->cpuid_xlevel2
;
2429 /* Support for VIA CPU's CPUID instruction */
2430 *eax
= env
->cpuid_version
;
2433 *edx
= env
->features
[FEAT_C000_0001_EDX
];
2438 /* Reserved for the future, and now filled with zero */
2445 /* reserved values: zero */
2454 /* CPUClass::reset() */
2455 static void x86_cpu_reset(CPUState
*s
)
2457 X86CPU
*cpu
= X86_CPU(s
);
2458 X86CPUClass
*xcc
= X86_CPU_GET_CLASS(cpu
);
2459 CPUX86State
*env
= &cpu
->env
;
2462 xcc
->parent_reset(s
);
2464 memset(env
, 0, offsetof(CPUX86State
, cpuid_level
));
2468 env
->old_exception
= -1;
2470 /* init to reset state */
2472 #ifdef CONFIG_SOFTMMU
2473 env
->hflags
|= HF_SOFTMMU_MASK
;
2475 env
->hflags2
|= HF2_GIF_MASK
;
2477 cpu_x86_update_cr0(env
, 0x60000010);
2478 env
->a20_mask
= ~0x0;
2479 env
->smbase
= 0x30000;
2481 env
->idt
.limit
= 0xffff;
2482 env
->gdt
.limit
= 0xffff;
2483 env
->ldt
.limit
= 0xffff;
2484 env
->ldt
.flags
= DESC_P_MASK
| (2 << DESC_TYPE_SHIFT
);
2485 env
->tr
.limit
= 0xffff;
2486 env
->tr
.flags
= DESC_P_MASK
| (11 << DESC_TYPE_SHIFT
);
2488 cpu_x86_load_seg_cache(env
, R_CS
, 0xf000, 0xffff0000, 0xffff,
2489 DESC_P_MASK
| DESC_S_MASK
| DESC_CS_MASK
|
2490 DESC_R_MASK
| DESC_A_MASK
);
2491 cpu_x86_load_seg_cache(env
, R_DS
, 0, 0, 0xffff,
2492 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
2494 cpu_x86_load_seg_cache(env
, R_ES
, 0, 0, 0xffff,
2495 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
2497 cpu_x86_load_seg_cache(env
, R_SS
, 0, 0, 0xffff,
2498 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
2500 cpu_x86_load_seg_cache(env
, R_FS
, 0, 0, 0xffff,
2501 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
2503 cpu_x86_load_seg_cache(env
, R_GS
, 0, 0, 0xffff,
2504 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
2508 env
->regs
[R_EDX
] = env
->cpuid_version
;
2513 for (i
= 0; i
< 8; i
++) {
2518 env
->mxcsr
= 0x1f80;
2519 env
->xstate_bv
= XSTATE_FP
| XSTATE_SSE
;
2521 env
->pat
= 0x0007040600070406ULL
;
2522 env
->msr_ia32_misc_enable
= MSR_IA32_MISC_ENABLE_DEFAULT
;
2524 memset(env
->dr
, 0, sizeof(env
->dr
));
2525 env
->dr
[6] = DR6_FIXED_1
;
2526 env
->dr
[7] = DR7_FIXED_1
;
2527 cpu_breakpoint_remove_all(s
, BP_CPU
);
2528 cpu_watchpoint_remove_all(s
, BP_CPU
);
2532 #if !defined(CONFIG_USER_ONLY)
2533 /* We hard-wire the BSP to the first CPU. */
2534 if (s
->cpu_index
== 0) {
2535 apic_designate_bsp(cpu
->apic_state
);
2538 s
->halted
= !cpu_is_bsp(cpu
);
2540 if (kvm_enabled()) {
2541 kvm_arch_reset_vcpu(cpu
);
2546 #ifndef CONFIG_USER_ONLY
2547 bool cpu_is_bsp(X86CPU
*cpu
)
2549 return cpu_get_apic_base(cpu
->apic_state
) & MSR_IA32_APICBASE_BSP
;
2552 /* TODO: remove me, when reset over QOM tree is implemented */
2553 static void x86_cpu_machine_reset_cb(void *opaque
)
2555 X86CPU
*cpu
= opaque
;
2556 cpu_reset(CPU(cpu
));
2560 static void mce_init(X86CPU
*cpu
)
2562 CPUX86State
*cenv
= &cpu
->env
;
2565 if (((cenv
->cpuid_version
>> 8) & 0xf) >= 6
2566 && (cenv
->features
[FEAT_1_EDX
] & (CPUID_MCE
| CPUID_MCA
)) ==
2567 (CPUID_MCE
| CPUID_MCA
)) {
2568 cenv
->mcg_cap
= MCE_CAP_DEF
| MCE_BANKS_DEF
;
2569 cenv
->mcg_ctl
= ~(uint64_t)0;
2570 for (bank
= 0; bank
< MCE_BANKS_DEF
; bank
++) {
2571 cenv
->mce_banks
[bank
* 4] = ~(uint64_t)0;
2576 #ifndef CONFIG_USER_ONLY
2577 static void x86_cpu_apic_create(X86CPU
*cpu
, Error
**errp
)
2579 CPUX86State
*env
= &cpu
->env
;
2580 DeviceState
*dev
= DEVICE(cpu
);
2581 APICCommonState
*apic
;
2582 const char *apic_type
= "apic";
2584 if (kvm_irqchip_in_kernel()) {
2585 apic_type
= "kvm-apic";
2586 } else if (xen_enabled()) {
2587 apic_type
= "xen-apic";
2590 cpu
->apic_state
= qdev_try_create(qdev_get_parent_bus(dev
), apic_type
);
2591 if (cpu
->apic_state
== NULL
) {
2592 error_setg(errp
, "APIC device '%s' could not be created", apic_type
);
2596 object_property_add_child(OBJECT(cpu
), "apic",
2597 OBJECT(cpu
->apic_state
), NULL
);
2598 qdev_prop_set_uint8(cpu
->apic_state
, "id", env
->cpuid_apic_id
);
2599 /* TODO: convert to link<> */
2600 apic
= APIC_COMMON(cpu
->apic_state
);
2604 static void x86_cpu_apic_realize(X86CPU
*cpu
, Error
**errp
)
2606 if (cpu
->apic_state
== NULL
) {
2610 if (qdev_init(cpu
->apic_state
)) {
2611 error_setg(errp
, "APIC device '%s' could not be initialized",
2612 object_get_typename(OBJECT(cpu
->apic_state
)));
2617 static void x86_cpu_apic_realize(X86CPU
*cpu
, Error
**errp
)
2622 static void x86_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
2624 CPUState
*cs
= CPU(dev
);
2625 X86CPU
*cpu
= X86_CPU(dev
);
2626 X86CPUClass
*xcc
= X86_CPU_GET_CLASS(dev
);
2627 CPUX86State
*env
= &cpu
->env
;
2628 Error
*local_err
= NULL
;
2630 if (env
->features
[FEAT_7_0_EBX
] && env
->cpuid_level
< 7) {
2631 env
->cpuid_level
= 7;
2634 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2637 if (env
->cpuid_vendor1
== CPUID_VENDOR_AMD_1
&&
2638 env
->cpuid_vendor2
== CPUID_VENDOR_AMD_2
&&
2639 env
->cpuid_vendor3
== CPUID_VENDOR_AMD_3
) {
2640 env
->features
[FEAT_8000_0001_EDX
] &= ~CPUID_EXT2_AMD_ALIASES
;
2641 env
->features
[FEAT_8000_0001_EDX
] |= (env
->features
[FEAT_1_EDX
]
2642 & CPUID_EXT2_AMD_ALIASES
);
2646 if (x86_cpu_filter_features(cpu
) && cpu
->enforce_cpuid
) {
2647 error_setg(&local_err
,
2649 "Host doesn't support requested features" :
2650 "TCG doesn't support requested features");
2654 #ifndef CONFIG_USER_ONLY
2655 qemu_register_reset(x86_cpu_machine_reset_cb
, cpu
);
2657 if (cpu
->env
.features
[FEAT_1_EDX
] & CPUID_APIC
|| smp_cpus
> 1) {
2658 x86_cpu_apic_create(cpu
, &local_err
);
2659 if (local_err
!= NULL
) {
2668 x86_cpu_apic_realize(cpu
, &local_err
);
2669 if (local_err
!= NULL
) {
2674 xcc
->parent_realize(dev
, &local_err
);
2676 if (local_err
!= NULL
) {
2677 error_propagate(errp
, local_err
);
2682 /* Enables contiguous-apic-ID mode, for compatibility */
2683 static bool compat_apic_id_mode
;
2685 void enable_compat_apic_id_mode(void)
2687 compat_apic_id_mode
= true;
2690 /* Calculates initial APIC ID for a specific CPU index
2692 * Currently we need to be able to calculate the APIC ID from the CPU index
2693 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
2694 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
2695 * all CPUs up to max_cpus.
2697 uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index
)
2699 uint32_t correct_id
;
2702 correct_id
= x86_apicid_from_cpu_idx(smp_cores
, smp_threads
, cpu_index
);
2703 if (compat_apic_id_mode
) {
2704 if (cpu_index
!= correct_id
&& !warned
) {
2705 error_report("APIC IDs set in compatibility mode, "
2706 "CPU topology won't match the configuration");
2715 static void x86_cpu_initfn(Object
*obj
)
2717 CPUState
*cs
= CPU(obj
);
2718 X86CPU
*cpu
= X86_CPU(obj
);
2719 X86CPUClass
*xcc
= X86_CPU_GET_CLASS(obj
);
2720 CPUX86State
*env
= &cpu
->env
;
2726 object_property_add(obj
, "family", "int",
2727 x86_cpuid_version_get_family
,
2728 x86_cpuid_version_set_family
, NULL
, NULL
, NULL
);
2729 object_property_add(obj
, "model", "int",
2730 x86_cpuid_version_get_model
,
2731 x86_cpuid_version_set_model
, NULL
, NULL
, NULL
);
2732 object_property_add(obj
, "stepping", "int",
2733 x86_cpuid_version_get_stepping
,
2734 x86_cpuid_version_set_stepping
, NULL
, NULL
, NULL
);
2735 object_property_add(obj
, "level", "int",
2736 x86_cpuid_get_level
,
2737 x86_cpuid_set_level
, NULL
, NULL
, NULL
);
2738 object_property_add(obj
, "xlevel", "int",
2739 x86_cpuid_get_xlevel
,
2740 x86_cpuid_set_xlevel
, NULL
, NULL
, NULL
);
2741 object_property_add_str(obj
, "vendor",
2742 x86_cpuid_get_vendor
,
2743 x86_cpuid_set_vendor
, NULL
);
2744 object_property_add_str(obj
, "model-id",
2745 x86_cpuid_get_model_id
,
2746 x86_cpuid_set_model_id
, NULL
);
2747 object_property_add(obj
, "tsc-frequency", "int",
2748 x86_cpuid_get_tsc_freq
,
2749 x86_cpuid_set_tsc_freq
, NULL
, NULL
, NULL
);
2750 object_property_add(obj
, "apic-id", "int",
2751 x86_cpuid_get_apic_id
,
2752 x86_cpuid_set_apic_id
, NULL
, NULL
, NULL
);
2753 object_property_add(obj
, "feature-words", "X86CPUFeatureWordInfo",
2754 x86_cpu_get_feature_words
,
2755 NULL
, NULL
, (void *)env
->features
, NULL
);
2756 object_property_add(obj
, "filtered-features", "X86CPUFeatureWordInfo",
2757 x86_cpu_get_feature_words
,
2758 NULL
, NULL
, (void *)cpu
->filtered_features
, NULL
);
2760 cpu
->hyperv_spinlock_attempts
= HYPERV_SPINLOCK_NEVER_RETRY
;
2761 env
->cpuid_apic_id
= x86_cpu_apic_id_from_index(cs
->cpu_index
);
2763 x86_cpu_load_def(cpu
, xcc
->cpu_def
, &error_abort
);
2765 /* init various static tables used in TCG mode */
2766 if (tcg_enabled() && !inited
) {
2768 optimize_flags_init();
2769 #ifndef CONFIG_USER_ONLY
2770 cpu_set_debug_excp_handler(breakpoint_handler
);
2775 static int64_t x86_cpu_get_arch_id(CPUState
*cs
)
2777 X86CPU
*cpu
= X86_CPU(cs
);
2778 CPUX86State
*env
= &cpu
->env
;
2780 return env
->cpuid_apic_id
;
2783 static bool x86_cpu_get_paging_enabled(const CPUState
*cs
)
2785 X86CPU
*cpu
= X86_CPU(cs
);
2787 return cpu
->env
.cr
[0] & CR0_PG_MASK
;
2790 static void x86_cpu_set_pc(CPUState
*cs
, vaddr value
)
2792 X86CPU
*cpu
= X86_CPU(cs
);
2794 cpu
->env
.eip
= value
;
2797 static void x86_cpu_synchronize_from_tb(CPUState
*cs
, TranslationBlock
*tb
)
2799 X86CPU
*cpu
= X86_CPU(cs
);
2801 cpu
->env
.eip
= tb
->pc
- tb
->cs_base
;
2804 static bool x86_cpu_has_work(CPUState
*cs
)
2806 X86CPU
*cpu
= X86_CPU(cs
);
2807 CPUX86State
*env
= &cpu
->env
;
2809 return ((cs
->interrupt_request
& (CPU_INTERRUPT_HARD
|
2810 CPU_INTERRUPT_POLL
)) &&
2811 (env
->eflags
& IF_MASK
)) ||
2812 (cs
->interrupt_request
& (CPU_INTERRUPT_NMI
|
2813 CPU_INTERRUPT_INIT
|
2814 CPU_INTERRUPT_SIPI
|
2815 CPU_INTERRUPT_MCE
));
2818 static Property x86_cpu_properties
[] = {
2819 DEFINE_PROP_BOOL("pmu", X86CPU
, enable_pmu
, false),
2820 { .name
= "hv-spinlocks", .info
= &qdev_prop_spinlocks
},
2821 DEFINE_PROP_BOOL("hv-relaxed", X86CPU
, hyperv_relaxed_timing
, false),
2822 DEFINE_PROP_BOOL("hv-vapic", X86CPU
, hyperv_vapic
, false),
2823 DEFINE_PROP_BOOL("hv-time", X86CPU
, hyperv_time
, false),
2824 DEFINE_PROP_BOOL("check", X86CPU
, check_cpuid
, false),
2825 DEFINE_PROP_BOOL("enforce", X86CPU
, enforce_cpuid
, false),
2826 DEFINE_PROP_BOOL("kvm", X86CPU
, expose_kvm
, true),
2827 DEFINE_PROP_END_OF_LIST()
2830 static void x86_cpu_common_class_init(ObjectClass
*oc
, void *data
)
2832 X86CPUClass
*xcc
= X86_CPU_CLASS(oc
);
2833 CPUClass
*cc
= CPU_CLASS(oc
);
2834 DeviceClass
*dc
= DEVICE_CLASS(oc
);
2836 xcc
->parent_realize
= dc
->realize
;
2837 dc
->realize
= x86_cpu_realizefn
;
2838 dc
->bus_type
= TYPE_ICC_BUS
;
2839 dc
->props
= x86_cpu_properties
;
2841 xcc
->parent_reset
= cc
->reset
;
2842 cc
->reset
= x86_cpu_reset
;
2843 cc
->reset_dump_flags
= CPU_DUMP_FPU
| CPU_DUMP_CCOP
;
2845 cc
->class_by_name
= x86_cpu_class_by_name
;
2846 cc
->parse_features
= x86_cpu_parse_featurestr
;
2847 cc
->has_work
= x86_cpu_has_work
;
2848 cc
->do_interrupt
= x86_cpu_do_interrupt
;
2849 cc
->dump_state
= x86_cpu_dump_state
;
2850 cc
->set_pc
= x86_cpu_set_pc
;
2851 cc
->synchronize_from_tb
= x86_cpu_synchronize_from_tb
;
2852 cc
->gdb_read_register
= x86_cpu_gdb_read_register
;
2853 cc
->gdb_write_register
= x86_cpu_gdb_write_register
;
2854 cc
->get_arch_id
= x86_cpu_get_arch_id
;
2855 cc
->get_paging_enabled
= x86_cpu_get_paging_enabled
;
2856 #ifdef CONFIG_USER_ONLY
2857 cc
->handle_mmu_fault
= x86_cpu_handle_mmu_fault
;
2859 cc
->get_memory_mapping
= x86_cpu_get_memory_mapping
;
2860 cc
->get_phys_page_debug
= x86_cpu_get_phys_page_debug
;
2861 cc
->write_elf64_note
= x86_cpu_write_elf64_note
;
2862 cc
->write_elf64_qemunote
= x86_cpu_write_elf64_qemunote
;
2863 cc
->write_elf32_note
= x86_cpu_write_elf32_note
;
2864 cc
->write_elf32_qemunote
= x86_cpu_write_elf32_qemunote
;
2865 cc
->vmsd
= &vmstate_x86_cpu
;
2867 cc
->gdb_num_core_regs
= CPU_NB_REGS
* 2 + 25;
2870 static const TypeInfo x86_cpu_type_info
= {
2871 .name
= TYPE_X86_CPU
,
2873 .instance_size
= sizeof(X86CPU
),
2874 .instance_init
= x86_cpu_initfn
,
2876 .class_size
= sizeof(X86CPUClass
),
2877 .class_init
= x86_cpu_common_class_init
,
2880 static void x86_cpu_register_types(void)
2884 type_register_static(&x86_cpu_type_info
);
2885 for (i
= 0; i
< ARRAY_SIZE(builtin_x86_defs
); i
++) {
2886 x86_register_cpudef_type(&builtin_x86_defs
[i
]);
2889 type_register_static(&host_x86_cpu_type_info
);
2893 type_init(x86_cpu_register_types
)