target-openrisc/sys_helper.c

   1 /*
   2  * OpenRISC system instructions helper routines
   3  *
   4  * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
   5  *                         Zhizhou Zhang <etouzh@gmail.com>
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "cpu.h"
  22 #include "helper.h"
  23
  24 #define TO_SPR(group, number) (((group) << 11) + (number))
  25
  26 void HELPER(mtspr)(CPUOpenRISCState *env,
  27                    target_ulong ra, target_ulong rb, target_ulong offset)
  28 {
  29 #ifndef CONFIG_USER_ONLY
  30     int spr = (ra | offset);
  31     int idx;
  32
  33     OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
  34     CPUState *cs = CPU(cpu);
  35
  36     switch (spr) {
  37     case TO_SPR(0, 0): /* VR */
  38         env->vr = rb;
  39         break;
  40
  41     case TO_SPR(0, 16): /* NPC */
  42         env->npc = rb;
  43         break;
  44
  45     case TO_SPR(0, 17): /* SR */
  46         if ((env->sr & (SR_IME | SR_DME | SR_SM)) ^
  47             (rb & (SR_IME | SR_DME | SR_SM))) {
  48             tlb_flush(env, 1);
  49         }
  50         env->sr = rb;
  51         env->sr |= SR_FO;      /* FO is const equal to 1 */
  52         if (env->sr & SR_DME) {
  53             env->tlb->cpu_openrisc_map_address_data =
  54                 &cpu_openrisc_get_phys_data;
  55         } else {
  56             env->tlb->cpu_openrisc_map_address_data =
  57                 &cpu_openrisc_get_phys_nommu;
  58         }
  59
  60         if (env->sr & SR_IME) {
  61             env->tlb->cpu_openrisc_map_address_code =
  62                 &cpu_openrisc_get_phys_code;
  63         } else {
  64             env->tlb->cpu_openrisc_map_address_code =
  65                 &cpu_openrisc_get_phys_nommu;
  66         }
  67         break;
  68
  69     case TO_SPR(0, 18): /* PPC */
  70         env->ppc = rb;
  71         break;
  72
  73     case TO_SPR(0, 32): /* EPCR */
  74         env->epcr = rb;
  75         break;
  76
  77     case TO_SPR(0, 48): /* EEAR */
  78         env->eear = rb;
  79         break;
  80
  81     case TO_SPR(0, 64): /* ESR */
  82         env->esr = rb;
  83         break;
  84     case TO_SPR(1, 512) ... TO_SPR(1, 639): /* DTLBW0MR 0-127 */
  85         idx = spr - TO_SPR(1, 512);
  86         if (!(rb & 1)) {
  87             tlb_flush_page(env, env->tlb->dtlb[0][idx].mr & TARGET_PAGE_MASK);
  88         }
  89         env->tlb->dtlb[0][idx].mr = rb;
  90         break;
  91
  92     case TO_SPR(1, 640) ... TO_SPR(1, 767): /* DTLBW0TR 0-127 */
  93         idx = spr - TO_SPR(1, 640);
  94         env->tlb->dtlb[0][idx].tr = rb;
  95         break;
  96     case TO_SPR(1, 768) ... TO_SPR(1, 895):   /* DTLBW1MR 0-127 */
  97     case TO_SPR(1, 896) ... TO_SPR(1, 1023):  /* DTLBW1TR 0-127 */
  98     case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */
  99     case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */
 100     case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */
 101     case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */
 102         break;
 103     case TO_SPR(2, 512) ... TO_SPR(2, 639):   /* ITLBW0MR 0-127 */
 104         idx = spr - TO_SPR(2, 512);
 105         if (!(rb & 1)) {
 106             tlb_flush_page(env, env->tlb->itlb[0][idx].mr & TARGET_PAGE_MASK);
 107         }
 108         env->tlb->itlb[0][idx].mr = rb;
 109         break;
 110
 111     case TO_SPR(2, 640) ... TO_SPR(2, 767): /* ITLBW0TR 0-127 */
 112         idx = spr - TO_SPR(2, 640);
 113         env->tlb->itlb[0][idx].tr = rb;
 114         break;
 115     case TO_SPR(2, 768) ... TO_SPR(2, 895):   /* ITLBW1MR 0-127 */
 116     case TO_SPR(2, 896) ... TO_SPR(2, 1023):  /* ITLBW1TR 0-127 */
 117     case TO_SPR(2, 1024) ... TO_SPR(2, 1151): /* ITLBW2MR 0-127 */
 118     case TO_SPR(2, 1152) ... TO_SPR(2, 1279): /* ITLBW2TR 0-127 */
 119     case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */
 120     case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */
 121         break;
 122     case TO_SPR(9, 0):  /* PICMR */
 123         env->picmr |= rb;
 124         break;
 125     case TO_SPR(9, 2):  /* PICSR */
 126         env->picsr &= ~rb;
 127         break;
 128     case TO_SPR(10, 0): /* TTMR */
 129         {
 130             int ip = env->ttmr & TTMR_IP;
 131
 132             if (rb & TTMR_IP) {    /* Keep IP bit.  */
 133                 env->ttmr = (rb & ~TTMR_IP) + ip;
 134             } else {    /* Clear IP bit.  */
 135                 env->ttmr = rb & ~TTMR_IP;
 136                 cs->interrupt_request &= ~CPU_INTERRUPT_TIMER;
 137             }
 138
 139             cpu_openrisc_count_update(cpu);
 140
 141             switch (env->ttmr & TTMR_M) {
 142             case TIMER_NONE:
 143                 cpu_openrisc_count_stop(cpu);
 144                 break;
 145             case TIMER_INTR:
 146                 cpu_openrisc_count_start(cpu);
 147                 break;
 148             case TIMER_SHOT:
 149                 cpu_openrisc_count_start(cpu);
 150                 break;
 151             case TIMER_CONT:
 152                 cpu_openrisc_count_start(cpu);
 153                 break;
 154             default:
 155                 break;
 156             }
 157         }
 158         break;
 159
 160     case TO_SPR(10, 1): /* TTCR */
 161         env->ttcr = rb;
 162         if (env->ttmr & TIMER_NONE) {
 163             return;
 164         }
 165         cpu_openrisc_count_start(cpu);
 166         break;
 167     default:
 168
 169         break;
 170     }
 171 #endif
 172 }
 173
 174 target_ulong HELPER(mfspr)(CPUOpenRISCState *env,
 175                            target_ulong rd, target_ulong ra, uint32_t offset)
 176 {
 177 #ifndef CONFIG_USER_ONLY
 178     int spr = (ra | offset);
 179     int idx;
 180
 181     OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
 182
 183     switch (spr) {
 184     case TO_SPR(0, 0): /* VR */
 185         return env->vr & SPR_VR;
 186
 187     case TO_SPR(0, 1): /* UPR */
 188         return env->upr;    /* TT, DM, IM, UP present */
 189
 190     case TO_SPR(0, 2): /* CPUCFGR */
 191         return env->cpucfgr;
 192
 193     case TO_SPR(0, 3): /* DMMUCFGR */
 194         return env->dmmucfgr;    /* 1Way, 64 entries */
 195
 196     case TO_SPR(0, 4): /* IMMUCFGR */
 197         return env->immucfgr;
 198
 199     case TO_SPR(0, 16): /* NPC */
 200         return env->npc;
 201
 202     case TO_SPR(0, 17): /* SR */
 203         return env->sr;
 204
 205     case TO_SPR(0, 18): /* PPC */
 206         return env->ppc;
 207
 208     case TO_SPR(0, 32): /* EPCR */
 209         return env->epcr;
 210
 211     case TO_SPR(0, 48): /* EEAR */
 212         return env->eear;
 213
 214     case TO_SPR(0, 64): /* ESR */
 215         return env->esr;
 216
 217     case TO_SPR(1, 512) ... TO_SPR(1, 639): /* DTLBW0MR 0-127 */
 218         idx = spr - TO_SPR(1, 512);
 219         return env->tlb->dtlb[0][idx].mr;
 220
 221     case TO_SPR(1, 640) ... TO_SPR(1, 767): /* DTLBW0TR 0-127 */
 222         idx = spr - TO_SPR(1, 640);
 223         return env->tlb->dtlb[0][idx].tr;
 224
 225     case TO_SPR(1, 768) ... TO_SPR(1, 895):   /* DTLBW1MR 0-127 */
 226     case TO_SPR(1, 896) ... TO_SPR(1, 1023):  /* DTLBW1TR 0-127 */
 227     case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */
 228     case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */
 229     case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */
 230     case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */
 231         break;
 232
 233     case TO_SPR(2, 512) ... TO_SPR(2, 639): /* ITLBW0MR 0-127 */
 234         idx = spr - TO_SPR(2, 512);
 235         return env->tlb->itlb[0][idx].mr;
 236
 237     case TO_SPR(2, 640) ... TO_SPR(2, 767): /* ITLBW0TR 0-127 */
 238         idx = spr - TO_SPR(2, 640);
 239         return env->tlb->itlb[0][idx].tr;
 240
 241     case TO_SPR(2, 768) ... TO_SPR(2, 895):   /* ITLBW1MR 0-127 */
 242     case TO_SPR(2, 896) ... TO_SPR(2, 1023):  /* ITLBW1TR 0-127 */
 243     case TO_SPR(2, 1024) ... TO_SPR(2, 1151): /* ITLBW2MR 0-127 */
 244     case TO_SPR(2, 1152) ... TO_SPR(2, 1279): /* ITLBW2TR 0-127 */
 245     case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */
 246     case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */
 247         break;
 248
 249     case TO_SPR(9, 0):  /* PICMR */
 250         return env->picmr;
 251
 252     case TO_SPR(9, 2):  /* PICSR */
 253         return env->picsr;
 254
 255     case TO_SPR(10, 0): /* TTMR */
 256         return env->ttmr;
 257
 258     case TO_SPR(10, 1): /* TTCR */
 259         cpu_openrisc_count_update(cpu);
 260         return env->ttcr;
 261
 262     default:
 263         break;
 264     }
 265 #endif
 266
 267 /*If we later need to add tracepoints (or debug printfs) for the return
 268 value, it may be useful to structure the code like this:
 269
 270 target_ulong ret = 0;
 271
 272 switch() {
 273 case x:
 274  ret = y;
 275  break;
 276 case z:
 277  ret = 42;
 278  break;
 279 ...
 280 }
 281
 282 later something like trace_spr_read(ret);
 283
 284 return ret;*/
 285
 286     /* for rd is passed in, if rd unchanged, just keep it back.  */
 287     return rd;
 288 }