2 * Copyright (C) 2010 Red Hat, Inc.
4 * written by Yaniv Kamay, Izik Eidus, Gerd Hoffmann
5 * maintained by Gerd Hoffmann <kraxel@redhat.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, see <http://www.gnu.org/licenses/>.
23 #include "qemu-common.h"
24 #include "qemu/timer.h"
25 #include "qemu/queue.h"
26 #include "monitor/monitor.h"
27 #include "sysemu/sysemu.h"
33 * NOTE: SPICE_RING_PROD_ITEM accesses memory on the pci bar and as
34 * such can be changed by the guest, so to avoid a guest trigerrable
35 * abort we just qxl_set_guest_bug and set the return to NULL. Still
36 * it may happen as a result of emulator bug as well.
38 #undef SPICE_RING_PROD_ITEM
39 #define SPICE_RING_PROD_ITEM(qxl, r, ret) { \
40 uint32_t prod = (r)->prod & SPICE_RING_INDEX_MASK(r); \
41 if (prod >= ARRAY_SIZE((r)->items)) { \
42 qxl_set_guest_bug(qxl, "SPICE_RING_PROD_ITEM indices mismatch " \
43 "%u >= %zu", prod, ARRAY_SIZE((r)->items)); \
46 ret = &(r)->items[prod].el; \
50 #undef SPICE_RING_CONS_ITEM
51 #define SPICE_RING_CONS_ITEM(qxl, r, ret) { \
52 uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r); \
53 if (cons >= ARRAY_SIZE((r)->items)) { \
54 qxl_set_guest_bug(qxl, "SPICE_RING_CONS_ITEM indices mismatch " \
55 "%u >= %zu", cons, ARRAY_SIZE((r)->items)); \
58 ret = &(r)->items[cons].el; \
63 #define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1))
65 #define PIXEL_SIZE 0.2936875 //1280x1024 is 14.8" x 11.9"
67 #define QXL_MODE(_x, _y, _b, _o) \
71 .stride = (_x) * (_b) / 8, \
72 .x_mili = PIXEL_SIZE * (_x), \
73 .y_mili = PIXEL_SIZE * (_y), \
77 #define QXL_MODE_16_32(x_res, y_res, orientation) \
78 QXL_MODE(x_res, y_res, 16, orientation), \
79 QXL_MODE(x_res, y_res, 32, orientation)
81 #define QXL_MODE_EX(x_res, y_res) \
82 QXL_MODE_16_32(x_res, y_res, 0), \
83 QXL_MODE_16_32(x_res, y_res, 1)
85 static QXLMode qxl_modes
[] = {
86 QXL_MODE_EX(640, 480),
87 QXL_MODE_EX(800, 480),
88 QXL_MODE_EX(800, 600),
89 QXL_MODE_EX(832, 624),
90 QXL_MODE_EX(960, 640),
91 QXL_MODE_EX(1024, 600),
92 QXL_MODE_EX(1024, 768),
93 QXL_MODE_EX(1152, 864),
94 QXL_MODE_EX(1152, 870),
95 QXL_MODE_EX(1280, 720),
96 QXL_MODE_EX(1280, 760),
97 QXL_MODE_EX(1280, 768),
98 QXL_MODE_EX(1280, 800),
99 QXL_MODE_EX(1280, 960),
100 QXL_MODE_EX(1280, 1024),
101 QXL_MODE_EX(1360, 768),
102 QXL_MODE_EX(1366, 768),
103 QXL_MODE_EX(1400, 1050),
104 QXL_MODE_EX(1440, 900),
105 QXL_MODE_EX(1600, 900),
106 QXL_MODE_EX(1600, 1200),
107 QXL_MODE_EX(1680, 1050),
108 QXL_MODE_EX(1920, 1080),
109 /* these modes need more than 8 MB video memory */
110 QXL_MODE_EX(1920, 1200),
111 QXL_MODE_EX(1920, 1440),
112 QXL_MODE_EX(2000, 2000),
113 QXL_MODE_EX(2048, 1536),
114 QXL_MODE_EX(2048, 2048),
115 QXL_MODE_EX(2560, 1440),
116 QXL_MODE_EX(2560, 1600),
117 /* these modes need more than 16 MB video memory */
118 QXL_MODE_EX(2560, 2048),
119 QXL_MODE_EX(2800, 2100),
120 QXL_MODE_EX(3200, 2400),
121 QXL_MODE_EX(3840, 2160), /* 4k mainstream */
122 QXL_MODE_EX(4096, 2160), /* 4k */
123 QXL_MODE_EX(7680, 4320), /* 8k mainstream */
124 QXL_MODE_EX(8192, 4320), /* 8k */
127 static void qxl_send_events(PCIQXLDevice
*d
, uint32_t events
);
128 static int qxl_destroy_primary(PCIQXLDevice
*d
, qxl_async_io async
);
129 static void qxl_reset_memslots(PCIQXLDevice
*d
);
130 static void qxl_reset_surfaces(PCIQXLDevice
*d
);
131 static void qxl_ring_set_dirty(PCIQXLDevice
*qxl
);
133 void qxl_set_guest_bug(PCIQXLDevice
*qxl
, const char *msg
, ...)
135 trace_qxl_set_guest_bug(qxl
->id
);
136 qxl_send_events(qxl
, QXL_INTERRUPT_ERROR
);
138 if (qxl
->guestdebug
) {
141 fprintf(stderr
, "qxl-%d: guest bug: ", qxl
->id
);
142 vfprintf(stderr
, msg
, ap
);
143 fprintf(stderr
, "\n");
148 static void qxl_clear_guest_bug(PCIQXLDevice
*qxl
)
153 void qxl_spice_update_area(PCIQXLDevice
*qxl
, uint32_t surface_id
,
154 struct QXLRect
*area
, struct QXLRect
*dirty_rects
,
155 uint32_t num_dirty_rects
,
156 uint32_t clear_dirty_region
,
157 qxl_async_io async
, struct QXLCookie
*cookie
)
159 trace_qxl_spice_update_area(qxl
->id
, surface_id
, area
->left
, area
->right
,
160 area
->top
, area
->bottom
);
161 trace_qxl_spice_update_area_rest(qxl
->id
, num_dirty_rects
,
163 if (async
== QXL_SYNC
) {
164 qxl
->ssd
.worker
->update_area(qxl
->ssd
.worker
, surface_id
, area
,
165 dirty_rects
, num_dirty_rects
, clear_dirty_region
);
167 assert(cookie
!= NULL
);
168 spice_qxl_update_area_async(&qxl
->ssd
.qxl
, surface_id
, area
,
169 clear_dirty_region
, (uintptr_t)cookie
);
173 static void qxl_spice_destroy_surface_wait_complete(PCIQXLDevice
*qxl
,
176 trace_qxl_spice_destroy_surface_wait_complete(qxl
->id
, id
);
177 qemu_mutex_lock(&qxl
->track_lock
);
178 qxl
->guest_surfaces
.cmds
[id
] = 0;
179 qxl
->guest_surfaces
.count
--;
180 qemu_mutex_unlock(&qxl
->track_lock
);
183 static void qxl_spice_destroy_surface_wait(PCIQXLDevice
*qxl
, uint32_t id
,
188 trace_qxl_spice_destroy_surface_wait(qxl
->id
, id
, async
);
190 cookie
= qxl_cookie_new(QXL_COOKIE_TYPE_IO
,
191 QXL_IO_DESTROY_SURFACE_ASYNC
);
192 cookie
->u
.surface_id
= id
;
193 spice_qxl_destroy_surface_async(&qxl
->ssd
.qxl
, id
, (uintptr_t)cookie
);
195 qxl
->ssd
.worker
->destroy_surface_wait(qxl
->ssd
.worker
, id
);
196 qxl_spice_destroy_surface_wait_complete(qxl
, id
);
200 static void qxl_spice_flush_surfaces_async(PCIQXLDevice
*qxl
)
202 trace_qxl_spice_flush_surfaces_async(qxl
->id
, qxl
->guest_surfaces
.count
,
204 spice_qxl_flush_surfaces_async(&qxl
->ssd
.qxl
,
205 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO
,
206 QXL_IO_FLUSH_SURFACES_ASYNC
));
209 void qxl_spice_loadvm_commands(PCIQXLDevice
*qxl
, struct QXLCommandExt
*ext
,
212 trace_qxl_spice_loadvm_commands(qxl
->id
, ext
, count
);
213 qxl
->ssd
.worker
->loadvm_commands(qxl
->ssd
.worker
, ext
, count
);
216 void qxl_spice_oom(PCIQXLDevice
*qxl
)
218 trace_qxl_spice_oom(qxl
->id
);
219 qxl
->ssd
.worker
->oom(qxl
->ssd
.worker
);
222 void qxl_spice_reset_memslots(PCIQXLDevice
*qxl
)
224 trace_qxl_spice_reset_memslots(qxl
->id
);
225 qxl
->ssd
.worker
->reset_memslots(qxl
->ssd
.worker
);
228 static void qxl_spice_destroy_surfaces_complete(PCIQXLDevice
*qxl
)
230 trace_qxl_spice_destroy_surfaces_complete(qxl
->id
);
231 qemu_mutex_lock(&qxl
->track_lock
);
232 memset(qxl
->guest_surfaces
.cmds
, 0,
233 sizeof(qxl
->guest_surfaces
.cmds
[0]) * qxl
->ssd
.num_surfaces
);
234 qxl
->guest_surfaces
.count
= 0;
235 qemu_mutex_unlock(&qxl
->track_lock
);
238 static void qxl_spice_destroy_surfaces(PCIQXLDevice
*qxl
, qxl_async_io async
)
240 trace_qxl_spice_destroy_surfaces(qxl
->id
, async
);
242 spice_qxl_destroy_surfaces_async(&qxl
->ssd
.qxl
,
243 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO
,
244 QXL_IO_DESTROY_ALL_SURFACES_ASYNC
));
246 qxl
->ssd
.worker
->destroy_surfaces(qxl
->ssd
.worker
);
247 qxl_spice_destroy_surfaces_complete(qxl
);
251 static void qxl_spice_monitors_config_async(PCIQXLDevice
*qxl
, int replay
)
253 trace_qxl_spice_monitors_config(qxl
->id
);
256 * don't use QXL_COOKIE_TYPE_IO:
257 * - we are not running yet (post_load), we will assert
259 * - this is not a guest io, but a reply, so async_io isn't set.
261 spice_qxl_monitors_config_async(&qxl
->ssd
.qxl
,
262 qxl
->guest_monitors_config
,
264 (uintptr_t)qxl_cookie_new(
265 QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG
,
268 qxl
->guest_monitors_config
= qxl
->ram
->monitors_config
;
269 spice_qxl_monitors_config_async(&qxl
->ssd
.qxl
,
270 qxl
->ram
->monitors_config
,
272 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO
,
273 QXL_IO_MONITORS_CONFIG_ASYNC
));
277 void qxl_spice_reset_image_cache(PCIQXLDevice
*qxl
)
279 trace_qxl_spice_reset_image_cache(qxl
->id
);
280 qxl
->ssd
.worker
->reset_image_cache(qxl
->ssd
.worker
);
283 void qxl_spice_reset_cursor(PCIQXLDevice
*qxl
)
285 trace_qxl_spice_reset_cursor(qxl
->id
);
286 qxl
->ssd
.worker
->reset_cursor(qxl
->ssd
.worker
);
287 qemu_mutex_lock(&qxl
->track_lock
);
288 qxl
->guest_cursor
= 0;
289 qemu_mutex_unlock(&qxl
->track_lock
);
290 if (qxl
->ssd
.cursor
) {
291 cursor_put(qxl
->ssd
.cursor
);
293 qxl
->ssd
.cursor
= cursor_builtin_hidden();
297 static inline uint32_t msb_mask(uint32_t val
)
302 mask
= ~(val
- 1) & val
;
304 } while (mask
< val
);
309 static ram_addr_t
qxl_rom_size(void)
311 uint32_t required_rom_size
= sizeof(QXLRom
) + sizeof(QXLModes
) +
313 uint32_t rom_size
= 8192; /* two pages */
315 required_rom_size
= MAX(required_rom_size
, TARGET_PAGE_SIZE
);
316 required_rom_size
= msb_mask(required_rom_size
* 2 - 1);
317 assert(required_rom_size
<= rom_size
);
321 static void init_qxl_rom(PCIQXLDevice
*d
)
323 QXLRom
*rom
= memory_region_get_ram_ptr(&d
->rom_bar
);
324 QXLModes
*modes
= (QXLModes
*)(rom
+ 1);
325 uint32_t ram_header_size
;
326 uint32_t surface0_area_size
;
331 memset(rom
, 0, d
->rom_size
);
333 rom
->magic
= cpu_to_le32(QXL_ROM_MAGIC
);
334 rom
->id
= cpu_to_le32(d
->id
);
335 rom
->log_level
= cpu_to_le32(d
->guestdebug
);
336 rom
->modes_offset
= cpu_to_le32(sizeof(QXLRom
));
338 rom
->slot_gen_bits
= MEMSLOT_GENERATION_BITS
;
339 rom
->slot_id_bits
= MEMSLOT_SLOT_BITS
;
340 rom
->slots_start
= 1;
341 rom
->slots_end
= NUM_MEMSLOTS
- 1;
342 rom
->n_surfaces
= cpu_to_le32(d
->ssd
.num_surfaces
);
344 for (i
= 0, n
= 0; i
< ARRAY_SIZE(qxl_modes
); i
++) {
345 fb
= qxl_modes
[i
].y_res
* qxl_modes
[i
].stride
;
346 if (fb
> d
->vgamem_size
) {
349 modes
->modes
[n
].id
= cpu_to_le32(i
);
350 modes
->modes
[n
].x_res
= cpu_to_le32(qxl_modes
[i
].x_res
);
351 modes
->modes
[n
].y_res
= cpu_to_le32(qxl_modes
[i
].y_res
);
352 modes
->modes
[n
].bits
= cpu_to_le32(qxl_modes
[i
].bits
);
353 modes
->modes
[n
].stride
= cpu_to_le32(qxl_modes
[i
].stride
);
354 modes
->modes
[n
].x_mili
= cpu_to_le32(qxl_modes
[i
].x_mili
);
355 modes
->modes
[n
].y_mili
= cpu_to_le32(qxl_modes
[i
].y_mili
);
356 modes
->modes
[n
].orientation
= cpu_to_le32(qxl_modes
[i
].orientation
);
359 modes
->n_modes
= cpu_to_le32(n
);
361 ram_header_size
= ALIGN(sizeof(QXLRam
), 4096);
362 surface0_area_size
= ALIGN(d
->vgamem_size
, 4096);
363 num_pages
= d
->vga
.vram_size
;
364 num_pages
-= ram_header_size
;
365 num_pages
-= surface0_area_size
;
366 num_pages
= num_pages
/ TARGET_PAGE_SIZE
;
368 rom
->draw_area_offset
= cpu_to_le32(0);
369 rom
->surface0_area_size
= cpu_to_le32(surface0_area_size
);
370 rom
->pages_offset
= cpu_to_le32(surface0_area_size
);
371 rom
->num_pages
= cpu_to_le32(num_pages
);
372 rom
->ram_header_offset
= cpu_to_le32(d
->vga
.vram_size
- ram_header_size
);
374 d
->shadow_rom
= *rom
;
379 static void init_qxl_ram(PCIQXLDevice
*d
)
384 buf
= d
->vga
.vram_ptr
;
385 d
->ram
= (QXLRam
*)(buf
+ le32_to_cpu(d
->shadow_rom
.ram_header_offset
));
386 d
->ram
->magic
= cpu_to_le32(QXL_RAM_MAGIC
);
387 d
->ram
->int_pending
= cpu_to_le32(0);
388 d
->ram
->int_mask
= cpu_to_le32(0);
389 d
->ram
->update_surface
= 0;
390 SPICE_RING_INIT(&d
->ram
->cmd_ring
);
391 SPICE_RING_INIT(&d
->ram
->cursor_ring
);
392 SPICE_RING_INIT(&d
->ram
->release_ring
);
393 SPICE_RING_PROD_ITEM(d
, &d
->ram
->release_ring
, item
);
396 qxl_ring_set_dirty(d
);
399 /* can be called from spice server thread context */
400 static void qxl_set_dirty(MemoryRegion
*mr
, ram_addr_t addr
, ram_addr_t end
)
402 memory_region_set_dirty(mr
, addr
, end
- addr
);
405 static void qxl_rom_set_dirty(PCIQXLDevice
*qxl
)
407 qxl_set_dirty(&qxl
->rom_bar
, 0, qxl
->rom_size
);
410 /* called from spice server thread context only */
411 static void qxl_ram_set_dirty(PCIQXLDevice
*qxl
, void *ptr
)
413 void *base
= qxl
->vga
.vram_ptr
;
417 offset
&= ~(TARGET_PAGE_SIZE
-1);
418 assert(offset
< qxl
->vga
.vram_size
);
419 qxl_set_dirty(&qxl
->vga
.vram
, offset
, offset
+ TARGET_PAGE_SIZE
);
422 /* can be called from spice server thread context */
423 static void qxl_ring_set_dirty(PCIQXLDevice
*qxl
)
425 ram_addr_t addr
= qxl
->shadow_rom
.ram_header_offset
;
426 ram_addr_t end
= qxl
->vga
.vram_size
;
427 qxl_set_dirty(&qxl
->vga
.vram
, addr
, end
);
431 * keep track of some command state, for savevm/loadvm.
432 * called from spice server thread context only
434 static int qxl_track_command(PCIQXLDevice
*qxl
, struct QXLCommandExt
*ext
)
436 switch (le32_to_cpu(ext
->cmd
.type
)) {
437 case QXL_CMD_SURFACE
:
439 QXLSurfaceCmd
*cmd
= qxl_phys2virt(qxl
, ext
->cmd
.data
, ext
->group_id
);
444 uint32_t id
= le32_to_cpu(cmd
->surface_id
);
446 if (id
>= qxl
->ssd
.num_surfaces
) {
447 qxl_set_guest_bug(qxl
, "QXL_CMD_SURFACE id %d >= %d", id
,
448 qxl
->ssd
.num_surfaces
);
451 if (cmd
->type
== QXL_SURFACE_CMD_CREATE
&&
452 (cmd
->u
.surface_create
.stride
& 0x03) != 0) {
453 qxl_set_guest_bug(qxl
, "QXL_CMD_SURFACE stride = %d %% 4 != 0\n",
454 cmd
->u
.surface_create
.stride
);
457 qemu_mutex_lock(&qxl
->track_lock
);
458 if (cmd
->type
== QXL_SURFACE_CMD_CREATE
) {
459 qxl
->guest_surfaces
.cmds
[id
] = ext
->cmd
.data
;
460 qxl
->guest_surfaces
.count
++;
461 if (qxl
->guest_surfaces
.max
< qxl
->guest_surfaces
.count
)
462 qxl
->guest_surfaces
.max
= qxl
->guest_surfaces
.count
;
464 if (cmd
->type
== QXL_SURFACE_CMD_DESTROY
) {
465 qxl
->guest_surfaces
.cmds
[id
] = 0;
466 qxl
->guest_surfaces
.count
--;
468 qemu_mutex_unlock(&qxl
->track_lock
);
473 QXLCursorCmd
*cmd
= qxl_phys2virt(qxl
, ext
->cmd
.data
, ext
->group_id
);
478 if (cmd
->type
== QXL_CURSOR_SET
) {
479 qemu_mutex_lock(&qxl
->track_lock
);
480 qxl
->guest_cursor
= ext
->cmd
.data
;
481 qemu_mutex_unlock(&qxl
->track_lock
);
489 /* spice display interface callbacks */
491 static void interface_attach_worker(QXLInstance
*sin
, QXLWorker
*qxl_worker
)
493 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
495 trace_qxl_interface_attach_worker(qxl
->id
);
496 qxl
->ssd
.worker
= qxl_worker
;
499 static void interface_set_compression_level(QXLInstance
*sin
, int level
)
501 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
503 trace_qxl_interface_set_compression_level(qxl
->id
, level
);
504 qxl
->shadow_rom
.compression_level
= cpu_to_le32(level
);
505 qxl
->rom
->compression_level
= cpu_to_le32(level
);
506 qxl_rom_set_dirty(qxl
);
509 static void interface_set_mm_time(QXLInstance
*sin
, uint32_t mm_time
)
511 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
513 trace_qxl_interface_set_mm_time(qxl
->id
, mm_time
);
514 qxl
->shadow_rom
.mm_clock
= cpu_to_le32(mm_time
);
515 qxl
->rom
->mm_clock
= cpu_to_le32(mm_time
);
516 qxl_rom_set_dirty(qxl
);
519 static void interface_get_init_info(QXLInstance
*sin
, QXLDevInitInfo
*info
)
521 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
523 trace_qxl_interface_get_init_info(qxl
->id
);
524 info
->memslot_gen_bits
= MEMSLOT_GENERATION_BITS
;
525 info
->memslot_id_bits
= MEMSLOT_SLOT_BITS
;
526 info
->num_memslots
= NUM_MEMSLOTS
;
527 info
->num_memslots_groups
= NUM_MEMSLOTS_GROUPS
;
528 info
->internal_groupslot_id
= 0;
529 info
->qxl_ram_size
= le32_to_cpu(qxl
->shadow_rom
.num_pages
) << TARGET_PAGE_BITS
;
530 info
->n_surfaces
= qxl
->ssd
.num_surfaces
;
533 static const char *qxl_mode_to_string(int mode
)
536 case QXL_MODE_COMPAT
:
538 case QXL_MODE_NATIVE
:
540 case QXL_MODE_UNDEFINED
:
548 static const char *io_port_to_string(uint32_t io_port
)
550 if (io_port
>= QXL_IO_RANGE_SIZE
) {
551 return "out of range";
553 static const char *io_port_to_string
[QXL_IO_RANGE_SIZE
+ 1] = {
554 [QXL_IO_NOTIFY_CMD
] = "QXL_IO_NOTIFY_CMD",
555 [QXL_IO_NOTIFY_CURSOR
] = "QXL_IO_NOTIFY_CURSOR",
556 [QXL_IO_UPDATE_AREA
] = "QXL_IO_UPDATE_AREA",
557 [QXL_IO_UPDATE_IRQ
] = "QXL_IO_UPDATE_IRQ",
558 [QXL_IO_NOTIFY_OOM
] = "QXL_IO_NOTIFY_OOM",
559 [QXL_IO_RESET
] = "QXL_IO_RESET",
560 [QXL_IO_SET_MODE
] = "QXL_IO_SET_MODE",
561 [QXL_IO_LOG
] = "QXL_IO_LOG",
562 [QXL_IO_MEMSLOT_ADD
] = "QXL_IO_MEMSLOT_ADD",
563 [QXL_IO_MEMSLOT_DEL
] = "QXL_IO_MEMSLOT_DEL",
564 [QXL_IO_DETACH_PRIMARY
] = "QXL_IO_DETACH_PRIMARY",
565 [QXL_IO_ATTACH_PRIMARY
] = "QXL_IO_ATTACH_PRIMARY",
566 [QXL_IO_CREATE_PRIMARY
] = "QXL_IO_CREATE_PRIMARY",
567 [QXL_IO_DESTROY_PRIMARY
] = "QXL_IO_DESTROY_PRIMARY",
568 [QXL_IO_DESTROY_SURFACE_WAIT
] = "QXL_IO_DESTROY_SURFACE_WAIT",
569 [QXL_IO_DESTROY_ALL_SURFACES
] = "QXL_IO_DESTROY_ALL_SURFACES",
570 [QXL_IO_UPDATE_AREA_ASYNC
] = "QXL_IO_UPDATE_AREA_ASYNC",
571 [QXL_IO_MEMSLOT_ADD_ASYNC
] = "QXL_IO_MEMSLOT_ADD_ASYNC",
572 [QXL_IO_CREATE_PRIMARY_ASYNC
] = "QXL_IO_CREATE_PRIMARY_ASYNC",
573 [QXL_IO_DESTROY_PRIMARY_ASYNC
] = "QXL_IO_DESTROY_PRIMARY_ASYNC",
574 [QXL_IO_DESTROY_SURFACE_ASYNC
] = "QXL_IO_DESTROY_SURFACE_ASYNC",
575 [QXL_IO_DESTROY_ALL_SURFACES_ASYNC
]
576 = "QXL_IO_DESTROY_ALL_SURFACES_ASYNC",
577 [QXL_IO_FLUSH_SURFACES_ASYNC
] = "QXL_IO_FLUSH_SURFACES_ASYNC",
578 [QXL_IO_FLUSH_RELEASE
] = "QXL_IO_FLUSH_RELEASE",
579 [QXL_IO_MONITORS_CONFIG_ASYNC
] = "QXL_IO_MONITORS_CONFIG_ASYNC",
581 return io_port_to_string
[io_port
];
584 /* called from spice server thread context only */
585 static int interface_get_command(QXLInstance
*sin
, struct QXLCommandExt
*ext
)
587 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
588 SimpleSpiceUpdate
*update
;
589 QXLCommandRing
*ring
;
593 trace_qxl_ring_command_check(qxl
->id
, qxl_mode_to_string(qxl
->mode
));
598 qemu_mutex_lock(&qxl
->ssd
.lock
);
599 update
= QTAILQ_FIRST(&qxl
->ssd
.updates
);
600 if (update
!= NULL
) {
601 QTAILQ_REMOVE(&qxl
->ssd
.updates
, update
, next
);
605 qemu_mutex_unlock(&qxl
->ssd
.lock
);
607 trace_qxl_ring_command_get(qxl
->id
, qxl_mode_to_string(qxl
->mode
));
608 qxl_log_command(qxl
, "vga", ext
);
611 case QXL_MODE_COMPAT
:
612 case QXL_MODE_NATIVE
:
613 case QXL_MODE_UNDEFINED
:
614 ring
= &qxl
->ram
->cmd_ring
;
615 if (qxl
->guest_bug
|| SPICE_RING_IS_EMPTY(ring
)) {
618 SPICE_RING_CONS_ITEM(qxl
, ring
, cmd
);
623 ext
->group_id
= MEMSLOT_GROUP_GUEST
;
624 ext
->flags
= qxl
->cmdflags
;
625 SPICE_RING_POP(ring
, notify
);
626 qxl_ring_set_dirty(qxl
);
628 qxl_send_events(qxl
, QXL_INTERRUPT_DISPLAY
);
630 qxl
->guest_primary
.commands
++;
631 qxl_track_command(qxl
, ext
);
632 qxl_log_command(qxl
, "cmd", ext
);
633 trace_qxl_ring_command_get(qxl
->id
, qxl_mode_to_string(qxl
->mode
));
640 /* called from spice server thread context only */
641 static int interface_req_cmd_notification(QXLInstance
*sin
)
643 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
646 trace_qxl_ring_command_req_notification(qxl
->id
);
648 case QXL_MODE_COMPAT
:
649 case QXL_MODE_NATIVE
:
650 case QXL_MODE_UNDEFINED
:
651 SPICE_RING_CONS_WAIT(&qxl
->ram
->cmd_ring
, wait
);
652 qxl_ring_set_dirty(qxl
);
661 /* called from spice server thread context only */
662 static inline void qxl_push_free_res(PCIQXLDevice
*d
, int flush
)
664 QXLReleaseRing
*ring
= &d
->ram
->release_ring
;
668 #define QXL_FREE_BUNCH_SIZE 32
670 if (ring
->prod
- ring
->cons
+ 1 == ring
->num_items
) {
671 /* ring full -- can't push */
674 if (!flush
&& d
->oom_running
) {
675 /* collect everything from oom handler before pushing */
678 if (!flush
&& d
->num_free_res
< QXL_FREE_BUNCH_SIZE
) {
679 /* collect a bit more before pushing */
683 SPICE_RING_PUSH(ring
, notify
);
684 trace_qxl_ring_res_push(d
->id
, qxl_mode_to_string(d
->mode
),
685 d
->guest_surfaces
.count
, d
->num_free_res
,
686 d
->last_release
, notify
? "yes" : "no");
687 trace_qxl_ring_res_push_rest(d
->id
, ring
->prod
- ring
->cons
,
688 ring
->num_items
, ring
->prod
, ring
->cons
);
690 qxl_send_events(d
, QXL_INTERRUPT_DISPLAY
);
692 SPICE_RING_PROD_ITEM(d
, ring
, item
);
698 d
->last_release
= NULL
;
699 qxl_ring_set_dirty(d
);
702 /* called from spice server thread context only */
703 static void interface_release_resource(QXLInstance
*sin
,
704 struct QXLReleaseInfoExt ext
)
706 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
707 QXLReleaseRing
*ring
;
710 if (ext
.group_id
== MEMSLOT_GROUP_HOST
) {
711 /* host group -> vga mode update request */
712 qemu_spice_destroy_update(&qxl
->ssd
, (void *)(intptr_t)ext
.info
->id
);
717 * ext->info points into guest-visible memory
718 * pci bar 0, $command.release_info
720 ring
= &qxl
->ram
->release_ring
;
721 SPICE_RING_PROD_ITEM(qxl
, ring
, item
);
726 /* stick head into the ring */
729 qxl_ram_set_dirty(qxl
, &ext
.info
->next
);
731 qxl_ring_set_dirty(qxl
);
733 /* append item to the list */
734 qxl
->last_release
->next
= ext
.info
->id
;
735 qxl_ram_set_dirty(qxl
, &qxl
->last_release
->next
);
737 qxl_ram_set_dirty(qxl
, &ext
.info
->next
);
739 qxl
->last_release
= ext
.info
;
741 trace_qxl_ring_res_put(qxl
->id
, qxl
->num_free_res
);
742 qxl_push_free_res(qxl
, 0);
745 /* called from spice server thread context only */
746 static int interface_get_cursor_command(QXLInstance
*sin
, struct QXLCommandExt
*ext
)
748 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
753 trace_qxl_ring_cursor_check(qxl
->id
, qxl_mode_to_string(qxl
->mode
));
756 case QXL_MODE_COMPAT
:
757 case QXL_MODE_NATIVE
:
758 case QXL_MODE_UNDEFINED
:
759 ring
= &qxl
->ram
->cursor_ring
;
760 if (SPICE_RING_IS_EMPTY(ring
)) {
763 SPICE_RING_CONS_ITEM(qxl
, ring
, cmd
);
768 ext
->group_id
= MEMSLOT_GROUP_GUEST
;
769 ext
->flags
= qxl
->cmdflags
;
770 SPICE_RING_POP(ring
, notify
);
771 qxl_ring_set_dirty(qxl
);
773 qxl_send_events(qxl
, QXL_INTERRUPT_CURSOR
);
775 qxl
->guest_primary
.commands
++;
776 qxl_track_command(qxl
, ext
);
777 qxl_log_command(qxl
, "csr", ext
);
779 qxl_render_cursor(qxl
, ext
);
781 trace_qxl_ring_cursor_get(qxl
->id
, qxl_mode_to_string(qxl
->mode
));
788 /* called from spice server thread context only */
789 static int interface_req_cursor_notification(QXLInstance
*sin
)
791 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
794 trace_qxl_ring_cursor_req_notification(qxl
->id
);
796 case QXL_MODE_COMPAT
:
797 case QXL_MODE_NATIVE
:
798 case QXL_MODE_UNDEFINED
:
799 SPICE_RING_CONS_WAIT(&qxl
->ram
->cursor_ring
, wait
);
800 qxl_ring_set_dirty(qxl
);
809 /* called from spice server thread context */
810 static void interface_notify_update(QXLInstance
*sin
, uint32_t update_id
)
813 * Called by spice-server as a result of a QXL_CMD_UPDATE which is not in
814 * use by xf86-video-qxl and is defined out in the qxl windows driver.
815 * Probably was at some earlier version that is prior to git start (2009),
816 * and is still guest trigerrable.
818 fprintf(stderr
, "%s: deprecated\n", __func__
);
821 /* called from spice server thread context only */
822 static int interface_flush_resources(QXLInstance
*sin
)
824 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
827 ret
= qxl
->num_free_res
;
829 qxl_push_free_res(qxl
, 1);
834 static void qxl_create_guest_primary_complete(PCIQXLDevice
*d
);
836 /* called from spice server thread context only */
837 static void interface_async_complete_io(PCIQXLDevice
*qxl
, QXLCookie
*cookie
)
839 uint32_t current_async
;
841 qemu_mutex_lock(&qxl
->async_lock
);
842 current_async
= qxl
->current_async
;
843 qxl
->current_async
= QXL_UNDEFINED_IO
;
844 qemu_mutex_unlock(&qxl
->async_lock
);
846 trace_qxl_interface_async_complete_io(qxl
->id
, current_async
, cookie
);
848 fprintf(stderr
, "qxl: %s: error, cookie is NULL\n", __func__
);
851 if (cookie
&& current_async
!= cookie
->io
) {
853 "qxl: %s: error: current_async = %d != %"
854 PRId64
" = cookie->io\n", __func__
, current_async
, cookie
->io
);
856 switch (current_async
) {
857 case QXL_IO_MEMSLOT_ADD_ASYNC
:
858 case QXL_IO_DESTROY_PRIMARY_ASYNC
:
859 case QXL_IO_UPDATE_AREA_ASYNC
:
860 case QXL_IO_FLUSH_SURFACES_ASYNC
:
861 case QXL_IO_MONITORS_CONFIG_ASYNC
:
863 case QXL_IO_CREATE_PRIMARY_ASYNC
:
864 qxl_create_guest_primary_complete(qxl
);
866 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC
:
867 qxl_spice_destroy_surfaces_complete(qxl
);
869 case QXL_IO_DESTROY_SURFACE_ASYNC
:
870 qxl_spice_destroy_surface_wait_complete(qxl
, cookie
->u
.surface_id
);
873 fprintf(stderr
, "qxl: %s: unexpected current_async %d\n", __func__
,
876 qxl_send_events(qxl
, QXL_INTERRUPT_IO_CMD
);
879 /* called from spice server thread context only */
880 static void interface_update_area_complete(QXLInstance
*sin
,
882 QXLRect
*dirty
, uint32_t num_updated_rects
)
884 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
888 qemu_mutex_lock(&qxl
->ssd
.lock
);
889 if (surface_id
!= 0 || !qxl
->render_update_cookie_num
) {
890 qemu_mutex_unlock(&qxl
->ssd
.lock
);
893 trace_qxl_interface_update_area_complete(qxl
->id
, surface_id
, dirty
->left
,
894 dirty
->right
, dirty
->top
, dirty
->bottom
);
895 trace_qxl_interface_update_area_complete_rest(qxl
->id
, num_updated_rects
);
896 if (qxl
->num_dirty_rects
+ num_updated_rects
> QXL_NUM_DIRTY_RECTS
) {
898 * overflow - treat this as a full update. Not expected to be common.
900 trace_qxl_interface_update_area_complete_overflow(qxl
->id
,
901 QXL_NUM_DIRTY_RECTS
);
902 qxl
->guest_primary
.resized
= 1;
904 if (qxl
->guest_primary
.resized
) {
906 * Don't bother copying or scheduling the bh since we will flip
907 * the whole area anyway on completion of the update_area async call
909 qemu_mutex_unlock(&qxl
->ssd
.lock
);
912 qxl_i
= qxl
->num_dirty_rects
;
913 for (i
= 0; i
< num_updated_rects
; i
++) {
914 qxl
->dirty
[qxl_i
++] = dirty
[i
];
916 qxl
->num_dirty_rects
+= num_updated_rects
;
917 trace_qxl_interface_update_area_complete_schedule_bh(qxl
->id
,
918 qxl
->num_dirty_rects
);
919 qemu_bh_schedule(qxl
->update_area_bh
);
920 qemu_mutex_unlock(&qxl
->ssd
.lock
);
923 /* called from spice server thread context only */
924 static void interface_async_complete(QXLInstance
*sin
, uint64_t cookie_token
)
926 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
927 QXLCookie
*cookie
= (QXLCookie
*)(uintptr_t)cookie_token
;
929 switch (cookie
->type
) {
930 case QXL_COOKIE_TYPE_IO
:
931 interface_async_complete_io(qxl
, cookie
);
934 case QXL_COOKIE_TYPE_RENDER_UPDATE_AREA
:
935 qxl_render_update_area_done(qxl
, cookie
);
937 case QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG
:
940 fprintf(stderr
, "qxl: %s: unexpected cookie type %d\n",
941 __func__
, cookie
->type
);
946 /* called from spice server thread context only */
947 static void interface_set_client_capabilities(QXLInstance
*sin
,
948 uint8_t client_present
,
951 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
953 if (qxl
->revision
< 4) {
954 trace_qxl_set_client_capabilities_unsupported_by_revision(qxl
->id
,
959 if (runstate_check(RUN_STATE_INMIGRATE
) ||
960 runstate_check(RUN_STATE_POSTMIGRATE
)) {
964 qxl
->shadow_rom
.client_present
= client_present
;
965 memcpy(qxl
->shadow_rom
.client_capabilities
, caps
,
966 sizeof(qxl
->shadow_rom
.client_capabilities
));
967 qxl
->rom
->client_present
= client_present
;
968 memcpy(qxl
->rom
->client_capabilities
, caps
,
969 sizeof(qxl
->rom
->client_capabilities
));
970 qxl_rom_set_dirty(qxl
);
972 qxl_send_events(qxl
, QXL_INTERRUPT_CLIENT
);
975 static uint32_t qxl_crc32(const uint8_t *p
, unsigned len
)
978 * zlib xors the seed with 0xffffffff, and xors the result
979 * again with 0xffffffff; Both are not done with linux's crc32,
980 * which we want to be compatible with, so undo that.
982 return crc32(0xffffffff, p
, len
) ^ 0xffffffff;
985 /* called from main context only */
986 static int interface_client_monitors_config(QXLInstance
*sin
,
987 VDAgentMonitorsConfig
*monitors_config
)
989 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
990 QXLRom
*rom
= memory_region_get_ram_ptr(&qxl
->rom_bar
);
993 if (qxl
->revision
< 4) {
994 trace_qxl_client_monitors_config_unsupported_by_device(qxl
->id
,
999 * Older windows drivers set int_mask to 0 when their ISR is called,
1000 * then later set it to ~0. So it doesn't relate to the actual interrupts
1001 * handled. However, they are old, so clearly they don't support this
1004 if (qxl
->ram
->int_mask
== 0 || qxl
->ram
->int_mask
== ~0 ||
1005 !(qxl
->ram
->int_mask
& QXL_INTERRUPT_CLIENT_MONITORS_CONFIG
)) {
1006 trace_qxl_client_monitors_config_unsupported_by_guest(qxl
->id
,
1011 if (!monitors_config
) {
1014 memset(&rom
->client_monitors_config
, 0,
1015 sizeof(rom
->client_monitors_config
));
1016 rom
->client_monitors_config
.count
= monitors_config
->num_of_monitors
;
1017 /* monitors_config->flags ignored */
1018 if (rom
->client_monitors_config
.count
>=
1019 ARRAY_SIZE(rom
->client_monitors_config
.heads
)) {
1020 trace_qxl_client_monitors_config_capped(qxl
->id
,
1021 monitors_config
->num_of_monitors
,
1022 ARRAY_SIZE(rom
->client_monitors_config
.heads
));
1023 rom
->client_monitors_config
.count
=
1024 ARRAY_SIZE(rom
->client_monitors_config
.heads
);
1026 for (i
= 0 ; i
< rom
->client_monitors_config
.count
; ++i
) {
1027 VDAgentMonConfig
*monitor
= &monitors_config
->monitors
[i
];
1028 QXLURect
*rect
= &rom
->client_monitors_config
.heads
[i
];
1029 /* monitor->depth ignored */
1030 rect
->left
= monitor
->x
;
1031 rect
->top
= monitor
->y
;
1032 rect
->right
= monitor
->x
+ monitor
->width
;
1033 rect
->bottom
= monitor
->y
+ monitor
->height
;
1035 rom
->client_monitors_config_crc
= qxl_crc32(
1036 (const uint8_t *)&rom
->client_monitors_config
,
1037 sizeof(rom
->client_monitors_config
));
1038 trace_qxl_client_monitors_config_crc(qxl
->id
,
1039 sizeof(rom
->client_monitors_config
),
1040 rom
->client_monitors_config_crc
);
1042 trace_qxl_interrupt_client_monitors_config(qxl
->id
,
1043 rom
->client_monitors_config
.count
,
1044 rom
->client_monitors_config
.heads
);
1045 qxl_send_events(qxl
, QXL_INTERRUPT_CLIENT_MONITORS_CONFIG
);
1049 static const QXLInterface qxl_interface
= {
1050 .base
.type
= SPICE_INTERFACE_QXL
,
1051 .base
.description
= "qxl gpu",
1052 .base
.major_version
= SPICE_INTERFACE_QXL_MAJOR
,
1053 .base
.minor_version
= SPICE_INTERFACE_QXL_MINOR
,
1055 .attache_worker
= interface_attach_worker
,
1056 .set_compression_level
= interface_set_compression_level
,
1057 .set_mm_time
= interface_set_mm_time
,
1058 .get_init_info
= interface_get_init_info
,
1060 /* the callbacks below are called from spice server thread context */
1061 .get_command
= interface_get_command
,
1062 .req_cmd_notification
= interface_req_cmd_notification
,
1063 .release_resource
= interface_release_resource
,
1064 .get_cursor_command
= interface_get_cursor_command
,
1065 .req_cursor_notification
= interface_req_cursor_notification
,
1066 .notify_update
= interface_notify_update
,
1067 .flush_resources
= interface_flush_resources
,
1068 .async_complete
= interface_async_complete
,
1069 .update_area_complete
= interface_update_area_complete
,
1070 .set_client_capabilities
= interface_set_client_capabilities
,
1071 .client_monitors_config
= interface_client_monitors_config
,
1074 static void qxl_enter_vga_mode(PCIQXLDevice
*d
)
1076 if (d
->mode
== QXL_MODE_VGA
) {
1079 trace_qxl_enter_vga_mode(d
->id
);
1080 qemu_spice_create_host_primary(&d
->ssd
);
1081 d
->mode
= QXL_MODE_VGA
;
1082 vga_dirty_log_start(&d
->vga
);
1083 graphic_hw_update(d
->vga
.con
);
1086 static void qxl_exit_vga_mode(PCIQXLDevice
*d
)
1088 if (d
->mode
!= QXL_MODE_VGA
) {
1091 trace_qxl_exit_vga_mode(d
->id
);
1092 vga_dirty_log_stop(&d
->vga
);
1093 qxl_destroy_primary(d
, QXL_SYNC
);
1096 static void qxl_update_irq(PCIQXLDevice
*d
)
1098 uint32_t pending
= le32_to_cpu(d
->ram
->int_pending
);
1099 uint32_t mask
= le32_to_cpu(d
->ram
->int_mask
);
1100 int level
= !!(pending
& mask
);
1101 qemu_set_irq(d
->pci
.irq
[0], level
);
1102 qxl_ring_set_dirty(d
);
1105 static void qxl_check_state(PCIQXLDevice
*d
)
1107 QXLRam
*ram
= d
->ram
;
1108 int spice_display_running
= qemu_spice_display_is_running(&d
->ssd
);
1110 assert(!spice_display_running
|| SPICE_RING_IS_EMPTY(&ram
->cmd_ring
));
1111 assert(!spice_display_running
|| SPICE_RING_IS_EMPTY(&ram
->cursor_ring
));
1114 static void qxl_reset_state(PCIQXLDevice
*d
)
1116 QXLRom
*rom
= d
->rom
;
1119 d
->shadow_rom
.update_id
= cpu_to_le32(0);
1120 *rom
= d
->shadow_rom
;
1121 qxl_rom_set_dirty(d
);
1123 d
->num_free_res
= 0;
1124 d
->last_release
= NULL
;
1125 memset(&d
->ssd
.dirty
, 0, sizeof(d
->ssd
.dirty
));
1128 static void qxl_soft_reset(PCIQXLDevice
*d
)
1130 trace_qxl_soft_reset(d
->id
);
1132 qxl_clear_guest_bug(d
);
1133 d
->current_async
= QXL_UNDEFINED_IO
;
1136 qxl_enter_vga_mode(d
);
1138 d
->mode
= QXL_MODE_UNDEFINED
;
1142 static void qxl_hard_reset(PCIQXLDevice
*d
, int loadvm
)
1144 trace_qxl_hard_reset(d
->id
, loadvm
);
1146 qxl_spice_reset_cursor(d
);
1147 qxl_spice_reset_image_cache(d
);
1148 qxl_reset_surfaces(d
);
1149 qxl_reset_memslots(d
);
1151 /* pre loadvm reset must not touch QXLRam. This lives in
1152 * device memory, is migrated together with RAM and thus
1153 * already loaded at this point */
1157 qemu_spice_create_host_memslot(&d
->ssd
);
1161 static void qxl_reset_handler(DeviceState
*dev
)
1163 PCIQXLDevice
*d
= DO_UPCAST(PCIQXLDevice
, pci
.qdev
, dev
);
1165 qxl_hard_reset(d
, 0);
1168 static void qxl_vga_ioport_write(void *opaque
, uint32_t addr
, uint32_t val
)
1170 VGACommonState
*vga
= opaque
;
1171 PCIQXLDevice
*qxl
= container_of(vga
, PCIQXLDevice
, vga
);
1173 trace_qxl_io_write_vga(qxl
->id
, qxl_mode_to_string(qxl
->mode
), addr
, val
);
1174 if (qxl
->mode
!= QXL_MODE_VGA
) {
1175 qxl_destroy_primary(qxl
, QXL_SYNC
);
1176 qxl_soft_reset(qxl
);
1178 vga_ioport_write(opaque
, addr
, val
);
1181 static const MemoryRegionPortio qxl_vga_portio_list
[] = {
1182 { 0x04, 2, 1, .read
= vga_ioport_read
,
1183 .write
= qxl_vga_ioport_write
}, /* 3b4 */
1184 { 0x0a, 1, 1, .read
= vga_ioport_read
,
1185 .write
= qxl_vga_ioport_write
}, /* 3ba */
1186 { 0x10, 16, 1, .read
= vga_ioport_read
,
1187 .write
= qxl_vga_ioport_write
}, /* 3c0 */
1188 { 0x24, 2, 1, .read
= vga_ioport_read
,
1189 .write
= qxl_vga_ioport_write
}, /* 3d4 */
1190 { 0x2a, 1, 1, .read
= vga_ioport_read
,
1191 .write
= qxl_vga_ioport_write
}, /* 3da */
1192 PORTIO_END_OF_LIST(),
1195 static int qxl_add_memslot(PCIQXLDevice
*d
, uint32_t slot_id
, uint64_t delta
,
1198 static const int regions
[] = {
1199 QXL_RAM_RANGE_INDEX
,
1200 QXL_VRAM_RANGE_INDEX
,
1201 QXL_VRAM64_RANGE_INDEX
,
1203 uint64_t guest_start
;
1208 intptr_t virt_start
;
1209 QXLDevMemSlot memslot
;
1212 guest_start
= le64_to_cpu(d
->guest_slots
[slot_id
].slot
.mem_start
);
1213 guest_end
= le64_to_cpu(d
->guest_slots
[slot_id
].slot
.mem_end
);
1215 trace_qxl_memslot_add_guest(d
->id
, slot_id
, guest_start
, guest_end
);
1217 if (slot_id
>= NUM_MEMSLOTS
) {
1218 qxl_set_guest_bug(d
, "%s: slot_id >= NUM_MEMSLOTS %d >= %d", __func__
,
1219 slot_id
, NUM_MEMSLOTS
);
1222 if (guest_start
> guest_end
) {
1223 qxl_set_guest_bug(d
, "%s: guest_start > guest_end 0x%" PRIx64
1224 " > 0x%" PRIx64
, __func__
, guest_start
, guest_end
);
1228 for (i
= 0; i
< ARRAY_SIZE(regions
); i
++) {
1229 pci_region
= regions
[i
];
1230 pci_start
= d
->pci
.io_regions
[pci_region
].addr
;
1231 pci_end
= pci_start
+ d
->pci
.io_regions
[pci_region
].size
;
1233 if (pci_start
== -1) {
1236 /* start address in range ? */
1237 if (guest_start
< pci_start
|| guest_start
> pci_end
) {
1240 /* end address in range ? */
1241 if (guest_end
> pci_end
) {
1247 if (i
== ARRAY_SIZE(regions
)) {
1248 qxl_set_guest_bug(d
, "%s: finished loop without match", __func__
);
1252 switch (pci_region
) {
1253 case QXL_RAM_RANGE_INDEX
:
1254 virt_start
= (intptr_t)memory_region_get_ram_ptr(&d
->vga
.vram
);
1256 case QXL_VRAM_RANGE_INDEX
:
1257 case 4 /* vram 64bit */:
1258 virt_start
= (intptr_t)memory_region_get_ram_ptr(&d
->vram_bar
);
1261 /* should not happen */
1262 qxl_set_guest_bug(d
, "%s: pci_region = %d", __func__
, pci_region
);
1266 memslot
.slot_id
= slot_id
;
1267 memslot
.slot_group_id
= MEMSLOT_GROUP_GUEST
; /* guest group */
1268 memslot
.virt_start
= virt_start
+ (guest_start
- pci_start
);
1269 memslot
.virt_end
= virt_start
+ (guest_end
- pci_start
);
1270 memslot
.addr_delta
= memslot
.virt_start
- delta
;
1271 memslot
.generation
= d
->rom
->slot_generation
= 0;
1272 qxl_rom_set_dirty(d
);
1274 qemu_spice_add_memslot(&d
->ssd
, &memslot
, async
);
1275 d
->guest_slots
[slot_id
].ptr
= (void*)memslot
.virt_start
;
1276 d
->guest_slots
[slot_id
].size
= memslot
.virt_end
- memslot
.virt_start
;
1277 d
->guest_slots
[slot_id
].delta
= delta
;
1278 d
->guest_slots
[slot_id
].active
= 1;
1282 static void qxl_del_memslot(PCIQXLDevice
*d
, uint32_t slot_id
)
1284 qemu_spice_del_memslot(&d
->ssd
, MEMSLOT_GROUP_HOST
, slot_id
);
1285 d
->guest_slots
[slot_id
].active
= 0;
1288 static void qxl_reset_memslots(PCIQXLDevice
*d
)
1290 qxl_spice_reset_memslots(d
);
1291 memset(&d
->guest_slots
, 0, sizeof(d
->guest_slots
));
1294 static void qxl_reset_surfaces(PCIQXLDevice
*d
)
1296 trace_qxl_reset_surfaces(d
->id
);
1297 d
->mode
= QXL_MODE_UNDEFINED
;
1298 qxl_spice_destroy_surfaces(d
, QXL_SYNC
);
1301 /* can be also called from spice server thread context */
1302 void *qxl_phys2virt(PCIQXLDevice
*qxl
, QXLPHYSICAL pqxl
, int group_id
)
1304 uint64_t phys
= le64_to_cpu(pqxl
);
1305 uint32_t slot
= (phys
>> (64 - 8)) & 0xff;
1306 uint64_t offset
= phys
& 0xffffffffffff;
1309 case MEMSLOT_GROUP_HOST
:
1310 return (void *)(intptr_t)offset
;
1311 case MEMSLOT_GROUP_GUEST
:
1312 if (slot
>= NUM_MEMSLOTS
) {
1313 qxl_set_guest_bug(qxl
, "slot too large %d >= %d", slot
,
1317 if (!qxl
->guest_slots
[slot
].active
) {
1318 qxl_set_guest_bug(qxl
, "inactive slot %d\n", slot
);
1321 if (offset
< qxl
->guest_slots
[slot
].delta
) {
1322 qxl_set_guest_bug(qxl
,
1323 "slot %d offset %"PRIu64
" < delta %"PRIu64
"\n",
1324 slot
, offset
, qxl
->guest_slots
[slot
].delta
);
1327 offset
-= qxl
->guest_slots
[slot
].delta
;
1328 if (offset
> qxl
->guest_slots
[slot
].size
) {
1329 qxl_set_guest_bug(qxl
,
1330 "slot %d offset %"PRIu64
" > size %"PRIu64
"\n",
1331 slot
, offset
, qxl
->guest_slots
[slot
].size
);
1334 return qxl
->guest_slots
[slot
].ptr
+ offset
;
1339 static void qxl_create_guest_primary_complete(PCIQXLDevice
*qxl
)
1341 /* for local rendering */
1342 qxl_render_resize(qxl
);
1345 static void qxl_create_guest_primary(PCIQXLDevice
*qxl
, int loadvm
,
1348 QXLDevSurfaceCreate surface
;
1349 QXLSurfaceCreate
*sc
= &qxl
->guest_primary
.surface
;
1351 int requested_height
= le32_to_cpu(sc
->height
);
1352 int requested_stride
= le32_to_cpu(sc
->stride
);
1354 size
= abs(requested_stride
) * requested_height
;
1355 if (size
> qxl
->vgamem_size
) {
1356 qxl_set_guest_bug(qxl
, "%s: requested primary larger then framebuffer"
1361 if (qxl
->mode
== QXL_MODE_NATIVE
) {
1362 qxl_set_guest_bug(qxl
, "%s: nop since already in QXL_MODE_NATIVE",
1365 qxl_exit_vga_mode(qxl
);
1367 surface
.format
= le32_to_cpu(sc
->format
);
1368 surface
.height
= le32_to_cpu(sc
->height
);
1369 surface
.mem
= le64_to_cpu(sc
->mem
);
1370 surface
.position
= le32_to_cpu(sc
->position
);
1371 surface
.stride
= le32_to_cpu(sc
->stride
);
1372 surface
.width
= le32_to_cpu(sc
->width
);
1373 surface
.type
= le32_to_cpu(sc
->type
);
1374 surface
.flags
= le32_to_cpu(sc
->flags
);
1375 trace_qxl_create_guest_primary(qxl
->id
, sc
->width
, sc
->height
, sc
->mem
,
1376 sc
->format
, sc
->position
);
1377 trace_qxl_create_guest_primary_rest(qxl
->id
, sc
->stride
, sc
->type
,
1380 if ((surface
.stride
& 0x3) != 0) {
1381 qxl_set_guest_bug(qxl
, "primary surface stride = %d %% 4 != 0",
1386 surface
.mouse_mode
= true;
1387 surface
.group_id
= MEMSLOT_GROUP_GUEST
;
1389 surface
.flags
|= QXL_SURF_FLAG_KEEP_DATA
;
1392 qxl
->mode
= QXL_MODE_NATIVE
;
1394 qemu_spice_create_primary_surface(&qxl
->ssd
, 0, &surface
, async
);
1396 if (async
== QXL_SYNC
) {
1397 qxl_create_guest_primary_complete(qxl
);
1401 /* return 1 if surface destoy was initiated (in QXL_ASYNC case) or
1402 * done (in QXL_SYNC case), 0 otherwise. */
1403 static int qxl_destroy_primary(PCIQXLDevice
*d
, qxl_async_io async
)
1405 if (d
->mode
== QXL_MODE_UNDEFINED
) {
1408 trace_qxl_destroy_primary(d
->id
);
1409 d
->mode
= QXL_MODE_UNDEFINED
;
1410 qemu_spice_destroy_primary_surface(&d
->ssd
, 0, async
);
1411 qxl_spice_reset_cursor(d
);
1415 static void qxl_set_mode(PCIQXLDevice
*d
, int modenr
, int loadvm
)
1417 pcibus_t start
= d
->pci
.io_regions
[QXL_RAM_RANGE_INDEX
].addr
;
1418 pcibus_t end
= d
->pci
.io_regions
[QXL_RAM_RANGE_INDEX
].size
+ start
;
1419 QXLMode
*mode
= d
->modes
->modes
+ modenr
;
1420 uint64_t devmem
= d
->pci
.io_regions
[QXL_RAM_RANGE_INDEX
].addr
;
1425 QXLSurfaceCreate surface
= {
1426 .width
= mode
->x_res
,
1427 .height
= mode
->y_res
,
1428 .stride
= -mode
->x_res
* 4,
1429 .format
= SPICE_SURFACE_FMT_32_xRGB
,
1430 .flags
= loadvm
? QXL_SURF_FLAG_KEEP_DATA
: 0,
1432 .mem
= devmem
+ d
->shadow_rom
.draw_area_offset
,
1435 trace_qxl_set_mode(d
->id
, modenr
, mode
->x_res
, mode
->y_res
, mode
->bits
,
1438 qxl_hard_reset(d
, 0);
1441 d
->guest_slots
[0].slot
= slot
;
1442 assert(qxl_add_memslot(d
, 0, devmem
, QXL_SYNC
) == 0);
1444 d
->guest_primary
.surface
= surface
;
1445 qxl_create_guest_primary(d
, 0, QXL_SYNC
);
1447 d
->mode
= QXL_MODE_COMPAT
;
1448 d
->cmdflags
= QXL_COMMAND_FLAG_COMPAT
;
1449 if (mode
->bits
== 16) {
1450 d
->cmdflags
|= QXL_COMMAND_FLAG_COMPAT_16BPP
;
1452 d
->shadow_rom
.mode
= cpu_to_le32(modenr
);
1453 d
->rom
->mode
= cpu_to_le32(modenr
);
1454 qxl_rom_set_dirty(d
);
1457 static void ioport_write(void *opaque
, hwaddr addr
,
1458 uint64_t val
, unsigned size
)
1460 PCIQXLDevice
*d
= opaque
;
1461 uint32_t io_port
= addr
;
1462 qxl_async_io async
= QXL_SYNC
;
1463 uint32_t orig_io_port
= io_port
;
1465 if (d
->guest_bug
&& io_port
!= QXL_IO_RESET
) {
1469 if (d
->revision
<= QXL_REVISION_STABLE_V10
&&
1470 io_port
> QXL_IO_FLUSH_RELEASE
) {
1471 qxl_set_guest_bug(d
, "unsupported io %d for revision %d\n",
1472 io_port
, d
->revision
);
1478 case QXL_IO_SET_MODE
:
1479 case QXL_IO_MEMSLOT_ADD
:
1480 case QXL_IO_MEMSLOT_DEL
:
1481 case QXL_IO_CREATE_PRIMARY
:
1482 case QXL_IO_UPDATE_IRQ
:
1484 case QXL_IO_MEMSLOT_ADD_ASYNC
:
1485 case QXL_IO_CREATE_PRIMARY_ASYNC
:
1488 if (d
->mode
!= QXL_MODE_VGA
) {
1491 trace_qxl_io_unexpected_vga_mode(d
->id
,
1492 addr
, val
, io_port_to_string(io_port
));
1493 /* be nice to buggy guest drivers */
1494 if (io_port
>= QXL_IO_UPDATE_AREA_ASYNC
&&
1495 io_port
< QXL_IO_RANGE_SIZE
) {
1496 qxl_send_events(d
, QXL_INTERRUPT_IO_CMD
);
1501 /* we change the io_port to avoid ifdeffery in the main switch */
1502 orig_io_port
= io_port
;
1504 case QXL_IO_UPDATE_AREA_ASYNC
:
1505 io_port
= QXL_IO_UPDATE_AREA
;
1507 case QXL_IO_MEMSLOT_ADD_ASYNC
:
1508 io_port
= QXL_IO_MEMSLOT_ADD
;
1510 case QXL_IO_CREATE_PRIMARY_ASYNC
:
1511 io_port
= QXL_IO_CREATE_PRIMARY
;
1513 case QXL_IO_DESTROY_PRIMARY_ASYNC
:
1514 io_port
= QXL_IO_DESTROY_PRIMARY
;
1516 case QXL_IO_DESTROY_SURFACE_ASYNC
:
1517 io_port
= QXL_IO_DESTROY_SURFACE_WAIT
;
1519 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC
:
1520 io_port
= QXL_IO_DESTROY_ALL_SURFACES
;
1522 case QXL_IO_FLUSH_SURFACES_ASYNC
:
1523 case QXL_IO_MONITORS_CONFIG_ASYNC
:
1526 qemu_mutex_lock(&d
->async_lock
);
1527 if (d
->current_async
!= QXL_UNDEFINED_IO
) {
1528 qxl_set_guest_bug(d
, "%d async started before last (%d) complete",
1529 io_port
, d
->current_async
);
1530 qemu_mutex_unlock(&d
->async_lock
);
1533 d
->current_async
= orig_io_port
;
1534 qemu_mutex_unlock(&d
->async_lock
);
1539 trace_qxl_io_write(d
->id
, qxl_mode_to_string(d
->mode
), addr
, val
, size
,
1543 case QXL_IO_UPDATE_AREA
:
1545 QXLCookie
*cookie
= NULL
;
1546 QXLRect update
= d
->ram
->update_area
;
1548 if (d
->ram
->update_surface
> d
->ssd
.num_surfaces
) {
1549 qxl_set_guest_bug(d
, "QXL_IO_UPDATE_AREA: invalid surface id %d\n",
1550 d
->ram
->update_surface
);
1553 if (update
.left
>= update
.right
|| update
.top
>= update
.bottom
||
1554 update
.left
< 0 || update
.top
< 0) {
1555 qxl_set_guest_bug(d
,
1556 "QXL_IO_UPDATE_AREA: invalid area (%ux%u)x(%ux%u)\n",
1557 update
.left
, update
.top
, update
.right
, update
.bottom
);
1560 if (async
== QXL_ASYNC
) {
1561 cookie
= qxl_cookie_new(QXL_COOKIE_TYPE_IO
,
1562 QXL_IO_UPDATE_AREA_ASYNC
);
1563 cookie
->u
.area
= update
;
1565 qxl_spice_update_area(d
, d
->ram
->update_surface
,
1566 cookie
? &cookie
->u
.area
: &update
,
1567 NULL
, 0, 0, async
, cookie
);
1570 case QXL_IO_NOTIFY_CMD
:
1571 qemu_spice_wakeup(&d
->ssd
);
1573 case QXL_IO_NOTIFY_CURSOR
:
1574 qemu_spice_wakeup(&d
->ssd
);
1576 case QXL_IO_UPDATE_IRQ
:
1579 case QXL_IO_NOTIFY_OOM
:
1580 if (!SPICE_RING_IS_EMPTY(&d
->ram
->release_ring
)) {
1587 case QXL_IO_SET_MODE
:
1588 qxl_set_mode(d
, val
, 0);
1591 trace_qxl_io_log(d
->id
, d
->ram
->log_buf
);
1592 if (d
->guestdebug
) {
1593 fprintf(stderr
, "qxl/guest-%d: %" PRId64
": %s", d
->id
,
1594 qemu_get_clock_ns(vm_clock
), d
->ram
->log_buf
);
1598 qxl_hard_reset(d
, 0);
1600 case QXL_IO_MEMSLOT_ADD
:
1601 if (val
>= NUM_MEMSLOTS
) {
1602 qxl_set_guest_bug(d
, "QXL_IO_MEMSLOT_ADD: val out of range");
1605 if (d
->guest_slots
[val
].active
) {
1606 qxl_set_guest_bug(d
,
1607 "QXL_IO_MEMSLOT_ADD: memory slot already active");
1610 d
->guest_slots
[val
].slot
= d
->ram
->mem_slot
;
1611 qxl_add_memslot(d
, val
, 0, async
);
1613 case QXL_IO_MEMSLOT_DEL
:
1614 if (val
>= NUM_MEMSLOTS
) {
1615 qxl_set_guest_bug(d
, "QXL_IO_MEMSLOT_DEL: val out of range");
1618 qxl_del_memslot(d
, val
);
1620 case QXL_IO_CREATE_PRIMARY
:
1622 qxl_set_guest_bug(d
, "QXL_IO_CREATE_PRIMARY (async=%d): val != 0",
1626 d
->guest_primary
.surface
= d
->ram
->create_surface
;
1627 qxl_create_guest_primary(d
, 0, async
);
1629 case QXL_IO_DESTROY_PRIMARY
:
1631 qxl_set_guest_bug(d
, "QXL_IO_DESTROY_PRIMARY (async=%d): val != 0",
1635 if (!qxl_destroy_primary(d
, async
)) {
1636 trace_qxl_io_destroy_primary_ignored(d
->id
,
1637 qxl_mode_to_string(d
->mode
));
1641 case QXL_IO_DESTROY_SURFACE_WAIT
:
1642 if (val
>= d
->ssd
.num_surfaces
) {
1643 qxl_set_guest_bug(d
, "QXL_IO_DESTROY_SURFACE (async=%d):"
1644 "%" PRIu64
" >= NUM_SURFACES", async
, val
);
1647 qxl_spice_destroy_surface_wait(d
, val
, async
);
1649 case QXL_IO_FLUSH_RELEASE
: {
1650 QXLReleaseRing
*ring
= &d
->ram
->release_ring
;
1651 if (ring
->prod
- ring
->cons
+ 1 == ring
->num_items
) {
1653 "ERROR: no flush, full release ring [p%d,%dc]\n",
1654 ring
->prod
, ring
->cons
);
1656 qxl_push_free_res(d
, 1 /* flush */);
1659 case QXL_IO_FLUSH_SURFACES_ASYNC
:
1660 qxl_spice_flush_surfaces_async(d
);
1662 case QXL_IO_DESTROY_ALL_SURFACES
:
1663 d
->mode
= QXL_MODE_UNDEFINED
;
1664 qxl_spice_destroy_surfaces(d
, async
);
1666 case QXL_IO_MONITORS_CONFIG_ASYNC
:
1667 qxl_spice_monitors_config_async(d
, 0);
1670 qxl_set_guest_bug(d
, "%s: unexpected ioport=0x%x\n", __func__
, io_port
);
1675 qxl_send_events(d
, QXL_INTERRUPT_IO_CMD
);
1676 qemu_mutex_lock(&d
->async_lock
);
1677 d
->current_async
= QXL_UNDEFINED_IO
;
1678 qemu_mutex_unlock(&d
->async_lock
);
1682 static uint64_t ioport_read(void *opaque
, hwaddr addr
,
1685 PCIQXLDevice
*qxl
= opaque
;
1687 trace_qxl_io_read_unexpected(qxl
->id
);
1691 static const MemoryRegionOps qxl_io_ops
= {
1692 .read
= ioport_read
,
1693 .write
= ioport_write
,
1695 .min_access_size
= 1,
1696 .max_access_size
= 1,
1700 static void pipe_read(void *opaque
)
1702 PCIQXLDevice
*d
= opaque
;
1707 len
= read(d
->pipe
[0], &dummy
, sizeof(dummy
));
1708 } while (len
== sizeof(dummy
));
1712 static void qxl_send_events(PCIQXLDevice
*d
, uint32_t events
)
1714 uint32_t old_pending
;
1715 uint32_t le_events
= cpu_to_le32(events
);
1717 trace_qxl_send_events(d
->id
, events
);
1718 if (!qemu_spice_display_is_running(&d
->ssd
)) {
1719 /* spice-server tracks guest running state and should not do this */
1720 fprintf(stderr
, "%s: spice-server bug: guest stopped, ignoring\n",
1722 trace_qxl_send_events_vm_stopped(d
->id
, events
);
1725 old_pending
= __sync_fetch_and_or(&d
->ram
->int_pending
, le_events
);
1726 if ((old_pending
& le_events
) == le_events
) {
1729 if (qemu_thread_is_self(&d
->main
)) {
1732 if (write(d
->pipe
[1], d
, 1) != 1) {
1733 dprint(d
, 1, "%s: write to pipe failed\n", __func__
);
1738 static void init_pipe_signaling(PCIQXLDevice
*d
)
1740 if (pipe(d
->pipe
) < 0) {
1741 fprintf(stderr
, "%s:%s: qxl pipe creation failed\n",
1742 __FILE__
, __func__
);
1745 fcntl(d
->pipe
[0], F_SETFL
, O_NONBLOCK
);
1746 fcntl(d
->pipe
[1], F_SETFL
, O_NONBLOCK
);
1747 fcntl(d
->pipe
[0], F_SETOWN
, getpid());
1749 qemu_thread_get_self(&d
->main
);
1750 qemu_set_fd_handler(d
->pipe
[0], pipe_read
, NULL
, d
);
1753 /* graphics console */
1755 static void qxl_hw_update(void *opaque
)
1757 PCIQXLDevice
*qxl
= opaque
;
1758 VGACommonState
*vga
= &qxl
->vga
;
1760 switch (qxl
->mode
) {
1762 vga
->hw_ops
->gfx_update(vga
);
1764 case QXL_MODE_COMPAT
:
1765 case QXL_MODE_NATIVE
:
1766 qxl_render_update(qxl
);
1773 static void qxl_hw_invalidate(void *opaque
)
1775 PCIQXLDevice
*qxl
= opaque
;
1776 VGACommonState
*vga
= &qxl
->vga
;
1778 if (qxl
->mode
== QXL_MODE_VGA
) {
1779 vga
->hw_ops
->invalidate(vga
);
1784 static void qxl_hw_text_update(void *opaque
, console_ch_t
*chardata
)
1786 PCIQXLDevice
*qxl
= opaque
;
1787 VGACommonState
*vga
= &qxl
->vga
;
1789 if (qxl
->mode
== QXL_MODE_VGA
) {
1790 vga
->hw_ops
->text_update(vga
, chardata
);
1795 static void qxl_dirty_surfaces(PCIQXLDevice
*qxl
)
1797 uintptr_t vram_start
;
1800 if (qxl
->mode
!= QXL_MODE_NATIVE
&& qxl
->mode
!= QXL_MODE_COMPAT
) {
1804 /* dirty the primary surface */
1805 qxl_set_dirty(&qxl
->vga
.vram
, qxl
->shadow_rom
.draw_area_offset
,
1806 qxl
->shadow_rom
.surface0_area_size
);
1808 vram_start
= (uintptr_t)memory_region_get_ram_ptr(&qxl
->vram_bar
);
1810 /* dirty the off-screen surfaces */
1811 for (i
= 0; i
< qxl
->ssd
.num_surfaces
; i
++) {
1813 intptr_t surface_offset
;
1816 if (qxl
->guest_surfaces
.cmds
[i
] == 0) {
1820 cmd
= qxl_phys2virt(qxl
, qxl
->guest_surfaces
.cmds
[i
],
1821 MEMSLOT_GROUP_GUEST
);
1823 assert(cmd
->type
== QXL_SURFACE_CMD_CREATE
);
1824 surface_offset
= (intptr_t)qxl_phys2virt(qxl
,
1825 cmd
->u
.surface_create
.data
,
1826 MEMSLOT_GROUP_GUEST
);
1827 assert(surface_offset
);
1828 surface_offset
-= vram_start
;
1829 surface_size
= cmd
->u
.surface_create
.height
*
1830 abs(cmd
->u
.surface_create
.stride
);
1831 trace_qxl_surfaces_dirty(qxl
->id
, i
, (int)surface_offset
, surface_size
);
1832 qxl_set_dirty(&qxl
->vram_bar
, surface_offset
, surface_size
);
1836 static void qxl_vm_change_state_handler(void *opaque
, int running
,
1839 PCIQXLDevice
*qxl
= opaque
;
1843 * if qxl_send_events was called from spice server context before
1844 * migration ended, qxl_update_irq for these events might not have been
1847 qxl_update_irq(qxl
);
1849 /* make sure surfaces are saved before migration */
1850 qxl_dirty_surfaces(qxl
);
1854 /* display change listener */
1856 static void display_update(DisplayChangeListener
*dcl
,
1857 int x
, int y
, int w
, int h
)
1859 PCIQXLDevice
*qxl
= container_of(dcl
, PCIQXLDevice
, ssd
.dcl
);
1861 if (qxl
->mode
== QXL_MODE_VGA
) {
1862 qemu_spice_display_update(&qxl
->ssd
, x
, y
, w
, h
);
1866 static void display_switch(DisplayChangeListener
*dcl
,
1867 struct DisplaySurface
*surface
)
1869 PCIQXLDevice
*qxl
= container_of(dcl
, PCIQXLDevice
, ssd
.dcl
);
1871 qxl
->ssd
.ds
= surface
;
1872 if (qxl
->mode
== QXL_MODE_VGA
) {
1873 qemu_spice_display_switch(&qxl
->ssd
, surface
);
1877 static void display_refresh(DisplayChangeListener
*dcl
)
1879 PCIQXLDevice
*qxl
= container_of(dcl
, PCIQXLDevice
, ssd
.dcl
);
1881 if (qxl
->mode
== QXL_MODE_VGA
) {
1882 qemu_spice_display_refresh(&qxl
->ssd
);
1884 qemu_mutex_lock(&qxl
->ssd
.lock
);
1885 qemu_spice_cursor_refresh_unlocked(&qxl
->ssd
);
1886 qemu_mutex_unlock(&qxl
->ssd
.lock
);
1890 static DisplayChangeListenerOps display_listener_ops
= {
1891 .dpy_name
= "spice/qxl",
1892 .dpy_gfx_update
= display_update
,
1893 .dpy_gfx_switch
= display_switch
,
1894 .dpy_refresh
= display_refresh
,
1897 static void qxl_init_ramsize(PCIQXLDevice
*qxl
)
1899 /* vga mode framebuffer / primary surface (bar 0, first part) */
1900 if (qxl
->vgamem_size_mb
< 8) {
1901 qxl
->vgamem_size_mb
= 8;
1903 qxl
->vgamem_size
= qxl
->vgamem_size_mb
* 1024 * 1024;
1905 /* vga ram (bar 0, total) */
1906 if (qxl
->ram_size_mb
!= -1) {
1907 qxl
->vga
.vram_size
= qxl
->ram_size_mb
* 1024 * 1024;
1909 if (qxl
->vga
.vram_size
< qxl
->vgamem_size
* 2) {
1910 qxl
->vga
.vram_size
= qxl
->vgamem_size
* 2;
1913 /* vram32 (surfaces, 32bit, bar 1) */
1914 if (qxl
->vram32_size_mb
!= -1) {
1915 qxl
->vram32_size
= qxl
->vram32_size_mb
* 1024 * 1024;
1917 if (qxl
->vram32_size
< 4096) {
1918 qxl
->vram32_size
= 4096;
1921 /* vram (surfaces, 64bit, bar 4+5) */
1922 if (qxl
->vram_size_mb
!= -1) {
1923 qxl
->vram_size
= qxl
->vram_size_mb
* 1024 * 1024;
1925 if (qxl
->vram_size
< qxl
->vram32_size
) {
1926 qxl
->vram_size
= qxl
->vram32_size
;
1929 if (qxl
->revision
== 1) {
1930 qxl
->vram32_size
= 4096;
1931 qxl
->vram_size
= 4096;
1933 qxl
->vgamem_size
= msb_mask(qxl
->vgamem_size
* 2 - 1);
1934 qxl
->vga
.vram_size
= msb_mask(qxl
->vga
.vram_size
* 2 - 1);
1935 qxl
->vram32_size
= msb_mask(qxl
->vram32_size
* 2 - 1);
1936 qxl
->vram_size
= msb_mask(qxl
->vram_size
* 2 - 1);
1939 static int qxl_init_common(PCIQXLDevice
*qxl
)
1941 uint8_t* config
= qxl
->pci
.config
;
1942 uint32_t pci_device_rev
;
1945 qxl
->mode
= QXL_MODE_UNDEFINED
;
1946 qxl
->generation
= 1;
1947 qxl
->num_memslots
= NUM_MEMSLOTS
;
1948 qemu_mutex_init(&qxl
->track_lock
);
1949 qemu_mutex_init(&qxl
->async_lock
);
1950 qxl
->current_async
= QXL_UNDEFINED_IO
;
1953 switch (qxl
->revision
) {
1954 case 1: /* spice 0.4 -- qxl-1 */
1955 pci_device_rev
= QXL_REVISION_STABLE_V04
;
1958 case 2: /* spice 0.6 -- qxl-2 */
1959 pci_device_rev
= QXL_REVISION_STABLE_V06
;
1963 pci_device_rev
= QXL_REVISION_STABLE_V10
;
1964 io_size
= 32; /* PCI region size must be pow2 */
1967 pci_device_rev
= QXL_REVISION_STABLE_V12
;
1968 io_size
= msb_mask(QXL_IO_RANGE_SIZE
* 2 - 1);
1971 error_report("Invalid revision %d for qxl device (max %d)",
1972 qxl
->revision
, QXL_DEFAULT_REVISION
);
1976 pci_set_byte(&config
[PCI_REVISION_ID
], pci_device_rev
);
1977 pci_set_byte(&config
[PCI_INTERRUPT_PIN
], 1);
1979 qxl
->rom_size
= qxl_rom_size();
1980 memory_region_init_ram(&qxl
->rom_bar
, "qxl.vrom", qxl
->rom_size
);
1981 vmstate_register_ram(&qxl
->rom_bar
, &qxl
->pci
.qdev
);
1985 qxl
->guest_surfaces
.cmds
= g_new0(QXLPHYSICAL
, qxl
->ssd
.num_surfaces
);
1986 memory_region_init_ram(&qxl
->vram_bar
, "qxl.vram", qxl
->vram_size
);
1987 vmstate_register_ram(&qxl
->vram_bar
, &qxl
->pci
.qdev
);
1988 memory_region_init_alias(&qxl
->vram32_bar
, "qxl.vram32", &qxl
->vram_bar
,
1989 0, qxl
->vram32_size
);
1991 memory_region_init_io(&qxl
->io_bar
, &qxl_io_ops
, qxl
,
1992 "qxl-ioports", io_size
);
1994 vga_dirty_log_start(&qxl
->vga
);
1996 memory_region_set_flush_coalesced(&qxl
->io_bar
);
1999 pci_register_bar(&qxl
->pci
, QXL_IO_RANGE_INDEX
,
2000 PCI_BASE_ADDRESS_SPACE_IO
, &qxl
->io_bar
);
2002 pci_register_bar(&qxl
->pci
, QXL_ROM_RANGE_INDEX
,
2003 PCI_BASE_ADDRESS_SPACE_MEMORY
, &qxl
->rom_bar
);
2005 pci_register_bar(&qxl
->pci
, QXL_RAM_RANGE_INDEX
,
2006 PCI_BASE_ADDRESS_SPACE_MEMORY
, &qxl
->vga
.vram
);
2008 pci_register_bar(&qxl
->pci
, QXL_VRAM_RANGE_INDEX
,
2009 PCI_BASE_ADDRESS_SPACE_MEMORY
, &qxl
->vram32_bar
);
2011 if (qxl
->vram32_size
< qxl
->vram_size
) {
2013 * Make the 64bit vram bar show up only in case it is
2014 * configured to be larger than the 32bit vram bar.
2016 pci_register_bar(&qxl
->pci
, QXL_VRAM64_RANGE_INDEX
,
2017 PCI_BASE_ADDRESS_SPACE_MEMORY
|
2018 PCI_BASE_ADDRESS_MEM_TYPE_64
|
2019 PCI_BASE_ADDRESS_MEM_PREFETCH
,
2023 /* print pci bar details */
2024 dprint(qxl
, 1, "ram/%s: %d MB [region 0]\n",
2025 qxl
->id
== 0 ? "pri" : "sec",
2026 qxl
->vga
.vram_size
/ (1024*1024));
2027 dprint(qxl
, 1, "vram/32: %d MB [region 1]\n",
2028 qxl
->vram32_size
/ (1024*1024));
2029 dprint(qxl
, 1, "vram/64: %d MB %s\n",
2030 qxl
->vram_size
/ (1024*1024),
2031 qxl
->vram32_size
< qxl
->vram_size
? "[region 4]" : "[unmapped]");
2033 qxl
->ssd
.qxl
.base
.sif
= &qxl_interface
.base
;
2034 qxl
->ssd
.qxl
.id
= qxl
->id
;
2035 if (qemu_spice_add_interface(&qxl
->ssd
.qxl
.base
) != 0) {
2036 error_report("qxl interface %d.%d not supported by spice-server",
2037 SPICE_INTERFACE_QXL_MAJOR
, SPICE_INTERFACE_QXL_MINOR
);
2040 qemu_add_vm_change_state_handler(qxl_vm_change_state_handler
, qxl
);
2042 init_pipe_signaling(qxl
);
2043 qxl_reset_state(qxl
);
2045 qxl
->update_area_bh
= qemu_bh_new(qxl_render_update_area_bh
, qxl
);
2050 static const GraphicHwOps qxl_ops
= {
2051 .invalidate
= qxl_hw_invalidate
,
2052 .gfx_update
= qxl_hw_update
,
2053 .text_update
= qxl_hw_text_update
,
2056 static int qxl_init_primary(PCIDevice
*dev
)
2058 PCIQXLDevice
*qxl
= DO_UPCAST(PCIQXLDevice
, pci
, dev
);
2059 VGACommonState
*vga
= &qxl
->vga
;
2060 PortioList
*qxl_vga_port_list
= g_new(PortioList
, 1);
2064 qxl_init_ramsize(qxl
);
2065 vga
->vram_size_mb
= qxl
->vga
.vram_size
>> 20;
2066 vga_common_init(vga
);
2067 vga_init(vga
, pci_address_space(dev
), pci_address_space_io(dev
), false);
2068 portio_list_init(qxl_vga_port_list
, qxl_vga_portio_list
, vga
, "vga");
2069 portio_list_add(qxl_vga_port_list
, pci_address_space_io(dev
), 0x3b0);
2071 vga
->con
= graphic_console_init(DEVICE(dev
), &qxl_ops
, qxl
);
2072 qemu_spice_display_init_common(&qxl
->ssd
);
2074 rc
= qxl_init_common(qxl
);
2079 qxl
->ssd
.dcl
.ops
= &display_listener_ops
;
2080 qxl
->ssd
.dcl
.con
= vga
->con
;
2081 register_displaychangelistener(&qxl
->ssd
.dcl
);
2085 static int qxl_init_secondary(PCIDevice
*dev
)
2087 static int device_id
= 1;
2088 PCIQXLDevice
*qxl
= DO_UPCAST(PCIQXLDevice
, pci
, dev
);
2090 qxl
->id
= device_id
++;
2091 qxl_init_ramsize(qxl
);
2092 memory_region_init_ram(&qxl
->vga
.vram
, "qxl.vgavram", qxl
->vga
.vram_size
);
2093 vmstate_register_ram(&qxl
->vga
.vram
, &qxl
->pci
.qdev
);
2094 qxl
->vga
.vram_ptr
= memory_region_get_ram_ptr(&qxl
->vga
.vram
);
2095 qxl
->vga
.con
= graphic_console_init(DEVICE(dev
), &qxl_ops
, qxl
);
2097 return qxl_init_common(qxl
);
2100 static void qxl_pre_save(void *opaque
)
2102 PCIQXLDevice
* d
= opaque
;
2103 uint8_t *ram_start
= d
->vga
.vram_ptr
;
2105 trace_qxl_pre_save(d
->id
);
2106 if (d
->last_release
== NULL
) {
2107 d
->last_release_offset
= 0;
2109 d
->last_release_offset
= (uint8_t *)d
->last_release
- ram_start
;
2111 assert(d
->last_release_offset
< d
->vga
.vram_size
);
2114 static int qxl_pre_load(void *opaque
)
2116 PCIQXLDevice
* d
= opaque
;
2118 trace_qxl_pre_load(d
->id
);
2119 qxl_hard_reset(d
, 1);
2120 qxl_exit_vga_mode(d
);
2124 static void qxl_create_memslots(PCIQXLDevice
*d
)
2128 for (i
= 0; i
< NUM_MEMSLOTS
; i
++) {
2129 if (!d
->guest_slots
[i
].active
) {
2132 qxl_add_memslot(d
, i
, 0, QXL_SYNC
);
2136 static int qxl_post_load(void *opaque
, int version
)
2138 PCIQXLDevice
* d
= opaque
;
2139 uint8_t *ram_start
= d
->vga
.vram_ptr
;
2140 QXLCommandExt
*cmds
;
2141 int in
, out
, newmode
;
2143 assert(d
->last_release_offset
< d
->vga
.vram_size
);
2144 if (d
->last_release_offset
== 0) {
2145 d
->last_release
= NULL
;
2147 d
->last_release
= (QXLReleaseInfo
*)(ram_start
+ d
->last_release_offset
);
2150 d
->modes
= (QXLModes
*)((uint8_t*)d
->rom
+ d
->rom
->modes_offset
);
2152 trace_qxl_post_load(d
->id
, qxl_mode_to_string(d
->mode
));
2154 d
->mode
= QXL_MODE_UNDEFINED
;
2157 case QXL_MODE_UNDEFINED
:
2158 qxl_create_memslots(d
);
2161 qxl_create_memslots(d
);
2162 qxl_enter_vga_mode(d
);
2164 case QXL_MODE_NATIVE
:
2165 qxl_create_memslots(d
);
2166 qxl_create_guest_primary(d
, 1, QXL_SYNC
);
2168 /* replay surface-create and cursor-set commands */
2169 cmds
= g_malloc0(sizeof(QXLCommandExt
) * (d
->ssd
.num_surfaces
+ 1));
2170 for (in
= 0, out
= 0; in
< d
->ssd
.num_surfaces
; in
++) {
2171 if (d
->guest_surfaces
.cmds
[in
] == 0) {
2174 cmds
[out
].cmd
.data
= d
->guest_surfaces
.cmds
[in
];
2175 cmds
[out
].cmd
.type
= QXL_CMD_SURFACE
;
2176 cmds
[out
].group_id
= MEMSLOT_GROUP_GUEST
;
2179 if (d
->guest_cursor
) {
2180 cmds
[out
].cmd
.data
= d
->guest_cursor
;
2181 cmds
[out
].cmd
.type
= QXL_CMD_CURSOR
;
2182 cmds
[out
].group_id
= MEMSLOT_GROUP_GUEST
;
2185 qxl_spice_loadvm_commands(d
, cmds
, out
);
2187 if (d
->guest_monitors_config
) {
2188 qxl_spice_monitors_config_async(d
, 1);
2191 case QXL_MODE_COMPAT
:
2192 /* note: no need to call qxl_create_memslots, qxl_set_mode
2193 * creates the mem slot. */
2194 qxl_set_mode(d
, d
->shadow_rom
.mode
, 1);
2200 #define QXL_SAVE_VERSION 21
2202 static bool qxl_monitors_config_needed(void *opaque
)
2204 PCIQXLDevice
*qxl
= opaque
;
2206 return qxl
->guest_monitors_config
!= 0;
2210 static VMStateDescription qxl_memslot
= {
2211 .name
= "qxl-memslot",
2212 .version_id
= QXL_SAVE_VERSION
,
2213 .minimum_version_id
= QXL_SAVE_VERSION
,
2214 .fields
= (VMStateField
[]) {
2215 VMSTATE_UINT64(slot
.mem_start
, struct guest_slots
),
2216 VMSTATE_UINT64(slot
.mem_end
, struct guest_slots
),
2217 VMSTATE_UINT32(active
, struct guest_slots
),
2218 VMSTATE_END_OF_LIST()
2222 static VMStateDescription qxl_surface
= {
2223 .name
= "qxl-surface",
2224 .version_id
= QXL_SAVE_VERSION
,
2225 .minimum_version_id
= QXL_SAVE_VERSION
,
2226 .fields
= (VMStateField
[]) {
2227 VMSTATE_UINT32(width
, QXLSurfaceCreate
),
2228 VMSTATE_UINT32(height
, QXLSurfaceCreate
),
2229 VMSTATE_INT32(stride
, QXLSurfaceCreate
),
2230 VMSTATE_UINT32(format
, QXLSurfaceCreate
),
2231 VMSTATE_UINT32(position
, QXLSurfaceCreate
),
2232 VMSTATE_UINT32(mouse_mode
, QXLSurfaceCreate
),
2233 VMSTATE_UINT32(flags
, QXLSurfaceCreate
),
2234 VMSTATE_UINT32(type
, QXLSurfaceCreate
),
2235 VMSTATE_UINT64(mem
, QXLSurfaceCreate
),
2236 VMSTATE_END_OF_LIST()
2240 static VMStateDescription qxl_vmstate_monitors_config
= {
2241 .name
= "qxl/monitors-config",
2243 .minimum_version_id
= 1,
2244 .fields
= (VMStateField
[]) {
2245 VMSTATE_UINT64(guest_monitors_config
, PCIQXLDevice
),
2246 VMSTATE_END_OF_LIST()
2250 static VMStateDescription qxl_vmstate
= {
2252 .version_id
= QXL_SAVE_VERSION
,
2253 .minimum_version_id
= QXL_SAVE_VERSION
,
2254 .pre_save
= qxl_pre_save
,
2255 .pre_load
= qxl_pre_load
,
2256 .post_load
= qxl_post_load
,
2257 .fields
= (VMStateField
[]) {
2258 VMSTATE_PCI_DEVICE(pci
, PCIQXLDevice
),
2259 VMSTATE_STRUCT(vga
, PCIQXLDevice
, 0, vmstate_vga_common
, VGACommonState
),
2260 VMSTATE_UINT32(shadow_rom
.mode
, PCIQXLDevice
),
2261 VMSTATE_UINT32(num_free_res
, PCIQXLDevice
),
2262 VMSTATE_UINT32(last_release_offset
, PCIQXLDevice
),
2263 VMSTATE_UINT32(mode
, PCIQXLDevice
),
2264 VMSTATE_UINT32(ssd
.unique
, PCIQXLDevice
),
2265 VMSTATE_INT32_EQUAL(num_memslots
, PCIQXLDevice
),
2266 VMSTATE_STRUCT_ARRAY(guest_slots
, PCIQXLDevice
, NUM_MEMSLOTS
, 0,
2267 qxl_memslot
, struct guest_slots
),
2268 VMSTATE_STRUCT(guest_primary
.surface
, PCIQXLDevice
, 0,
2269 qxl_surface
, QXLSurfaceCreate
),
2270 VMSTATE_INT32_EQUAL(ssd
.num_surfaces
, PCIQXLDevice
),
2271 VMSTATE_VARRAY_INT32(guest_surfaces
.cmds
, PCIQXLDevice
,
2272 ssd
.num_surfaces
, 0,
2273 vmstate_info_uint64
, uint64_t),
2274 VMSTATE_UINT64(guest_cursor
, PCIQXLDevice
),
2275 VMSTATE_END_OF_LIST()
2277 .subsections
= (VMStateSubsection
[]) {
2279 .vmsd
= &qxl_vmstate_monitors_config
,
2280 .needed
= qxl_monitors_config_needed
,
2287 static Property qxl_properties
[] = {
2288 DEFINE_PROP_UINT32("ram_size", PCIQXLDevice
, vga
.vram_size
,
2290 DEFINE_PROP_UINT32("vram_size", PCIQXLDevice
, vram32_size
,
2292 DEFINE_PROP_UINT32("revision", PCIQXLDevice
, revision
,
2293 QXL_DEFAULT_REVISION
),
2294 DEFINE_PROP_UINT32("debug", PCIQXLDevice
, debug
, 0),
2295 DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice
, guestdebug
, 0),
2296 DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice
, cmdlog
, 0),
2297 DEFINE_PROP_UINT32("ram_size_mb", PCIQXLDevice
, ram_size_mb
, -1),
2298 DEFINE_PROP_UINT32("vram_size_mb", PCIQXLDevice
, vram32_size_mb
, -1),
2299 DEFINE_PROP_UINT32("vram64_size_mb", PCIQXLDevice
, vram_size_mb
, -1),
2300 DEFINE_PROP_UINT32("vgamem_mb", PCIQXLDevice
, vgamem_size_mb
, 16),
2301 DEFINE_PROP_INT32("surfaces", PCIQXLDevice
, ssd
.num_surfaces
, 1024),
2302 DEFINE_PROP_END_OF_LIST(),
2305 static void qxl_primary_class_init(ObjectClass
*klass
, void *data
)
2307 DeviceClass
*dc
= DEVICE_CLASS(klass
);
2308 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
2311 k
->init
= qxl_init_primary
;
2312 k
->romfile
= "vgabios-qxl.bin";
2313 k
->vendor_id
= REDHAT_PCI_VENDOR_ID
;
2314 k
->device_id
= QXL_DEVICE_ID_STABLE
;
2315 k
->class_id
= PCI_CLASS_DISPLAY_VGA
;
2316 dc
->desc
= "Spice QXL GPU (primary, vga compatible)";
2317 dc
->reset
= qxl_reset_handler
;
2318 dc
->vmsd
= &qxl_vmstate
;
2319 dc
->props
= qxl_properties
;
2322 static const TypeInfo qxl_primary_info
= {
2324 .parent
= TYPE_PCI_DEVICE
,
2325 .instance_size
= sizeof(PCIQXLDevice
),
2326 .class_init
= qxl_primary_class_init
,
2329 static void qxl_secondary_class_init(ObjectClass
*klass
, void *data
)
2331 DeviceClass
*dc
= DEVICE_CLASS(klass
);
2332 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
2334 k
->init
= qxl_init_secondary
;
2335 k
->vendor_id
= REDHAT_PCI_VENDOR_ID
;
2336 k
->device_id
= QXL_DEVICE_ID_STABLE
;
2337 k
->class_id
= PCI_CLASS_DISPLAY_OTHER
;
2338 dc
->desc
= "Spice QXL GPU (secondary)";
2339 dc
->reset
= qxl_reset_handler
;
2340 dc
->vmsd
= &qxl_vmstate
;
2341 dc
->props
= qxl_properties
;
2344 static const TypeInfo qxl_secondary_info
= {
2346 .parent
= TYPE_PCI_DEVICE
,
2347 .instance_size
= sizeof(PCIQXLDevice
),
2348 .class_init
= qxl_secondary_class_init
,
2351 static void qxl_register_types(void)
2353 type_register_static(&qxl_primary_info
);
2354 type_register_static(&qxl_secondary_info
);
2357 type_init(qxl_register_types
)