hw/pci.h

   1 #ifndef QEMU_PCI_H
   2 #define QEMU_PCI_H
   3
   4 #include "qemu-common.h"
   5
   6 #include "qdev.h"
   7 #include "memory.h"
   8
   9 /* PCI includes legacy ISA access.  */
  10 #include "isa.h"
  11
  12 #include "pcie.h"
  13
  14 /* PCI bus */
  15
  16 #define PCI_DEVFN(slot, func)   ((((slot) & 0x1f) << 3) | ((func) & 0x07))
  17 #define PCI_SLOT(devfn)         (((devfn) >> 3) & 0x1f)
  18 #define PCI_FUNC(devfn)         ((devfn) & 0x07)
  19 #define PCI_SLOT_MAX            32
  20 #define PCI_FUNC_MAX            8
  21
  22 /* Class, Vendor and Device IDs from Linux's pci_ids.h */
  23 #include "pci_ids.h"
  24
  25 /* QEMU-specific Vendor and Device ID definitions */
  26
  27 /* IBM (0x1014) */
  28 #define PCI_DEVICE_ID_IBM_440GX          0x027f
  29 #define PCI_DEVICE_ID_IBM_OPENPIC2       0xffff
  30
  31 /* Hitachi (0x1054) */
  32 #define PCI_VENDOR_ID_HITACHI            0x1054
  33 #define PCI_DEVICE_ID_HITACHI_SH7751R    0x350e
  34
  35 /* Apple (0x106b) */
  36 #define PCI_DEVICE_ID_APPLE_343S1201     0x0010
  37 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI  0x001e
  38 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI    0x001f
  39 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL   0x0022
  40 #define PCI_DEVICE_ID_APPLE_IPID_USB     0x003f
  41
  42 /* Realtek (0x10ec) */
  43 #define PCI_DEVICE_ID_REALTEK_8029       0x8029
  44
  45 /* Xilinx (0x10ee) */
  46 #define PCI_DEVICE_ID_XILINX_XC2VP30     0x0300
  47
  48 /* Marvell (0x11ab) */
  49 #define PCI_DEVICE_ID_MARVELL_GT6412X    0x4620
  50
  51 /* QEMU/Bochs VGA (0x1234) */
  52 #define PCI_VENDOR_ID_QEMU               0x1234
  53 #define PCI_DEVICE_ID_QEMU_VGA           0x1111
  54
  55 /* VMWare (0x15ad) */
  56 #define PCI_VENDOR_ID_VMWARE             0x15ad
  57 #define PCI_DEVICE_ID_VMWARE_SVGA2       0x0405
  58 #define PCI_DEVICE_ID_VMWARE_SVGA        0x0710
  59 #define PCI_DEVICE_ID_VMWARE_NET         0x0720
  60 #define PCI_DEVICE_ID_VMWARE_SCSI        0x0730
  61 #define PCI_DEVICE_ID_VMWARE_IDE         0x1729
  62
  63 /* Intel (0x8086) */
  64 #define PCI_DEVICE_ID_INTEL_82551IT      0x1209
  65 #define PCI_DEVICE_ID_INTEL_82557        0x1229
  66 #define PCI_DEVICE_ID_INTEL_82801IR      0x2922
  67
  68 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
  69 #define PCI_VENDOR_ID_REDHAT_QUMRANET    0x1af4
  70 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
  71 #define PCI_SUBDEVICE_ID_QEMU            0x1100
  72
  73 #define PCI_DEVICE_ID_VIRTIO_NET         0x1000
  74 #define PCI_DEVICE_ID_VIRTIO_BLOCK       0x1001
  75 #define PCI_DEVICE_ID_VIRTIO_BALLOON     0x1002
  76 #define PCI_DEVICE_ID_VIRTIO_CONSOLE     0x1003
  77
  78 #define FMT_PCIBUS                      PRIx64
  79
  80 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
  81                                 uint32_t address, uint32_t data, int len);
  82 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
  83                                    uint32_t address, int len);
  84 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
  85                                 pcibus_t addr, pcibus_t size, int type);
  86 typedef int PCIUnregisterFunc(PCIDevice *pci_dev);
  87
  88 typedef struct PCIIORegion {
  89     pcibus_t addr; /* current PCI mapping address. -1 means not mapped */
  90 #define PCI_BAR_UNMAPPED (~(pcibus_t)0)
  91     pcibus_t size;
  92     uint8_t type;
  93     MemoryRegion *memory;
  94     MemoryRegion *address_space;
  95 } PCIIORegion;
  96
  97 #define PCI_ROM_SLOT 6
  98 #define PCI_NUM_REGIONS 7
  99
 100 #include "pci_regs.h"
 101
 102 /* PCI HEADER_TYPE */
 103 #define  PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
 104
 105 /* Size of the standard PCI config header */
 106 #define PCI_CONFIG_HEADER_SIZE 0x40
 107 /* Size of the standard PCI config space */
 108 #define PCI_CONFIG_SPACE_SIZE 0x100
 109 /* Size of the standart PCIe config space: 4KB */
 110 #define PCIE_CONFIG_SPACE_SIZE  0x1000
 111
 112 #define PCI_NUM_PINS 4 /* A-D */
 113
 114 /* Bits in cap_present field. */
 115 enum {
 116     QEMU_PCI_CAP_MSI = 0x1,
 117     QEMU_PCI_CAP_MSIX = 0x2,
 118     QEMU_PCI_CAP_EXPRESS = 0x4,
 119
 120     /* multifunction capable device */
 121 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR        3
 122     QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR),
 123
 124     /* command register SERR bit enabled */
 125 #define QEMU_PCI_CAP_SERR_BITNR 4
 126     QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR),
 127 };
 128
 129 struct PCIDevice {
 130     DeviceState qdev;
 131     /* PCI config space */
 132     uint8_t *config;
 133
 134     /* Used to enable config checks on load. Note that writable bits are
 135      * never checked even if set in cmask. */
 136     uint8_t *cmask;
 137
 138     /* Used to implement R/W bytes */
 139     uint8_t *wmask;
 140
 141     /* Used to implement RW1C(Write 1 to Clear) bytes */
 142     uint8_t *w1cmask;
 143
 144     /* Used to allocate config space for capabilities. */
 145     uint8_t *used;
 146
 147     /* the following fields are read only */
 148     PCIBus *bus;
 149     uint32_t devfn;
 150     char name[64];
 151     PCIIORegion io_regions[PCI_NUM_REGIONS];
 152
 153     /* do not access the following fields */
 154     PCIConfigReadFunc *config_read;
 155     PCIConfigWriteFunc *config_write;
 156
 157     /* IRQ objects for the INTA-INTD pins.  */
 158     qemu_irq *irq;
 159
 160     /* Current IRQ levels.  Used internally by the generic PCI code.  */
 161     uint8_t irq_state;
 162
 163     /* Capability bits */
 164     uint32_t cap_present;
 165
 166     /* Offset of MSI-X capability in config space */
 167     uint8_t msix_cap;
 168
 169     /* MSI-X entries */
 170     int msix_entries_nr;
 171
 172     /* Space to store MSIX table */
 173     uint8_t *msix_table_page;
 174     /* MMIO index used to map MSIX table and pending bit entries. */
 175     MemoryRegion msix_mmio;
 176     /* Reference-count for entries actually in use by driver. */
 177     unsigned *msix_entry_used;
 178     /* Region including the MSI-X table */
 179     uint32_t msix_bar_size;
 180     /* Version id needed for VMState */
 181     int32_t version_id;
 182
 183     /* Offset of MSI capability in config space */
 184     uint8_t msi_cap;
 185
 186     /* PCI Express */
 187     PCIExpressDevice exp;
 188
 189     /* Location of option rom */
 190     char *romfile;
 191     bool has_rom;
 192     MemoryRegion rom;
 193     uint32_t rom_bar;
 194 };
 195
 196 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 197                                int instance_size, int devfn,
 198                                PCIConfigReadFunc *config_read,
 199                                PCIConfigWriteFunc *config_write);
 200
 201 void pci_register_bar(PCIDevice *pci_dev, int region_num,
 202                       uint8_t attr, MemoryRegion *memory);
 203 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num);
 204
 205 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
 206                        uint8_t offset, uint8_t size);
 207
 208 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
 209
 210 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id);
 211
 212
 213 uint32_t pci_default_read_config(PCIDevice *d,
 214                                  uint32_t address, int len);
 215 void pci_default_write_config(PCIDevice *d,
 216                               uint32_t address, uint32_t val, int len);
 217 void pci_device_save(PCIDevice *s, QEMUFile *f);
 218 int pci_device_load(PCIDevice *s, QEMUFile *f);
 219 MemoryRegion *pci_address_space(PCIDevice *dev);
 220 MemoryRegion *pci_address_space_io(PCIDevice *dev);
 221
 222 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
 223 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
 224
 225 typedef enum {
 226     PCI_HOTPLUG_DISABLED,
 227     PCI_HOTPLUG_ENABLED,
 228     PCI_COLDPLUG_ENABLED,
 229 } PCIHotplugState;
 230
 231 typedef int (*pci_hotplug_fn)(DeviceState *qdev, PCIDevice *pci_dev,
 232                               PCIHotplugState state);
 233 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
 234                          const char *name,
 235                          MemoryRegion *address_space_mem,
 236                          MemoryRegion *address_space_io,
 237                          uint8_t devfn_min);
 238 PCIBus *pci_bus_new(DeviceState *parent, const char *name,
 239                     MemoryRegion *address_space_mem,
 240                     MemoryRegion *address_space_io,
 241                     uint8_t devfn_min);
 242 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 243                   void *irq_opaque, int nirq);
 244 int pci_bus_get_irq_level(PCIBus *bus, int irq_num);
 245 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *dev);
 246 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
 247                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 248                          void *irq_opaque,
 249                          MemoryRegion *address_space_mem,
 250                          MemoryRegion *address_space_io,
 251                          uint8_t devfn_min, int nirq);
 252 void pci_device_reset(PCIDevice *dev);
 253 void pci_bus_reset(PCIBus *bus);
 254
 255 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
 256                         const char *default_devaddr);
 257 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
 258                                const char *default_devaddr);
 259 int pci_bus_num(PCIBus *s);
 260 void pci_for_each_device(PCIBus *bus, int bus_num, void (*fn)(PCIBus *bus, PCIDevice *d));
 261 PCIBus *pci_find_root_bus(int domain);
 262 int pci_find_domain(const PCIBus *bus);
 263 PCIBus *pci_find_bus(PCIBus *bus, int bus_num);
 264 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn);
 265 int pci_qdev_find_device(const char *id, PCIDevice **pdev);
 266 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr);
 267
 268 int pci_parse_devaddr(const char *addr, int *domp, int *busp,
 269                       unsigned int *slotp, unsigned int *funcp);
 270 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
 271                      unsigned *slotp);
 272
 273 void pci_device_deassert_intx(PCIDevice *dev);
 274
 275 static inline void
 276 pci_set_byte(uint8_t *config, uint8_t val)
 277 {
 278     *config = val;
 279 }
 280
 281 static inline uint8_t
 282 pci_get_byte(const uint8_t *config)
 283 {
 284     return *config;
 285 }
 286
 287 static inline void
 288 pci_set_word(uint8_t *config, uint16_t val)
 289 {
 290     cpu_to_le16wu((uint16_t *)config, val);
 291 }
 292
 293 static inline uint16_t
 294 pci_get_word(const uint8_t *config)
 295 {
 296     return le16_to_cpupu((const uint16_t *)config);
 297 }
 298
 299 static inline void
 300 pci_set_long(uint8_t *config, uint32_t val)
 301 {
 302     cpu_to_le32wu((uint32_t *)config, val);
 303 }
 304
 305 static inline uint32_t
 306 pci_get_long(const uint8_t *config)
 307 {
 308     return le32_to_cpupu((const uint32_t *)config);
 309 }
 310
 311 static inline void
 312 pci_set_quad(uint8_t *config, uint64_t val)
 313 {
 314     cpu_to_le64w((uint64_t *)config, val);
 315 }
 316
 317 static inline uint64_t
 318 pci_get_quad(const uint8_t *config)
 319 {
 320     return le64_to_cpup((const uint64_t *)config);
 321 }
 322
 323 static inline void
 324 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
 325 {
 326     pci_set_word(&pci_config[PCI_VENDOR_ID], val);
 327 }
 328
 329 static inline void
 330 pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
 331 {
 332     pci_set_word(&pci_config[PCI_DEVICE_ID], val);
 333 }
 334
 335 static inline void
 336 pci_config_set_revision(uint8_t *pci_config, uint8_t val)
 337 {
 338     pci_set_byte(&pci_config[PCI_REVISION_ID], val);
 339 }
 340
 341 static inline void
 342 pci_config_set_class(uint8_t *pci_config, uint16_t val)
 343 {
 344     pci_set_word(&pci_config[PCI_CLASS_DEVICE], val);
 345 }
 346
 347 static inline void
 348 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val)
 349 {
 350     pci_set_byte(&pci_config[PCI_CLASS_PROG], val);
 351 }
 352
 353 static inline void
 354 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val)
 355 {
 356     pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val);
 357 }
 358
 359 /*
 360  * helper functions to do bit mask operation on configuration space.
 361  * Just to set bit, use test-and-set and discard returned value.
 362  * Just to clear bit, use test-and-clear and discard returned value.
 363  * NOTE: They aren't atomic.
 364  */
 365 static inline uint8_t
 366 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask)
 367 {
 368     uint8_t val = pci_get_byte(config);
 369     pci_set_byte(config, val & ~mask);
 370     return val & mask;
 371 }
 372
 373 static inline uint8_t
 374 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask)
 375 {
 376     uint8_t val = pci_get_byte(config);
 377     pci_set_byte(config, val | mask);
 378     return val & mask;
 379 }
 380
 381 static inline uint16_t
 382 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask)
 383 {
 384     uint16_t val = pci_get_word(config);
 385     pci_set_word(config, val & ~mask);
 386     return val & mask;
 387 }
 388
 389 static inline uint16_t
 390 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask)
 391 {
 392     uint16_t val = pci_get_word(config);
 393     pci_set_word(config, val | mask);
 394     return val & mask;
 395 }
 396
 397 static inline uint32_t
 398 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask)
 399 {
 400     uint32_t val = pci_get_long(config);
 401     pci_set_long(config, val & ~mask);
 402     return val & mask;
 403 }
 404
 405 static inline uint32_t
 406 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask)
 407 {
 408     uint32_t val = pci_get_long(config);
 409     pci_set_long(config, val | mask);
 410     return val & mask;
 411 }
 412
 413 static inline uint64_t
 414 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask)
 415 {
 416     uint64_t val = pci_get_quad(config);
 417     pci_set_quad(config, val & ~mask);
 418     return val & mask;
 419 }
 420
 421 static inline uint64_t
 422 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask)
 423 {
 424     uint64_t val = pci_get_quad(config);
 425     pci_set_quad(config, val | mask);
 426     return val & mask;
 427 }
 428
 429 typedef int (*pci_qdev_initfn)(PCIDevice *dev);
 430 typedef struct {
 431     DeviceInfo qdev;
 432     pci_qdev_initfn init;
 433     PCIUnregisterFunc *exit;
 434     PCIConfigReadFunc *config_read;
 435     PCIConfigWriteFunc *config_write;
 436
 437     uint16_t vendor_id;
 438     uint16_t device_id;
 439     uint8_t revision;
 440     uint16_t class_id;
 441     uint16_t subsystem_vendor_id;       /* only for header type = 0 */
 442     uint16_t subsystem_id;              /* only for header type = 0 */
 443
 444     /*
 445      * pci-to-pci bridge or normal device.
 446      * This doesn't mean pci host switch.
 447      * When card bus bridge is supported, this would be enhanced.
 448      */
 449     int is_bridge;
 450
 451     /* pcie stuff */
 452     int is_express;   /* is this device pci express? */
 453
 454     /* device isn't hot-pluggable */
 455     int no_hotplug;
 456
 457     /* rom bar */
 458     const char *romfile;
 459 } PCIDeviceInfo;
 460
 461 void pci_qdev_register(PCIDeviceInfo *info);
 462 void pci_qdev_register_many(PCIDeviceInfo *info);
 463
 464 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
 465                                     const char *name);
 466 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
 467                                            bool multifunction,
 468                                            const char *name);
 469 PCIDevice *pci_try_create_multifunction(PCIBus *bus, int devfn,
 470                                         bool multifunction,
 471                                         const char *name);
 472 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name);
 473 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
 474 PCIDevice *pci_try_create(PCIBus *bus, int devfn, const char *name);
 475
 476 static inline int pci_is_express(const PCIDevice *d)
 477 {
 478     return d->cap_present & QEMU_PCI_CAP_EXPRESS;
 479 }
 480
 481 static inline uint32_t pci_config_size(const PCIDevice *d)
 482 {
 483     return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
 484 }
 485
 486 #endif