2 * QEMU PowerPC PowerNV machine model
4 * Copyright (c) 2016, IBM Corporation.
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qemu-common.h"
22 #include "qemu/datadir.h"
23 #include "qemu/units.h"
24 #include "qemu/cutils.h"
25 #include "qapi/error.h"
26 #include "sysemu/qtest.h"
27 #include "sysemu/sysemu.h"
28 #include "sysemu/numa.h"
29 #include "sysemu/reset.h"
30 #include "sysemu/runstate.h"
31 #include "sysemu/cpus.h"
32 #include "sysemu/device_tree.h"
33 #include "sysemu/hw_accel.h"
34 #include "target/ppc/cpu.h"
35 #include "hw/ppc/fdt.h"
36 #include "hw/ppc/ppc.h"
37 #include "hw/ppc/pnv.h"
38 #include "hw/ppc/pnv_core.h"
39 #include "hw/loader.h"
41 #include "qapi/visitor.h"
42 #include "monitor/monitor.h"
43 #include "hw/intc/intc.h"
44 #include "hw/ipmi/ipmi.h"
45 #include "target/ppc/mmu-hash64.h"
46 #include "hw/pci/msi.h"
48 #include "hw/ppc/xics.h"
49 #include "hw/qdev-properties.h"
50 #include "hw/ppc/pnv_xscom.h"
51 #include "hw/ppc/pnv_pnor.h"
53 #include "hw/isa/isa.h"
54 #include "hw/char/serial.h"
55 #include "hw/rtc/mc146818rtc.h"
59 #define FDT_MAX_SIZE (1 * MiB)
61 #define FW_FILE_NAME "skiboot.lid"
62 #define FW_LOAD_ADDR 0x0
63 #define FW_MAX_SIZE (16 * MiB)
65 #define KERNEL_LOAD_ADDR 0x20000000
66 #define KERNEL_MAX_SIZE (128 * MiB)
67 #define INITRD_LOAD_ADDR 0x28000000
68 #define INITRD_MAX_SIZE (128 * MiB)
70 static const char *pnv_chip_core_typename(const PnvChip
*o
)
72 const char *chip_type
= object_class_get_name(object_get_class(OBJECT(o
)));
73 int len
= strlen(chip_type
) - strlen(PNV_CHIP_TYPE_SUFFIX
);
74 char *s
= g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len
, chip_type
);
75 const char *core_type
= object_class_get_name(object_class_by_name(s
));
81 * On Power Systems E880 (POWER8), the max cpus (threads) should be :
82 * 4 * 4 sockets * 12 cores * 8 threads = 1536
88 * Memory nodes are created by hostboot, one for each range of memory
89 * that has a different "affinity". In practice, it means one range
92 static void pnv_dt_memory(void *fdt
, int chip_id
, hwaddr start
, hwaddr size
)
95 uint64_t mem_reg_property
[2];
98 mem_reg_property
[0] = cpu_to_be64(start
);
99 mem_reg_property
[1] = cpu_to_be64(size
);
101 mem_name
= g_strdup_printf("memory@%"HWADDR_PRIx
, start
);
102 off
= fdt_add_subnode(fdt
, 0, mem_name
);
105 _FDT((fdt_setprop_string(fdt
, off
, "device_type", "memory")));
106 _FDT((fdt_setprop(fdt
, off
, "reg", mem_reg_property
,
107 sizeof(mem_reg_property
))));
108 _FDT((fdt_setprop_cell(fdt
, off
, "ibm,chip-id", chip_id
)));
111 static int get_cpus_node(void *fdt
)
113 int cpus_offset
= fdt_path_offset(fdt
, "/cpus");
115 if (cpus_offset
< 0) {
116 cpus_offset
= fdt_add_subnode(fdt
, 0, "cpus");
118 _FDT((fdt_setprop_cell(fdt
, cpus_offset
, "#address-cells", 0x1)));
119 _FDT((fdt_setprop_cell(fdt
, cpus_offset
, "#size-cells", 0x0)));
127 * The PowerNV cores (and threads) need to use real HW ids and not an
128 * incremental index like it has been done on other platforms. This HW
129 * id is stored in the CPU PIR, it is used to create cpu nodes in the
130 * device tree, used in XSCOM to address cores and in interrupt
133 static void pnv_dt_core(PnvChip
*chip
, PnvCore
*pc
, void *fdt
)
135 PowerPCCPU
*cpu
= pc
->threads
[0];
136 CPUState
*cs
= CPU(cpu
);
137 DeviceClass
*dc
= DEVICE_GET_CLASS(cs
);
138 int smt_threads
= CPU_CORE(pc
)->nr_threads
;
139 CPUPPCState
*env
= &cpu
->env
;
140 PowerPCCPUClass
*pcc
= POWERPC_CPU_GET_CLASS(cs
);
141 uint32_t servers_prop
[smt_threads
];
143 uint32_t segs
[] = {cpu_to_be32(28), cpu_to_be32(40),
144 0xffffffff, 0xffffffff};
145 uint32_t tbfreq
= PNV_TIMEBASE_FREQ
;
146 uint32_t cpufreq
= 1000000000;
147 uint32_t page_sizes_prop
[64];
148 size_t page_sizes_prop_size
;
149 const uint8_t pa_features
[] = { 24, 0,
150 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0,
151 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
152 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
153 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
156 int cpus_offset
= get_cpus_node(fdt
);
158 nodename
= g_strdup_printf("%s@%x", dc
->fw_name
, pc
->pir
);
159 offset
= fdt_add_subnode(fdt
, cpus_offset
, nodename
);
163 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,chip-id", chip
->chip_id
)));
165 _FDT((fdt_setprop_cell(fdt
, offset
, "reg", pc
->pir
)));
166 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,pir", pc
->pir
)));
167 _FDT((fdt_setprop_string(fdt
, offset
, "device_type", "cpu")));
169 _FDT((fdt_setprop_cell(fdt
, offset
, "cpu-version", env
->spr
[SPR_PVR
])));
170 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-block-size",
171 env
->dcache_line_size
)));
172 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-line-size",
173 env
->dcache_line_size
)));
174 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-block-size",
175 env
->icache_line_size
)));
176 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-line-size",
177 env
->icache_line_size
)));
179 if (pcc
->l1_dcache_size
) {
180 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-size",
181 pcc
->l1_dcache_size
)));
183 warn_report("Unknown L1 dcache size for cpu");
185 if (pcc
->l1_icache_size
) {
186 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-size",
187 pcc
->l1_icache_size
)));
189 warn_report("Unknown L1 icache size for cpu");
192 _FDT((fdt_setprop_cell(fdt
, offset
, "timebase-frequency", tbfreq
)));
193 _FDT((fdt_setprop_cell(fdt
, offset
, "clock-frequency", cpufreq
)));
194 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,slb-size",
195 cpu
->hash64_opts
->slb_size
)));
196 _FDT((fdt_setprop_string(fdt
, offset
, "status", "okay")));
197 _FDT((fdt_setprop(fdt
, offset
, "64-bit", NULL
, 0)));
199 if (ppc_has_spr(cpu
, SPR_PURR
)) {
200 _FDT((fdt_setprop(fdt
, offset
, "ibm,purr", NULL
, 0)));
203 if (ppc_hash64_has(cpu
, PPC_HASH64_1TSEG
)) {
204 _FDT((fdt_setprop(fdt
, offset
, "ibm,processor-segment-sizes",
205 segs
, sizeof(segs
))));
209 * Advertise VMX/VSX (vector extensions) if available
210 * 0 / no property == no vector extensions
211 * 1 == VMX / Altivec available
214 if (env
->insns_flags
& PPC_ALTIVEC
) {
215 uint32_t vmx
= (env
->insns_flags2
& PPC2_VSX
) ? 2 : 1;
217 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,vmx", vmx
)));
221 * Advertise DFP (Decimal Floating Point) if available
222 * 0 / no property == no DFP
225 if (env
->insns_flags2
& PPC2_DFP
) {
226 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,dfp", 1)));
229 page_sizes_prop_size
= ppc_create_page_sizes_prop(cpu
, page_sizes_prop
,
230 sizeof(page_sizes_prop
));
231 if (page_sizes_prop_size
) {
232 _FDT((fdt_setprop(fdt
, offset
, "ibm,segment-page-sizes",
233 page_sizes_prop
, page_sizes_prop_size
)));
236 _FDT((fdt_setprop(fdt
, offset
, "ibm,pa-features",
237 pa_features
, sizeof(pa_features
))));
239 /* Build interrupt servers properties */
240 for (i
= 0; i
< smt_threads
; i
++) {
241 servers_prop
[i
] = cpu_to_be32(pc
->pir
+ i
);
243 _FDT((fdt_setprop(fdt
, offset
, "ibm,ppc-interrupt-server#s",
244 servers_prop
, sizeof(servers_prop
))));
247 static void pnv_dt_icp(PnvChip
*chip
, void *fdt
, uint32_t pir
,
250 uint64_t addr
= PNV_ICP_BASE(chip
) | (pir
<< 12);
252 const char compat
[] = "IBM,power8-icp\0IBM,ppc-xicp";
253 uint32_t irange
[2], i
, rsize
;
257 irange
[0] = cpu_to_be32(pir
);
258 irange
[1] = cpu_to_be32(nr_threads
);
260 rsize
= sizeof(uint64_t) * 2 * nr_threads
;
261 reg
= g_malloc(rsize
);
262 for (i
= 0; i
< nr_threads
; i
++) {
263 reg
[i
* 2] = cpu_to_be64(addr
| ((pir
+ i
) * 0x1000));
264 reg
[i
* 2 + 1] = cpu_to_be64(0x1000);
267 name
= g_strdup_printf("interrupt-controller@%"PRIX64
, addr
);
268 offset
= fdt_add_subnode(fdt
, 0, name
);
272 _FDT((fdt_setprop(fdt
, offset
, "compatible", compat
, sizeof(compat
))));
273 _FDT((fdt_setprop(fdt
, offset
, "reg", reg
, rsize
)));
274 _FDT((fdt_setprop_string(fdt
, offset
, "device_type",
275 "PowerPC-External-Interrupt-Presentation")));
276 _FDT((fdt_setprop(fdt
, offset
, "interrupt-controller", NULL
, 0)));
277 _FDT((fdt_setprop(fdt
, offset
, "ibm,interrupt-server-ranges",
278 irange
, sizeof(irange
))));
279 _FDT((fdt_setprop_cell(fdt
, offset
, "#interrupt-cells", 1)));
280 _FDT((fdt_setprop_cell(fdt
, offset
, "#address-cells", 0)));
284 static void pnv_chip_power8_dt_populate(PnvChip
*chip
, void *fdt
)
286 static const char compat
[] = "ibm,power8-xscom\0ibm,xscom";
289 pnv_dt_xscom(chip
, fdt
, 0,
290 cpu_to_be64(PNV_XSCOM_BASE(chip
)),
291 cpu_to_be64(PNV_XSCOM_SIZE
),
292 compat
, sizeof(compat
));
294 for (i
= 0; i
< chip
->nr_cores
; i
++) {
295 PnvCore
*pnv_core
= chip
->cores
[i
];
297 pnv_dt_core(chip
, pnv_core
, fdt
);
299 /* Interrupt Control Presenters (ICP). One per core. */
300 pnv_dt_icp(chip
, fdt
, pnv_core
->pir
, CPU_CORE(pnv_core
)->nr_threads
);
303 if (chip
->ram_size
) {
304 pnv_dt_memory(fdt
, chip
->chip_id
, chip
->ram_start
, chip
->ram_size
);
308 static void pnv_chip_power9_dt_populate(PnvChip
*chip
, void *fdt
)
310 static const char compat
[] = "ibm,power9-xscom\0ibm,xscom";
313 pnv_dt_xscom(chip
, fdt
, 0,
314 cpu_to_be64(PNV9_XSCOM_BASE(chip
)),
315 cpu_to_be64(PNV9_XSCOM_SIZE
),
316 compat
, sizeof(compat
));
318 for (i
= 0; i
< chip
->nr_cores
; i
++) {
319 PnvCore
*pnv_core
= chip
->cores
[i
];
321 pnv_dt_core(chip
, pnv_core
, fdt
);
324 if (chip
->ram_size
) {
325 pnv_dt_memory(fdt
, chip
->chip_id
, chip
->ram_start
, chip
->ram_size
);
328 pnv_dt_lpc(chip
, fdt
, 0, PNV9_LPCM_BASE(chip
), PNV9_LPCM_SIZE
);
331 static void pnv_chip_power10_dt_populate(PnvChip
*chip
, void *fdt
)
333 static const char compat
[] = "ibm,power10-xscom\0ibm,xscom";
336 pnv_dt_xscom(chip
, fdt
, 0,
337 cpu_to_be64(PNV10_XSCOM_BASE(chip
)),
338 cpu_to_be64(PNV10_XSCOM_SIZE
),
339 compat
, sizeof(compat
));
341 for (i
= 0; i
< chip
->nr_cores
; i
++) {
342 PnvCore
*pnv_core
= chip
->cores
[i
];
344 pnv_dt_core(chip
, pnv_core
, fdt
);
347 if (chip
->ram_size
) {
348 pnv_dt_memory(fdt
, chip
->chip_id
, chip
->ram_start
, chip
->ram_size
);
351 pnv_dt_lpc(chip
, fdt
, 0, PNV10_LPCM_BASE(chip
), PNV10_LPCM_SIZE
);
354 static void pnv_dt_rtc(ISADevice
*d
, void *fdt
, int lpc_off
)
356 uint32_t io_base
= d
->ioport_id
;
357 uint32_t io_regs
[] = {
359 cpu_to_be32(io_base
),
365 name
= g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d
)), io_base
);
366 node
= fdt_add_subnode(fdt
, lpc_off
, name
);
370 _FDT((fdt_setprop(fdt
, node
, "reg", io_regs
, sizeof(io_regs
))));
371 _FDT((fdt_setprop_string(fdt
, node
, "compatible", "pnpPNP,b00")));
374 static void pnv_dt_serial(ISADevice
*d
, void *fdt
, int lpc_off
)
376 const char compatible
[] = "ns16550\0pnpPNP,501";
377 uint32_t io_base
= d
->ioport_id
;
378 uint32_t io_regs
[] = {
380 cpu_to_be32(io_base
),
386 name
= g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d
)), io_base
);
387 node
= fdt_add_subnode(fdt
, lpc_off
, name
);
391 _FDT((fdt_setprop(fdt
, node
, "reg", io_regs
, sizeof(io_regs
))));
392 _FDT((fdt_setprop(fdt
, node
, "compatible", compatible
,
393 sizeof(compatible
))));
395 _FDT((fdt_setprop_cell(fdt
, node
, "clock-frequency", 1843200)));
396 _FDT((fdt_setprop_cell(fdt
, node
, "current-speed", 115200)));
397 _FDT((fdt_setprop_cell(fdt
, node
, "interrupts", d
->isairq
[0])));
398 _FDT((fdt_setprop_cell(fdt
, node
, "interrupt-parent",
399 fdt_get_phandle(fdt
, lpc_off
))));
401 /* This is needed by Linux */
402 _FDT((fdt_setprop_string(fdt
, node
, "device_type", "serial")));
405 static void pnv_dt_ipmi_bt(ISADevice
*d
, void *fdt
, int lpc_off
)
407 const char compatible
[] = "bt\0ipmi-bt";
409 uint32_t io_regs
[] = {
411 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */
418 io_base
= object_property_get_int(OBJECT(d
), "ioport", &error_fatal
);
419 io_regs
[1] = cpu_to_be32(io_base
);
421 irq
= object_property_get_int(OBJECT(d
), "irq", &error_fatal
);
423 name
= g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d
)), io_base
);
424 node
= fdt_add_subnode(fdt
, lpc_off
, name
);
428 _FDT((fdt_setprop(fdt
, node
, "reg", io_regs
, sizeof(io_regs
))));
429 _FDT((fdt_setprop(fdt
, node
, "compatible", compatible
,
430 sizeof(compatible
))));
432 /* Mark it as reserved to avoid Linux trying to claim it */
433 _FDT((fdt_setprop_string(fdt
, node
, "status", "reserved")));
434 _FDT((fdt_setprop_cell(fdt
, node
, "interrupts", irq
)));
435 _FDT((fdt_setprop_cell(fdt
, node
, "interrupt-parent",
436 fdt_get_phandle(fdt
, lpc_off
))));
439 typedef struct ForeachPopulateArgs
{
442 } ForeachPopulateArgs
;
444 static int pnv_dt_isa_device(DeviceState
*dev
, void *opaque
)
446 ForeachPopulateArgs
*args
= opaque
;
447 ISADevice
*d
= ISA_DEVICE(dev
);
449 if (object_dynamic_cast(OBJECT(dev
), TYPE_MC146818_RTC
)) {
450 pnv_dt_rtc(d
, args
->fdt
, args
->offset
);
451 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_ISA_SERIAL
)) {
452 pnv_dt_serial(d
, args
->fdt
, args
->offset
);
453 } else if (object_dynamic_cast(OBJECT(dev
), "isa-ipmi-bt")) {
454 pnv_dt_ipmi_bt(d
, args
->fdt
, args
->offset
);
456 error_report("unknown isa device %s@i%x", qdev_fw_name(dev
),
464 * The default LPC bus of a multichip system is on chip 0. It's
465 * recognized by the firmware (skiboot) using a "primary" property.
467 static void pnv_dt_isa(PnvMachineState
*pnv
, void *fdt
)
469 int isa_offset
= fdt_path_offset(fdt
, pnv
->chips
[0]->dt_isa_nodename
);
470 ForeachPopulateArgs args
= {
472 .offset
= isa_offset
,
476 _FDT((fdt_setprop(fdt
, isa_offset
, "primary", NULL
, 0)));
478 phandle
= qemu_fdt_alloc_phandle(fdt
);
480 _FDT((fdt_setprop_cell(fdt
, isa_offset
, "phandle", phandle
)));
483 * ISA devices are not necessarily parented to the ISA bus so we
484 * can not use object_child_foreach()
486 qbus_walk_children(BUS(pnv
->isa_bus
), pnv_dt_isa_device
, NULL
, NULL
, NULL
,
490 static void pnv_dt_power_mgt(PnvMachineState
*pnv
, void *fdt
)
494 off
= fdt_add_subnode(fdt
, 0, "ibm,opal");
495 off
= fdt_add_subnode(fdt
, off
, "power-mgt");
497 _FDT(fdt_setprop_cell(fdt
, off
, "ibm,enabled-stop-levels", 0xc0000000));
500 static void *pnv_dt_create(MachineState
*machine
)
502 PnvMachineClass
*pmc
= PNV_MACHINE_GET_CLASS(machine
);
503 PnvMachineState
*pnv
= PNV_MACHINE(machine
);
509 fdt
= g_malloc0(FDT_MAX_SIZE
);
510 _FDT((fdt_create_empty_tree(fdt
, FDT_MAX_SIZE
)));
513 _FDT((fdt_add_subnode(fdt
, 0, "qemu")));
516 _FDT((fdt_setprop_cell(fdt
, 0, "#address-cells", 0x2)));
517 _FDT((fdt_setprop_cell(fdt
, 0, "#size-cells", 0x2)));
518 _FDT((fdt_setprop_string(fdt
, 0, "model",
519 "IBM PowerNV (emulated by qemu)")));
520 _FDT((fdt_setprop(fdt
, 0, "compatible", pmc
->compat
, pmc
->compat_size
)));
522 buf
= qemu_uuid_unparse_strdup(&qemu_uuid
);
523 _FDT((fdt_setprop_string(fdt
, 0, "vm,uuid", buf
)));
525 _FDT((fdt_setprop_string(fdt
, 0, "system-id", buf
)));
529 off
= fdt_add_subnode(fdt
, 0, "chosen");
530 if (machine
->kernel_cmdline
) {
531 _FDT((fdt_setprop_string(fdt
, off
, "bootargs",
532 machine
->kernel_cmdline
)));
535 if (pnv
->initrd_size
) {
536 uint32_t start_prop
= cpu_to_be32(pnv
->initrd_base
);
537 uint32_t end_prop
= cpu_to_be32(pnv
->initrd_base
+ pnv
->initrd_size
);
539 _FDT((fdt_setprop(fdt
, off
, "linux,initrd-start",
540 &start_prop
, sizeof(start_prop
))));
541 _FDT((fdt_setprop(fdt
, off
, "linux,initrd-end",
542 &end_prop
, sizeof(end_prop
))));
545 /* Populate device tree for each chip */
546 for (i
= 0; i
< pnv
->num_chips
; i
++) {
547 PNV_CHIP_GET_CLASS(pnv
->chips
[i
])->dt_populate(pnv
->chips
[i
], fdt
);
550 /* Populate ISA devices on chip 0 */
551 pnv_dt_isa(pnv
, fdt
);
554 pnv_dt_bmc_sensors(pnv
->bmc
, fdt
);
557 /* Create an extra node for power management on machines that support it */
558 if (pmc
->dt_power_mgt
) {
559 pmc
->dt_power_mgt(pnv
, fdt
);
565 static void pnv_powerdown_notify(Notifier
*n
, void *opaque
)
567 PnvMachineState
*pnv
= container_of(n
, PnvMachineState
, powerdown_notifier
);
570 pnv_bmc_powerdown(pnv
->bmc
);
574 static void pnv_reset(MachineState
*machine
)
576 PnvMachineState
*pnv
= PNV_MACHINE(machine
);
580 qemu_devices_reset();
583 * The machine should provide by default an internal BMC simulator.
584 * If not, try to use the BMC device that was provided on the command
587 bmc
= pnv_bmc_find(&error_fatal
);
590 if (!qtest_enabled()) {
591 warn_report("machine has no BMC device. Use '-device "
592 "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' "
596 pnv_bmc_set_pnor(bmc
, pnv
->pnor
);
601 fdt
= pnv_dt_create(machine
);
603 /* Pack resulting tree */
604 _FDT((fdt_pack(fdt
)));
606 qemu_fdt_dumpdtb(fdt
, fdt_totalsize(fdt
));
607 cpu_physical_memory_write(PNV_FDT_ADDR
, fdt
, fdt_totalsize(fdt
));
612 static ISABus
*pnv_chip_power8_isa_create(PnvChip
*chip
, Error
**errp
)
614 Pnv8Chip
*chip8
= PNV8_CHIP(chip
);
615 return pnv_lpc_isa_create(&chip8
->lpc
, true, errp
);
618 static ISABus
*pnv_chip_power8nvl_isa_create(PnvChip
*chip
, Error
**errp
)
620 Pnv8Chip
*chip8
= PNV8_CHIP(chip
);
621 return pnv_lpc_isa_create(&chip8
->lpc
, false, errp
);
624 static ISABus
*pnv_chip_power9_isa_create(PnvChip
*chip
, Error
**errp
)
626 Pnv9Chip
*chip9
= PNV9_CHIP(chip
);
627 return pnv_lpc_isa_create(&chip9
->lpc
, false, errp
);
630 static ISABus
*pnv_chip_power10_isa_create(PnvChip
*chip
, Error
**errp
)
632 Pnv10Chip
*chip10
= PNV10_CHIP(chip
);
633 return pnv_lpc_isa_create(&chip10
->lpc
, false, errp
);
636 static ISABus
*pnv_isa_create(PnvChip
*chip
, Error
**errp
)
638 return PNV_CHIP_GET_CLASS(chip
)->isa_create(chip
, errp
);
641 static void pnv_chip_power8_pic_print_info(PnvChip
*chip
, Monitor
*mon
)
643 Pnv8Chip
*chip8
= PNV8_CHIP(chip
);
646 ics_pic_print_info(&chip8
->psi
.ics
, mon
);
647 for (i
= 0; i
< chip
->num_phbs
; i
++) {
648 pnv_phb3_msi_pic_print_info(&chip8
->phbs
[i
].msis
, mon
);
649 ics_pic_print_info(&chip8
->phbs
[i
].lsis
, mon
);
653 static void pnv_chip_power9_pic_print_info(PnvChip
*chip
, Monitor
*mon
)
655 Pnv9Chip
*chip9
= PNV9_CHIP(chip
);
658 pnv_xive_pic_print_info(&chip9
->xive
, mon
);
659 pnv_psi_pic_print_info(&chip9
->psi
, mon
);
661 for (i
= 0; i
< PNV9_CHIP_MAX_PEC
; i
++) {
662 PnvPhb4PecState
*pec
= &chip9
->pecs
[i
];
663 for (j
= 0; j
< pec
->num_stacks
; j
++) {
664 pnv_phb4_pic_print_info(&pec
->stacks
[j
].phb
, mon
);
669 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip
*chip
,
672 return PNV_XSCOM_EX_BASE(core_id
);
675 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip
*chip
,
678 return PNV9_XSCOM_EC_BASE(core_id
);
681 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip
*chip
,
684 return PNV10_XSCOM_EC_BASE(core_id
);
687 static bool pnv_match_cpu(const char *default_type
, const char *cpu_type
)
689 PowerPCCPUClass
*ppc_default
=
690 POWERPC_CPU_CLASS(object_class_by_name(default_type
));
691 PowerPCCPUClass
*ppc
=
692 POWERPC_CPU_CLASS(object_class_by_name(cpu_type
));
694 return ppc_default
->pvr_match(ppc_default
, ppc
->pvr
);
697 static void pnv_ipmi_bt_init(ISABus
*bus
, IPMIBmc
*bmc
, uint32_t irq
)
699 ISADevice
*dev
= isa_new("isa-ipmi-bt");
701 object_property_set_link(OBJECT(dev
), "bmc", OBJECT(bmc
), &error_fatal
);
702 object_property_set_int(OBJECT(dev
), "irq", irq
, &error_fatal
);
703 isa_realize_and_unref(dev
, bus
, &error_fatal
);
706 static void pnv_chip_power10_pic_print_info(PnvChip
*chip
, Monitor
*mon
)
708 Pnv10Chip
*chip10
= PNV10_CHIP(chip
);
710 pnv_psi_pic_print_info(&chip10
->psi
, mon
);
713 /* Always give the first 1GB to chip 0 else we won't boot */
714 static uint64_t pnv_chip_get_ram_size(PnvMachineState
*pnv
, int chip_id
)
716 MachineState
*machine
= MACHINE(pnv
);
717 uint64_t ram_per_chip
;
719 assert(machine
->ram_size
>= 1 * GiB
);
721 ram_per_chip
= machine
->ram_size
/ pnv
->num_chips
;
722 if (ram_per_chip
>= 1 * GiB
) {
723 return QEMU_ALIGN_DOWN(ram_per_chip
, 1 * MiB
);
726 assert(pnv
->num_chips
> 1);
728 ram_per_chip
= (machine
->ram_size
- 1 * GiB
) / (pnv
->num_chips
- 1);
729 return chip_id
== 0 ? 1 * GiB
: QEMU_ALIGN_DOWN(ram_per_chip
, 1 * MiB
);
732 static void pnv_init(MachineState
*machine
)
734 const char *bios_name
= machine
->firmware
?: FW_FILE_NAME
;
735 PnvMachineState
*pnv
= PNV_MACHINE(machine
);
736 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
739 uint64_t chip_ram_start
= 0;
742 DriveInfo
*pnor
= drive_get(IF_MTD
, 0, 0);
746 error_report("The powernv machine does not work with KVM acceleration");
751 if (machine
->ram_size
< mc
->default_ram_size
) {
752 char *sz
= size_to_str(mc
->default_ram_size
);
753 error_report("Invalid RAM size, should be bigger than %s", sz
);
757 memory_region_add_subregion(get_system_memory(), 0, machine
->ram
);
760 * Create our simple PNOR device
762 dev
= qdev_new(TYPE_PNV_PNOR
);
764 qdev_prop_set_drive(dev
, "drive", blk_by_legacy_dinfo(pnor
));
766 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
767 pnv
->pnor
= PNV_PNOR(dev
);
769 /* load skiboot firmware */
770 fw_filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
772 error_report("Could not find OPAL firmware '%s'", bios_name
);
776 fw_size
= load_image_targphys(fw_filename
, pnv
->fw_load_addr
, FW_MAX_SIZE
);
778 error_report("Could not load OPAL firmware '%s'", fw_filename
);
784 if (machine
->kernel_filename
) {
787 kernel_size
= load_image_targphys(machine
->kernel_filename
,
788 KERNEL_LOAD_ADDR
, KERNEL_MAX_SIZE
);
789 if (kernel_size
< 0) {
790 error_report("Could not load kernel '%s'",
791 machine
->kernel_filename
);
797 if (machine
->initrd_filename
) {
798 pnv
->initrd_base
= INITRD_LOAD_ADDR
;
799 pnv
->initrd_size
= load_image_targphys(machine
->initrd_filename
,
800 pnv
->initrd_base
, INITRD_MAX_SIZE
);
801 if (pnv
->initrd_size
< 0) {
802 error_report("Could not load initial ram disk '%s'",
803 machine
->initrd_filename
);
808 /* MSIs are supported on this platform */
809 msi_nonbroken
= true;
812 * Check compatibility of the specified CPU with the machine
815 if (!pnv_match_cpu(mc
->default_cpu_type
, machine
->cpu_type
)) {
816 error_report("invalid CPU model '%s' for %s machine",
817 machine
->cpu_type
, mc
->name
);
821 /* Create the processor chips */
822 i
= strlen(machine
->cpu_type
) - strlen(POWERPC_CPU_TYPE_SUFFIX
);
823 chip_typename
= g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"),
824 i
, machine
->cpu_type
);
825 if (!object_class_by_name(chip_typename
)) {
826 error_report("invalid chip model '%.*s' for %s machine",
827 i
, machine
->cpu_type
, mc
->name
);
832 machine
->smp
.max_cpus
/ (machine
->smp
.cores
* machine
->smp
.threads
);
834 * TODO: should we decide on how many chips we can create based
835 * on #cores and Venice vs. Murano vs. Naples chip type etc...,
837 if (!is_power_of_2(pnv
->num_chips
) || pnv
->num_chips
> 16) {
838 error_report("invalid number of chips: '%d'", pnv
->num_chips
);
840 "Try '-smp sockets=N'. Valid values are : 1, 2, 4, 8 and 16.\n");
844 pnv
->chips
= g_new0(PnvChip
*, pnv
->num_chips
);
845 for (i
= 0; i
< pnv
->num_chips
; i
++) {
847 Object
*chip
= OBJECT(qdev_new(chip_typename
));
848 uint64_t chip_ram_size
= pnv_chip_get_ram_size(pnv
, i
);
850 pnv
->chips
[i
] = PNV_CHIP(chip
);
852 /* Distribute RAM among the chips */
853 object_property_set_int(chip
, "ram-start", chip_ram_start
,
855 object_property_set_int(chip
, "ram-size", chip_ram_size
,
857 chip_ram_start
+= chip_ram_size
;
859 snprintf(chip_name
, sizeof(chip_name
), "chip[%d]", i
);
860 object_property_add_child(OBJECT(pnv
), chip_name
, chip
);
861 object_property_set_int(chip
, "chip-id", i
, &error_fatal
);
862 object_property_set_int(chip
, "nr-cores", machine
->smp
.cores
,
864 object_property_set_int(chip
, "nr-threads", machine
->smp
.threads
,
867 * The POWER8 machine use the XICS interrupt interface.
868 * Propagate the XICS fabric to the chip and its controllers.
870 if (object_dynamic_cast(OBJECT(pnv
), TYPE_XICS_FABRIC
)) {
871 object_property_set_link(chip
, "xics", OBJECT(pnv
), &error_abort
);
873 if (object_dynamic_cast(OBJECT(pnv
), TYPE_XIVE_FABRIC
)) {
874 object_property_set_link(chip
, "xive-fabric", OBJECT(pnv
),
877 sysbus_realize_and_unref(SYS_BUS_DEVICE(chip
), &error_fatal
);
879 g_free(chip_typename
);
881 /* Instantiate ISA bus on chip 0 */
882 pnv
->isa_bus
= pnv_isa_create(pnv
->chips
[0], &error_fatal
);
884 /* Create serial port */
885 serial_hds_isa_init(pnv
->isa_bus
, 0, MAX_ISA_SERIAL_PORTS
);
887 /* Create an RTC ISA device too */
888 mc146818_rtc_init(pnv
->isa_bus
, 2000, NULL
);
891 * Create the machine BMC simulator and the IPMI BT device for
892 * communication with the BMC
894 if (defaults_enabled()) {
895 pnv
->bmc
= pnv_bmc_create(pnv
->pnor
);
896 pnv_ipmi_bt_init(pnv
->isa_bus
, pnv
->bmc
, 10);
900 * The PNOR is mapped on the LPC FW address space by the BMC.
901 * Since we can not reach the remote BMC machine with LPC memops,
902 * map it always for now.
904 memory_region_add_subregion(pnv
->chips
[0]->fw_mr
, PNOR_SPI_OFFSET
,
908 * OpenPOWER systems use a IPMI SEL Event message to notify the
911 pnv
->powerdown_notifier
.notify
= pnv_powerdown_notify
;
912 qemu_register_powerdown_notifier(&pnv
->powerdown_notifier
);
916 * 0:21 Reserved - Read as zeros
921 static uint32_t pnv_chip_core_pir_p8(PnvChip
*chip
, uint32_t core_id
)
923 return (chip
->chip_id
<< 7) | (core_id
<< 3);
926 static void pnv_chip_power8_intc_create(PnvChip
*chip
, PowerPCCPU
*cpu
,
929 Pnv8Chip
*chip8
= PNV8_CHIP(chip
);
930 Error
*local_err
= NULL
;
932 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
934 obj
= icp_create(OBJECT(cpu
), TYPE_PNV_ICP
, chip8
->xics
, &local_err
);
936 error_propagate(errp
, local_err
);
944 static void pnv_chip_power8_intc_reset(PnvChip
*chip
, PowerPCCPU
*cpu
)
946 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
948 icp_reset(ICP(pnv_cpu
->intc
));
951 static void pnv_chip_power8_intc_destroy(PnvChip
*chip
, PowerPCCPU
*cpu
)
953 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
955 icp_destroy(ICP(pnv_cpu
->intc
));
956 pnv_cpu
->intc
= NULL
;
959 static void pnv_chip_power8_intc_print_info(PnvChip
*chip
, PowerPCCPU
*cpu
,
962 icp_pic_print_info(ICP(pnv_cpu_state(cpu
)->intc
), mon
);
966 * 0:48 Reserved - Read as zeroes
969 * 56 Reserved - Read as zero
973 * We only care about the lower bits. uint32_t is fine for the moment.
975 static uint32_t pnv_chip_core_pir_p9(PnvChip
*chip
, uint32_t core_id
)
977 return (chip
->chip_id
<< 8) | (core_id
<< 2);
980 static uint32_t pnv_chip_core_pir_p10(PnvChip
*chip
, uint32_t core_id
)
982 return (chip
->chip_id
<< 8) | (core_id
<< 2);
985 static void pnv_chip_power9_intc_create(PnvChip
*chip
, PowerPCCPU
*cpu
,
988 Pnv9Chip
*chip9
= PNV9_CHIP(chip
);
989 Error
*local_err
= NULL
;
991 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
994 * The core creates its interrupt presenter but the XIVE interrupt
995 * controller object is initialized afterwards. Hopefully, it's
996 * only used at runtime.
998 obj
= xive_tctx_create(OBJECT(cpu
), XIVE_PRESENTER(&chip9
->xive
),
1001 error_propagate(errp
, local_err
);
1005 pnv_cpu
->intc
= obj
;
1008 static void pnv_chip_power9_intc_reset(PnvChip
*chip
, PowerPCCPU
*cpu
)
1010 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
1012 xive_tctx_reset(XIVE_TCTX(pnv_cpu
->intc
));
1015 static void pnv_chip_power9_intc_destroy(PnvChip
*chip
, PowerPCCPU
*cpu
)
1017 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
1019 xive_tctx_destroy(XIVE_TCTX(pnv_cpu
->intc
));
1020 pnv_cpu
->intc
= NULL
;
1023 static void pnv_chip_power9_intc_print_info(PnvChip
*chip
, PowerPCCPU
*cpu
,
1026 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu
)->intc
), mon
);
1029 static void pnv_chip_power10_intc_create(PnvChip
*chip
, PowerPCCPU
*cpu
,
1032 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
1034 /* Will be defined when the interrupt controller is */
1035 pnv_cpu
->intc
= NULL
;
1038 static void pnv_chip_power10_intc_reset(PnvChip
*chip
, PowerPCCPU
*cpu
)
1043 static void pnv_chip_power10_intc_destroy(PnvChip
*chip
, PowerPCCPU
*cpu
)
1045 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
1047 pnv_cpu
->intc
= NULL
;
1050 static void pnv_chip_power10_intc_print_info(PnvChip
*chip
, PowerPCCPU
*cpu
,
1056 * Allowed core identifiers on a POWER8 Processor Chip :
1065 * <EX7,8 reserved> <reserved>
1067 * EX10 - Venice only
1068 * EX11 - Venice only
1074 #define POWER8E_CORE_MASK (0x7070ull)
1075 #define POWER8_CORE_MASK (0x7e7eull)
1078 * POWER9 has 24 cores, ids starting at 0x0
1080 #define POWER9_CORE_MASK (0xffffffffffffffull)
1083 #define POWER10_CORE_MASK (0xffffffffffffffull)
1085 static void pnv_chip_power8_instance_init(Object
*obj
)
1087 PnvChip
*chip
= PNV_CHIP(obj
);
1088 Pnv8Chip
*chip8
= PNV8_CHIP(obj
);
1089 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(obj
);
1092 object_property_add_link(obj
, "xics", TYPE_XICS_FABRIC
,
1093 (Object
**)&chip8
->xics
,
1094 object_property_allow_set_link
,
1095 OBJ_PROP_LINK_STRONG
);
1097 object_initialize_child(obj
, "psi", &chip8
->psi
, TYPE_PNV8_PSI
);
1099 object_initialize_child(obj
, "lpc", &chip8
->lpc
, TYPE_PNV8_LPC
);
1101 object_initialize_child(obj
, "occ", &chip8
->occ
, TYPE_PNV8_OCC
);
1103 object_initialize_child(obj
, "homer", &chip8
->homer
, TYPE_PNV8_HOMER
);
1105 for (i
= 0; i
< pcc
->num_phbs
; i
++) {
1106 object_initialize_child(obj
, "phb[*]", &chip8
->phbs
[i
], TYPE_PNV_PHB3
);
1110 * Number of PHBs is the chip default
1112 chip
->num_phbs
= pcc
->num_phbs
;
1115 static void pnv_chip_icp_realize(Pnv8Chip
*chip8
, Error
**errp
)
1117 PnvChip
*chip
= PNV_CHIP(chip8
);
1118 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(chip
);
1122 name
= g_strdup_printf("icp-%x", chip
->chip_id
);
1123 memory_region_init(&chip8
->icp_mmio
, OBJECT(chip
), name
, PNV_ICP_SIZE
);
1124 sysbus_init_mmio(SYS_BUS_DEVICE(chip
), &chip8
->icp_mmio
);
1127 sysbus_mmio_map(SYS_BUS_DEVICE(chip
), 1, PNV_ICP_BASE(chip
));
1129 /* Map the ICP registers for each thread */
1130 for (i
= 0; i
< chip
->nr_cores
; i
++) {
1131 PnvCore
*pnv_core
= chip
->cores
[i
];
1132 int core_hwid
= CPU_CORE(pnv_core
)->core_id
;
1134 for (j
= 0; j
< CPU_CORE(pnv_core
)->nr_threads
; j
++) {
1135 uint32_t pir
= pcc
->core_pir(chip
, core_hwid
) + j
;
1136 PnvICPState
*icp
= PNV_ICP(xics_icp_get(chip8
->xics
, pir
));
1138 memory_region_add_subregion(&chip8
->icp_mmio
, pir
<< 12,
1144 static void pnv_chip_power8_realize(DeviceState
*dev
, Error
**errp
)
1146 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(dev
);
1147 PnvChip
*chip
= PNV_CHIP(dev
);
1148 Pnv8Chip
*chip8
= PNV8_CHIP(dev
);
1149 Pnv8Psi
*psi8
= &chip8
->psi
;
1150 Error
*local_err
= NULL
;
1153 assert(chip8
->xics
);
1155 /* XSCOM bridge is first */
1156 pnv_xscom_realize(chip
, PNV_XSCOM_SIZE
, &local_err
);
1158 error_propagate(errp
, local_err
);
1161 sysbus_mmio_map(SYS_BUS_DEVICE(chip
), 0, PNV_XSCOM_BASE(chip
));
1163 pcc
->parent_realize(dev
, &local_err
);
1165 error_propagate(errp
, local_err
);
1169 /* Processor Service Interface (PSI) Host Bridge */
1170 object_property_set_int(OBJECT(&chip8
->psi
), "bar", PNV_PSIHB_BASE(chip
),
1172 object_property_set_link(OBJECT(&chip8
->psi
), ICS_PROP_XICS
,
1173 OBJECT(chip8
->xics
), &error_abort
);
1174 if (!qdev_realize(DEVICE(&chip8
->psi
), NULL
, errp
)) {
1177 pnv_xscom_add_subregion(chip
, PNV_XSCOM_PSIHB_BASE
,
1178 &PNV_PSI(psi8
)->xscom_regs
);
1180 /* Create LPC controller */
1181 object_property_set_link(OBJECT(&chip8
->lpc
), "psi", OBJECT(&chip8
->psi
),
1183 qdev_realize(DEVICE(&chip8
->lpc
), NULL
, &error_fatal
);
1184 pnv_xscom_add_subregion(chip
, PNV_XSCOM_LPC_BASE
, &chip8
->lpc
.xscom_regs
);
1186 chip
->fw_mr
= &chip8
->lpc
.isa_fw
;
1187 chip
->dt_isa_nodename
= g_strdup_printf("/xscom@%" PRIx64
"/isa@%x",
1188 (uint64_t) PNV_XSCOM_BASE(chip
),
1189 PNV_XSCOM_LPC_BASE
);
1192 * Interrupt Management Area. This is the memory region holding
1193 * all the Interrupt Control Presenter (ICP) registers
1195 pnv_chip_icp_realize(chip8
, &local_err
);
1197 error_propagate(errp
, local_err
);
1201 /* Create the simplified OCC model */
1202 object_property_set_link(OBJECT(&chip8
->occ
), "psi", OBJECT(&chip8
->psi
),
1204 if (!qdev_realize(DEVICE(&chip8
->occ
), NULL
, errp
)) {
1207 pnv_xscom_add_subregion(chip
, PNV_XSCOM_OCC_BASE
, &chip8
->occ
.xscom_regs
);
1209 /* OCC SRAM model */
1210 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip
),
1211 &chip8
->occ
.sram_regs
);
1214 object_property_set_link(OBJECT(&chip8
->homer
), "chip", OBJECT(chip
),
1216 if (!qdev_realize(DEVICE(&chip8
->homer
), NULL
, errp
)) {
1219 /* Homer Xscom region */
1220 pnv_xscom_add_subregion(chip
, PNV_XSCOM_PBA_BASE
, &chip8
->homer
.pba_regs
);
1222 /* Homer mmio region */
1223 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip
),
1224 &chip8
->homer
.regs
);
1226 /* PHB3 controllers */
1227 for (i
= 0; i
< chip
->num_phbs
; i
++) {
1228 PnvPHB3
*phb
= &chip8
->phbs
[i
];
1230 object_property_set_int(OBJECT(phb
), "index", i
, &error_fatal
);
1231 object_property_set_int(OBJECT(phb
), "chip-id", chip
->chip_id
,
1233 object_property_set_link(OBJECT(phb
), "chip", OBJECT(chip
),
1235 if (!sysbus_realize(SYS_BUS_DEVICE(phb
), errp
)) {
1241 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip
*chip
, uint64_t addr
)
1243 addr
&= (PNV_XSCOM_SIZE
- 1);
1244 return ((addr
>> 4) & ~0xfull
) | ((addr
>> 3) & 0xf);
1247 static void pnv_chip_power8e_class_init(ObjectClass
*klass
, void *data
)
1249 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1250 PnvChipClass
*k
= PNV_CHIP_CLASS(klass
);
1252 k
->chip_cfam_id
= 0x221ef04980000000ull
; /* P8 Murano DD2.1 */
1253 k
->cores_mask
= POWER8E_CORE_MASK
;
1255 k
->core_pir
= pnv_chip_core_pir_p8
;
1256 k
->intc_create
= pnv_chip_power8_intc_create
;
1257 k
->intc_reset
= pnv_chip_power8_intc_reset
;
1258 k
->intc_destroy
= pnv_chip_power8_intc_destroy
;
1259 k
->intc_print_info
= pnv_chip_power8_intc_print_info
;
1260 k
->isa_create
= pnv_chip_power8_isa_create
;
1261 k
->dt_populate
= pnv_chip_power8_dt_populate
;
1262 k
->pic_print_info
= pnv_chip_power8_pic_print_info
;
1263 k
->xscom_core_base
= pnv_chip_power8_xscom_core_base
;
1264 k
->xscom_pcba
= pnv_chip_power8_xscom_pcba
;
1265 dc
->desc
= "PowerNV Chip POWER8E";
1267 device_class_set_parent_realize(dc
, pnv_chip_power8_realize
,
1268 &k
->parent_realize
);
1271 static void pnv_chip_power8_class_init(ObjectClass
*klass
, void *data
)
1273 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1274 PnvChipClass
*k
= PNV_CHIP_CLASS(klass
);
1276 k
->chip_cfam_id
= 0x220ea04980000000ull
; /* P8 Venice DD2.0 */
1277 k
->cores_mask
= POWER8_CORE_MASK
;
1279 k
->core_pir
= pnv_chip_core_pir_p8
;
1280 k
->intc_create
= pnv_chip_power8_intc_create
;
1281 k
->intc_reset
= pnv_chip_power8_intc_reset
;
1282 k
->intc_destroy
= pnv_chip_power8_intc_destroy
;
1283 k
->intc_print_info
= pnv_chip_power8_intc_print_info
;
1284 k
->isa_create
= pnv_chip_power8_isa_create
;
1285 k
->dt_populate
= pnv_chip_power8_dt_populate
;
1286 k
->pic_print_info
= pnv_chip_power8_pic_print_info
;
1287 k
->xscom_core_base
= pnv_chip_power8_xscom_core_base
;
1288 k
->xscom_pcba
= pnv_chip_power8_xscom_pcba
;
1289 dc
->desc
= "PowerNV Chip POWER8";
1291 device_class_set_parent_realize(dc
, pnv_chip_power8_realize
,
1292 &k
->parent_realize
);
1295 static void pnv_chip_power8nvl_class_init(ObjectClass
*klass
, void *data
)
1297 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1298 PnvChipClass
*k
= PNV_CHIP_CLASS(klass
);
1300 k
->chip_cfam_id
= 0x120d304980000000ull
; /* P8 Naples DD1.0 */
1301 k
->cores_mask
= POWER8_CORE_MASK
;
1303 k
->core_pir
= pnv_chip_core_pir_p8
;
1304 k
->intc_create
= pnv_chip_power8_intc_create
;
1305 k
->intc_reset
= pnv_chip_power8_intc_reset
;
1306 k
->intc_destroy
= pnv_chip_power8_intc_destroy
;
1307 k
->intc_print_info
= pnv_chip_power8_intc_print_info
;
1308 k
->isa_create
= pnv_chip_power8nvl_isa_create
;
1309 k
->dt_populate
= pnv_chip_power8_dt_populate
;
1310 k
->pic_print_info
= pnv_chip_power8_pic_print_info
;
1311 k
->xscom_core_base
= pnv_chip_power8_xscom_core_base
;
1312 k
->xscom_pcba
= pnv_chip_power8_xscom_pcba
;
1313 dc
->desc
= "PowerNV Chip POWER8NVL";
1315 device_class_set_parent_realize(dc
, pnv_chip_power8_realize
,
1316 &k
->parent_realize
);
1319 static void pnv_chip_power9_instance_init(Object
*obj
)
1321 PnvChip
*chip
= PNV_CHIP(obj
);
1322 Pnv9Chip
*chip9
= PNV9_CHIP(obj
);
1323 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(obj
);
1326 object_initialize_child(obj
, "xive", &chip9
->xive
, TYPE_PNV_XIVE
);
1327 object_property_add_alias(obj
, "xive-fabric", OBJECT(&chip9
->xive
),
1330 object_initialize_child(obj
, "psi", &chip9
->psi
, TYPE_PNV9_PSI
);
1332 object_initialize_child(obj
, "lpc", &chip9
->lpc
, TYPE_PNV9_LPC
);
1334 object_initialize_child(obj
, "occ", &chip9
->occ
, TYPE_PNV9_OCC
);
1336 object_initialize_child(obj
, "homer", &chip9
->homer
, TYPE_PNV9_HOMER
);
1338 for (i
= 0; i
< PNV9_CHIP_MAX_PEC
; i
++) {
1339 object_initialize_child(obj
, "pec[*]", &chip9
->pecs
[i
],
1344 * Number of PHBs is the chip default
1346 chip
->num_phbs
= pcc
->num_phbs
;
1349 static void pnv_chip_quad_realize(Pnv9Chip
*chip9
, Error
**errp
)
1351 PnvChip
*chip
= PNV_CHIP(chip9
);
1354 chip9
->nr_quads
= DIV_ROUND_UP(chip
->nr_cores
, 4);
1355 chip9
->quads
= g_new0(PnvQuad
, chip9
->nr_quads
);
1357 for (i
= 0; i
< chip9
->nr_quads
; i
++) {
1359 PnvQuad
*eq
= &chip9
->quads
[i
];
1360 PnvCore
*pnv_core
= chip
->cores
[i
* 4];
1361 int core_id
= CPU_CORE(pnv_core
)->core_id
;
1363 snprintf(eq_name
, sizeof(eq_name
), "eq[%d]", core_id
);
1364 object_initialize_child_with_props(OBJECT(chip
), eq_name
, eq
,
1365 sizeof(*eq
), TYPE_PNV_QUAD
,
1366 &error_fatal
, NULL
);
1368 object_property_set_int(OBJECT(eq
), "quad-id", core_id
, &error_fatal
);
1369 qdev_realize(DEVICE(eq
), NULL
, &error_fatal
);
1371 pnv_xscom_add_subregion(chip
, PNV9_XSCOM_EQ_BASE(eq
->quad_id
),
1376 static void pnv_chip_power9_phb_realize(PnvChip
*chip
, Error
**errp
)
1378 Pnv9Chip
*chip9
= PNV9_CHIP(chip
);
1382 for (i
= 0; i
< PNV9_CHIP_MAX_PEC
; i
++) {
1383 PnvPhb4PecState
*pec
= &chip9
->pecs
[i
];
1384 PnvPhb4PecClass
*pecc
= PNV_PHB4_PEC_GET_CLASS(pec
);
1385 uint32_t pec_nest_base
;
1386 uint32_t pec_pci_base
;
1388 object_property_set_int(OBJECT(pec
), "index", i
, &error_fatal
);
1394 object_property_set_int(OBJECT(pec
), "num-stacks", i
+ 1,
1396 object_property_set_int(OBJECT(pec
), "chip-id", chip
->chip_id
,
1398 object_property_set_link(OBJECT(pec
), "system-memory",
1399 OBJECT(get_system_memory()), &error_abort
);
1400 if (!qdev_realize(DEVICE(pec
), NULL
, errp
)) {
1404 pec_nest_base
= pecc
->xscom_nest_base(pec
);
1405 pec_pci_base
= pecc
->xscom_pci_base(pec
);
1407 pnv_xscom_add_subregion(chip
, pec_nest_base
, &pec
->nest_regs_mr
);
1408 pnv_xscom_add_subregion(chip
, pec_pci_base
, &pec
->pci_regs_mr
);
1410 for (j
= 0; j
< pec
->num_stacks
&& phb_id
< chip
->num_phbs
;
1412 PnvPhb4PecStack
*stack
= &pec
->stacks
[j
];
1413 Object
*obj
= OBJECT(&stack
->phb
);
1415 object_property_set_int(obj
, "index", phb_id
, &error_fatal
);
1416 object_property_set_int(obj
, "chip-id", chip
->chip_id
,
1418 object_property_set_int(obj
, "version", PNV_PHB4_VERSION
,
1420 object_property_set_int(obj
, "device-id", PNV_PHB4_DEVICE_ID
,
1422 object_property_set_link(obj
, "stack", OBJECT(stack
),
1424 if (!sysbus_realize(SYS_BUS_DEVICE(obj
), errp
)) {
1428 /* Populate the XSCOM address space. */
1429 pnv_xscom_add_subregion(chip
,
1430 pec_nest_base
+ 0x40 * (stack
->stack_no
+ 1),
1431 &stack
->nest_regs_mr
);
1432 pnv_xscom_add_subregion(chip
,
1433 pec_pci_base
+ 0x40 * (stack
->stack_no
+ 1),
1434 &stack
->pci_regs_mr
);
1435 pnv_xscom_add_subregion(chip
,
1436 pec_pci_base
+ PNV9_XSCOM_PEC_PCI_STK0
+
1437 0x40 * stack
->stack_no
,
1438 &stack
->phb_regs_mr
);
1443 static void pnv_chip_power9_realize(DeviceState
*dev
, Error
**errp
)
1445 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(dev
);
1446 Pnv9Chip
*chip9
= PNV9_CHIP(dev
);
1447 PnvChip
*chip
= PNV_CHIP(dev
);
1448 Pnv9Psi
*psi9
= &chip9
->psi
;
1449 Error
*local_err
= NULL
;
1451 /* XSCOM bridge is first */
1452 pnv_xscom_realize(chip
, PNV9_XSCOM_SIZE
, &local_err
);
1454 error_propagate(errp
, local_err
);
1457 sysbus_mmio_map(SYS_BUS_DEVICE(chip
), 0, PNV9_XSCOM_BASE(chip
));
1459 pcc
->parent_realize(dev
, &local_err
);
1461 error_propagate(errp
, local_err
);
1465 pnv_chip_quad_realize(chip9
, &local_err
);
1467 error_propagate(errp
, local_err
);
1471 /* XIVE interrupt controller (POWER9) */
1472 object_property_set_int(OBJECT(&chip9
->xive
), "ic-bar",
1473 PNV9_XIVE_IC_BASE(chip
), &error_fatal
);
1474 object_property_set_int(OBJECT(&chip9
->xive
), "vc-bar",
1475 PNV9_XIVE_VC_BASE(chip
), &error_fatal
);
1476 object_property_set_int(OBJECT(&chip9
->xive
), "pc-bar",
1477 PNV9_XIVE_PC_BASE(chip
), &error_fatal
);
1478 object_property_set_int(OBJECT(&chip9
->xive
), "tm-bar",
1479 PNV9_XIVE_TM_BASE(chip
), &error_fatal
);
1480 object_property_set_link(OBJECT(&chip9
->xive
), "chip", OBJECT(chip
),
1482 if (!sysbus_realize(SYS_BUS_DEVICE(&chip9
->xive
), errp
)) {
1485 pnv_xscom_add_subregion(chip
, PNV9_XSCOM_XIVE_BASE
,
1486 &chip9
->xive
.xscom_regs
);
1488 /* Processor Service Interface (PSI) Host Bridge */
1489 object_property_set_int(OBJECT(&chip9
->psi
), "bar", PNV9_PSIHB_BASE(chip
),
1491 if (!qdev_realize(DEVICE(&chip9
->psi
), NULL
, errp
)) {
1494 pnv_xscom_add_subregion(chip
, PNV9_XSCOM_PSIHB_BASE
,
1495 &PNV_PSI(psi9
)->xscom_regs
);
1498 object_property_set_link(OBJECT(&chip9
->lpc
), "psi", OBJECT(&chip9
->psi
),
1500 if (!qdev_realize(DEVICE(&chip9
->lpc
), NULL
, errp
)) {
1503 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip
),
1504 &chip9
->lpc
.xscom_regs
);
1506 chip
->fw_mr
= &chip9
->lpc
.isa_fw
;
1507 chip
->dt_isa_nodename
= g_strdup_printf("/lpcm-opb@%" PRIx64
"/lpc@0",
1508 (uint64_t) PNV9_LPCM_BASE(chip
));
1510 /* Create the simplified OCC model */
1511 object_property_set_link(OBJECT(&chip9
->occ
), "psi", OBJECT(&chip9
->psi
),
1513 if (!qdev_realize(DEVICE(&chip9
->occ
), NULL
, errp
)) {
1516 pnv_xscom_add_subregion(chip
, PNV9_XSCOM_OCC_BASE
, &chip9
->occ
.xscom_regs
);
1518 /* OCC SRAM model */
1519 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip
),
1520 &chip9
->occ
.sram_regs
);
1523 object_property_set_link(OBJECT(&chip9
->homer
), "chip", OBJECT(chip
),
1525 if (!qdev_realize(DEVICE(&chip9
->homer
), NULL
, errp
)) {
1528 /* Homer Xscom region */
1529 pnv_xscom_add_subregion(chip
, PNV9_XSCOM_PBA_BASE
, &chip9
->homer
.pba_regs
);
1531 /* Homer mmio region */
1532 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip
),
1533 &chip9
->homer
.regs
);
1536 pnv_chip_power9_phb_realize(chip
, &local_err
);
1538 error_propagate(errp
, local_err
);
1543 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip
*chip
, uint64_t addr
)
1545 addr
&= (PNV9_XSCOM_SIZE
- 1);
1549 static void pnv_chip_power9_class_init(ObjectClass
*klass
, void *data
)
1551 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1552 PnvChipClass
*k
= PNV_CHIP_CLASS(klass
);
1554 k
->chip_cfam_id
= 0x220d104900008000ull
; /* P9 Nimbus DD2.0 */
1555 k
->cores_mask
= POWER9_CORE_MASK
;
1556 k
->core_pir
= pnv_chip_core_pir_p9
;
1557 k
->intc_create
= pnv_chip_power9_intc_create
;
1558 k
->intc_reset
= pnv_chip_power9_intc_reset
;
1559 k
->intc_destroy
= pnv_chip_power9_intc_destroy
;
1560 k
->intc_print_info
= pnv_chip_power9_intc_print_info
;
1561 k
->isa_create
= pnv_chip_power9_isa_create
;
1562 k
->dt_populate
= pnv_chip_power9_dt_populate
;
1563 k
->pic_print_info
= pnv_chip_power9_pic_print_info
;
1564 k
->xscom_core_base
= pnv_chip_power9_xscom_core_base
;
1565 k
->xscom_pcba
= pnv_chip_power9_xscom_pcba
;
1566 dc
->desc
= "PowerNV Chip POWER9";
1569 device_class_set_parent_realize(dc
, pnv_chip_power9_realize
,
1570 &k
->parent_realize
);
1573 static void pnv_chip_power10_instance_init(Object
*obj
)
1575 Pnv10Chip
*chip10
= PNV10_CHIP(obj
);
1577 object_initialize_child(obj
, "psi", &chip10
->psi
, TYPE_PNV10_PSI
);
1578 object_initialize_child(obj
, "lpc", &chip10
->lpc
, TYPE_PNV10_LPC
);
1581 static void pnv_chip_power10_realize(DeviceState
*dev
, Error
**errp
)
1583 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(dev
);
1584 PnvChip
*chip
= PNV_CHIP(dev
);
1585 Pnv10Chip
*chip10
= PNV10_CHIP(dev
);
1586 Error
*local_err
= NULL
;
1588 /* XSCOM bridge is first */
1589 pnv_xscom_realize(chip
, PNV10_XSCOM_SIZE
, &local_err
);
1591 error_propagate(errp
, local_err
);
1594 sysbus_mmio_map(SYS_BUS_DEVICE(chip
), 0, PNV10_XSCOM_BASE(chip
));
1596 pcc
->parent_realize(dev
, &local_err
);
1598 error_propagate(errp
, local_err
);
1602 /* Processor Service Interface (PSI) Host Bridge */
1603 object_property_set_int(OBJECT(&chip10
->psi
), "bar",
1604 PNV10_PSIHB_BASE(chip
), &error_fatal
);
1605 if (!qdev_realize(DEVICE(&chip10
->psi
), NULL
, errp
)) {
1608 pnv_xscom_add_subregion(chip
, PNV10_XSCOM_PSIHB_BASE
,
1609 &PNV_PSI(&chip10
->psi
)->xscom_regs
);
1612 object_property_set_link(OBJECT(&chip10
->lpc
), "psi",
1613 OBJECT(&chip10
->psi
), &error_abort
);
1614 if (!qdev_realize(DEVICE(&chip10
->lpc
), NULL
, errp
)) {
1617 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip
),
1618 &chip10
->lpc
.xscom_regs
);
1620 chip
->fw_mr
= &chip10
->lpc
.isa_fw
;
1621 chip
->dt_isa_nodename
= g_strdup_printf("/lpcm-opb@%" PRIx64
"/lpc@0",
1622 (uint64_t) PNV10_LPCM_BASE(chip
));
1625 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip
*chip
, uint64_t addr
)
1627 addr
&= (PNV10_XSCOM_SIZE
- 1);
1631 static void pnv_chip_power10_class_init(ObjectClass
*klass
, void *data
)
1633 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1634 PnvChipClass
*k
= PNV_CHIP_CLASS(klass
);
1636 k
->chip_cfam_id
= 0x120da04900008000ull
; /* P10 DD1.0 (with NX) */
1637 k
->cores_mask
= POWER10_CORE_MASK
;
1638 k
->core_pir
= pnv_chip_core_pir_p10
;
1639 k
->intc_create
= pnv_chip_power10_intc_create
;
1640 k
->intc_reset
= pnv_chip_power10_intc_reset
;
1641 k
->intc_destroy
= pnv_chip_power10_intc_destroy
;
1642 k
->intc_print_info
= pnv_chip_power10_intc_print_info
;
1643 k
->isa_create
= pnv_chip_power10_isa_create
;
1644 k
->dt_populate
= pnv_chip_power10_dt_populate
;
1645 k
->pic_print_info
= pnv_chip_power10_pic_print_info
;
1646 k
->xscom_core_base
= pnv_chip_power10_xscom_core_base
;
1647 k
->xscom_pcba
= pnv_chip_power10_xscom_pcba
;
1648 dc
->desc
= "PowerNV Chip POWER10";
1650 device_class_set_parent_realize(dc
, pnv_chip_power10_realize
,
1651 &k
->parent_realize
);
1654 static void pnv_chip_core_sanitize(PnvChip
*chip
, Error
**errp
)
1656 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(chip
);
1660 * No custom mask for this chip, let's use the default one from *
1663 if (!chip
->cores_mask
) {
1664 chip
->cores_mask
= pcc
->cores_mask
;
1667 /* filter alien core ids ! some are reserved */
1668 if ((chip
->cores_mask
& pcc
->cores_mask
) != chip
->cores_mask
) {
1669 error_setg(errp
, "warning: invalid core mask for chip Ox%"PRIx64
" !",
1673 chip
->cores_mask
&= pcc
->cores_mask
;
1675 /* now that we have a sane layout, let check the number of cores */
1676 cores_max
= ctpop64(chip
->cores_mask
);
1677 if (chip
->nr_cores
> cores_max
) {
1678 error_setg(errp
, "warning: too many cores for chip ! Limit is %d",
1684 static void pnv_chip_core_realize(PnvChip
*chip
, Error
**errp
)
1686 Error
*error
= NULL
;
1687 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(chip
);
1688 const char *typename
= pnv_chip_core_typename(chip
);
1690 PnvMachineState
*pnv
= PNV_MACHINE(qdev_get_machine());
1692 if (!object_class_by_name(typename
)) {
1693 error_setg(errp
, "Unable to find PowerNV CPU Core '%s'", typename
);
1698 pnv_chip_core_sanitize(chip
, &error
);
1700 error_propagate(errp
, error
);
1704 chip
->cores
= g_new0(PnvCore
*, chip
->nr_cores
);
1706 for (i
= 0, core_hwid
= 0; (core_hwid
< sizeof(chip
->cores_mask
) * 8)
1707 && (i
< chip
->nr_cores
); core_hwid
++) {
1710 uint64_t xscom_core_base
;
1712 if (!(chip
->cores_mask
& (1ull << core_hwid
))) {
1716 pnv_core
= PNV_CORE(object_new(typename
));
1718 snprintf(core_name
, sizeof(core_name
), "core[%d]", core_hwid
);
1719 object_property_add_child(OBJECT(chip
), core_name
, OBJECT(pnv_core
));
1720 chip
->cores
[i
] = pnv_core
;
1721 object_property_set_int(OBJECT(pnv_core
), "nr-threads",
1722 chip
->nr_threads
, &error_fatal
);
1723 object_property_set_int(OBJECT(pnv_core
), CPU_CORE_PROP_CORE_ID
,
1724 core_hwid
, &error_fatal
);
1725 object_property_set_int(OBJECT(pnv_core
), "pir",
1726 pcc
->core_pir(chip
, core_hwid
), &error_fatal
);
1727 object_property_set_int(OBJECT(pnv_core
), "hrmor", pnv
->fw_load_addr
,
1729 object_property_set_link(OBJECT(pnv_core
), "chip", OBJECT(chip
),
1731 qdev_realize(DEVICE(pnv_core
), NULL
, &error_fatal
);
1733 /* Each core has an XSCOM MMIO region */
1734 xscom_core_base
= pcc
->xscom_core_base(chip
, core_hwid
);
1736 pnv_xscom_add_subregion(chip
, xscom_core_base
,
1737 &pnv_core
->xscom_regs
);
1742 static void pnv_chip_realize(DeviceState
*dev
, Error
**errp
)
1744 PnvChip
*chip
= PNV_CHIP(dev
);
1745 Error
*error
= NULL
;
1748 pnv_chip_core_realize(chip
, &error
);
1750 error_propagate(errp
, error
);
1755 static Property pnv_chip_properties
[] = {
1756 DEFINE_PROP_UINT32("chip-id", PnvChip
, chip_id
, 0),
1757 DEFINE_PROP_UINT64("ram-start", PnvChip
, ram_start
, 0),
1758 DEFINE_PROP_UINT64("ram-size", PnvChip
, ram_size
, 0),
1759 DEFINE_PROP_UINT32("nr-cores", PnvChip
, nr_cores
, 1),
1760 DEFINE_PROP_UINT64("cores-mask", PnvChip
, cores_mask
, 0x0),
1761 DEFINE_PROP_UINT32("nr-threads", PnvChip
, nr_threads
, 1),
1762 DEFINE_PROP_END_OF_LIST(),
1765 static void pnv_chip_class_init(ObjectClass
*klass
, void *data
)
1767 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1769 set_bit(DEVICE_CATEGORY_CPU
, dc
->categories
);
1770 dc
->realize
= pnv_chip_realize
;
1771 device_class_set_props(dc
, pnv_chip_properties
);
1772 dc
->desc
= "PowerNV Chip";
1775 PowerPCCPU
*pnv_chip_find_cpu(PnvChip
*chip
, uint32_t pir
)
1779 for (i
= 0; i
< chip
->nr_cores
; i
++) {
1780 PnvCore
*pc
= chip
->cores
[i
];
1781 CPUCore
*cc
= CPU_CORE(pc
);
1783 for (j
= 0; j
< cc
->nr_threads
; j
++) {
1784 if (ppc_cpu_pir(pc
->threads
[j
]) == pir
) {
1785 return pc
->threads
[j
];
1792 static ICSState
*pnv_ics_get(XICSFabric
*xi
, int irq
)
1794 PnvMachineState
*pnv
= PNV_MACHINE(xi
);
1797 for (i
= 0; i
< pnv
->num_chips
; i
++) {
1798 PnvChip
*chip
= pnv
->chips
[i
];
1799 Pnv8Chip
*chip8
= PNV8_CHIP(pnv
->chips
[i
]);
1801 if (ics_valid_irq(&chip8
->psi
.ics
, irq
)) {
1802 return &chip8
->psi
.ics
;
1804 for (j
= 0; j
< chip
->num_phbs
; j
++) {
1805 if (ics_valid_irq(&chip8
->phbs
[j
].lsis
, irq
)) {
1806 return &chip8
->phbs
[j
].lsis
;
1808 if (ics_valid_irq(ICS(&chip8
->phbs
[j
].msis
), irq
)) {
1809 return ICS(&chip8
->phbs
[j
].msis
);
1816 static void pnv_ics_resend(XICSFabric
*xi
)
1818 PnvMachineState
*pnv
= PNV_MACHINE(xi
);
1821 for (i
= 0; i
< pnv
->num_chips
; i
++) {
1822 PnvChip
*chip
= pnv
->chips
[i
];
1823 Pnv8Chip
*chip8
= PNV8_CHIP(pnv
->chips
[i
]);
1825 ics_resend(&chip8
->psi
.ics
);
1826 for (j
= 0; j
< chip
->num_phbs
; j
++) {
1827 ics_resend(&chip8
->phbs
[j
].lsis
);
1828 ics_resend(ICS(&chip8
->phbs
[j
].msis
));
1833 static ICPState
*pnv_icp_get(XICSFabric
*xi
, int pir
)
1835 PowerPCCPU
*cpu
= ppc_get_vcpu_by_pir(pir
);
1837 return cpu
? ICP(pnv_cpu_state(cpu
)->intc
) : NULL
;
1840 static void pnv_pic_print_info(InterruptStatsProvider
*obj
,
1843 PnvMachineState
*pnv
= PNV_MACHINE(obj
);
1848 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
1850 /* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */
1851 PNV_CHIP_GET_CLASS(pnv
->chips
[0])->intc_print_info(pnv
->chips
[0], cpu
,
1855 for (i
= 0; i
< pnv
->num_chips
; i
++) {
1856 PNV_CHIP_GET_CLASS(pnv
->chips
[i
])->pic_print_info(pnv
->chips
[i
], mon
);
1860 static int pnv_match_nvt(XiveFabric
*xfb
, uint8_t format
,
1861 uint8_t nvt_blk
, uint32_t nvt_idx
,
1862 bool cam_ignore
, uint8_t priority
,
1863 uint32_t logic_serv
,
1864 XiveTCTXMatch
*match
)
1866 PnvMachineState
*pnv
= PNV_MACHINE(xfb
);
1867 int total_count
= 0;
1870 for (i
= 0; i
< pnv
->num_chips
; i
++) {
1871 Pnv9Chip
*chip9
= PNV9_CHIP(pnv
->chips
[i
]);
1872 XivePresenter
*xptr
= XIVE_PRESENTER(&chip9
->xive
);
1873 XivePresenterClass
*xpc
= XIVE_PRESENTER_GET_CLASS(xptr
);
1876 count
= xpc
->match_nvt(xptr
, format
, nvt_blk
, nvt_idx
, cam_ignore
,
1877 priority
, logic_serv
, match
);
1883 total_count
+= count
;
1889 static void pnv_machine_power8_class_init(ObjectClass
*oc
, void *data
)
1891 MachineClass
*mc
= MACHINE_CLASS(oc
);
1892 XICSFabricClass
*xic
= XICS_FABRIC_CLASS(oc
);
1893 PnvMachineClass
*pmc
= PNV_MACHINE_CLASS(oc
);
1894 static const char compat
[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv";
1896 mc
->desc
= "IBM PowerNV (Non-Virtualized) POWER8";
1897 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power8_v2.0");
1899 xic
->icp_get
= pnv_icp_get
;
1900 xic
->ics_get
= pnv_ics_get
;
1901 xic
->ics_resend
= pnv_ics_resend
;
1903 pmc
->compat
= compat
;
1904 pmc
->compat_size
= sizeof(compat
);
1907 static void pnv_machine_power9_class_init(ObjectClass
*oc
, void *data
)
1909 MachineClass
*mc
= MACHINE_CLASS(oc
);
1910 XiveFabricClass
*xfc
= XIVE_FABRIC_CLASS(oc
);
1911 PnvMachineClass
*pmc
= PNV_MACHINE_CLASS(oc
);
1912 static const char compat
[] = "qemu,powernv9\0ibm,powernv";
1914 mc
->desc
= "IBM PowerNV (Non-Virtualized) POWER9";
1915 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power9_v2.0");
1916 xfc
->match_nvt
= pnv_match_nvt
;
1918 mc
->alias
= "powernv";
1920 pmc
->compat
= compat
;
1921 pmc
->compat_size
= sizeof(compat
);
1922 pmc
->dt_power_mgt
= pnv_dt_power_mgt
;
1925 static void pnv_machine_power10_class_init(ObjectClass
*oc
, void *data
)
1927 MachineClass
*mc
= MACHINE_CLASS(oc
);
1928 PnvMachineClass
*pmc
= PNV_MACHINE_CLASS(oc
);
1929 static const char compat
[] = "qemu,powernv10\0ibm,powernv";
1931 mc
->desc
= "IBM PowerNV (Non-Virtualized) POWER10";
1932 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power10_v2.0");
1934 pmc
->compat
= compat
;
1935 pmc
->compat_size
= sizeof(compat
);
1936 pmc
->dt_power_mgt
= pnv_dt_power_mgt
;
1939 static bool pnv_machine_get_hb(Object
*obj
, Error
**errp
)
1941 PnvMachineState
*pnv
= PNV_MACHINE(obj
);
1943 return !!pnv
->fw_load_addr
;
1946 static void pnv_machine_set_hb(Object
*obj
, bool value
, Error
**errp
)
1948 PnvMachineState
*pnv
= PNV_MACHINE(obj
);
1951 pnv
->fw_load_addr
= 0x8000000;
1955 static void pnv_cpu_do_nmi_on_cpu(CPUState
*cs
, run_on_cpu_data arg
)
1957 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
1958 CPUPPCState
*env
= &cpu
->env
;
1960 cpu_synchronize_state(cs
);
1961 ppc_cpu_do_system_reset(cs
);
1962 if (env
->spr
[SPR_SRR1
] & SRR1_WAKESTATE
) {
1964 * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the
1965 * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100
1968 if (!(env
->spr
[SPR_SRR1
] & SRR1_WAKERESET
)) {
1969 warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason");
1970 env
->spr
[SPR_SRR1
] |= SRR1_WAKERESET
;
1974 * For non-powersave system resets, SRR1[42:45] are defined to be
1975 * implementation-dependent. The POWER9 User Manual specifies that
1976 * an external (SCOM driven, which may come from a BMC nmi command or
1977 * another CPU requesting a NMI IPI) system reset exception should be
1978 * 0b0010 (PPC_BIT(44)).
1980 env
->spr
[SPR_SRR1
] |= SRR1_WAKESCOM
;
1984 static void pnv_nmi(NMIState
*n
, int cpu_index
, Error
**errp
)
1989 async_run_on_cpu(cs
, pnv_cpu_do_nmi_on_cpu
, RUN_ON_CPU_NULL
);
1993 static void pnv_machine_class_init(ObjectClass
*oc
, void *data
)
1995 MachineClass
*mc
= MACHINE_CLASS(oc
);
1996 InterruptStatsProviderClass
*ispc
= INTERRUPT_STATS_PROVIDER_CLASS(oc
);
1997 NMIClass
*nc
= NMI_CLASS(oc
);
1999 mc
->desc
= "IBM PowerNV (Non-Virtualized)";
2000 mc
->init
= pnv_init
;
2001 mc
->reset
= pnv_reset
;
2002 mc
->max_cpus
= MAX_CPUS
;
2003 /* Pnv provides a AHCI device for storage */
2004 mc
->block_default_type
= IF_IDE
;
2005 mc
->no_parallel
= 1;
2006 mc
->default_boot_order
= NULL
;
2008 * RAM defaults to less than 2048 for 32-bit hosts, and large
2009 * enough to fit the maximum initrd size at it's load address
2011 mc
->default_ram_size
= 1 * GiB
;
2012 mc
->default_ram_id
= "pnv.ram";
2013 ispc
->print_info
= pnv_pic_print_info
;
2014 nc
->nmi_monitor_handler
= pnv_nmi
;
2016 object_class_property_add_bool(oc
, "hb-mode",
2017 pnv_machine_get_hb
, pnv_machine_set_hb
);
2018 object_class_property_set_description(oc
, "hb-mode",
2019 "Use a hostboot like boot loader");
2022 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \
2025 .class_init = class_initfn, \
2026 .parent = TYPE_PNV8_CHIP, \
2029 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \
2032 .class_init = class_initfn, \
2033 .parent = TYPE_PNV9_CHIP, \
2036 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \
2039 .class_init = class_initfn, \
2040 .parent = TYPE_PNV10_CHIP, \
2043 static const TypeInfo types
[] = {
2045 .name
= MACHINE_TYPE_NAME("powernv10"),
2046 .parent
= TYPE_PNV_MACHINE
,
2047 .class_init
= pnv_machine_power10_class_init
,
2050 .name
= MACHINE_TYPE_NAME("powernv9"),
2051 .parent
= TYPE_PNV_MACHINE
,
2052 .class_init
= pnv_machine_power9_class_init
,
2053 .interfaces
= (InterfaceInfo
[]) {
2054 { TYPE_XIVE_FABRIC
},
2059 .name
= MACHINE_TYPE_NAME("powernv8"),
2060 .parent
= TYPE_PNV_MACHINE
,
2061 .class_init
= pnv_machine_power8_class_init
,
2062 .interfaces
= (InterfaceInfo
[]) {
2063 { TYPE_XICS_FABRIC
},
2068 .name
= TYPE_PNV_MACHINE
,
2069 .parent
= TYPE_MACHINE
,
2071 .instance_size
= sizeof(PnvMachineState
),
2072 .class_init
= pnv_machine_class_init
,
2073 .class_size
= sizeof(PnvMachineClass
),
2074 .interfaces
= (InterfaceInfo
[]) {
2075 { TYPE_INTERRUPT_STATS_PROVIDER
},
2081 .name
= TYPE_PNV_CHIP
,
2082 .parent
= TYPE_SYS_BUS_DEVICE
,
2083 .class_init
= pnv_chip_class_init
,
2084 .instance_size
= sizeof(PnvChip
),
2085 .class_size
= sizeof(PnvChipClass
),
2090 * P10 chip and variants
2093 .name
= TYPE_PNV10_CHIP
,
2094 .parent
= TYPE_PNV_CHIP
,
2095 .instance_init
= pnv_chip_power10_instance_init
,
2096 .instance_size
= sizeof(Pnv10Chip
),
2098 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10
, pnv_chip_power10_class_init
),
2101 * P9 chip and variants
2104 .name
= TYPE_PNV9_CHIP
,
2105 .parent
= TYPE_PNV_CHIP
,
2106 .instance_init
= pnv_chip_power9_instance_init
,
2107 .instance_size
= sizeof(Pnv9Chip
),
2109 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9
, pnv_chip_power9_class_init
),
2112 * P8 chip and variants
2115 .name
= TYPE_PNV8_CHIP
,
2116 .parent
= TYPE_PNV_CHIP
,
2117 .instance_init
= pnv_chip_power8_instance_init
,
2118 .instance_size
= sizeof(Pnv8Chip
),
2120 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8
, pnv_chip_power8_class_init
),
2121 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E
, pnv_chip_power8e_class_init
),
2122 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL
,
2123 pnv_chip_power8nvl_class_init
),