hw/mc146818rtc.c

   1 /*
   2  * QEMU MC146818 RTC emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "qemu-timer.h"
  26 #include "sysemu.h"
  27 #include "pc.h"
  28 #include "apic.h"
  29 #include "isa.h"
  30 #include "hpet_emul.h"
  31 #include "mc146818rtc.h"
  32
  33 //#define DEBUG_CMOS
  34 //#define DEBUG_COALESCED
  35
  36 #ifdef DEBUG_CMOS
  37 # define CMOS_DPRINTF(format, ...)      printf(format, ## __VA_ARGS__)
  38 #else
  39 # define CMOS_DPRINTF(format, ...)      do { } while (0)
  40 #endif
  41
  42 #ifdef DEBUG_COALESCED
  43 # define DPRINTF_C(format, ...)      printf(format, ## __VA_ARGS__)
  44 #else
  45 # define DPRINTF_C(format, ...)      do { } while (0)
  46 #endif
  47
  48 #define RTC_REINJECT_ON_ACK_COUNT 20
  49
  50 #define RTC_SECONDS             0
  51 #define RTC_SECONDS_ALARM       1
  52 #define RTC_MINUTES             2
  53 #define RTC_MINUTES_ALARM       3
  54 #define RTC_HOURS               4
  55 #define RTC_HOURS_ALARM         5
  56 #define RTC_ALARM_DONT_CARE    0xC0
  57
  58 #define RTC_DAY_OF_WEEK         6
  59 #define RTC_DAY_OF_MONTH        7
  60 #define RTC_MONTH               8
  61 #define RTC_YEAR                9
  62
  63 #define RTC_REG_A               10
  64 #define RTC_REG_B               11
  65 #define RTC_REG_C               12
  66 #define RTC_REG_D               13
  67
  68 #define REG_A_UIP 0x80
  69
  70 #define REG_B_SET  0x80
  71 #define REG_B_PIE  0x40
  72 #define REG_B_AIE  0x20
  73 #define REG_B_UIE  0x10
  74 #define REG_B_SQWE 0x08
  75 #define REG_B_DM   0x04
  76
  77 #define REG_C_UF   0x10
  78 #define REG_C_IRQF 0x80
  79 #define REG_C_PF   0x40
  80 #define REG_C_AF   0x20
  81
  82 typedef struct RTCState {
  83     ISADevice dev;
  84     uint8_t cmos_data[128];
  85     uint8_t cmos_index;
  86     struct tm current_tm;
  87     int32_t base_year;
  88     qemu_irq irq;
  89     qemu_irq sqw_irq;
  90     int it_shift;
  91     /* periodic timer */
  92     QEMUTimer *periodic_timer;
  93     int64_t next_periodic_time;
  94     /* second update */
  95     int64_t next_second_time;
  96     uint16_t irq_reinject_on_ack_count;
  97     uint32_t irq_coalesced;
  98     uint32_t period;
  99     QEMUTimer *coalesced_timer;
 100     QEMUTimer *second_timer;
 101     QEMUTimer *second_timer2;
 102 } RTCState;
 103
 104 static void rtc_irq_raise(qemu_irq irq)
 105 {
 106     /* When HPET is operating in legacy mode, RTC interrupts are disabled
 107      * We block qemu_irq_raise, but not qemu_irq_lower, in case legacy
 108      * mode is established while interrupt is raised. We want it to
 109      * be lowered in any case
 110      */
 111 #if defined TARGET_I386
 112     if (!hpet_in_legacy_mode())
 113 #endif
 114         qemu_irq_raise(irq);
 115 }
 116
 117 static void rtc_set_time(RTCState *s);
 118 static void rtc_copy_date(RTCState *s);
 119
 120 #ifdef TARGET_I386
 121 static void rtc_coalesced_timer_update(RTCState *s)
 122 {
 123     if (s->irq_coalesced == 0) {
 124         qemu_del_timer(s->coalesced_timer);
 125     } else {
 126         /* divide each RTC interval to 2 - 8 smaller intervals */
 127         int c = MIN(s->irq_coalesced, 7) + 1;
 128         int64_t next_clock = qemu_get_clock(rtc_clock) +
 129             muldiv64(s->period / c, get_ticks_per_sec(), 32768);
 130         qemu_mod_timer(s->coalesced_timer, next_clock);
 131     }
 132 }
 133
 134 static void rtc_coalesced_timer(void *opaque)
 135 {
 136     RTCState *s = opaque;
 137
 138     if (s->irq_coalesced != 0) {
 139         apic_reset_irq_delivered();
 140         s->cmos_data[RTC_REG_C] |= 0xc0;
 141         DPRINTF_C("cmos: injecting from timer\n");
 142         rtc_irq_raise(s->irq);
 143         if (apic_get_irq_delivered()) {
 144             s->irq_coalesced--;
 145             DPRINTF_C("cmos: coalesced irqs decreased to %d\n",
 146                       s->irq_coalesced);
 147         }
 148     }
 149
 150     rtc_coalesced_timer_update(s);
 151 }
 152 #endif
 153
 154 static void rtc_timer_update(RTCState *s, int64_t current_time)
 155 {
 156     int period_code, period;
 157     int64_t cur_clock, next_irq_clock;
 158     int enable_pie;
 159
 160     period_code = s->cmos_data[RTC_REG_A] & 0x0f;
 161 #if defined TARGET_I386
 162     /* disable periodic timer if hpet is in legacy mode, since interrupts are
 163      * disabled anyway.
 164      */
 165     enable_pie = !hpet_in_legacy_mode();
 166 #else
 167     enable_pie = 1;
 168 #endif
 169     if (period_code != 0
 170         && (((s->cmos_data[RTC_REG_B] & REG_B_PIE) && enable_pie)
 171             || ((s->cmos_data[RTC_REG_B] & REG_B_SQWE) && s->sqw_irq))) {
 172         if (period_code <= 2)
 173             period_code += 7;
 174         /* period in 32 Khz cycles */
 175         period = 1 << (period_code - 1);
 176 #ifdef TARGET_I386
 177         if (period != s->period) {
 178             s->irq_coalesced = (s->irq_coalesced * s->period) / period;
 179             DPRINTF_C("cmos: coalesced irqs scaled to %d\n", s->irq_coalesced);
 180         }
 181         s->period = period;
 182 #endif
 183         /* compute 32 khz clock */
 184         cur_clock = muldiv64(current_time, 32768, get_ticks_per_sec());
 185         next_irq_clock = (cur_clock & ~(period - 1)) + period;
 186         s->next_periodic_time =
 187             muldiv64(next_irq_clock, get_ticks_per_sec(), 32768) + 1;
 188         qemu_mod_timer(s->periodic_timer, s->next_periodic_time);
 189     } else {
 190 #ifdef TARGET_I386
 191         s->irq_coalesced = 0;
 192 #endif
 193         qemu_del_timer(s->periodic_timer);
 194     }
 195 }
 196
 197 static void rtc_periodic_timer(void *opaque)
 198 {
 199     RTCState *s = opaque;
 200
 201     rtc_timer_update(s, s->next_periodic_time);
 202     if (s->cmos_data[RTC_REG_B] & REG_B_PIE) {
 203         s->cmos_data[RTC_REG_C] |= 0xc0;
 204 #ifdef TARGET_I386
 205         if(rtc_td_hack) {
 206             if (s->irq_reinject_on_ack_count >= RTC_REINJECT_ON_ACK_COUNT)
 207                 s->irq_reinject_on_ack_count = 0;
 208             apic_reset_irq_delivered();
 209             rtc_irq_raise(s->irq);
 210             if (!apic_get_irq_delivered()) {
 211                 s->irq_coalesced++;
 212                 rtc_coalesced_timer_update(s);
 213                 DPRINTF_C("cmos: coalesced irqs increased to %d\n",
 214                           s->irq_coalesced);
 215             }
 216         } else
 217 #endif
 218         rtc_irq_raise(s->irq);
 219     }
 220     if (s->cmos_data[RTC_REG_B] & REG_B_SQWE) {
 221         /* Not square wave at all but we don't want 2048Hz interrupts!
 222            Must be seen as a pulse.  */
 223         qemu_irq_raise(s->sqw_irq);
 224     }
 225 }
 226
 227 static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data)
 228 {
 229     RTCState *s = opaque;
 230
 231     if ((addr & 1) == 0) {
 232         s->cmos_index = data & 0x7f;
 233     } else {
 234         CMOS_DPRINTF("cmos: write index=0x%02x val=0x%02x\n",
 235                      s->cmos_index, data);
 236         switch(s->cmos_index) {
 237         case RTC_SECONDS_ALARM:
 238         case RTC_MINUTES_ALARM:
 239         case RTC_HOURS_ALARM:
 240             /* XXX: not supported */
 241             s->cmos_data[s->cmos_index] = data;
 242             break;
 243         case RTC_SECONDS:
 244         case RTC_MINUTES:
 245         case RTC_HOURS:
 246         case RTC_DAY_OF_WEEK:
 247         case RTC_DAY_OF_MONTH:
 248         case RTC_MONTH:
 249         case RTC_YEAR:
 250             s->cmos_data[s->cmos_index] = data;
 251             /* if in set mode, do not update the time */
 252             if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
 253                 rtc_set_time(s);
 254             }
 255             break;
 256         case RTC_REG_A:
 257             /* UIP bit is read only */
 258             s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) |
 259                 (s->cmos_data[RTC_REG_A] & REG_A_UIP);
 260             rtc_timer_update(s, qemu_get_clock(rtc_clock));
 261             break;
 262         case RTC_REG_B:
 263             if (data & REG_B_SET) {
 264                 /* set mode: reset UIP mode */
 265                 s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
 266                 data &= ~REG_B_UIE;
 267             } else {
 268                 /* if disabling set mode, update the time */
 269                 if (s->cmos_data[RTC_REG_B] & REG_B_SET) {
 270                     rtc_set_time(s);
 271                 }
 272             }
 273             s->cmos_data[RTC_REG_B] = data;
 274             rtc_timer_update(s, qemu_get_clock(rtc_clock));
 275             break;
 276         case RTC_REG_C:
 277         case RTC_REG_D:
 278             /* cannot write to them */
 279             break;
 280         default:
 281             s->cmos_data[s->cmos_index] = data;
 282             break;
 283         }
 284     }
 285 }
 286
 287 static inline int rtc_to_bcd(RTCState *s, int a)
 288 {
 289     if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
 290         return a;
 291     } else {
 292         return ((a / 10) << 4) | (a % 10);
 293     }
 294 }
 295
 296 static inline int rtc_from_bcd(RTCState *s, int a)
 297 {
 298     if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
 299         return a;
 300     } else {
 301         return ((a >> 4) * 10) + (a & 0x0f);
 302     }
 303 }
 304
 305 static void rtc_set_time(RTCState *s)
 306 {
 307     struct tm *tm = &s->current_tm;
 308
 309     tm->tm_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS]);
 310     tm->tm_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES]);
 311     tm->tm_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS] & 0x7f);
 312     if (!(s->cmos_data[RTC_REG_B] & 0x02) &&
 313         (s->cmos_data[RTC_HOURS] & 0x80)) {
 314         tm->tm_hour += 12;
 315     }
 316     tm->tm_wday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_WEEK]) - 1;
 317     tm->tm_mday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_MONTH]);
 318     tm->tm_mon = rtc_from_bcd(s, s->cmos_data[RTC_MONTH]) - 1;
 319     tm->tm_year = rtc_from_bcd(s, s->cmos_data[RTC_YEAR]) + s->base_year - 1900;
 320
 321     rtc_change_mon_event(tm);
 322 }
 323
 324 static void rtc_copy_date(RTCState *s)
 325 {
 326     const struct tm *tm = &s->current_tm;
 327     int year;
 328
 329     s->cmos_data[RTC_SECONDS] = rtc_to_bcd(s, tm->tm_sec);
 330     s->cmos_data[RTC_MINUTES] = rtc_to_bcd(s, tm->tm_min);
 331     if (s->cmos_data[RTC_REG_B] & 0x02) {
 332         /* 24 hour format */
 333         s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, tm->tm_hour);
 334     } else {
 335         /* 12 hour format */
 336         s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, tm->tm_hour % 12);
 337         if (tm->tm_hour >= 12)
 338             s->cmos_data[RTC_HOURS] |= 0x80;
 339     }
 340     s->cmos_data[RTC_DAY_OF_WEEK] = rtc_to_bcd(s, tm->tm_wday + 1);
 341     s->cmos_data[RTC_DAY_OF_MONTH] = rtc_to_bcd(s, tm->tm_mday);
 342     s->cmos_data[RTC_MONTH] = rtc_to_bcd(s, tm->tm_mon + 1);
 343     year = (tm->tm_year - s->base_year) % 100;
 344     if (year < 0)
 345         year += 100;
 346     s->cmos_data[RTC_YEAR] = rtc_to_bcd(s, year);
 347 }
 348
 349 /* month is between 0 and 11. */
 350 static int get_days_in_month(int month, int year)
 351 {
 352     static const int days_tab[12] = {
 353         31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31
 354     };
 355     int d;
 356     if ((unsigned )month >= 12)
 357         return 31;
 358     d = days_tab[month];
 359     if (month == 1) {
 360         if ((year % 4) == 0 && ((year % 100) != 0 || (year % 400) == 0))
 361             d++;
 362     }
 363     return d;
 364 }
 365
 366 /* update 'tm' to the next second */
 367 static void rtc_next_second(struct tm *tm)
 368 {
 369     int days_in_month;
 370
 371     tm->tm_sec++;
 372     if ((unsigned)tm->tm_sec >= 60) {
 373         tm->tm_sec = 0;
 374         tm->tm_min++;
 375         if ((unsigned)tm->tm_min >= 60) {
 376             tm->tm_min = 0;
 377             tm->tm_hour++;
 378             if ((unsigned)tm->tm_hour >= 24) {
 379                 tm->tm_hour = 0;
 380                 /* next day */
 381                 tm->tm_wday++;
 382                 if ((unsigned)tm->tm_wday >= 7)
 383                     tm->tm_wday = 0;
 384                 days_in_month = get_days_in_month(tm->tm_mon,
 385                                                   tm->tm_year + 1900);
 386                 tm->tm_mday++;
 387                 if (tm->tm_mday < 1) {
 388                     tm->tm_mday = 1;
 389                 } else if (tm->tm_mday > days_in_month) {
 390                     tm->tm_mday = 1;
 391                     tm->tm_mon++;
 392                     if (tm->tm_mon >= 12) {
 393                         tm->tm_mon = 0;
 394                         tm->tm_year++;
 395                     }
 396                 }
 397             }
 398         }
 399     }
 400 }
 401
 402
 403 static void rtc_update_second(void *opaque)
 404 {
 405     RTCState *s = opaque;
 406     int64_t delay;
 407
 408     /* if the oscillator is not in normal operation, we do not update */
 409     if ((s->cmos_data[RTC_REG_A] & 0x70) != 0x20) {
 410         s->next_second_time += get_ticks_per_sec();
 411         qemu_mod_timer(s->second_timer, s->next_second_time);
 412     } else {
 413         rtc_next_second(&s->current_tm);
 414
 415         if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
 416             /* update in progress bit */
 417             s->cmos_data[RTC_REG_A] |= REG_A_UIP;
 418         }
 419         /* should be 244 us = 8 / 32768 seconds, but currently the
 420            timers do not have the necessary resolution. */
 421         delay = (get_ticks_per_sec() * 1) / 100;
 422         if (delay < 1)
 423             delay = 1;
 424         qemu_mod_timer(s->second_timer2,
 425                        s->next_second_time + delay);
 426     }
 427 }
 428
 429 static void rtc_update_second2(void *opaque)
 430 {
 431     RTCState *s = opaque;
 432
 433     if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
 434         rtc_copy_date(s);
 435     }
 436
 437     /* check alarm */
 438     if (s->cmos_data[RTC_REG_B] & REG_B_AIE) {
 439         if (((s->cmos_data[RTC_SECONDS_ALARM] & 0xc0) == 0xc0 ||
 440              s->cmos_data[RTC_SECONDS_ALARM] == s->current_tm.tm_sec) &&
 441             ((s->cmos_data[RTC_MINUTES_ALARM] & 0xc0) == 0xc0 ||
 442              s->cmos_data[RTC_MINUTES_ALARM] == s->current_tm.tm_mon) &&
 443             ((s->cmos_data[RTC_HOURS_ALARM] & 0xc0) == 0xc0 ||
 444              s->cmos_data[RTC_HOURS_ALARM] == s->current_tm.tm_hour)) {
 445
 446             s->cmos_data[RTC_REG_C] |= 0xa0;
 447             rtc_irq_raise(s->irq);
 448         }
 449     }
 450
 451     /* update ended interrupt */
 452     s->cmos_data[RTC_REG_C] |= REG_C_UF;
 453     if (s->cmos_data[RTC_REG_B] & REG_B_UIE) {
 454       s->cmos_data[RTC_REG_C] |= REG_C_IRQF;
 455       rtc_irq_raise(s->irq);
 456     }
 457
 458     /* clear update in progress bit */
 459     s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
 460
 461     s->next_second_time += get_ticks_per_sec();
 462     qemu_mod_timer(s->second_timer, s->next_second_time);
 463 }
 464
 465 static uint32_t cmos_ioport_read(void *opaque, uint32_t addr)
 466 {
 467     RTCState *s = opaque;
 468     int ret;
 469     if ((addr & 1) == 0) {
 470         return 0xff;
 471     } else {
 472         switch(s->cmos_index) {
 473         case RTC_SECONDS:
 474         case RTC_MINUTES:
 475         case RTC_HOURS:
 476         case RTC_DAY_OF_WEEK:
 477         case RTC_DAY_OF_MONTH:
 478         case RTC_MONTH:
 479         case RTC_YEAR:
 480             ret = s->cmos_data[s->cmos_index];
 481             break;
 482         case RTC_REG_A:
 483             ret = s->cmos_data[s->cmos_index];
 484             break;
 485         case RTC_REG_C:
 486             ret = s->cmos_data[s->cmos_index];
 487             qemu_irq_lower(s->irq);
 488 #ifdef TARGET_I386
 489             if(s->irq_coalesced &&
 490                     s->irq_reinject_on_ack_count < RTC_REINJECT_ON_ACK_COUNT) {
 491                 s->irq_reinject_on_ack_count++;
 492                 apic_reset_irq_delivered();
 493                 DPRINTF_C("cmos: injecting on ack\n");
 494                 qemu_irq_raise(s->irq);
 495                 if (apic_get_irq_delivered()) {
 496                     s->irq_coalesced--;
 497                     DPRINTF_C("cmos: coalesced irqs decreased to %d\n",
 498                               s->irq_coalesced);
 499                 }
 500                 break;
 501             }
 502 #endif
 503
 504             s->cmos_data[RTC_REG_C] = 0x00;
 505             break;
 506         default:
 507             ret = s->cmos_data[s->cmos_index];
 508             break;
 509         }
 510         CMOS_DPRINTF("cmos: read index=0x%02x val=0x%02x\n",
 511                      s->cmos_index, ret);
 512         return ret;
 513     }
 514 }
 515
 516 void rtc_set_memory(ISADevice *dev, int addr, int val)
 517 {
 518     RTCState *s = DO_UPCAST(RTCState, dev, dev);
 519     if (addr >= 0 && addr <= 127)
 520         s->cmos_data[addr] = val;
 521 }
 522
 523 void rtc_set_date(ISADevice *dev, const struct tm *tm)
 524 {
 525     RTCState *s = DO_UPCAST(RTCState, dev, dev);
 526     s->current_tm = *tm;
 527     rtc_copy_date(s);
 528 }
 529
 530 /* PC cmos mappings */
 531 #define REG_IBM_CENTURY_BYTE        0x32
 532 #define REG_IBM_PS2_CENTURY_BYTE    0x37
 533
 534 static void rtc_set_date_from_host(ISADevice *dev)
 535 {
 536     RTCState *s = DO_UPCAST(RTCState, dev, dev);
 537     struct tm tm;
 538     int val;
 539
 540     /* set the CMOS date */
 541     qemu_get_timedate(&tm, 0);
 542     rtc_set_date(dev, &tm);
 543
 544     val = rtc_to_bcd(s, (tm.tm_year / 100) + 19);
 545     rtc_set_memory(dev, REG_IBM_CENTURY_BYTE, val);
 546     rtc_set_memory(dev, REG_IBM_PS2_CENTURY_BYTE, val);
 547 }
 548
 549 static int rtc_post_load(void *opaque, int version_id)
 550 {
 551 #ifdef TARGET_I386
 552     RTCState *s = opaque;
 553
 554     if (version_id >= 2) {
 555         if (rtc_td_hack) {
 556             rtc_coalesced_timer_update(s);
 557         }
 558     }
 559 #endif
 560     return 0;
 561 }
 562
 563 static const VMStateDescription vmstate_rtc = {
 564     .name = "mc146818rtc",
 565     .version_id = 2,
 566     .minimum_version_id = 1,
 567     .minimum_version_id_old = 1,
 568     .post_load = rtc_post_load,
 569     .fields      = (VMStateField []) {
 570         VMSTATE_BUFFER(cmos_data, RTCState),
 571         VMSTATE_UINT8(cmos_index, RTCState),
 572         VMSTATE_INT32(current_tm.tm_sec, RTCState),
 573         VMSTATE_INT32(current_tm.tm_min, RTCState),
 574         VMSTATE_INT32(current_tm.tm_hour, RTCState),
 575         VMSTATE_INT32(current_tm.tm_wday, RTCState),
 576         VMSTATE_INT32(current_tm.tm_mday, RTCState),
 577         VMSTATE_INT32(current_tm.tm_mon, RTCState),
 578         VMSTATE_INT32(current_tm.tm_year, RTCState),
 579         VMSTATE_TIMER(periodic_timer, RTCState),
 580         VMSTATE_INT64(next_periodic_time, RTCState),
 581         VMSTATE_INT64(next_second_time, RTCState),
 582         VMSTATE_TIMER(second_timer, RTCState),
 583         VMSTATE_TIMER(second_timer2, RTCState),
 584         VMSTATE_UINT32_V(irq_coalesced, RTCState, 2),
 585         VMSTATE_UINT32_V(period, RTCState, 2),
 586         VMSTATE_END_OF_LIST()
 587     }
 588 };
 589
 590 static void rtc_reset(void *opaque)
 591 {
 592     RTCState *s = opaque;
 593
 594     s->cmos_data[RTC_REG_B] &= ~(REG_B_PIE | REG_B_AIE | REG_B_SQWE);
 595     s->cmos_data[RTC_REG_C] &= ~(REG_C_UF | REG_C_IRQF | REG_C_PF | REG_C_AF);
 596
 597     qemu_irq_lower(s->irq);
 598
 599 #ifdef TARGET_I386
 600     if (rtc_td_hack)
 601             s->irq_coalesced = 0;
 602 #endif
 603 }
 604
 605 static int rtc_initfn(ISADevice *dev)
 606 {
 607     RTCState *s = DO_UPCAST(RTCState, dev, dev);
 608     int base = 0x70;
 609     int isairq = 8;
 610
 611     isa_init_irq(dev, &s->irq, isairq);
 612
 613     s->cmos_data[RTC_REG_A] = 0x26;
 614     s->cmos_data[RTC_REG_B] = 0x02;
 615     s->cmos_data[RTC_REG_C] = 0x00;
 616     s->cmos_data[RTC_REG_D] = 0x80;
 617
 618     rtc_set_date_from_host(dev);
 619
 620     s->periodic_timer = qemu_new_timer(rtc_clock, rtc_periodic_timer, s);
 621 #ifdef TARGET_I386
 622     if (rtc_td_hack)
 623         s->coalesced_timer =
 624             qemu_new_timer(rtc_clock, rtc_coalesced_timer, s);
 625 #endif
 626     s->second_timer = qemu_new_timer(rtc_clock, rtc_update_second, s);
 627     s->second_timer2 = qemu_new_timer(rtc_clock, rtc_update_second2, s);
 628
 629     s->next_second_time =
 630         qemu_get_clock(rtc_clock) + (get_ticks_per_sec() * 99) / 100;
 631     qemu_mod_timer(s->second_timer2, s->next_second_time);
 632
 633     register_ioport_write(base, 2, 1, cmos_ioport_write, s);
 634     register_ioport_read(base, 2, 1, cmos_ioport_read, s);
 635
 636     qdev_set_legacy_instance_id(&dev->qdev, base, 2);
 637     qemu_register_reset(rtc_reset, s);
 638     return 0;
 639 }
 640
 641 ISADevice *rtc_init(int base_year)
 642 {
 643     ISADevice *dev;
 644
 645     dev = isa_create("mc146818rtc");
 646     qdev_prop_set_int32(&dev->qdev, "base_year", base_year);
 647     qdev_init_nofail(&dev->qdev);
 648     return dev;
 649 }
 650
 651 static ISADeviceInfo mc146818rtc_info = {
 652     .qdev.name     = "mc146818rtc",
 653     .qdev.size     = sizeof(RTCState),
 654     .qdev.no_user  = 1,
 655     .qdev.vmsd     = &vmstate_rtc,
 656     .init          = rtc_initfn,
 657     .qdev.props    = (Property[]) {
 658         DEFINE_PROP_INT32("base_year", RTCState, base_year, 1980),
 659         DEFINE_PROP_END_OF_LIST(),
 660     }
 661 };
 662
 663 static void mc146818rtc_register(void)
 664 {
 665     isa_qdev_register(&mc146818rtc_info);
 666 }
 667 device_init(mc146818rtc_register)