hw/arm/stm32f100_soc.c

   1 /*
   2  * STM32F100 SoC
   3  *
   4  * Copyright (c) 2021 Alexandre Iooss <erdnaxe@crans.org>
   5  * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 #include "qemu/osdep.h"
  27 #include "qapi/error.h"
  28 #include "qemu/module.h"
  29 #include "hw/arm/boot.h"
  30 #include "exec/address-spaces.h"
  31 #include "hw/arm/stm32f100_soc.h"
  32 #include "hw/qdev-properties.h"
  33 #include "hw/misc/unimp.h"
  34 #include "sysemu/sysemu.h"
  35
  36 /* stm32f100_soc implementation is derived from stm32f205_soc */
  37
  38 static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40013800, 0x40004400,
  39     0x40004800 };
  40 static const uint32_t spi_addr[STM_NUM_SPIS] = { 0x40013000, 0x40003800 };
  41
  42 static const int usart_irq[STM_NUM_USARTS] = {37, 38, 39};
  43 static const int spi_irq[STM_NUM_SPIS] = {35, 36};
  44
  45 static void stm32f100_soc_initfn(Object *obj)
  46 {
  47     STM32F100State *s = STM32F100_SOC(obj);
  48     int i;
  49
  50     object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M);
  51
  52     for (i = 0; i < STM_NUM_USARTS; i++) {
  53         object_initialize_child(obj, "usart[*]", &s->usart[i],
  54                                 TYPE_STM32F2XX_USART);
  55     }
  56
  57     for (i = 0; i < STM_NUM_SPIS; i++) {
  58         object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_STM32F2XX_SPI);
  59     }
  60 }
  61
  62 static void stm32f100_soc_realize(DeviceState *dev_soc, Error **errp)
  63 {
  64     STM32F100State *s = STM32F100_SOC(dev_soc);
  65     DeviceState *dev, *armv7m;
  66     SysBusDevice *busdev;
  67     int i;
  68
  69     MemoryRegion *system_memory = get_system_memory();
  70     MemoryRegion *sram = g_new(MemoryRegion, 1);
  71     MemoryRegion *flash = g_new(MemoryRegion, 1);
  72     MemoryRegion *flash_alias = g_new(MemoryRegion, 1);
  73
  74     /*
  75      * Init flash region
  76      * Flash starts at 0x08000000 and then is aliased to boot memory at 0x0
  77      */
  78     memory_region_init_rom(flash, OBJECT(dev_soc), "STM32F100.flash",
  79                            FLASH_SIZE, &error_fatal);
  80     memory_region_init_alias(flash_alias, OBJECT(dev_soc),
  81                              "STM32F100.flash.alias", flash, 0, FLASH_SIZE);
  82     memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, flash);
  83     memory_region_add_subregion(system_memory, 0, flash_alias);
  84
  85     /* Init SRAM region */
  86     memory_region_init_ram(sram, NULL, "STM32F100.sram", SRAM_SIZE,
  87                            &error_fatal);
  88     memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
  89
  90     /* Init ARMv7m */
  91     armv7m = DEVICE(&s->armv7m);
  92     qdev_prop_set_uint32(armv7m, "num-irq", 61);
  93     qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
  94     qdev_prop_set_bit(armv7m, "enable-bitband", true);
  95     object_property_set_link(OBJECT(&s->armv7m), "memory",
  96                              OBJECT(get_system_memory()), &error_abort);
  97     if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) {
  98         return;
  99     }
 100
 101     /* Attach UART (uses USART registers) and USART controllers */
 102     for (i = 0; i < STM_NUM_USARTS; i++) {
 103         dev = DEVICE(&(s->usart[i]));
 104         qdev_prop_set_chr(dev, "chardev", serial_hd(i));
 105         if (!sysbus_realize(SYS_BUS_DEVICE(&s->usart[i]), errp)) {
 106             return;
 107         }
 108         busdev = SYS_BUS_DEVICE(dev);
 109         sysbus_mmio_map(busdev, 0, usart_addr[i]);
 110         sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i]));
 111     }
 112
 113     /* SPI 1 and 2 */
 114     for (i = 0; i < STM_NUM_SPIS; i++) {
 115         dev = DEVICE(&(s->spi[i]));
 116         if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
 117             return;
 118         }
 119         busdev = SYS_BUS_DEVICE(dev);
 120         sysbus_mmio_map(busdev, 0, spi_addr[i]);
 121         sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i]));
 122     }
 123
 124     create_unimplemented_device("timer[2]",  0x40000000, 0x400);
 125     create_unimplemented_device("timer[3]",  0x40000400, 0x400);
 126     create_unimplemented_device("timer[4]",  0x40000800, 0x400);
 127     create_unimplemented_device("timer[6]",  0x40001000, 0x400);
 128     create_unimplemented_device("timer[7]",  0x40001400, 0x400);
 129     create_unimplemented_device("RTC",       0x40002800, 0x400);
 130     create_unimplemented_device("WWDG",      0x40002C00, 0x400);
 131     create_unimplemented_device("IWDG",      0x40003000, 0x400);
 132     create_unimplemented_device("I2C1",      0x40005400, 0x400);
 133     create_unimplemented_device("I2C2",      0x40005800, 0x400);
 134     create_unimplemented_device("BKP",       0x40006C00, 0x400);
 135     create_unimplemented_device("PWR",       0x40007000, 0x400);
 136     create_unimplemented_device("DAC",       0x40007400, 0x400);
 137     create_unimplemented_device("CEC",       0x40007800, 0x400);
 138     create_unimplemented_device("AFIO",      0x40010000, 0x400);
 139     create_unimplemented_device("EXTI",      0x40010400, 0x400);
 140     create_unimplemented_device("GPIOA",     0x40010800, 0x400);
 141     create_unimplemented_device("GPIOB",     0x40010C00, 0x400);
 142     create_unimplemented_device("GPIOC",     0x40011000, 0x400);
 143     create_unimplemented_device("GPIOD",     0x40011400, 0x400);
 144     create_unimplemented_device("GPIOE",     0x40011800, 0x400);
 145     create_unimplemented_device("ADC1",      0x40012400, 0x400);
 146     create_unimplemented_device("timer[1]",  0x40012C00, 0x400);
 147     create_unimplemented_device("timer[15]", 0x40014000, 0x400);
 148     create_unimplemented_device("timer[16]", 0x40014400, 0x400);
 149     create_unimplemented_device("timer[17]", 0x40014800, 0x400);
 150     create_unimplemented_device("DMA",       0x40020000, 0x400);
 151     create_unimplemented_device("RCC",       0x40021000, 0x400);
 152     create_unimplemented_device("Flash Int", 0x40022000, 0x400);
 153     create_unimplemented_device("CRC",       0x40023000, 0x400);
 154 }
 155
 156 static Property stm32f100_soc_properties[] = {
 157     DEFINE_PROP_STRING("cpu-type", STM32F100State, cpu_type),
 158     DEFINE_PROP_END_OF_LIST(),
 159 };
 160
 161 static void stm32f100_soc_class_init(ObjectClass *klass, void *data)
 162 {
 163     DeviceClass *dc = DEVICE_CLASS(klass);
 164
 165     dc->realize = stm32f100_soc_realize;
 166     device_class_set_props(dc, stm32f100_soc_properties);
 167 }
 168
 169 static const TypeInfo stm32f100_soc_info = {
 170     .name          = TYPE_STM32F100_SOC,
 171     .parent        = TYPE_SYS_BUS_DEVICE,
 172     .instance_size = sizeof(STM32F100State),
 173     .instance_init = stm32f100_soc_initfn,
 174     .class_init    = stm32f100_soc_class_init,
 175 };
 176
 177 static void stm32f100_soc_types(void)
 178 {
 179     type_register_static(&stm32f100_soc_info);
 180 }
 181
 182 type_init(stm32f100_soc_types)